A continuous-time current comparator capable of outputting maximum and minimum currents

Abstract

This invention discloses a continuous-time current comparator capable of outputting maximum and minimum currents, comprising eight sets of common-source cascode current mirrors composed of NMOS transistors N1-N20 and PMOS transistors P1-P8; the drain of PMOS transistor P2 is simultaneously connected to the drains of NMOS transistors N5 and N7, the drain of PMOS transistor P6 is simultaneously connected to the drains of NMOS transistors N11 and N13, and the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N17; the current to be compared, Ia, is input from the drain of NMOS transistor N1, and after the input, the current to be compared, Ib, is split into two paths, flowing to the drains of NMOS transistors N3 and N9 respectively; the drain of NMOS transistor N19 outputs the maximum current Imax, and the drain of NMOS transistor N15 outputs the minimum current Imin. After the input currents Ia and Ib are compared, the maximum current Imax and minimum current Imin corresponding to Ia and Ib are output through the current replication, summation and difference operation of the common source cascode current mirror, and the maximum current Imax and minimum current Imin are both continuous analog current signals.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more specifically to a continuous-time current comparator capable of outputting maximum and minimum currents. Background Technology

[0002] CMOS current comparators have undergone many years of development and numerous implementation methods exist, the simplest of which include... Figure 1 The current mirror comparator circuit shown has P1-P4 and N1-N4 each forming a common-source cascode current mirror, and P5 and N5 forming a single-stage inverter. Its core function is to compare two input currents Iin1 and Iin2 and output a digital signal (high or low). Its operation is as follows: assuming transistor P4 replicates the current of P3 1:1 (I_P4 ≈ Iin1), and transistor N2 replicates the current of N1 1:1 (I_N2 ≈ Iin2). If I_P4 > I_N2, the current supplied by P4 is greater than the current absorbed by N2, resulting in a quiescent current injection into node Vx, pulling the voltage high (close to VDD). After passing through the inverter, the output Vout is low. If I_P4 < I_N2, the current absorbed by N2 is greater than the current supplied by P4, resulting in a quiescent current outflow from node Vx, pulling the voltage low (close to VSS). After passing through the inverter, the output Vout is high. This circuit structure is simple and easy to implement. It also accurately replicates the current due to the use of a common source cascode current mirror. However, it also has some drawbacks. First, the final output of the circuit is a digital signal, which is not suitable for some systems that require analog signal processing (such as those that require the output to be the maximum or minimum of the input current). In addition, the inverter may introduce additional propagation delay, affecting the comparison speed and reducing the circuit's response speed.

[0003] In addition, other implementation methods based on voltage comparators are not only slow, but also require precise resistors and high-performance voltage comparators, which increases power consumption and chip area; while high-speed latching current comparators for high-speed applications are time-driven and cannot output continuously. Summary of the Invention

[0004] The purpose of this invention is to propose a continuous-time current comparator that can directly and accurately output the maximum and minimum currents without the need for current-to-voltage conversion.

[0005] The present invention provides a continuous-time current comparator capable of outputting maximum and minimum current, comprising 8 sets of common-source cascode current mirrors;

[0006] Among them, NMOS transistors N1, N2, N3, and N4 constitute the first group of common-source cascode current mirrors.

[0007] NMOS transistors N1, N2, N5, and N6 form the second set of common-source cascode current mirrors.

[0008] NMOS transistors N7, N8, N9, and N10 form the third set of common-source cascode current mirrors.

[0009] NMOS transistors N9, N10, N11, and N12 form the fourth set of common-source cascode current mirrors.

[0010] NMOS transistors N13, N14, N15, and N16 form the fifth group of common-source cascode current mirrors.

[0011] NMOS transistors N17, N18, N19, and N20 form the sixth group of common-source cascode current mirrors.

[0012] PMOS transistors P1, P2, P7, and P8 form the seventh group of common-source cascode current mirrors.

[0013] PMOS transistors P3, P4, P5, and P6 form the eighth group of common-source cascode current mirrors;

[0014] The drain of PMOS transistor P2 is connected to the drains of both NMOS transistors N5 and NMOS transistor N7, with the drain of NMOS transistor N5 connected to the drain of NMOS transistor N7; the drain of PMOS transistor P6 is connected to the drains of both NMOS transistors N11 and NMOS transistor N13, with the drain of NMOS transistor N11 connected to the drain of NMOS transistor N13; the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N17.

[0015] The current Ia to be compared is input from the drain of NMOS transistor N1. After the current Ib to be compared is input, it is split into two paths, flowing to the drain of NMOS transistor N3 and the drain of NMOS transistor N9 respectively.

[0016] The drain output of NMOS transistor N19 is the maximum current Imax, and the drain output of NMOS transistor N15 is the minimum current Imin. Both the maximum current Imax and the minimum current Imin are continuous analog current signals.

[0017] Furthermore, in the continuous-time current comparator of the present invention, the gate of NMOS transistor N1 in the first group of common-source common-gate current mirrors is connected to the gate of NMOS transistor N3, and the gate of NMOS transistor N2 is connected to the gate of NMOS transistor N4; the source of NMOS transistor N1 is connected to the drain of NMOS transistor N2, the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4, and the sources of NMOS transistor N2 and NMOS transistor N4 are both grounded; the gates and drains of NMOS transistors N1 and NMOS transistor N2 are both short-circuited.

[0018] Furthermore, in the continuous-time current comparator of the present invention, the gate of NMOS transistor N5 in the second set of common-source common-gate current mirrors is connected to the gate of NMOS transistor N1, and the gate of NMOS transistor N6 is connected to the gate of NMOS transistor N2; the source of NMOS transistor N5 is connected to the drain of NMOS transistor N6, and the source of NMOS transistor N6 is grounded.

[0019] Furthermore, in the continuous-time current comparator of the present invention, the gate of NMOS transistor N7 in the third group of common-source cascode current mirrors is connected to the gate of NMOS transistor N9, and the gate of NMOS transistor N8 is connected to the gate of NMOS transistor N10; the source of NMOS transistor N7 is connected to the drain of NMOS transistor N8, and the source of NMOS transistor N9 is connected to the drain of NMOS transistor N10; the sources of NMOS transistor N8 and NMOS transistor N10 are both grounded; the gates and drains of NMOS transistors N9 and NMOS transistor N10 are both short-circuited.

[0020] Furthermore, in the continuous-time current comparator of the present invention, the gate of NMOS transistor N11 in the fourth group of common-source common-gate current mirrors is connected to the gate of NMOS transistor N9, and the gate of NMOS transistor N12 is connected to the gate of NMOS transistor N10; the source of NMOS transistor N11 is connected to the drain of NMOS transistor N12, and the source of NMOS transistor N12 is grounded.

[0021] Furthermore, in the continuous-time current comparator of the present invention, the gate of NMOS transistor N13 in the fifth group of common-source common-gate current mirrors is connected to the gate of NMOS transistor N15, and the gate of NMOS transistor N14 is connected to the gate of NMOS transistor N16; the source of NMOS transistor N13 is connected to the drain of NMOS transistor N14, the source of NMOS transistor N15 is connected to the drain of NMOS transistor N16, and the sources of NMOS transistors N14 and NMOS transistor N16 are both grounded; the gates and drains of NMOS transistors N13 and NMOS transistor N14 are both short-circuited.

[0022] Furthermore, in the continuous-time current comparator of the present invention, the gate of NMOS transistor N17 in the sixth group of common-source common-gate current mirrors is connected to the gate of NMOS transistor N19, and the gate of NMOS transistor N18 is connected to the gate of NMOS transistor N20; the source of NMOS transistor N17 is connected to the drain of NMOS transistor N18, the source of NMOS transistor N19 is connected to the drain of NMOS transistor N20, and the sources of NMOS transistors N18 and NMOS transistor N20 are both grounded; the gates and drains of NMOS transistors N17 and NMOS transistor N18 are both shorted.

[0023] Furthermore, in the continuous-time current comparator of the present invention, the gate of PMOS transistor P1 in the seventh common-source common-gate current mirror is connected to the gate of PMOS transistor P7, and the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P8; the sources of PMOS transistors P1 and PMOS transistor P7 are both connected to the power supply; the drain of PMOS transistor P1 is connected to the source of PMOS transistor P2, and the drain of PMOS transistor P7 is connected to the source of PMOS transistor P8; the gates and drains of PMOS transistors P1 and PMOS transistor P2 are both short-circuited.

[0024] Furthermore, in the continuous-time current comparator of the present invention, the gate of PMOS transistor P3 in the eighth common-source common-gate current mirror is connected to the gate of PMOS transistor P5, and the gate of PMOS transistor P4 is connected to the gate of PMOS transistor P6; the sources of PMOS transistors P3 and P5 are both connected to the power supply; the drain of PMOS transistor P3 is connected to the source of PMOS transistor P4, and the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the gates and drains of PMOS transistors P3 and P4 are both short-circuited.

[0025] When Ib > Ia, the current in branch N3 replicates the current Ia in branch N1, and is also Ia; therefore, the current in branch N9 is Ib - Ia. The current in branch N7 replicates the current in branch N9, and is also Ib - Ia; the current in branch N5 replicates the current Ia in branch N1, and is also Ia. Therefore, the current in branch P2 is the sum of the currents in branches N5 and N7, which is Ia + Ib - Ia = Ib; branch P8 replicates the current in branch P2, so the current in branch N17 is also Ib. Branch N19 replicates the current in branch N17, so the final maximum current Imax outputs Ib, which is the maximum value of Ib and Ia.

[0026] Similarly, when Ib > Ia, the current in branch N11 replicates the current in branch N9, which is Ib - Ia; the current in branch P6 replicates the current in branch P4, which is also Ib; therefore, the current in branch N13 is the difference between the currents in branch P6 and branch N11, which is Ib - (Ib - Ia) = Ia; the current in branch N15 replicates the current in branch N13, which is Ia, so the final minimum current Imin outputs Ia, which is the minimum value of Ib and Ia.

[0027] Conversely, when Ib < Ia, the current in branch N3 is no longer Ia, but Ib, because Ib < Ia, the maximum current in branch N3 can only reach Ib; therefore, the current in branch N9 is 0, and the current in branch N7 replicates the current in branch N9, which is also 0; the current in branch N5 replicates the current in branch N1, which is Ia, so the current in branch P2 is the sum of the currents in branches N5 and N7, which is Ia + 0 = Ia; branch P8 replicates the current in branch P2, so the current in branch N17 is also Ia, and branch N19 replicates the current in branch N17, so the final maximum current Imax outputs Ia, which is the maximum value of Ib and Ia.

[0028] When Ib < Ia, the current in branch N11 replicates the current in branch N9, which is 0; the current in branch P6 replicates the current in branch P4, which is Ib; therefore, the current in branch N13 is the difference between the currents in branch P6 and branch N11, which is Ib - 0 = Ib; the current in branch N15 replicates the current in branch N13, which is Ib, so the final minimum current Imin outputs Ib, which is the minimum value between Ib and Ia.

[0029] Furthermore, the continuous-time current comparator of the present invention is a continuous-time current comparator with a rise time of less than 15ns, a transmission error of less than 2nA, and an input offset current of less than or equal to 4nA; the rise time is the time required for the current signal to rise from 10% of the amplitude to 90%.

[0030] The continuous-time current comparator capable of outputting maximum and minimum current described in this invention has the following advantages:

[0031] First, the continuous-time current comparator described in this invention, capable of outputting maximum and minimum currents, eliminates the need for current-to-voltage conversion, allowing direct current comparison. The entire signal path processes current signals, avoiding the bottleneck of current-to-voltage conversion in existing technologies. Current summation and replication are directly accomplished via a current mirror, and the response speed is primarily determined by the transconductance and parasitic capacitance of the transistor, achieving extremely high speeds with modern manufacturing processes. The measured rise time of the continuous-time current comparator is consistently below 15 ns.

[0032] Secondly, the multiple current mirrors described in this invention all use common source cascode current mirrors, which have accurate current replication and high output accuracy. Through simulation, the transmission errors of the maximum current Imax and the minimum current Imin are both below 2nA, the input offset current is less than or equal to 4nA, and the ability to distinguish two currents of similar magnitude is high, so that the output can be correctly judged.

[0033] Furthermore, this invention can simultaneously output analog comparison results, offering rich functionality. This design can simultaneously output the maximum current Imax and the minimum current Imin, which are continuous, analog current signals, not just digital signals. This is extremely valuable for many analog signal processing systems (such as fuzzy logic, signal limiting, automatic gain control, etc.), providing two key analog outputs—maximum and minimum values—resulting in very high functional density.

[0034] Furthermore, the continuous-time current comparator described in this invention features a simple, efficient, and low-power circuit structure. The maximum and minimum value output circuits of the entire core comparator consist of only a dozen or so MOSFETs, making it very compact. Its overall area is significantly smaller than solutions requiring operational amplifiers and resistors, and it is also simpler than solutions requiring clocks and latches. Attached Figure Description

[0035] Figure 1 The current mirror comparator circuit described in the background art;

[0036] Figure 2 This is a circuit diagram of the continuous-time current comparator described in Embodiment 1 of the present invention;

[0037] Figure 3 The input currents Ia and Ib are those described in Embodiment 1 of the present invention.

[0038] Figure 4 The static accuracy DC simulation results of the continuous-time current comparator described in Embodiment 1 of the present invention;

[0039] Figure 5 The simulation results of the input offset current of the continuous-time current comparator described in Embodiment 1 of the present invention;

[0040] Figure 6 The simulation results show the response speed of the continuous-time current comparator described in Embodiment 1 of the present invention. Detailed Implementation

[0041] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments are now described in detail with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the detailed embodiments, conventional conditions or conditions provided by the manufacturer shall apply.

[0042] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0043] A continuous-time current comparator capable of outputting maximum and minimum current includes 8 sets of common-source cascode current mirrors;

[0044] Among them, NMOS transistors N1, N2, N3, and N4 constitute the first group of common-source cascode current mirrors.

[0045] NMOS transistors N1, N2, N5, and N6 form the second set of common-source cascode current mirrors.

[0046] NMOS transistors N7, N8, N9, and N10 form the third set of common-source cascode current mirrors.

[0047] NMOS transistors N9, N10, N11, and N12 form the fourth set of common-source cascode current mirrors.

[0048] NMOS transistors N13, N14, N15, and N16 form the fifth group of common-source cascode current mirrors.

[0049] NMOS transistors N17, N18, N19, and N20 form the sixth group of common-source cascode current mirrors.

[0050] PMOS transistors P1, P2, P7, and P8 form the seventh group of common-source cascode current mirrors.

[0051] PMOS transistors P3, P4, P5, and P6 form the eighth group of common-source cascode current mirrors;

[0052] The drain of PMOS transistor P2 is connected to the drains of both NMOS transistors N5 and NMOS transistor N7, with the drain of NMOS transistor N5 connected to the drain of NMOS transistor N7; the drain of PMOS transistor P6 is connected to the drains of both NMOS transistors N11 and NMOS transistor N13, with the drain of NMOS transistor N11 connected to the drain of NMOS transistor N13; the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N17.

[0053] The current Ia to be compared is input from the drain of NMOS transistor N1. After the current Ib to be compared is input, it is split into two paths, flowing to the drain of NMOS transistor N3 and the drain of NMOS transistor N9 respectively.

[0054] The drain output of NMOS transistor N19 is the maximum current Imax, and the drain output of NMOS transistor N15 is the minimum current Imin. Both the maximum current Imax and the minimum current Imin are continuous analog current signals.

[0055] In other embodiments, in the first set of common-source common-gate current mirrors, the gate of NMOS transistor N1 is connected to the gate of NMOS transistor N3, and the gate of NMOS transistor N2 is connected to the gate of NMOS transistor N4; the source of NMOS transistor N1 is connected to the drain of NMOS transistor N2, the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4, and the sources of NMOS transistor N2 and NMOS transistor N4 are both grounded; the gates and drains of NMOS transistors N1 and NMOS transistor N2 are both short-circuited.

[0056] In other embodiments, the gate of NMOS transistor N5 in the second set of common-source common-gate current mirrors is connected to the gate of NMOS transistor N1, and the gate of NMOS transistor N6 is connected to the gate of NMOS transistor N2; the source of NMOS transistor N5 is connected to the drain of NMOS transistor N6, and the source of NMOS transistor N6 is grounded.

[0057] In other embodiments, in the third set of common-source common-gate current mirrors, the gate of NMOS transistor N7 is connected to the gate of NMOS transistor N9, and the gate of NMOS transistor N8 is connected to the gate of NMOS transistor N10; the source of NMOS transistor N7 is connected to the drain of NMOS transistor N8, the source of NMOS transistor N9 is connected to the drain of NMOS transistor N10, and the sources of NMOS transistor N8 and NMOS transistor N10 are both grounded; the gates and drains of NMOS transistors N9 and NMOS transistor N10 are both short-circuited.

[0058] In other embodiments, in the fourth set of common-source common-gate current mirrors, the gate of NMOS transistor N11 is connected to the gate of NMOS transistor N9, and the gate of NMOS transistor N12 is connected to the gate of NMOS transistor N10; the source of NMOS transistor N11 is connected to the drain of NMOS transistor N12, and the source of NMOS transistor N12 is grounded.

[0059] In other embodiments, in the fifth group of common-source common-gate current mirrors, the gate of NMOS transistor N13 is connected to the gate of NMOS transistor N15, and the gate of NMOS transistor N14 is connected to the gate of NMOS transistor N16; the source of NMOS transistor N13 is connected to the drain of NMOS transistor N14, the source of NMOS transistor N15 is connected to the drain of NMOS transistor N16, and the sources of NMOS transistor N14 and NMOS transistor N16 are both grounded; the gates and drains of NMOS transistors N13 and NMOS transistor N14 are both short-circuited.

[0060] In other embodiments, in the sixth group of common-source common-gate current mirrors, the gate of NMOS transistor N17 is connected to the gate of NMOS transistor N19, and the gate of NMOS transistor N18 is connected to the gate of NMOS transistor N20; the source of NMOS transistor N17 is connected to the drain of NMOS transistor N18, the source of NMOS transistor N19 is connected to the drain of NMOS transistor N20, and the sources of NMOS transistor N18 and NMOS transistor N20 are both grounded; the gates and drains of NMOS transistors N17 and NMOS transistor N18 are both short-circuited.

[0061] In other embodiments, in the seventh group of common-source common-gate current mirrors, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P7, and the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P8; the sources of PMOS transistors P1 and PMOS transistor P7 are both connected to the power supply; the drain of PMOS transistor P1 is connected to the source of PMOS transistor P2, and the drain of PMOS transistor P7 is connected to the source of PMOS transistor P8; the gates and drains of PMOS transistors P1 and PMOS transistor P2 are both short-circuited.

[0062] In other embodiments, in the eighth group of common-source common-gate current mirrors, the gate of PMOS transistor P3 is connected to the gate of PMOS transistor P5, and the gate of PMOS transistor P4 is connected to the gate of PMOS transistor P6; the sources of PMOS transistors P3 and P5 are both connected to the power supply; the drain of PMOS transistor P3 is connected to the source of PMOS transistor P4, and the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the gates and drains of PMOS transistors P3 and P4 are both short-circuited.

[0063] In other embodiments, the continuous-time current comparator is a continuous-time current comparator with a rise time of less than 15 ns, a transmission error of less than 2 nA, and an input offset current of less than or equal to 4 nA; the rise time is the time required for the current signal to rise from 10% to 90% of its amplitude. Example

[0064] A continuous-time current comparator capable of outputting maximum and minimum current, such as Figure 2 As shown, it includes 8 sets of common-source cascode current mirrors;

[0065] Among them, NMOS transistors N1, N2, N3, and N4 constitute the first group of common-source cascode current mirrors.

[0066] NMOS transistors N1, N2, N5, and N6 form the second set of common-source cascode current mirrors.

[0067] NMOS transistors N7, N8, N9, and N10 form the third set of common-source cascode current mirrors.

[0068] NMOS transistors N9, N10, N11, and N12 form the fourth set of common-source cascode current mirrors.

[0069] NMOS transistors N13, N14, N15, and N16 form the fifth group of common-source cascode current mirrors.

[0070] NMOS transistors N17, N18, N19, and N20 form the sixth group of common-source cascode current mirrors.

[0071] PMOS transistors P1, P2, P7, and P8 form the seventh group of common-source cascode current mirrors.

[0072] PMOS transistors P3, P4, P5, and P6 form the eighth group of common-source cascode current mirrors;

[0073] The drain of PMOS transistor P2 is connected to the drains of both NMOS transistors N5 and NMOS transistor N7, with the drain of NMOS transistor N5 connected to the drain of NMOS transistor N7; the drain of PMOS transistor P6 is connected to the drains of both NMOS transistors N11 and NMOS transistor N13, with the drain of NMOS transistor N11 connected to the drain of NMOS transistor N13; the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N17.

[0074] The current Ia to be compared is input from the drain of NMOS transistor N1. After the current Ib to be compared is input, it is split into two paths, flowing to the drain of NMOS transistor N3 and the drain of NMOS transistor N9 respectively.

[0075] The drain output of NMOS transistor N19 is the maximum current Imax, and the drain output of NMOS transistor N15 is the minimum current Imin. Both the maximum current Imax and the minimum current Imin are continuous analog current signals.

[0076] In the first set of common-source common-gate current mirrors, the gate of NMOS transistor N1 is connected to the gate of NMOS transistor N3, and the gate of NMOS transistor N2 is connected to the gate of NMOS transistor N4; the source of NMOS transistor N1 is connected to the drain of NMOS transistor N2, and the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4; the sources of NMOS transistor N2 and NMOS transistor N4 are both grounded; the gates and drains of NMOS transistors N1 and NMOS transistor N2 are both shorted.

[0077] In the second set of common-source common-gate current mirrors, the gate of NMOS transistor N5 is connected to the gate of NMOS transistor N1, and the gate of NMOS transistor N6 is connected to the gate of NMOS transistor N2; the source of NMOS transistor N5 is connected to the drain of NMOS transistor N6, and the source of NMOS transistor N6 is grounded.

[0078] In the third set of common-source common-gate current mirrors, the gate of NMOS transistor N7 is connected to the gate of NMOS transistor N9, and the gate of NMOS transistor N8 is connected to the gate of NMOS transistor N10; the source of NMOS transistor N7 is connected to the drain of NMOS transistor N8, and the source of NMOS transistor N9 is connected to the drain of NMOS transistor N10; the sources of NMOS transistor N8 and NMOS transistor N10 are both grounded; the gates and drains of NMOS transistors N9 and NMOS transistor N10 are both shorted.

[0079] In the fourth group of common-source common-gate current mirrors, the gate of NMOS transistor N11 is connected to the gate of NMOS transistor N9, and the gate of NMOS transistor N12 is connected to the gate of NMOS transistor N10; the source of NMOS transistor N11 is connected to the drain of NMOS transistor N12, and the source of NMOS transistor N12 is grounded.

[0080] In the fifth group of common-source common-gate current mirrors, the gate of NMOS transistor N13 is connected to the gate of NMOS transistor N15, and the gate of NMOS transistor N14 is connected to the gate of NMOS transistor N16; the source of NMOS transistor N13 is connected to the drain of NMOS transistor N14, the source of NMOS transistor N15 is connected to the drain of NMOS transistor N16, and the sources of NMOS transistors N14 and NMOS transistor N16 are both grounded; the gates and drains of NMOS transistors N13 and NMOS transistor N14 are both shorted.

[0081] In the sixth group of common-source common-gate current mirrors, the gate of NMOS transistor N17 is connected to the gate of NMOS transistor N19, and the gate of NMOS transistor N18 is connected to the gate of NMOS transistor N20; the source of NMOS transistor N17 is connected to the drain of NMOS transistor N18, the source of NMOS transistor N19 is connected to the drain of NMOS transistor N20, and the sources of NMOS transistors N18 and NMOS transistor N20 are both grounded; the gates and drains of NMOS transistors N17 and NMOS transistor N18 are both shorted.

[0082] In the seventh group of common-source common-gate current mirrors, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P7, and the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P8; the sources of PMOS transistors P1 and PMOS transistor P7 are both connected to the power supply; the drain of PMOS transistor P1 is connected to the source of PMOS transistor P2, and the drain of PMOS transistor P7 is connected to the source of PMOS transistor P8; the gates and drains of PMOS transistors P1 and PMOS transistor P2 are both shorted.

[0083] In the eighth group of common-source common-gate current mirrors, the gate of PMOS transistor P3 is connected to the gate of PMOS transistor P5, and the gate of PMOS transistor P4 is connected to the gate of PMOS transistor P6; the sources of PMOS transistors P3 and P5 are both connected to the power supply; the drain of PMOS transistor P3 is connected to the source of PMOS transistor P4, and the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the gates and drains of PMOS transistors P3 and P4 are both shorted.

[0084] For the continuous-time current comparator described in Embodiment 1, a DC simulation was performed to test the error between the maximum output current Imax and minimum output current Imin under steady-state conditions and the input currents to be compared, Ia and Ib. Figure 3 As shown, the input current to be compared, Ia, varies from 1uA to 10uA, while the current to be compared, Ib, is fixed at 5uA.

[0085] Test results are as follows Figure 4 As shown, when Ib > Ia, the maximum current Imax outputs Ib, and the minimum current Imin outputs Ia; when Ib < Ia, the maximum current Imax outputs Ia, and the minimum current Imin outputs Ib.

[0086] Furthermore, the maximum current Imax and minimum current Imin highly coincide with the input current curve, resulting in high output accuracy. Testing showed that the transmission error of the maximum current Imax is between 0.06nA and 1.75nA. For example, when Ia = 2uA and Ib = 5uA, ideally the maximum current Imax should be equal to 5uA. The actual simulation result is 4.99995uA, with a transmission error of 0.00005uA. The relative error (absolute error / signal size) is 0.00005uA / 5uA = 0.00001 = 0.001%.

[0087] The transmission error of the minimum current Imin is between 0.61nA and 1.8nA. Larger output errors occur when the maximum current Imax or the minimum current Imin equals the dynamically changing Ia.

[0088] Measure the input offset current:

[0089] The input current to be compared, Ib, was fixed at 5uA. The input current to be compared, Ia, was varied from 4.9uA to 5.1uA. The input offset current was measured, which is the minimum difference between the two input currents required for the output to switch correctly (i.e., switch from one input channel to another as the maximum / minimum value). The test results are as follows: Figure 5As shown, the maximum current Imax starts switching around Ia equals 4.996uA, and the minimum current Imin starts switching around Ia equals 5.004uA. The input offset current is 0.004uA, or 4nA. This demonstrates that the continuous-time current comparator described in this invention can identify two close currents.

[0090] The response speed of this circuit was evaluated using transient simulation. The input current to be compared, Ib, was a DC current source, IDC, fixed at 5uA. The current to be compared, Ia, was tested using a pulsed current source, ipulse, with an initial value of 1uA, a pulse value of 9uA, a delay time of 100ns, a rise time of 0.1ns, and a pulse width of 500ns. The simulation results are as follows: Figure 6 As shown, the rise time of the minimum current Imin (from 10% to 90%) is approximately 8.77 ns. Changing the value of the pulse current source ipulse, with an initial value of i1 set to 4uA and a pulse value of 6uA, while keeping Ib fixed at 5uA, and performing another transient simulation, the rise time of the minimum current Imin is 14.76 ns. Similarly, after repeatedly changing the initial value and pulse value of ipulse, the rise time remains below 15 ns.

Claims

1. A continuous-time current comparator capable of outputting maximum and minimum currents, characterized in that, Includes 8 sets of common-source cascode current mirrors; Among them, NMOS transistors N1, N2, N3, and N4 constitute the first group of common-source cascode current mirrors. NMOS transistors N1, N2, N5, and N6 form the second set of common-source cascode current mirrors. NMOS transistors N7, N8, N9, and N10 form the third set of common-source cascode current mirrors. NMOS transistors N9, N10, N11, and N12 form the fourth set of common-source cascode current mirrors. NMOS transistors N13, N14, N15, and N16 form the fifth group of common-source cascode current mirrors. NMOS transistors N17, N18, N19, and N20 form the sixth group of common-source cascode current mirrors. PMOS transistors P1, P2, P7, and P8 form the seventh group of common-source cascode current mirrors. PMOS transistors P3, P4, P5, and P6 form the eighth group of common-source cascode current mirrors; The drain of PMOS transistor P2 is connected to the drains of both NMOS transistors N5 and NMOS transistor N7, with the drain of NMOS transistor N5 connected to the drain of NMOS transistor N7; the drain of PMOS transistor P6 is connected to the drains of both NMOS transistors N11 and NMOS transistor N13, with the drain of NMOS transistor N11 connected to the drain of NMOS transistor N13; the drain of PMOS transistor P8 is connected to the drain of NMOS transistor N17. The current Ia to be compared is input from the drain of NMOS transistor N1. After the current Ib to be compared is input, it is split into two paths, flowing to the drain of NMOS transistor N3 and the drain of NMOS transistor N9 respectively. The drain output of NMOS transistor N19 is the maximum current Imax, and the drain output of NMOS transistor N15 is the minimum current Imin. Both the maximum current Imax and the minimum current Imin are continuous analog current signals.

2. The continuous-time current comparator according to claim 1, characterized in that: In the first set of common-source common-gate current mirrors, the gate of NMOS transistor N1 is connected to the gate of NMOS transistor N3, and the gate of NMOS transistor N2 is connected to the gate of NMOS transistor N4; the source of NMOS transistor N1 is connected to the drain of NMOS transistor N2, and the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4; the sources of NMOS transistor N2 and NMOS transistor N4 are both grounded; the gates and drains of NMOS transistors N1 and NMOS transistor N2 are both shorted.

3. The continuous-time current comparator according to claim 2, characterized in that: In the second set of common-source common-gate current mirrors, the gate of NMOS transistor N5 is connected to the gate of NMOS transistor N1, and the gate of NMOS transistor N6 is connected to the gate of NMOS transistor N2; the source of NMOS transistor N5 is connected to the drain of NMOS transistor N6, and the source of NMOS transistor N6 is grounded.

4. The continuous-time current comparator according to claim 1, characterized in that: In the third set of common-source common-gate current mirrors, the gate of NMOS transistor N7 is connected to the gate of NMOS transistor N9, and the gate of NMOS transistor N8 is connected to the gate of NMOS transistor N10; the source of NMOS transistor N7 is connected to the drain of NMOS transistor N8, and the source of NMOS transistor N9 is connected to the drain of NMOS transistor N10; the sources of NMOS transistor N8 and NMOS transistor N10 are both grounded; the gates and drains of NMOS transistors N9 and NMOS transistor N10 are both shorted.

5. The continuous-time current comparator according to claim 4, characterized in that, In the fourth group of common-source common-gate current mirrors, the gate of NMOS transistor N11 is connected to the gate of NMOS transistor N9, and the gate of NMOS transistor N12 is connected to the gate of NMOS transistor N10; the source of NMOS transistor N11 is connected to the drain of NMOS transistor N12, and the source of NMOS transistor N12 is grounded.

6. The continuous-time current comparator according to claim 1, characterized in that, In the fifth group of common-source common-gate current mirrors, the gate of NMOS transistor N13 is connected to the gate of NMOS transistor N15, and the gate of NMOS transistor N14 is connected to the gate of NMOS transistor N16; the source of NMOS transistor N13 is connected to the drain of NMOS transistor N14, the source of NMOS transistor N15 is connected to the drain of NMOS transistor N16, and the sources of NMOS transistors N14 and NMOS transistor N16 are both grounded; the gates and drains of NMOS transistors N13 and NMOS transistor N14 are both shorted.

7. The continuous-time current comparator according to claim 1, characterized in that: In the sixth group of common-source common-gate current mirrors, the gate of NMOS transistor N17 is connected to the gate of NMOS transistor N19, and the gate of NMOS transistor N18 is connected to the gate of NMOS transistor N20; the source of NMOS transistor N17 is connected to the drain of NMOS transistor N18, the source of NMOS transistor N19 is connected to the drain of NMOS transistor N20, and the sources of NMOS transistors N18 and NMOS transistor N20 are both grounded; the gates and drains of NMOS transistors N17 and NMOS transistor N18 are both shorted.

8. The continuous-time current comparator according to claim 1, characterized in that: In the seventh group of common-source common-gate current mirrors, the gate of PMOS transistor P1 is connected to the gate of PMOS transistor P7, and the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P8; the sources of PMOS transistors P1 and PMOS transistor P7 are both connected to the power supply; the drain of PMOS transistor P1 is connected to the source of PMOS transistor P2, and the drain of PMOS transistor P7 is connected to the source of PMOS transistor P8; the gates and drains of PMOS transistors P1 and PMOS transistor P2 are both shorted.

9. The continuous-time current comparator according to claim 1, characterized in that: In the eighth group of common-source common-gate current mirrors, the gate of PMOS transistor P3 is connected to the gate of PMOS transistor P5, and the gate of PMOS transistor P4 is connected to the gate of PMOS transistor P6; the sources of PMOS transistors P3 and P5 are both connected to the power supply; the drain of PMOS transistor P3 is connected to the source of PMOS transistor P4, and the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the gates and drains of PMOS transistors P3 and P4 are both shorted.

10. The continuous-time current comparator according to claim 1, characterized in that: The continuous-time current comparator is a continuous-time current comparator with a rise time of less than 15 ns, a transmission error of less than 2 nA, and an input offset current of less than or equal to 4 nA; the rise time is the time required for the current signal to rise from 10% of its amplitude to 90%.

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