Preparation method of solar cell and solar cell

Abstract

The invention provides a preparation method of a solar cell and the solar cell. The preparation method comprises the following steps: carrying out surface treatment on a silicon substrate; preparing a tunneling layer and an intrinsic polycrystalline silicon layer on the back surface of the silicon substrate in sequence; respectively forming a patterned N-type doped source layer and a patterned P-type doped source layer on the intrinsic polycrystalline silicon layer, and enabling the N-type doped source layer and the P-type doped source layer to be distributed at an interval; performing low-temperature annealing on the N-type doped source layer to form an N-type doped polycrystalline silicon layer; performing patterned annealing treatment on the P-type doped source layer by adopting laser to form a P-type doped polycrystalline silicon layer; cleaning and removing oxides formed in the annealing process; preparing passivation anti-reflection layers on the front surface and the back surface of the silicon substrate; preparing electrodes on the passivation anti-reflection layer corresponding to the N-type doped polycrystalline silicon layer and the P-type doped polycrystalline silicon layer; the weak light response of the solar cell can be improved; and the preparation method of the solar cell is simplified.

Description

Technical Field

[0001] This invention relates to the field of solar cell manufacturing technology, and in particular to a method for preparing a solar cell and the solar cell itself. Background Technology

[0002] Back-contact solar cells are solar cells with a first doped layer and a second doped layer arranged in a cross pattern on the back of the cell, where the doping types of the first and second doped layers are opposite. Since the light-receiving surface of this cell is free of any metal electrodes, it completely avoids optical losses caused by shading from the front electrode grid lines, maximizes the utilization of incident light, increases short-circuit current, and improves the energy conversion efficiency of the cell. This technology has received considerable attention in recent years.

[0003] However, one of the challenges of back-contact battery technology lies in forming a cross-shaped first and second doped layer on the back of the battery. As described in Chinese Patent No. CN114823991A, a solid first doped layer is typically formed on one side of the silicon substrate first, and then patterning is performed on the first doped layer using laser ablation technology to form the area for shaping the second doped layer. Although laser ablation technology has advantages such as low cost and ease of mass production, the high power required for laser ablation can cause damage to the silicon substrate, resulting in disadvantages such as low minority carrier lifetime and low response in weak light. Summary of the Invention

[0004] The purpose of this invention is to provide a method for preparing a solar cell and a solar cell, wherein the method for preparing the solar cell does not require laser ablation technology and will not cause thermal damage to the silicon substrate.

[0005] To achieve the above-mentioned objective, the present invention provides a method for preparing a solar cell, comprising the following steps:

[0006] Surface treatment of the silicon substrate;

[0007] A tunneling layer and an intrinsic polycrystalline silicon layer are sequentially fabricated on the back side of a silicon substrate;

[0008] Patterned N-type doped source layers and P-type doped source layers are formed on the intrinsic polysilicon layer, such that the N-type doped source layers and the P-type doped source layers are distributed alternately.

[0009] An N-type doped polycrystalline silicon layer is formed by low-temperature annealing of the N-type doped source layer.

[0010] A P-type doped polycrystalline silicon layer is formed by laser patterning annealing of the P-type doped source layer.

[0011] Cleaning removes oxides formed during the annealing process;

[0012] Passivation and antireflection layers are fabricated on the front and back sides of a silicon substrate;

[0013] Electrodes are fabricated on passivation antireflection layers corresponding to N-type doped polycrystalline silicon layers and P-type doped polycrystalline silicon layers.

[0014] As a further improvement of the present invention, "forming patterned N-type doped source layers and P-type doped source layers on the intrinsic polysilicon layer respectively" specifically means forming patterned N-type doped source layers and P-type doped source layers on the intrinsic polysilicon layer respectively by printing or inkjet printing.

[0015] As a further improvement of the present invention, when performing low-temperature annealing on the N-type doped source layer, the peak annealing temperature is 800-950°C and the annealing time is 1-3 hours.

[0016] As a further improvement of the present invention, when using laser to perform patterned annealing on the P-type doped source layer, the laser power is 30-150W, the laser speed is 20-60m / s, the laser frequency is 10-1000KHz, and the laser pulse width is either continuous laser or nanosecond laser.

[0017] As a further improvement of the present invention, the width of the intrinsic polysilicon layer located between the N-type doped polysilicon layer and the P-type doped polysilicon layer is 30 to 100 μm.

[0018] As a further improvement of the present invention, the thickness of the tunneling layer is 1 nm to 3 nm.

[0019] As a further improvement of the present invention, the thickness of the intrinsic polycrystalline silicon layer is 80 nm to 500 nm.

[0020] As a further improvement of the present invention, "surface treatment of silicon substrate" specifically includes the following steps: first, double-sided alkaline texturing of silicon substrate, and then polishing of the back side of silicon substrate.

[0021] As a further improvement of the present invention, the passivation antireflection layer is at least one of aluminum oxide layer, silicon oxide layer, gallium oxide layer, silicon nitride layer, aluminum nitride layer, and silicon oxynitride layer.

[0022] To achieve the above-mentioned objectives, the present invention also provides a solar cell, which is prepared using the above-described preparation method.

[0023] The beneficial effects of this invention are as follows: In the method for preparing a solar cell, patterned and spaced-apart N-type doped source layers and P-type doped source layers are first formed on an intrinsic polycrystalline silicon layer. For the N-type doped source layer that requires low-temperature annealing for diffusion, it is diffused through low-temperature annealing to form an N-type doped polycrystalline silicon layer. For the P-type doped source layer that requires high-temperature annealing for diffusion, it is patterned by laser annealing to diffuse and form a P-type doped polycrystalline silicon layer. This avoids damage to the N-type doped source layer caused by high temperature and avoids the use of laser ablation technology, which is beneficial to improving the weak light response of the solar cell. Furthermore, there is no need to separately form an isolation region between the N-type doped polycrystalline silicon layer and the P-type doped polycrystalline silicon layer, which simplifies the preparation method of the solar cell, reduces production costs, and facilitates industrialization and application. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the main process of the solar cell fabrication method of the present invention;

[0025] Figure 2 This is a schematic diagram of the structure of the solar cell in this invention;

[0026] 10. Solar cell; 1. Silicon substrate; 2. Tunneling layer; 31. N-type doped polycrystalline silicon layer; 32. P-type doped polycrystalline silicon layer; 33. Intrinsic polycrystalline silicon layer; 41. First back electrode; 42. Second back electrode. Detailed Implementation

[0027] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0028] Please refer to Figures 1-2 As shown, the present invention provides a method for preparing a solar cell 10, the method comprising the following steps:

[0029] The silicon substrate 1 is surface treated;

[0030] A tunneling layer 2 and an intrinsic polycrystalline silicon layer 33 are sequentially fabricated on the back side of a silicon substrate 1.

[0031] Patterned N-type doped source layers and P-type doped source layers are formed on the intrinsic polysilicon layer 33, such that the N-type doped source layers and the P-type doped source layers are distributed alternately.

[0032] An N-type doped polysilicon layer 31 is formed by low-temperature annealing of the N-type doped source layer;

[0033] A P-type doped polycrystalline silicon layer 32 is formed by patterning annealing of the P-type doped source layer using laser;

[0034] Cleaning removes oxides formed during the annealing process;

[0035] Passivation and antireflection layers are fabricated on the front and back sides of silicon substrate 1;

[0036] Electrodes are fabricated on the passivation and antireflection layers corresponding to the N-type doped polycrystalline silicon layer 31 and the P-type doped polycrystalline silicon layer 32 to obtain a solar cell 10.

[0037] In the fabrication method of the solar cell 10 of the present invention, a patterned N-type doped source layer and a P-type doped source layer are first formed on the intrinsic polycrystalline silicon layer 33. For the N-type doped source layer that requires low-temperature annealing to achieve diffusion, the N-type doped polycrystalline silicon layer 31 is formed by low-temperature annealing diffusion. For the P-type doped source layer that requires high-temperature annealing to achieve diffusion, laser is used for patterned annealing treatment to diffuse and form the P-type doped polycrystalline silicon layer 32. This avoids the damage of the N-type doped source layer caused by high temperature. At the same time, it avoids the use of laser ablation technology, thereby avoiding thermal damage to the silicon substrate 1 caused by laser ablation. This is beneficial to improving the weak light response of the solar cell 10. Moreover, the fabrication method of the solar cell 10 of the present invention has a simple process flow, which is conducive to large-scale production.

[0038] Furthermore, it is known that the N-type doped source layer and the P-type doped source layer are distributed alternately. After annealing and diffusion, the intrinsic polycrystalline silicon layer 33 located in the spacer region between the N-type doped source layer and the P-type doped source layer cannot form a conductive polycrystalline silicon layer because it has no doping source. After annealing and diffusion, the intrinsic polycrystalline silicon layer 33 located between the N-type doped polycrystalline silicon layer 31 and the P-type doped polycrystalline silicon layer 32 forms an isolation region that isolates the N-type doped polycrystalline silicon layer 31 and the P-type doped polycrystalline silicon layer 32. Therefore, it is not necessary to separately form an isolation region that isolates the N-type doped polycrystalline silicon layer 31 and the P-type doped polycrystalline silicon layer 32, which simplifies the fabrication method of the solar cell 10 and is beneficial for large-scale production.

[0039] Specifically, experiments have shown that the solar cell 10 prepared by the method of the present invention has a low light response of 95%, while the low light response of the existing solar cell 10 prepared by using laser ablation technology as the method of realizing the back patterning of the solar cell 10 is 92%.

[0040] In one specific embodiment, "forming patterned N-type doped source layers and P-type doped source layers on the intrinsic polycrystalline silicon layer 33" specifically involves forming patterned N-type doped source layers and P-type doped source layers on the intrinsic polycrystalline silicon layer 33 by printing or inkjet printing doped sources. This method allows for relatively simple formation of N-type and P-type doped source layers in a predetermined area, simplifying the fabrication method of the solar cell 10 and avoiding damage caused by laser ablation technology.

[0041] It is known that a patterned N-type doped source layer can be formed on the intrinsic polysilicon layer 33 by first printing or inkjet printing N-type doped sources in a predetermined area of ​​the intrinsic polysilicon layer 33, and then a patterned P-type doped source layer can be formed on the intrinsic polysilicon layer 33 by printing or inkjet printing P-type doped sources in a predetermined area of ​​the intrinsic polysilicon layer 33; or, a patterned P-type doped source layer can be formed on the intrinsic polysilicon layer 33 by first printing or inkjet printing P-type doped sources in a predetermined area of ​​the intrinsic polysilicon layer 33, and then a patterned N-type doped source layer can be formed on the intrinsic polysilicon layer 33 by printing or inkjet printing N-type doped sources in a predetermined area of ​​the intrinsic polysilicon layer 33.

[0042] Specifically, the N-type dopant sources in the N-type doped source layer include, but are not limited to, one or more phosphorus-containing compounds or phosphorus compounds. The P-type dopant sources in the P-type doped source layer include, but are not limited to, one or more boron-containing compounds or boron compounds.

[0043] In one specific embodiment, the N-type doped source layer is first subjected to low-temperature annealing to form an N-type doped polysilicon layer 31, and then the P-type doped source layer is subjected to laser patterned annealing to form a P-type doped polysilicon layer 32. However, this is not a limitation; in other embodiments, the P-type doped source layer may be first subjected to laser patterned annealing to form a P-type doped polysilicon layer 32, and then the N-type doped source layer may be subjected to low-temperature annealing to form an N-type doped polysilicon layer 31.

[0044] Specifically, when performing low-temperature annealing on the N-type doped source layer, the peak annealing temperature is 800–950°C, and the annealing time is 1–3 hours, to improve the diffusion effect of the N-type doped source layer. The peak annealing temperature can be 800°C, 900°C, 950°C, etc., and the annealing time can be specifically set to 1 hour, 2 hours, 3 hours, etc. In one specific embodiment, the peak annealing temperature is 900°C, and the annealing time is 2 hours.

[0045] Patterned annealing of the P-type doped source layer using laser is employed, where a laser beam moves along the pattern of the P-type doped source layer to perform patterned annealing. Specifically, when performing patterned annealing of the P-type doped source layer using laser, the laser power is 30–150 W, the laser velocity is 20–60 m / s, the laser frequency is 10–1000 kHz, and the laser pulse width is either continuous laser or nanosecond laser, in order to improve and precisely control the diffusion of the P-type doped source layer.

[0046] In one specific embodiment, when performing patterned annealing of the P-type doped source layer using laser, the laser power is 80W, the laser velocity is 60m / s, the laser frequency is continuous laser, and the laser pulse width is continuous laser. However, this is not a limitation.

[0047] In some optional embodiments, “surface treatment of silicon substrate 1” specifically includes the following steps: first, double-sided alkaline texturing of silicon substrate 1, and then polishing of the back side of silicon substrate 1.

[0048] Specifically, an aqueous solution of KOH, NaOH, or TMAH can be used to perform double-sided alkaline texturing on the silicon substrate 1, forming a pyramidal textured surface on both the front and back sides of the silicon substrate 1 to remove cutting damage to the surface of the silicon substrate 1. The silicon substrate 1 can be either P-type silicon or N-type silicon.

[0049] In one specific embodiment, a chain-type alkaline polishing device is used to polish the back side of the silicon substrate 1 on one side to remove the pyramidal textured surface of the entire back side of the silicon substrate 1. Specifically, a water film is first applied to the front side of the silicon substrate 1 to protect it. Then, the back side of the silicon substrate 1 is placed on a roller containing an alkaline solution. The pyramidal textured surface of the back side of the silicon substrate 1 is removed by the etching of the silicon by the alkaline solution, forming a polished surface.

[0050] Specifically, the alkaline solution used in the polishing process is KOH or NaOH.

[0051] In one specific embodiment, the tunneling layer 2 is a SiO2 film layer, which is prepared by any one or a combination of two of the following methods: chemical oxidation, thermal oxidation, and ozone oxidation. The aforementioned chemical oxidation method typically refers to the reaction of HNO3 with the back side of the silicon substrate 1 to generate the SiO2 film layer. The intrinsic polycrystalline silicon layer 33 can be prepared by LPCVD or PECVD methods. However, this is not a limitation; in other embodiments of the present invention, the tunneling layer 2 may also be SiO2. x N y The film layer, the SiO x N y The film can be prepared by PECVD.

[0052] Specifically, the thickness of the tunneling layer 2 is 1 nm to 3 nm. The thickness of the intrinsic polysilicon layer 33 is 80 nm to 500 nm.

[0053] Specifically, "cleaning to remove oxides formed during annealing" refers to cleaning with chemical solutions, such as using HF to clean and remove SiO2 from the surface.

[0054] After the silicon substrate 1 is dried after cleaning, passivation and antireflection layers are prepared on the front and back sides of the silicon substrate 1 to provide certain protection and antireflection effects.

[0055] Specifically, the passivation antireflection layer is at least one of an aluminum oxide layer, a silicon oxide layer, a gallium oxide layer, a silicon nitride layer, an aluminum nitride layer, and a silicon oxynitride layer. The aluminum oxide layer can be prepared by an ALD process, and the silicon nitride layer is generally prepared by a plasma-enhanced chemical vapor deposition method.

[0056] Specifically, "electrode fabrication" can be achieved by screen printing metal grid lines on the passivation antireflection layers corresponding to the N-type doped polycrystalline silicon layer 31 and the P-type doped polycrystalline silicon layer 32, followed by drying and sintering to form electrodes, ultimately forming the solar cell 10.

[0057] Furthermore, combined Figure 2 As shown, the present invention also provides a solar cell 10 fabricated using the above-described method for fabricating solar cell 10. The solar cell 10 includes a silicon substrate 1, a tunneling layer 2 disposed on the back side of the silicon substrate 1, a polycrystalline silicon layer disposed on the tunneling layer 2, a passivation and antireflection layer (not shown) disposed on the back side of the polycrystalline silicon layer and the front side of the silicon substrate 1, and electrodes. The polycrystalline silicon layer includes N-type doped polycrystalline silicon layers 31, P-type doped polycrystalline silicon layers 32, and intrinsic polycrystalline silicon layers 33 arranged alternately in sequence. Adjacent N-type doped polycrystalline silicon layers 31 and P-type doped polycrystalline silicon layers 32 are isolated by the intrinsic polycrystalline silicon layer 33. Therefore, when fabricating the solar cell 10, it is not necessary to separately form an isolation region separating the N-type doped polycrystalline silicon layers 31 and P-type doped polycrystalline silicon layers 32, simplifying the fabrication method of the solar cell 10 and facilitating large-scale production.

[0058] Specifically, the width of the intrinsic polysilicon layer 33 located between the N-type doped polysilicon layer 31 and the P-type doped polysilicon layer 32 is 30–100 μm. In one specific embodiment, the width of the intrinsic polysilicon layer 33 located between the N-type doped polysilicon layer 31 and the P-type doped polysilicon layer 32 is 60 μm, but it is not limited to this.

[0059] The electrode includes a first back electrode 41 in contact with the N-type doped polysilicon layer 31 and a second back electrode 42 in contact with the P-type doped polysilicon layer 32.

[0060] Specifically, the silicon substrate 1 is either N-type silicon or P-type silicon. The tunneling layer 2 is configured as a SiO2 film or a SiO2 film. x N y The thickness of the tunneling layer 22 is set to 1 nm to 3 nm; the thickness of the intrinsic polycrystalline silicon layer 33 is 80 nm to 500 nm.

[0061] In the fabrication method of the solar cell 10 of the present invention, patterned and spaced N-type doped source layers and P-type doped source layers are first formed on the intrinsic polycrystalline silicon layer 33. For the N-type doped source layer that requires low-temperature annealing for diffusion, N-type doped polycrystalline silicon layer 31 is formed by low-temperature annealing diffusion. For the P-type doped source layer that requires high-temperature annealing for diffusion, laser patterned annealing is used to diffuse and form P-type doped polycrystalline silicon layer 32. This method avoids damage to the N-type doped source layer caused by high temperature and avoids the use of laser ablation technology, which is beneficial to improving the weak light response of the solar cell 10. Furthermore, it eliminates the need to separately form an isolation region between the N-type doped polycrystalline silicon layer 31 and the P-type doped polycrystalline silicon layer 32, simplifying the fabrication method of the solar cell 10, reducing production costs, and facilitating industrialization and application.

[0062] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0063] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: Includes the following steps: Surface treatment of the silicon substrate; A tunneling layer and an intrinsic polycrystalline silicon layer are sequentially fabricated on the back side of a silicon substrate; Patterned N-type doped source layers and P-type doped source layers are formed on the intrinsic polysilicon layer, such that the N-type doped source layers and the P-type doped source layers are distributed alternately. An N-type doped polycrystalline silicon layer is formed by low-temperature annealing of the N-type doped source layer. A P-type doped polycrystalline silicon layer is formed by laser patterning annealing of the P-type doped source layer. Cleaning removes oxides formed during the annealing process; Passivation and antireflection layers are fabricated on the front and back sides of a silicon substrate; Electrodes are fabricated on passivation antireflection layers corresponding to N-type doped polycrystalline silicon layers and P-type doped polycrystalline silicon layers.

2. The method for preparing a solar cell according to claim 1, characterized in that: "Forming patterned N-type doped source layers and P-type doped source layers on the intrinsic polysilicon layer" specifically means forming patterned N-type doped source layers and P-type doped source layers on the intrinsic polysilicon layer by printing or inkjet printing.

3. The method for preparing a solar cell according to claim 1, characterized in that: When performing low-temperature annealing on the N-type doped source layer, the peak annealing temperature is 800–950℃, and the annealing time is 1–3 hours.

4. The method for preparing a solar cell according to claim 1, characterized in that: When using laser to perform patterned annealing on the P-type doped source layer, the laser power is 30–150 W, the laser speed is 20–60 m / s, the laser frequency is 10–1000 kHz, and the laser pulse width is either continuous laser or nanosecond laser.

5. The method for preparing a solar cell according to claim 1, characterized in that: The width of the intrinsic polysilicon layer located between the N-type doped polysilicon layer and the P-type doped polysilicon layer is 30–100 μm.

6. The method for preparing a solar cell according to claim 1, characterized in that: The thickness of the tunneling layer is 1 nm to 3 nm.

7. The method for preparing a solar cell according to claim 1, characterized in that: The thickness of the intrinsic polycrystalline silicon layer is 80 nm to 500 nm.

8. The method for preparing a solar cell according to claim 1, characterized in that: The "surface treatment of silicon substrate" specifically includes the following steps: first, the silicon substrate is subjected to double-sided alkaline texturing, and then the back side of the silicon substrate is polished.

9. The method for preparing a solar cell according to claim 1, characterized in that: The passivation and antireflection layer is at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

10. A solar cell, characterized in that: The solar cell is prepared by the preparation method described in any one of claims 1-9.

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