Air gap forming method for isolating metal interconnection wires
By forming air gaps through wafer bonding, the problem of high etching requirements in traditional processes is solved, and the uniformity and integrity of air gaps are achieved, simplifying the process flow.
Patent Information
- Application Number
- CN202511759668.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-02-17
AI Technical Summary
In the existing technology, the air gap formation process has high requirements for the trench etching process, making it difficult to form air gaps with good uniformity and integrity. Furthermore, it requires subsequent chemical vapor deposition processes to clamp and seal, which affects the isolation effect between the wires.
The wafer bonding process is used to bond the etched trench wafer to the dielectric layer of another wafer. High-temperature annealing is used to seal the trenches and form an air gap, which reduces the requirements for the etching process and eliminates the need for subsequent CVD sealing.
It improves the spatial size, uniformity, and integrity of air gaps, reduces dependence on etching processes, and simplifies the process flow.
Smart Images
Figure CN121548293A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor manufacturing technology, and more specifically to a method for forming an air gap in a semiconductor device for isolating metal interconnect wires. Background Technology
[0002] With the development of integrated circuit technology, device size is constantly shrinking, and the integration density of device units per unit area is becoming increasingly higher. This leads to smaller and smaller spacing between wires, and the coupling capacitance between wires becomes significant. All of these factors increase the RC delay between interconnect layers, i.e., increase the useless power consumption in the circuit, hindering further improvement in the performance of integrated circuit devices. Since the equivalent capacitance C in the RC delay is proportional to the dielectric constant k of the medium between the wires, reducing the dielectric constant k of the interconnect medium can reduce the equivalent capacitance, thereby reducing the RC delay effect and improving the performance of integrated circuit devices.
[0003] Air-gap technology is a process for obtaining low-k interconnect dielectric layers. It involves sealing an air bubble between two conductors to replace the original solid dielectric material, making the corresponding k value as close as possible to 1 (i.e., the lowest limit of the k value), thereby greatly reducing the dielectric constant of the interconnect dielectric layer.
[0004] Traditional air-gap formation processes involve etching trenches between conductive lines to create the desired air gap, followed by chemical vapor deposition (CVD), a process with poor step coverage but rapid lateral growth, to quickly clamp and seal the gaps, thus retaining the air within. Since the step coverage of typical CVD processes heavily depends on the trench morphology, this places extremely high demands on dry etching processes, requiring them to create trenches with smooth sidewalls and perpendicular to the substrate. When the trench sidewalls are completely perpendicular to the substrate, the reactant arrival angle affects their accumulation at the trench opening, hindering subsequent reactant entry into the trench and achieving rapid clamping and sealing. However, in reality, the sidewalls of trenches created by etching processes (especially near the trench opening) often exhibit a certain angle (e.g., ...). Figure 1 As shown), the opening at the top of the sloping trench is relatively larger than that at the bottom. Compared to trenches with completely vertical sidewalls, reactants have a higher chance of entering the trench and reacting to form a film, causing the bottom of the trench to be filled with dielectric material. Even if the step coverage of the CVD process is adjusted to extremely poor, the bottom of the trench will still be partially filled with dielectric material (e.g., Figure 2As shown in the figure, the cross-sectional area of the air gap is reduced, the shape of the air gap is irregular, and the uniformity of the air gap is difficult to control, thus reducing the isolation effect accordingly. Furthermore, the sidewall at the groove opening is at a certain angle, which makes it impossible for the CVD process to quickly clamp and form a seal at the groove opening. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a method for forming air gaps for isolating metal interconnect wires, which reduces the requirements for trench etching process, can seal the trench to form air gaps without the need for subsequent chemical vapor deposition process to cut off, and can maximize the spatial size, uniformity and integrity of air gaps.
[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming an air gap for isolating metal interconnect wires, comprising the following steps: S1. Provide a wafer 1 with a metal interconnect structure formed thereon, on the front side there are metal interconnect wires 12 and a first dielectric layer 11, the metal interconnect wires 12 are formed in the first dielectric layer 11, and the first dielectric layer 11 between adjacent metal interconnect wires 12 is etched to form trenches 13; A patternless silicon wafer 2 is provided, on the front side of which a second dielectric layer 21 for bonding is deposited; S2. The first dielectric layer 11 of the wafer 1 with the metal interconnect structure and the second dielectric layer 21 of the patternless silicon wafer 2 are bonded together face to face, and high-temperature annealing is performed to bond the wafer 1 with the metal interconnect structure and the patternless silicon wafer 2 together. The second dielectric layer 21 of the patternless silicon wafer 2 seals the upper end of the trench 13 in the first dielectric layer 11 between the adjacent metal interconnect wires 12 of the wafer 1 with the metal interconnect structure to form an air gap.
[0007] Preferably, step S3 is performed after step S2, in which the silicon substrate 20 on the back side of the patternless silicon wafer 2 is removed by a thinning process, leaving only the second dielectric layer 21.
[0008] Preferably, step S4 is performed after step S3, where subsequent metal interconnect structure processes are carried out on the second dielectric layer 21 of the retained patternless silicon wafer 2.
[0009] Preferably, steps S1 to S4 are repeated until the fabrication of all metal interconnect structures at the back end of the semiconductor device is completed.
[0010] Preferably, in step S2, the high-temperature annealing temperature is 200–400°C.
[0011] Preferably, in step S1, the front side of the first dielectric layer 11 and the metal interconnect wire 12 of the wafer 1 with the metal interconnect structure already formed has been polished by a chemical mechanical polishing process.
[0012] Preferably, in step S1, the front side of the second dielectric layer 21 of the patternless silicon wafer 2 is surface polished by a chemical mechanical polishing process.
[0013] Preferably, in step S1, the dielectric constant of the first dielectric layer of the wafer with the metal interconnect structure formed is not higher than 3.9; The dielectric constant of the second dielectric layer 21 of the patternless silicon wafer is not higher than 3.9.
[0014] Preferably, in step S1, the first dielectric layer of the wafer with the metal interconnect structure already formed is silicon dioxide; The second dielectric layer 21 of the patternless silicon wafer is silicon dioxide.
[0015] Preferably, the thickness of the second dielectric layer 21 of the patternless silicon wafer 2 is greater than the depth of the trench 13.
[0016] Preferably, the thickness of the second dielectric layer 21 of the patternless silicon wafer 2 is 1.1 to 2 times the depth of the trench 13.
[0017] The present invention provides a method for forming an air gap for isolating metal interconnect wires. By using a wafer bonding process, a wafer with trenches 13 pre-etched in the dielectric layer surrounding the metal interconnect layer is bonded to another wafer with a dielectric layer formed thereon. The originally open trenches 13 are then sealed by the dielectric layer of the other wafer, thereby forming a complete air gap isolation structure. This reduces the requirements for the trench 13 etching process, eliminates the need for subsequent chemical vapor deposition (CVD) processes to clamp the trenches 13 and form an air gap, and maximizes the spatial size, uniformity, and integrity of the air gap. Attached Figure Description
[0018] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of the inclination angle of the grooves formed by etching; Figure 2 This is a schematic diagram of the air gap structure formed by traditional CVD process; Figure 3 This is a schematic cross-sectional view of a wafer with a pre-formed metal interconnect structure, according to an embodiment of the method for forming an air gap for isolating metal interconnect wires of the present invention. Figure 4This is a schematic cross-sectional view of a patternless silicon wafer according to an embodiment of the method for forming an air gap for isolating metal interconnect wires of the present invention. Figure 5 This is a cross-sectional schematic diagram of a method for forming an air gap for isolating metal interconnect wires according to an embodiment of the present invention, showing the first dielectric layer and the second dielectric layer bonded together face to face; Figure 6 This is a cross-sectional schematic diagram of a method for forming an air gap for isolating metal interconnect wires according to an embodiment of the present invention, after removing the silicon substrate on the back side of a patternless silicon wafer; Figure 7 This is a cross-sectional schematic diagram of a method for forming an air gap for isolating metal interconnect wires according to an embodiment of the present invention, showing the subsequent metal interconnect structure process.
[0020] Explanation of reference numerals in the attached figures: 1. Wafer with formed metal interconnect structure; 11. First dielectric layer; 12. Metal interconnect wire; 13. Trench; 2. Unpatterned silicon wafer; 20. Silicon substrate; 21. Second dielectric layer. Detailed Implementation
[0021] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Example
[0022] A method for forming an air gap for isolating metal interconnect wires includes the following steps: S1. A wafer 1 with a pre-formed metal interconnect structure is provided, on the front side of which metal interconnect wires 12 and a first dielectric layer 11 are formed. The metal interconnect wires 12 are formed in the first dielectric layer 11, and trenches 13 are formed between adjacent metal interconnect wires 12 in the first dielectric layer 11. Figure 3 As shown; groove 13 is used to form an air gap; Provides a patternless silicon wafer 2, on the front side of which a second dielectric layer 21 for bonding is deposited, such as Figure 4 As shown; S2. The first dielectric layer 11 of the wafer 1 with the formed metal interconnect structure and the second dielectric layer 21 of the patternless silicon wafer 2 are bonded together face to face, and high-temperature annealing is performed to bond the wafer 1 with the formed metal interconnect structure and the patternless silicon wafer 2 together; the second dielectric layer 21 of the patternless silicon wafer 2 closes the upper end of the trench 13 in the first dielectric layer 11 between adjacent metal interconnect wires 12 of the wafer 1 with the formed metal interconnect structure to form an air gap, such as Figure 5 As shown.
[0023] The air gap formation method for isolating metal interconnect wires in Embodiment 1 utilizes a wafer bonding process. By combining a wafer with trenches 13 pre-etched in the dielectric layer surrounding the metal interconnect layer with another wafer having a dielectric layer formed, the originally open trenches 13 are sealed by the dielectric layer of the other wafer, thereby forming a complete air gap isolation structure. This reduces the requirements for the trench 13 etching process, eliminates the need for subsequent chemical vapor deposition (CVD) processes to clamp the trenches 13 and form air gaps, and maximizes the spatial size, uniformity, and integrity of the air gaps. Example
[0024] Based on the air gap formation method for isolating metal interconnect wires in Embodiment 1, after step S2, step S3 is performed whereby the silicon substrate 20 on the back side of the patternless silicon wafer 2 is removed by a thinning process, leaving only the second dielectric layer 21. Figure 6 As shown.
[0025] Preferably, step S4 is performed after step S3, where subsequent metal interconnect structure processes are carried out on the second dielectric layer 21 of the retained unpatterned silicon wafer 2, such as... Figure 7 As shown.
[0026] Preferably, steps S1 to S4 are repeated until the fabrication of all metal interconnect structures at the back end of the semiconductor device is completed. Example
[0027] Based on the air gap formation method for isolating metal interconnect wires in Embodiment 1, in step S2, the high temperature of high-temperature annealing is 200-400°C to achieve sufficiently high bonding strength.
[0028] Preferably, in step S1, the front side of the first dielectric layer 11 and the metal interconnect wire 12 of the wafer 1 with the metal interconnect structure already formed has been polished by a chemical mechanical polishing process.
[0029] Preferably, in step S1, the front side of the second dielectric layer 21 of the patternless silicon wafer 2 is surface polished by a chemical mechanical polishing process.
[0030] Preferably, in step S1, the dielectric constant of the first dielectric layer of the wafer with the metal interconnect structure formed is not higher than 3.9; The dielectric constant of the second dielectric layer 21 of the patternless silicon wafer is not higher than 3.9.
[0031] Preferably, in step S1, the first dielectric layer of the wafer with the metal interconnect structure already formed is silicon dioxide; The second dielectric layer 21 of the patternless silicon wafer is silicon dioxide.
[0032] Preferably, the thickness of the second dielectric layer 21 of the patternless silicon wafer 2 is greater than the depth of the trench 13.
[0033] Preferably, the thickness of the second dielectric layer 21 of the patternless silicon wafer 2 is 1.1 to 2 times the depth of the trench 13.
[0034] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. An air gap forming method for isolating metal interconnection lines, characterized by, The method comprises the following steps: S1. providing a wafer (1) with formed metal interconnection structure, the front surface of which is formed with metal interconnection wires (12) and a first dielectric layer (11), the metal interconnection wires (12) being formed in the first dielectric layer (11), and etching the first dielectric layer (11) between adjacent metal interconnection wires (12) to form a groove (13); providing a non-patterned silicon wafer (2) with a second dielectric layer 21 deposited on the front surface thereof for bonding; S2. bonding the first dielectric layer (11) of the wafer (1) with formed metal interconnection structure and the second dielectric layer 21 of the non-patterned silicon wafer (2) face to face together, and performing high-temperature annealing to bond the wafer (1) with formed metal interconnection structure and the non-patterned silicon wafer (2) together, the second dielectric layer 21 of the non-patterned silicon wafer (2) closing the upper end of the groove (13) in the first dielectric layer (11) between adjacent metal interconnection wires (12) of the wafer (1) with formed metal interconnection structure to form an air gap.
2. The method according to claim 1, wherein, after step S2, step S3 is performed to remove the silicon substrate (20) on the back surface of the non-patterned silicon wafer (2) by thinning process, and only the second dielectric layer 21 is reserved.
3. The method according to claim 2, wherein, after step S3, step S4 is performed to perform subsequent metal interconnection structure process on the second dielectric layer 21 of the reserved non-patterned silicon wafer (2).
4. The method according to claim 3, wherein, steps S1 to S4 are repeatedly performed until the preparation of all metal interconnection structures of the semiconductor device is completed.
5. The method according to claim 1, wherein, in step S2, the high-temperature annealing is performed at a high-temperature temperature of 200-400 ℃.
6. The method according to claim 1, wherein, in step S1, the front surface of the first dielectric layer (11) and the metal interconnection wires (12) of the wafer (1) with formed metal interconnection structure has been polished by a chemical mechanical polishing process.
7. The method according to claim 1, wherein, in step S1, the front surface of the second dielectric layer 21 of the non-patterned silicon wafer (2) is polished by a chemical mechanical polishing process.
8. The method according to claim 1, wherein, in step S1, the dielectric constant of the first dielectric layer of the wafer with formed metal interconnection structure is not higher than 3.9; and the dielectric constant of the second dielectric layer 21 of the non-patterned silicon wafer is not higher than 3.
9.
9. The method according to claim 8, wherein, in step S1, the first dielectric layer of the wafer with formed metal interconnection structure is silicon dioxide. The second dielectric layer 21 of the non-patterned silicon wafer is silicon dioxide.
10. The method for forming an air gap for isolating metal interconnection lines according to claim 1, wherein The thickness of the second dielectric layer 21 of the non-patterned silicon wafer (2) is greater than the depth of the trench (13).
11. The method for forming an air gap for isolating metal interconnection lines according to claim 1, wherein The thickness of the second dielectric layer 21 of the non-patterned silicon wafer (2) is 1.1 to 2 times the depth of the trench (13).