Application of low thermal resistance high power patch chip packaging process and equipment

Abstract

The application provides a low-thermal-resistance high-power patch chip packaging process and device, and belongs to the technical field of chip packaging. The method comprises the following steps: performing plasma surface activation treatment on a chip substrate in a vacuum environment, and constructing an intelligent pretreatment system; configuring a composite heat-conducting material, and controlling material ratio and coating thickness; adopting a multi-stage temperature and pressure curve to complete chip mounting, and forming an initial packaging structure; implementing a gradient temperature rising process in a reflow soldering furnace, monitoring temperature distribution in real time through an infrared thermal imager, and dynamically adjusting heating parameters by using a neural network algorithm; and performing three-dimensional scanning detection on the welded chip, and obtaining a low-thermal-resistance high-power patch chip finished product. Through full-process quality closed-loop control, the application greatly improves the bonding force of the chip and the substrate, the heat dissipation efficiency and the packaging precision, reduces the labor cost, avoids high-temperature damage of the chip, and adapts to the demand of high-end electronic equipment.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically to the process and equipment for low thermal resistance high-power surface mount chip packaging. Background Technology

[0002] With the rapid development of new energy vehicles, 5G communications, industrial control and other fields, stringent requirements have been placed on the power density and thermal management capabilities of chips. Low thermal resistance high-power surface-mount chips have become core components of high-end electronic devices due to their high energy conversion efficiency, but their packaging process faces many technical bottlenecks.

[0003] In traditional packaging processes, insufficient activation of the substrate surface leads to weak adhesion between the chip and the substrate, resulting in chip detachment and failure. Poor compatibility of thermally conductive materials and excessively high thermal resistance fail to meet the heat dissipation requirements of high-power chips. Low precision in pressure and temperature control during mounting easily leads to defects such as solder voids and chip misalignment. Uneven heat distribution during reflow soldering causes stress concentration within the chip, affecting its lifespan. Furthermore, existing processes lack end-to-end quality control, and poor correlation between testing data and process parameters results in low product yield and insufficient consistency, making it difficult to meet the high reliability and stability requirements of high-end electronic devices. Therefore, there is an urgent need to develop a high-precision, intelligent, low-thermal-resistance, high-power chip packaging process and equipment. Summary of the Invention

[0004] This invention provides a process and equipment for low thermal resistance, high-power surface mount chip packaging, in order to overcome the deficiencies in the prior art.

[0005] On one hand, the present invention provides a low thermal resistance, high-power surface-mount chip packaging process, comprising:

[0006] S1: Perform plasma surface activation treatment on the chip substrate in a vacuum environment, and monitor the surface roughness in real time through optical sensors to build an intelligent pretreatment system.

[0007] S2: Under the control of an intelligent pretreatment system, nano-silver paste-graphene composite thermal conductive material is configured, and a multi-stage feeding system is used to control the material ratio and coating thickness.

[0008] S3: The chip is transferred to the substrate pads by a positioning robot, and the chip is mounted using a multi-stage temperature and pressure curve to form the initial package structure.

[0009] S4: Based on the initial packaging structure, a gradient heating process is implemented in the reflow oven. The temperature distribution is monitored in real time using an infrared thermal imager, and the heating parameters are dynamically adjusted using a neural network algorithm.

[0010] S5: Perform 3D scanning inspection on the soldered chips, select qualified products as the benchmark samples for the next batch, form a closed-loop quality control, and use vapor phase cleaning to treat residual flux.

[0011] S6: The cleaned chip is fed into a microwave-vacuum combined curing equipment, where it is cured at low temperature and protected by inert gas to obtain a low thermal resistance, high-power surface mount chip product.

[0012] According to the low thermal resistance high-power surface mount chip packaging process provided by the present invention, the specific steps for constructing the intelligent preprocessing system in step S1 are as follows:

[0013] S11: Radio frequency plasma generators and optical detection probes are symmetrically arranged in a vacuum chamber.

[0014] S12: Connect the signal output terminal of the optical detection probe to the data acquisition card, load the physical model based on material surface energy optimization, and calibrate the delay parameters of the signal transmission path.

[0015] S13: By simulating the activation effect on the surface of substrates with different materials, the adaptability of the plasma parameter adjustment logic is verified.

[0016] S14: Establish a matching table of processing time and power parameters based on the verification results.

[0017] S15: Integrates temperature and humidity environmental monitoring modules to form a complete intelligent preprocessing system, realizing multi-parameter collaborative control.

[0018] According to the low thermal resistance high-power surface mount chip packaging process provided by the present invention, the specific steps for configuring the composite thermally conductive material in step S2 are as follows:

[0019] S21: Based on the chip power density and heat dissipation requirements, the mass fraction ratio of nano-silver paste to graphene is determined through thermal simulation calculations.

[0020] S22: The material is uniformly mixed under the protection of inert gas by using a dual-frequency ultrasonic dispersion process.

[0021] S23: Real-time monitoring of material viscosity changes using a rotational rheometer.

[0022] S24: Use a screw dispensing system for patterned coating to control the deviation of glue line width.

[0023] S25: Verify the consistency of coating thickness using a laser confocal thickness gauge to control thickness tolerance.

[0024] According to the low thermal resistance high-power surface mount chip packaging process provided by the present invention, the specific steps for determining the mass fraction ratio in step S21 are as follows:

[0025] S211: Calculate the thermal resistance value under different ratios based on the finite element analysis of thermal conduction, and determine the optimal ratio range.

[0026] S212: Verify the uniformity of material dispersion using scanning electron microscopy.

[0027] S213: The thermal stability of the material is tested using modulated differential scanning calorimetry at a preset heating rate.

[0028] According to the low thermal resistance high-power surface mount chip packaging process provided by the present invention, the specific steps for forming the initial package structure in step S3 are as follows:

[0029] S31: Locate the chip and pad positions using a machine vision system.

[0030] S32: Adaptive control algorithm based on pressure feedback is used to adjust the mounting pressure in real time.

[0031] S33: Real-time monitoring of mounting accuracy via a laser triangulation sensor at a preset sampling frequency.

[0032] S34: Completely record the three-dimensional process curves of pressure-temperature-time and establish a process parameter database.

[0033] According to the low thermal resistance high-power surface mount chip packaging process provided by the present invention, the specific steps for implementing adaptive pressure control in step S32 are as follows:

[0034] S321: Real-time pressure data is acquired at a preset frequency using distributed piezoelectric pressure sensors.

[0035] S322: Automatically calculates ideal pressure values ​​based on 3D point cloud data of chip thickness and pad height.

[0036] S323: Employs a fuzzy PID controller to dynamically adjust the output torque of the servo motor.

[0037] S324: Record the pressure fluctuation curve and analyze the frequency domain characteristics through Fourier transform to optimize control parameters.

[0038] According to the low thermal resistance high-power surface mount chip packaging process provided by the present invention, the specific steps for dynamically adjusting the heating parameters in step S4 are as follows:

[0039] S41: Collects thermal field distribution data of the entire reflow oven through multi-zone temperature sensors.

[0040] S42: Input the temperature distribution map into the pre-trained convolutional neural network model to obtain thermal field optimization suggestions.

[0041] S43: Adjust the power output of each heating zone based on the thermal field optimization recommendation value.

[0042] S44: Update the temperature curve in real time and correct the model weight parameters through the backpropagation algorithm.

[0043] S45: Generate a quality report that includes thermal field uniformity indicators and store the optimal parameter combination.

[0044] According to the present invention, in the low thermal resistance high-power surface mount chip packaging process, the specific steps for obtaining the thermal field optimization suggestion value in step S42 are as follows:

[0045] S421: Extract the feature vector of the temperature distribution map and perform principal component analysis for dimensionality reduction. Obtain the spatial distribution feature vector of the temperature gradient through a feature extraction network.

[0046] S422: An improved Euclidean distance algorithm is used to match the current temperature distribution with the historical best process database. The similarity score between the current temperature distribution and the standard template is calculated. A similarity threshold exceeding a preset threshold is considered a valid match.

[0047] S423: Optimize network weight parameters using a genetic algorithm.

[0048] S424: Outputs suggested values ​​for thermal field optimization for each heating zone. These suggested values ​​include power adjustment recommendations and confidence level assessments.

[0049] According to the low thermal resistance high-power surface mount chip packaging process provided by the present invention, the specific steps for performing three-dimensional scanning detection in step S5 are as follows:

[0050] S51: A white light interferometer is used to perform three-dimensional topographic scanning, collect surface height data, and generate a three-dimensional topological map.

[0051] S52: Detect the internal weld void rate, obtain tomographic images, and identify welding defects through image segmentation algorithms.

[0052] S53: Use a multispectral automatic optical inspection system to identify surface defects, and use the YOLOv5 deep learning target detection algorithm model for defect classification and identification.

[0053] S54: Establish a traceability database containing process parameters and quality indicators, design a relational database table structure, and realize data association analysis.

[0054] On the other hand, the present invention also provides an application in a low thermal resistance, high-power surface-mount chip packaging device, comprising:

[0055] The pretreatment module includes a substrate pretreatment unit and a composite material pre-preparation unit. The substrate pretreatment unit is used to activate the substrate surface before chip packaging; the composite material pre-preparation unit is used to formulate the nanocomposite thermal conductive material and control the coating thickness.

[0056] The chip packaging module includes a positioning and mounting unit and a thermal control unit. The positioning and mounting unit is used to align and mount the chip to the substrate to form an initial package structure; the thermal control unit performs thermal control of the packaging process.

[0057] The quality inspection and analysis module is used for quality inspection and data analysis of the initial packaging structure;

[0058] The intelligent central control module is used to establish real-time data exchange via industrial Ethernet and output control commands.

[0059] This invention provides a process and equipment for low thermal resistance, high-power surface-mount chip packaging. By employing vacuum plasma surface activation and a multi-parameter collaborative control system, it significantly enhances the surface activity of the substrate, ensuring a strong bond between the chip and the substrate, improving adhesion, and effectively reducing the risk of detachment and failure. Through customized formulation of nano-silver paste-graphene composite thermally conductive material, combined with dual-frequency ultrasonic dispersion and precise coating technology, the thermal resistance is controlled at 1.5℃·cm. 2 Within a range of / W, heat dissipation efficiency is improved compared to traditional materials, ensuring long-term stable operation of high-power chips. Through placement technology based on machine vision and fuzzy PID control, combined with reflow soldering thermal field control optimized by neural networks, placement positioning accuracy is improved, soldering void rate is reduced, and packaging accuracy and soldering quality are significantly enhanced. By constructing a full-process quality traceability and closed-loop control system, real-time linkage between inspection data and process parameters is achieved, improving product yield while reducing manual intervention costs. Low-temperature curing and inert gas protection processes prevent high-temperature damage to chips, extending product lifespan and adapting to diverse high-end electronic device applications. Attached Figure Description

[0060] The invention will now be further described with reference to the accompanying drawings.

[0061] Figure 1 This is a schematic diagram of the process applied to the low thermal resistance high power surface mount chip packaging technology in this invention;

[0062] Figure 2 This is a schematic diagram of the structure of the low thermal resistance high power surface mount chip packaging equipment of the present invention. Detailed Implementation

[0063] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0064] like Figures 1 to 2 As shown, the embodiments of the present invention provide a process and equipment for packaging low thermal resistance high-power surface mount chips. The executing entity can be an entity used in the packaging process for low thermal resistance high-power surface mount chips, and the method includes:

[0065] S1: Plasma surface activation treatment is performed on the chip substrate in a vacuum environment. Surface roughness is monitored in real time using optical sensors. An intelligent pretreatment system is constructed. The specific steps are as follows:

[0066] S11: A radio frequency plasma generator and a high-resolution optical detection probe are symmetrically arranged within a vacuum chamber, and the vacuum level of the vacuum chamber is strictly controlled at 1×10⁻⁶. -4 Pa to 5×10 -4 A distance of Pa is maintained between the substrate surface and the surrounding environment to completely isolate the substrate from the influence of air and moisture. The frequency of the radio frequency plasma generator is set to 13.56 MHz, which can effectively excite plasma without damaging the substrate material. The high-resolution optical detection probe has a pixel accuracy of 0.1 μm, ensuring accurate capture of microscopic morphological changes on the substrate surface.

[0067] S12: Connect the signal output terminal of the optical detection probe to the data acquisition card, load the physical model based on material surface energy optimization, and calibrate the delay parameters of the signal transmission path. Set the sampling frequency of the data acquisition card to 1kHz to ensure real-time acquisition of surface roughness data fed back by the probe. The physical model based on material surface energy optimization comprehensively considers factors such as the chemical composition and surface tension of the substrate material. This model can establish a direct correlation between roughness data and surface activation effect. The delay parameter calibration of the signal transmission path adopts the standard signal source comparison method to control the delay error within ±1μs.

[0068] S13: By simulating the activation effect on the surface of substrates with different materials, the adaptability of the plasma parameter adjustment logic is verified. The simulated substrate materials include common chip packaging substrates such as ceramic substrates, FR-4 epoxy resin substrates, and aluminum-based copper-clad laminates. Three batches of samples from different materials are selected for testing. The plasma parameter adjustment logic covers the power adjustment range (50W-300W) and the processing time adjustment range (30s-300s). By comparing the surface activation effect of each substrate material under different parameter combinations, it is verified whether the adjustment logic can meet the processing requirements of diverse materials.

[0069] S14: Based on the verification results, establish a matching table for processing time and power parameters. The table should be categorized by substrate material, specifying the optimal processing time and power parameter combinations for different surface roughness target values ​​(e.g., Ra≤0.2μm, Ra≤0.3μm, etc.). For example, when a ceramic substrate needs to achieve a roughness target of Ra≤0.2μm, the corresponding processing time is 120s and the power is 180W. The applicable environmental humidity range (40%-60%RH) and temperature range (20℃-25℃) for each parameter combination should also be indicated.

[0070] S15: Integrates temperature and humidity monitoring modules to form a complete intelligent pretreatment system, achieving multi-parameter coordinated control. The temperature monitoring module has a measurement accuracy of ±0.1℃, and the humidity monitoring module has a measurement accuracy of ±2%RH. The detection data from both modules are fed back to the system controller in real time. The system controller adopts a PLC programmable logic controller. When the ambient temperature or humidity exceeds the preset range, it automatically adjusts the plasma parameters or pauses the processing flow. For example, when the ambient humidity is higher than 60%RH, it automatically extends the processing time by 10%-20% to ensure that the activation effect is not affected by environmental factors, truly realizing coordinated closed-loop control of multiple parameters such as processing time, power, temperature, and humidity.

[0071] S2: Under the control of an intelligent pretreatment system, nano-silver paste-graphene composite thermal conductive material is prepared, and a multi-stage feeding system is used to control the material ratio and coating thickness. The specific steps for preparing the composite thermal conductive material are as follows:

[0072] S21: Based on the chip power density and heat dissipation requirements, the mass fraction ratio of nano-silver paste to graphene is determined through thermal simulation calculations. The specific steps are as follows:

[0073] S211: Based on the finite element analysis of thermal conduction, the thermal resistance values ​​under different ratios were calculated to determine the optimal ratio range. The ANSYS Icepak thermal simulation software was used for the finite element analysis of thermal conduction. The mesh generation accuracy of the simulation model was 0.01 mm, and the boundary conditions were set to the actual power density of the chip during operation (10 W / cm²). 2 -50W / cm 2 The thermal resistance was determined to be ≤1.5℃·cm by calculating the thermal resistance values ​​of different combinations of nano-silver paste mass fraction (60%-90%) and graphene mass fraction (10%-40%). 2 The / W ratio range is the optimal ratio range, and the thermal conductivity of the material within this range can meet the heat dissipation requirements of low thermal resistance high-power chips.

[0074] S212: The uniformity of material dispersion was verified using scanning electron microscopy (SEM). The SEM magnification was set to 5000x-20000x. Composite thermally conductive material samples with different proportions were selected, and 10 observation points were randomly selected on the sample surface for imaging. The dispersed particle size of graphene in the nano-silver paste was calculated using image analysis software. The dispersed particle size was required to be ≤5μm, and the number of graphene agglomerates in a single observation point should not exceed 3. This was used as the criterion for judging the uniformity of material dispersion.

[0075] S213: Modulated differential scanning calorimetry (MSC) is used to test the thermal stability of the material at a preset heating rate of 5℃ / min. The test temperature range is 25℃-300℃, which covers the common temperature range in chip packaging and subsequent use. Key parameters such as the glass transition temperature and thermal decomposition temperature of the material are obtained through testing. The thermal decomposition temperature of the material must be ≥250℃, and the glass transition temperature ≥120℃ to ensure that the material's performance does not degrade due to temperature changes during chip operation.

[0076] S22: A dual-frequency ultrasonic dispersion process is employed to ensure uniform mixing of materials under inert gas protection. This process utilizes a 20kHz low-frequency ultrasonic wave and an 80kHz high-frequency ultrasonic wave working synergistically. The low-frequency ultrasonic wave breaks up large agglomerates, while the high-frequency ultrasonic wave refines small agglomerates. The ultrasonic power density is 30W / L, and the dispersion time is 30-60 minutes, adjusted according to the material ratio. Higher graphene content requires a longer dispersion time. Nitrogen gas with a purity ≥99.999% is used as the inert gas. Continuous nitrogen purging keeps the oxygen concentration in the mixing vessel below 100ppm to prevent oxidation of the nano-silver paste and graphene.

[0077] S23: Real-time monitoring of material viscosity changes using a rotational rheometer. The rotational rheometer's test temperature is set to 25℃, and the shear rate range is 1s. -1 -100s -1 Viscosity data was recorded every 1 minute during the test. The target viscosity range for the composite thermally conductive material is 5000 mPa·s-20000 mPa·s. When the viscosity exceeds this range, the system automatically adjusts the ultrasonic dispersion time or replenishes the raw material. For example, when the viscosity is higher than 20000 mPa·s, the ultrasonic dispersion time is extended by 5-10 minutes to ensure that the material viscosity meets the requirements of the subsequent coating process.

[0078] S24: A high-precision screw dispensing system is used for patterned coating to control the glue line width deviation. The screw precision of the high-precision screw dispensing system is 0.001mm, and the dispensing pressure adjustment range is 0.1MPa-0.5MPa. The appropriate dispensing needle is selected according to the different coating patterns, with an inner diameter range of 0.1mm-0.5mm. The glue line width for patterned coating is determined based on the chip size and pad layout, generally 0.2mm-1.0mm. The movement speed of the dispensing system is controlled by a servo motor (5mm / s-20mm / s) to strictly control the glue line width deviation within ±0.02mm.

[0079] S25: Verify coating thickness consistency and control thickness tolerance using a laser confocal thickness gauge. The laser confocal thickness gauge has a measurement accuracy of ±0.1μm and a measurement point spacing of 0.5mm, performing full-coverage measurements on each coating area. The coating thickness is set to 10μm-50μm based on chip power and packaging requirements, with thickness tolerance controlled within ±1μm. For areas with thickness exceeding the tolerance (deviation exceeding ±1μm) detected during measurement, the system automatically marks them and feeds them back to the dispensing system. The dispensing parameters for that area are adjusted for recoating or scraping to ensure thickness consistency across the entire coating surface.

[0080] S3: The chip is transferred to the substrate pads using a positioning robot, and chip mounting is completed using a multi-stage temperature and pressure profile to form the initial package structure. The specific steps are as follows:

[0081] S31: The machine vision system locates the chip and pad positions. This system consists of two high-resolution CCD cameras, each with 5 megapixels and a 30fps shooting frame rate, equipped with telecentric lenses to ensure measurement accuracy. Image recognition algorithms extract edge features of the chip pins and substrate pads, achieving a positioning accuracy of ±0.5μm. A reference point calibration method is used during positioning, with three preset reference points on the substrate surface. Positioning errors are corrected by comparing the positions of these reference points captured by the camera with the preset coordinates.

[0082] S32: The mounting pressure is adjusted in real time using an adaptive control algorithm based on pressure feedback. The specific steps are as follows:

[0083] S321: Real-time pressure data is acquired via distributed piezoelectric pressure sensors at a preset frequency. Eight distributed piezoelectric pressure sensors are evenly distributed below the placement head. Each sensor has a measurement range of 0N-50N and a measurement accuracy of ±0.01N. The preset acquisition frequency is 100Hz, enabling real-time capture of dynamic pressure changes during placement, providing continuous data stream support for subsequent pressure adjustments.

[0084] S322: Automatically calculates the ideal pressure value based on 3D point cloud data of chip thickness and pad height. It acquires 3D point cloud data of chip thickness and pad height using a laser rangefinder. The laser rangefinder has a measurement accuracy of ±0.1μm, and the point cloud data sampling density is 100 points / mm. 2 The ideal pressure value calculation model comprehensively considers the elastic modulus of the chip material (silicon, silicon carbide, etc.), the pad material (copper, gold, etc.), as well as the chip thickness deviation (±5μm) and the pad height deviation (±3μm). For example, when a silicon chip (elastic modulus 170GPa) is combined with a copper pad (elastic modulus 110GPa), and the chip thickness is 200μm and the pad height is 50μm, the ideal pressure value is calculated to be 8N.

[0085] S323: Employs a fuzzy PID controller to dynamically adjust the servo motor's output torque. The inputs to the fuzzy PID controller are the deviation (e) between the actual and ideal pressure values ​​and the rate of change of that deviation (ec). The output is the torque adjustment amount for the servo motor. The controller's fuzzy rule base contains 25 fuzzy rules, each corresponding to a different PID parameter adjustment strategy based on different ranges of e and ec. For example, when e > 1N and ec > 0.5N / s, the proportional coefficient Kp is increased, while the integral coefficient Ki and derivative coefficient Kd are decreased to quickly reduce the pressure deviation. The servo motor's torque adjustment accuracy is ±0.001N·m, ensuring the smoothness and precision of pressure adjustment.

[0086] S324: Record the pressure fluctuation curve and analyze the frequency domain characteristics through Fourier transform to optimize the control parameters. The recording time of the pressure fluctuation curve is the entire mounting process (generally 2s-5s), and the sampling interval is 10μs. The multi-stage process includes a pre-positioning stage, a main bonding stage, a stabilization and pressure holding stage, and a pressure release and release stage. In the pre-positioning stage, the chip moves above the pads, the temperature is maintained between room temperature and 60°C, and the pressure is controlled between 0.1MPa and 0.2MPa to avoid scratching the pads; this stage lasts 0.5s to 1s. In the main bonding stage, the temperature rises to between 60°C and 100°C to activate the initial tack of the composite thermally conductive material, and the pressure rises to between 0.3MPa and 0.6MPa to ensure tight bonding between the chip and the substrate; this stage lasts 1s to 2s. In the stabilization and pressure holding stage, the temperature is maintained between 100°C and 120°C, and the pressure is stabilized at between 0.4MPa and 0.5MPa to eliminate bonding gaps; this stage lasts 0.5s to 1s. In the pressure release and release stage, the temperature drops to between room temperature and 80°C, and the pressure is gradually reduced to below 0.1MPa to prevent chip displacement due to excessively rapid pressure release; this stage lasts 0.5s to 1s.

[0087] The pressure fluctuation signal in the time domain is converted into a frequency domain signal by Fourier transform. The main frequency components of the pressure fluctuation are analyzed. If there is a large fluctuation at a specific frequency (fluctuation amplitude exceeds 0.5N), the relevant parameters of the fuzzy PID controller (such as proportional coefficient, integral time, etc.) are adjusted to suppress the fluctuation at that frequency, so that the pressure fluctuation amplitude is controlled within ±0.1N, and the stability of the mounting pressure is further optimized.

[0088] S33: The system monitors the placement accuracy in real time using a laser triangulation sensor at a preset sampling frequency. The laser triangulation sensor has a measurement range of 0mm-50mm, a measurement accuracy of ±0.1μm, and a preset sampling frequency of 500Hz, enabling real-time monitoring of height changes during chip placement. Evaluation indicators for placement accuracy include the parallelism between the chip and the substrate (≤0.5μm / m) and the offset between the chip center and the pad center (≤1μm). When the placement accuracy exceeds the allowable range, the system automatically pauses the placement process, adjusts the positioning or pressure parameters, and then re-places the chip.

[0089] S34: Completely record the three-dimensional process curves of pressure, temperature, and time, and establish a process parameter database. The recording accuracy of pressure data is ±0.01N, the recording accuracy of temperature data (placement ambient temperature) is ±0.1℃, and the recording accuracy of time data is ±1ms. The process parameter database adopts a MySQL database management system. The database table structure includes fields such as chip model, substrate model, placement date, pressure curve data, temperature curve data, and placement accuracy test results. Each record corresponds to a complete placement process, which facilitates subsequent process optimization and quality traceability.

[0090] S4: Based on the initial packaging structure, a gradient heating process is implemented in the reflow oven. The temperature distribution is monitored in real time using an infrared thermal imager, and the heating parameters are dynamically adjusted using a neural network algorithm. The specific steps are as follows:

[0091] S41: The thermal distribution data of the entire reflow oven is collected using multi-zone temperature sensors. The oven is evenly divided into 20 temperature monitoring zones, each equipped with a high-precision platinum resistance temperature sensor. The sensor's measurement range is 0℃-300℃, with a measurement accuracy of ±0.2℃. The data acquisition frequency is 10Hz, covering the entire gradient heating process cycle (typically 8-12 minutes), ensuring comprehensive capture of the dynamic changes in the oven's thermal field. Temperature data from each zone is transmitted to the control system in real time, forming a complete thermal distribution dataset.

[0092] S42: Input the temperature distribution map into the pre-trained convolutional neural network model to obtain thermal field optimization suggestions. The specific steps are as follows:

[0093] S421: The feature vector of the temperature distribution map is extracted and dimensionality reduction is performed using principal component analysis. Image noise is removed using a Gaussian filter algorithm, and the Sobel edge detection operator is used to identify thermal field boundary features. The spatial distribution feature vector of the temperature gradient is obtained through a feature extraction network. The standard deviation of the Gaussian filter algorithm is set to 1.5, and the filter window size is 3×3, which effectively removes random noise in the temperature distribution map while retaining the main distribution features of the thermal field. The horizontal and vertical convolution kernels of the Sobel edge detection operator are [-1,0,1; -2,0,2; -1,0,1] and [-1,-2,-1; 0,0,0; 1,2,1], respectively. This operator can accurately identify the boundary regions of temperature abrupt changes in the thermal field. The feature extraction network adopts a structure of 3 convolutional layers and 2 pooling layers. The convolutional kernel size of the convolutional layers is 3×3, and the pooling layers use max pooling with a pooling window size of 2×2. The final extracted spatial distribution feature vector of the temperature gradient has a dimension of 128.

[0094] S422: An improved Euclidean distance algorithm is used to match the current temperature distribution with a historical optimal process database. The similarity score between the current temperature distribution and the standard template is calculated. A similarity threshold exceeding a preset threshold is considered a valid match. The matching results are then weighted and averaged. The improved Euclidean distance algorithm introduces a temperature weight coefficient on top of the traditional Euclidean distance calculation, assigning higher weight (1.5) to temperature differences in key thermal areas (such as the chip center and pad connection areas), while non-key areas have a weight coefficient of 1.0. The historical optimal process database contains over 1000 optimal thermal distribution templates corresponding to different chip models and packaging structures. The similarity score ranges from 0 to 100, with a preset similarity threshold of 85. A score ≥ 85 is considered a valid match. A weighted average is applied to the thermal parameters corresponding to multiple validly matched templates, with templates showing higher matching scores having higher weights (weight = similarity score / sum of similarity scores for all validly matched templates).

[0095] S423: This section optimizes network weight parameters using an improved genetic algorithm. The population size is initialized, and a roulette wheel selection strategy is employed. Crossover probability, mutation probability, and the number of iterations are set. The improved genetic algorithm introduces an adaptive crossover and mutation probability mechanism based on the traditional genetic algorithm. The crossover probability is dynamically adjusted according to the population fitness variance, ranging from 0.6 to 0.9, and the mutation probability ranges from 0.01 to 0.05. The initial population size is set to 50, and each individual in the population corresponds to a set of network weight parameters. In the roulette wheel selection strategy, the selection probability of an individual is proportional to its fitness value. The fitness value is calculated using the thermal field uniformity error (the sum of squared temperature deviations between the actual and ideal thermal fields); the smaller the error, the higher the fitness value. The number of iterations is set to 100. When the fitness value no longer significantly improves after 50 iterations (improvement ≤ 0.1%), the iteration can be terminated early, and the optimal network weight parameters are output.

[0096] S424: Outputs suggested values ​​for thermal field optimization in each heating zone. These values ​​include power adjustment suggestions and confidence level assessments. The suggested values ​​are normalized to generate a three-dimensional control command matrix containing adjustment range, direction, and duration. The power adjustment suggestion range is -20% to +20% of the current heating power. The confidence level assessment is calculated based on the matching similarity score and the fitness value from the genetic algorithm optimization results, with a confidence level range of 0-100%. Suggestions with a confidence level ≥90% are directly adopted; those with 80%-90% require judgment based on human experience; and those <80% are recalculated for optimization. The normalization process converts parameters such as power adjustment suggestions and adjustment duration into normalized values ​​of 0-1, facilitating identification and execution by the control system. The rows of the three-dimensional control command matrix represent the heating area (20 rows), and the columns represent the adjustment range (after normalization), adjustment direction (up / down), and adjustment duration (s). For example, the control command for the 5th heating area is [0.15, up, 30], which means that the power of this area needs to be increased by 15% and the adjustment duration is 30s.

[0097] S43: Based on the thermal field optimization recommendations, the power output of each heating zone is adjusted. Each heating zone of the reflow oven is equipped with an independent power adjustment module with a power adjustment accuracy of ±1%. The power output of each heating zone is adjusted in real time according to the adjustment amplitude and direction in the three-dimensional control command matrix. The adjustment process adopts a smooth adjustment method, and the power change rate is controlled within 5% / s to avoid drastic fluctuations in the thermal field caused by sudden power changes, which could affect the chip soldering quality.

[0098] S44: The temperature curve is updated in real time, and the model weight parameters are corrected using a backpropagation algorithm. The update frequency of the temperature curve is consistent with the temperature data acquisition frequency. After each update, the deviation between the actual temperature curve and the ideal temperature curve is calculated. The backpropagation algorithm uses the gradient descent method with a learning rate set to 0.001. The correction amount of the model weight parameters is calculated based on the temperature deviation, and the weight parameters are gradually adjusted to make the thermal field optimization suggestions output by the model increasingly accurate. The corrected weight parameters are stored in the model parameter library in real time, realizing the online self-learning and optimization of the model.

[0099] S45: Generate a quality report containing thermal uniformity indicators and store the optimal parameter combination. Thermal uniformity is measured using two parameters: maximum temperature difference and temperature standard deviation. The maximum temperature difference must be ≤5℃, and the temperature standard deviation ≤1.5℃. The quality report also includes power adjustment records for each heating zone, temperature change curves, and confidence level assessment results. The optimal parameter combination is the power parameter combination that achieves the best thermal uniformity in this process, and is stored in the historical best process database along with the corresponding chip model, package structure, and process time information.

[0100] S5: Perform 3D scanning inspection on the soldered chips, select qualified products as benchmark samples for the next batch, forming a closed-loop quality control system. Residual flux is treated using vapor phase cleaning. The specific steps for 3D scanning inspection are as follows:

[0101] S51: A white light interferometer is used for 3D topographic scanning. Instrument calibration is performed, and a standard template is used for benchmark correction. The scanning step size is set to 1 μm, and the scanning range is a 10 mm × 10 mm area. Surface height data is collected, and a 3D topological map is generated. The measurement accuracy of the white light interferometer is ±0.01 μm. Instrument calibration uses the standard interference fringe calibration method to ensure the accuracy of the measurement data. The surface roughness of the standard template is Ra = 0.1 μm, and the flatness is ≤0.2 μm. Benchmark correction is completed by comparing the results of the instrument scanning of the standard template with the actual parameters of the template. During the scanning process, the light source intensity of the white light interferometer is automatically adjusted to adapt to chip surfaces with different reflectivities. The collected surface height data is stored in point cloud form with a point cloud density of 1 point / μm. 2 The generated 3D topology map can clearly show the protrusions, depressions and other morphological defects on the chip surface. The defect judgment criteria are that the protrusion height ≥2μm or the depression depth ≥2μm is judged as unqualified.

[0102] S52: Internal weld void rate was detected using a microfocus X-ray inspection system at 80kV. The tube current was set to 100μA, and the exposure time to 200ms. A fan-beam scanning method was used to acquire tomographic images. Welding defects were identified using an image segmentation algorithm. The microfocus X-ray inspection system has a focal size of 5μm, which can clearly penetrate the chip packaging structure to observe the internal welding conditions. The fan-beam scanning angle range was 0°-180°, the scanning step was 0.5°, and the acquired tomographic image resolution was 1μm / pixel. The image segmentation algorithm combined threshold segmentation and edge detection. First, the segmentation threshold for void areas was determined using the maximum inter-class variance method. Then, the Canny edge detection operator was used to extract void boundaries. The void rate was calculated as the ratio of the void area to the total weld area, requiring a weld void rate ≤3% and a single void area ≤0.01mm. 2 Otherwise, it is judged as a welding defect.

[0103] S53: A multispectral automated optical inspection system is used to identify surface defects. Five LED light sources of different wavelengths (365nm, 450nm, 520nm, 630nm, and 850nm) are configured. The YOLOv5 deep learning target detection algorithm is used for defect classification and identification. The 365nm ultraviolet light source is used to detect organic contaminant defects on the chip surface; the 450nm blue light source is used to detect surface scratches; the 520nm green light source is used to detect surface dents; the 630nm red light source is used to detect surface protrusions; and the 850nm infrared light source is used to detect surface cracks. The multispectral automated optical inspection system has a 12-megapixel camera with a frame rate of 20fps. Each wavelength light source is captured individually, resulting in five images of the chip surface under different spectra. The YOLOv5 model was trained with 10,000 defect sample images, achieving a defect detection accuracy of ≥99%. Defect classification includes scratches (length ≥0.5mm, width ≥0.01mm) and dents (depth ≥1μm, area ≥0.01mm). 2 ), protrusions (height ≥ 1 μm, area ≥ 0.01 mm²) 2 Cracks (length ≥ 0.3 mm, width ≥ 0.005 mm), contaminants (area ≥ 0.02 mm²) 2 These technologies, such as [missing information], can quickly and accurately identify and classify surface defects.

[0104] S54: Establish a traceability database containing process parameters and quality indicators. Design a relational database table structure, including a process parameter table, a test result table, and a quality rating table. Implement data association analysis through SQL queries. The process parameter table includes fields such as: process number, chip model, substrate model, process parameters for each process (e.g., plasma treatment parameters, mounting pressure parameters, reflow soldering temperature parameters, etc.), and process time. The test result table includes fields such as: test number, process number, 3D morphology test results (surface roughness, defect type, and parameters), internal soldering test results (void rate, defect location, and size), and surface defect test results (defect type, quantity, location, and parameters). The quality rating table includes fields such as: rating number, test number, overall quality level (A, B, C, and D levels; A level indicates no defects, B level indicates minor defects that do not affect use, C level indicates moderate defects requiring rework, and D level indicates severe defects and is considered unqualified), and the basis for the rating criteria. SQL queries can be used to correlate process parameters with test results and quality ratings for the same process number. For example, you can query the process parameter combinations for all Grade A products corresponding to a certain chip model, providing data support for process optimization.

[0105] S55: Real-time feedback of inspection results to the upstream process parameter adjustment system. A real-time communication interface based on the TCP / IP protocol is established, with a data update frequency of 1Hz. This enables closed-loop linkage control between inspection data and process parameters. The feedback content includes quality rating, specific parameters of various defects, and analysis of their causes (based on database correlation analysis results). The TCP / IP protocol communication baud rate is set to 10Mbps to ensure real-time and stable data transmission. The 1Hz data update frequency ensures that the upstream process receives inspection feedback promptly. The closed-loop linkage control logic is as follows: When a C-grade or D-grade product is detected, the system automatically analyzes the relevant process parameters that caused the defect. For example, if the defect is an excessive weld void rate, the gradient heating parameters of the reflow oven are adjusted (e.g., extending the holding time by 5%-10% and increasing the peak temperature by 2℃-5℃). The adjusted parameters are then applied to the production of the next batch of products. Simultaneously, the changes in product quality before and after parameter adjustment are recorded, continuously optimizing the process parameters.

[0106] S6: The cleaned chip is input into a microwave-vacuum combined curing equipment. Low-temperature curing combined with inert gas protection yields a low-thermal-resistance, high-power surface-mount chip. The vapor phase cleaning uses trichloroethylene as the cleaning medium, with the cleaning temperature controlled at 60℃-80℃ and the cleaning time at 15-20 minutes. Vapor phase cleaning thoroughly removes residual flux from the chip surface, and the residual contaminant content on the chip surface after cleaning is ≤10μg / cm³. 2 The vacuum level of the microwave-vacuum combined curing equipment is controlled at 1×10⁻⁶. -3 Pa-5×10 -3The microwave frequency is 2.45 GHz, the microwave power is 500 W-1000 W, the low-temperature curing temperature is set to 120℃-150℃, and the curing time is 60 min-90 min. Argon gas with a purity ≥99.999% is used as the inert gas and is continuously introduced to purge air from the equipment and prevent chip oxidation during curing. The chip temperature is monitored in real time by a temperature sensor during curing to ensure it remains stable within the set range. After curing, the chip is allowed to cool naturally to room temperature (20℃-25℃). The resulting chip must have a thermal resistance ≤1.5℃·cm. 2 Performance indicators include / W, welding strength ≥5N, and surface roughness Ra≤0.3μm.

[0107] In summary, this embodiment provides a low thermal resistance, high-power surface-mount chip packaging process. By employing vacuum plasma surface activation and a multi-parameter collaborative control system, the surface activity of the substrate is significantly improved, ensuring a strong bond between the chip and the substrate, enhancing adhesion, and effectively reducing the risk of detachment failure. Through customized formulation of nano-silver paste-graphene composite thermally conductive material, combined with dual-frequency ultrasonic dispersion and precise coating technology, the thermal resistance is controlled at 1.5℃·cm. 2 Within a range of / W, heat dissipation efficiency is improved compared to traditional materials, ensuring long-term stable operation of high-power chips. Through placement technology based on machine vision and fuzzy PID control, combined with reflow soldering thermal field control optimized by neural networks, placement positioning accuracy is improved, soldering void rate is reduced, and packaging accuracy and soldering quality are significantly enhanced. By constructing a full-process quality traceability and closed-loop control system, real-time linkage between inspection data and process parameters is achieved, improving product yield while reducing manual intervention costs. Low-temperature curing and inert gas protection processes prevent high-temperature damage to chips, extending product lifespan and adapting to diverse high-end electronic device applications.

[0108] Based on the same general inventive concept, this invention also protects applications in low thermal resistance high-power surface mount chip packaging equipment. The following describes the low thermal resistance high-power surface mount chip packaging equipment provided by this invention. The low thermal resistance high-power surface mount chip packaging equipment described below can be referred to in correspondence with the low thermal resistance high-power surface mount chip packaging process and equipment described above.

[0109] Applications in low thermal resistance, high-power surface mount chip packaging equipment include:

[0110] The pretreatment module includes a substrate pretreatment unit and a composite material pre-preparation unit. The substrate pretreatment unit is used to activate the substrate surface before chip packaging. The composite material pre-preparation unit is used to formulate the nanocomposite thermal conductive material and control the coating thickness.

[0111] The substrate pretreatment unit includes:

[0112] Vacuum chambers are used to provide an oxygen-free and dust-free clean processing environment to prevent oxidation and contamination of the substrate surface.

[0113] Radio frequency plasma generators are used to generate high-frequency plasmas to achieve chemical modification and cleaning activation of substrate surfaces.

[0114] A high-resolution optical inspection probe is used to monitor the surface roughness and cleanliness of the substrate in real time, providing feedback data for adjusting process parameters.

[0115] The substrate fixing platform is used to accurately position and fix the substrate to be processed, ensuring uniform processing.

[0116] A three-dimensional robotic arm is used to achieve precise positioning and scanning motion of optical detection probes in space.

[0117] The composite material pre-preparation unit includes:

[0118] Nanomaterial mixing vessel, used to contain and mix thermally conductive material raw materials of different components.

[0119] An ultrasonic dispersion device is used to achieve uniform dispersion of nanoparticles using ultrasonic energy, preventing agglomeration.

[0120] The rheometer monitoring unit is used to monitor changes in material viscosity in real time to ensure the stability of the coating process.

[0121] Temperature control jackets are used to precisely control the mixing temperature and ensure consistent material properties.

[0122] High-speed mixers are used to achieve rapid and uniform mixing of materials.

[0123] The chip packaging module includes a positioning and mounting unit and a thermal control unit. The positioning and mounting unit is used to align and mount the chip to the substrate to form an initial package structure; the thermal control unit performs thermal control of the packaging process.

[0124] The positioning and mounting unit includes:

[0125] A six-degree-of-freedom precision positioning robot is used to achieve precise movement and positioning of chips in three-dimensional space.

[0126] An adaptive pressure control system is used to automatically adjust the mounting pressure according to the chip size and thickness.

[0127] A dual-CCD vision positioning system is used to simultaneously capture the positions of the chip and the substrate, achieving sub-micron level alignment accuracy.

[0128] A piezoelectric sensor array is used to monitor the pressure distribution during the mounting process in real time.

[0129] The thermal control unit includes:

[0130] Multi-zone reflow ovens are used to provide a precise and controllable temperature environment to achieve the melting and solidification of welding materials.

[0131] Infrared thermal imagers are used for non-contact measurement of the temperature distribution across the entire surface of a substrate.

[0132] A neural network controller is used to intelligently adjust the heating power of each temperature zone based on temperature data.

[0133] A PID temperature controller is used to achieve precise temperature control for each temperature zone.

[0134] The quality inspection and analysis module is used to perform quality inspection and data analysis on the initial packaging structure, including:

[0135] White light interferometric 3D scanner is used for high-precision measurement of the morphological features of packaged structures.

[0136] Microfocus X-ray inspection instrument is used for the inspection of internal welding quality and defects.

[0137] Multispectral optical inspection systems are used to identify surface defects and contaminants at different wavelengths.

[0138] The intelligent central control module is used to establish real-time data exchange via industrial Ethernet and output control commands, including:

[0139] Industrial-grade computers are used to run control algorithms and data processing programs.

[0140] High-speed data acquisition card, used to acquire monitoring data from various sensors in real time.

[0141] Multi-axis motion control card, used to precisely control the motion trajectory of each actuator.

[0142] A real-time operating system is used to ensure the response speed and stability of the control system.

[0143] The output of the substrate pretreatment unit is connected to the input station of the composite material pre-preparation unit through a conveying mechanism. The output of the composite material pre-preparation unit is transferred to the working area of ​​the positioning and mounting unit by a robot. After the positioning and mounting unit completes the mounting, it enters the thermal control unit through a conveyor line. After the thermal control unit completes the processing, it enters the quality inspection and analysis module for final inspection. The intelligent central control module establishes real-time data exchange and control command transmission with each module through industrial Ethernet.

[0144] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging process for low thermal resistance, high-power surface-mount chips, characterized in that, include: S1: Perform plasma surface activation treatment on the chip substrate in a vacuum environment, monitor the surface roughness in real time through optical sensors, and build an intelligent pretreatment system; S2: Under the control of the intelligent pretreatment system, nano-silver paste-graphene composite thermal conductive material is configured, and a multi-stage feeding system is used to control the material ratio and coating thickness. S3: The chip is transferred to the substrate pads by a positioning robot, and the chip is mounted using a multi-stage temperature and pressure profile to form the initial package structure; S4: Based on the initial packaging structure, a gradient heating process is implemented in the reflow oven. The temperature distribution is monitored in real time using an infrared thermal imager, and the heating parameters are dynamically adjusted using a neural network algorithm. The specific steps are as follows: S41: Collects thermal field distribution data of the entire reflow oven through multi-zone temperature sensors; S42: Input the temperature distribution map into the pre-trained convolutional neural network model to obtain thermal field optimization suggestions; S43: Adjust the power output of each heating zone based on the aforementioned thermal field optimization recommendation value; S44: Update the temperature curve in real time and correct the model weight parameters through the backpropagation algorithm; S45: Generate a quality report containing thermal field uniformity indicators and store the optimal parameter combination; S5: Perform 3D scanning inspection on the completed soldered chips, select qualified products as the benchmark samples for the next batch, form a closed-loop quality control, and use vapor phase cleaning to treat residual flux. S6: The cleaned chip is fed into a microwave-vacuum combined curing equipment, where it is cured at low temperature and protected by inert gas to obtain a low thermal resistance, high-power surface mount chip product.

2. The low thermal resistance, high power surface mount chip packaging process according to claim 1, characterized in that, In step S1, the specific steps for constructing the intelligent preprocessing system are as follows: S11: Radio frequency plasma generators and optical detection probes are symmetrically arranged in a vacuum chamber; S12: Connect the signal output terminal of the optical detection probe to the data acquisition card, load the physical model based on material surface energy optimization, and calibrate the delay parameters of the signal transmission path; S13: By simulating the activation effect on the surface of substrates with different materials, the adaptability of the plasma parameter adjustment logic is verified; S14: Establish a matching table of processing time and power parameters based on the verification results; S15: Integrates temperature and humidity environmental monitoring modules to form a complete intelligent preprocessing system, realizing multi-parameter collaborative control.

3. The low thermal resistance, high power surface mount chip packaging process according to claim 1, characterized in that, In step S2, the specific steps for configuring the composite thermally conductive material are as follows: S21: Based on the chip power density and heat dissipation requirements, the mass fraction ratio of nano-silver paste to graphene is determined through thermal simulation calculations; S22: The material is uniformly mixed under the protection of inert gas by using a dual-frequency ultrasonic dispersion process; S23: Real-time monitoring of material viscosity changes using a rotational rheometer; S24: Use a screw dispensing system for patterned coating to control the deviation of glue line width; S25: Verify the consistency of coating thickness using a laser confocal thickness gauge to control thickness tolerance.

4. The low thermal resistance, high power surface mount chip packaging process according to claim 3, characterized in that, In step S21, the specific steps for determining the mass fraction ratio are as follows: S211: Calculate the thermal resistance values ​​under different proportions based on the finite element analysis of thermal conduction, and determine the optimal proportion range; S212: Verify the uniformity of material dispersion using scanning electron microscopy; S213: The thermal stability of the material is tested using modulated differential scanning calorimetry at a preset heating rate.

5. The low thermal resistance, high power surface mount chip packaging process according to claim 1, characterized in that, In step S3, the specific steps for forming the initial packaging structure are as follows: S31: Locate the chip and pad positions using a machine vision system; S32: Employs an adaptive control algorithm based on pressure feedback to adjust the mounting pressure in real time; S33: Real-time monitoring of mounting accuracy via a laser triangulation sensor at a preset sampling frequency; S34: Completely record the three-dimensional process curves of pressure-temperature-time and establish a process parameter database.

6. The low thermal resistance, high power surface-mount chip packaging process according to claim 5, characterized in that, In step S32, the specific steps for implementing adaptive pressure control are as follows: S321: Real-time pressure data is acquired at a preset frequency using distributed piezoelectric pressure sensors; S322: Automatically calculates ideal pressure values ​​based on 3D point cloud data of chip thickness and pad height; S323: Employs a fuzzy PID controller to dynamically adjust the output torque of the servo motor; S324: Record the pressure fluctuation curve and analyze the frequency domain characteristics through Fourier transform to optimize control parameters.

7. The low thermal resistance, high power surface mount chip packaging process according to claim 1, characterized in that, In step S42, the specific steps for obtaining the thermal field optimization recommendation value are as follows: S421: Extract the feature vector of the temperature distribution map and perform principal component analysis for dimensionality reduction. Obtain the spatial distribution feature vector of the temperature gradient through a feature extraction network. S422: An improved Euclidean distance algorithm is used to match the current temperature distribution with the historical best process database. The similarity score between the current temperature distribution and the standard template is calculated. A similarity threshold exceeding the preset threshold is considered a valid match. S423: Optimize network weight parameters using a genetic algorithm; S424: Output thermal field optimization suggestions for each heating zone, including power adjustment suggestions and confidence level assessments.

8. The low thermal resistance, high power surface mount chip packaging process according to claim 1, characterized in that, In step S5, the specific steps for performing three-dimensional scanning detection are as follows: S51: A white light interferometer is used to perform three-dimensional topography scanning, collect surface height data, and generate a three-dimensional topology map; S52: Detect the internal weld void rate, acquire tomographic images, and identify welding defects through image segmentation algorithms; S53: Use a multispectral automatic optical inspection system to identify surface defects, and use the YOLOv5 deep learning target detection algorithm model for defect classification and identification; S54: Establish a traceability database containing process parameters and quality indicators, design a relational database table structure, and realize data association analysis.

9. A packaging equipment for low thermal resistance high-power surface mount chips, implementing the low thermal resistance high-power surface mount chip packaging process as described in any one of claims 1 to 8, characterized in that, include: The pretreatment module includes a substrate pretreatment unit and a composite material pre-preparation unit. The substrate pretreatment unit is used to activate the substrate surface before chip packaging. The composite material pre-preparation unit is used to formulate the nanocomposite thermally conductive material and control the coating thickness. The chip packaging module includes a positioning and mounting unit and a thermal control unit. The positioning and mounting unit is used to align and mount the chip to the substrate to form an initial packaging structure. The thermal control unit performs thermal control of the packaging process. The quality inspection and analysis module is used to perform quality inspection and data analysis on the initial packaging structure. The intelligent central control module is used to establish real-time data exchange via industrial Ethernet and output control commands.

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