Bit segmentation for processing high bit depth images

Abstract

The present disclosure provides systems, methods, and devices for image signal processing that support high dynamic range (HDR) image processing. In a first aspect, an image processing method includes receiving, by a processor, first image data including a plurality of image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, where the plurality of image frames represent a same scene; and determining a processed image frame having an output bit width higher than the first bit width and higher than the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width. Other aspects and features are also claimed and described.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Patent Application No. 18 / 360,577, filed July 27, 2023, entitled “BIT SPLITTING TO PROCESS HIGHBIT DEPTH IMAGES”, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates generally to image processing, and more specifically to processing image data with higher bit widths using image processing designed for lower bit widths. Several features enable and provide improved image processing, including improving image quality by processing high dynamic range (HDR) images. Background Technology

[0003] An image capture device is a device capable of capturing one or more digital images (whether still images for photographs or sequences of images for video). Capture devices can be integrated into a variety of devices. For example, an image capture device may include a standalone digital camera or digital video camera, a wireless communication device with a camera (such as a mobile phone, cellular, or satellite radio phone), a personal digital assistant (PDA), a panel or tablet device, a gaming device, a computing device (such as a webcam or video surveillance camera), or other devices with digital imaging or video capabilities.

[0004] The amount of image data captured by image sensors has increased with subsequent generations of image capture devices. The amount of information captured by an image sensor is related to the number of pixels in the image sensor of the image capture device, which can be measured as the number of megapixels, indicating the number of millions of sensors in the image sensor. For example, a 12-megapixel image sensor has 12 million pixels. Higher megapixel values ​​generally indicate higher resolution images that are more suitable for user viewing.

[0005] The increased amount of image data captured by an image capture device can have some negative effects as the resolution of the additional image data increases. The additional image data increases the amount of processing the image capture device performs when determining image frames and video from the image data, and performing other operations related to the image data. For example, the image data may be processed through several processing blocks to enhance the image before it is displayed to a user or sent to a recipient in a message. Each processing block consumes additional power proportional to the amount of image data captured or the number of megapixels. This additional power consumption can reduce the operating time of battery-powered image capture devices, such as mobile phones. Summary of the Invention

[0006] The following summary outlines some aspects of this disclosure to provide a basic understanding of the techniques discussed. This summary is not an exhaustive overview of all the intended features of this disclosure, nor is it intended to identify key or essential elements of all aspects of this disclosure, nor to define the scope of any or all aspects of this disclosure. The sole purpose of this summary is to present, in a general form, some concepts of one or more aspects of this disclosure as a prelude to the more detailed description that follows.

[0007] In some aspects, image processing may include techniques for processing higher bit-width images using lower bit-width logic. These techniques may include compressively expanding data by changing the bit width, such that multiple lower bit-width image frames can represent a single higher bit-width image frame. The techniques may also include decompressively expanding the data to create a higher bit-width original representation from multiple lower bit-width image frames. This disclosure provides techniques for improving image quality by supporting processing of higher bit-width image data obtainable from image sensors with in-sensor high dynamic range (HDR) capabilities. Higher bit-width data can be used to support higher-quality photographs and videos with a wider color gamut, thereby more accurately representing scenes. A wider color gamut allows for more accurate representation of scenes, particularly scenes with significant brightness differences between dark and bright areas.

[0008] In one aspect of this disclosure, a method for image processing includes: receiving by a processor first image data comprising a plurality of image frames, the plurality of image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the plurality of image frames represent the same scene; and determining a processed image frame having an output bit width greater than the first bit width and greater than the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0009] In an additional aspect of this disclosure, an apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to perform operations including: receiving first image data comprising a plurality of image frames, the plurality of image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the plurality of image frames represent the same scene; and determining processed image frames having an output bit width greater than the first bit width and greater than the second bit width, the processed image frames being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0010] In an additional aspect of this disclosure, an apparatus includes: means for receiving by a processor first image data comprising a plurality of image frames, the plurality of image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the plurality of image frames represent the same scene; and means for determining a processed image frame having an output bit width greater than the first bit width and greater than the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0011] In an additional aspect of this disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform operations. The operations include: receiving by the processor first image data comprising a plurality of image frames, the plurality of image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the plurality of image frames represent the same scene; and determining a processed image frame having an output bit width greater than both the first bit width and the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0012] In another aspect of this disclosure, an image capture device may include: an image sensor configured to output a single exposure of a scene as a first image frame having a first bit width and a second image frame having a second bit width, wherein the first bit width and the second bit width are each lower than the sensor bit width captured by the image sensor; a memory storing processor-readable code; and at least one processor coupled to the memory and the image sensor, the at least one processor being configured to execute the processor-readable code to cause the at least one processor to perform an operation including: receiving first image data comprising a plurality of image frames, the plurality of image frames including the first image frame and the second image frame; and determining a processed image frame having an output bit width higher than the first bit width and higher than the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0013] The image processing methods described herein can be performed by an image capture device and / or on image data captured by one or more image capture devices. An image capture device (a device capable of capturing one or more digital images, whether still photographs or video sequences) can be incorporated into a variety of devices. By way of example, an image capture device may include a standalone digital camera or digital video camera, a wireless communication device equipped with a camera (such as a mobile phone, cellular, or satellite radiophone), a personal digital assistant (PDA), a panel or tablet device, a gaming device, a computing device (such as a webcam, video surveillance camera), or other devices with digital imaging or video capabilities.

[0014] The image processing techniques described herein may relate to a digital camera having an image sensor and processing circuitry (e.g., an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), or a central processing unit (CPU)). An image signal processor (ISP) may include one or more of these processing circuits and is configured to perform operations to acquire image data for processing according to the image processing techniques described herein and / or those involved in the image processing techniques described herein. An ISP may be configured to control the capture of image frames from one or more image sensors and to determine one or more image frames from said one or more image sensors to generate a view of a scene in an output image frame. The output image frame may be part of a sequence of image frames forming a video sequence. The video sequence may include additional image frames received from the image sensor or other image sensors.

[0015] In an example application, an image signal processor (ISP) may receive instructions for capturing a sequence of image frames in response to the loading of software, such as a camera application, to generate a preview display from an image capture device. The ISP may be configured to generate a single output image frame stream based on image frames received from one or more image sensors. The single output image frame stream may include raw image data from the image sensors, merged image data from the image sensors, or corrected image data processed by one or more algorithms within the ISP. For example, image frames may be processed by an image post-processing engine (IPE) and / or other image processing circuitry to process the image frames obtained from the image sensors (which may have undergone some processing before being output to the ISP), thereby performing one or more of tone mapping, portrait lighting, contrast enhancement, gamma correction, etc. The output image frames from the ISP may be stored in memory and retrieved by an application processor executing the camera application, which may perform further processing on the output image frames to adjust their appearance and reproduce them on a display for user viewing.

[0016] After an image signal processor and / or application processor (such as the image processing techniques described in the various embodiments herein) determines an output image frame representing a scene, the output image frame may be displayed on a device display as a single still image and / or as part of a video sequence, saved to a storage device as a picture or video sequence, transmitted over a network, and / or printed to an output medium. For example, an image signal processor (ISP) may be configured to acquire input frames of image data (e.g., pixel values) from one or more image sensors and subsequently generate corresponding output image frames (e.g., preview display frames, still image captures, frames for video, frames for object tracking, etc.). In other examples, the image signal processor may output image frames to various output devices and / or camera modules for further processing, such as for 3A parameter synchronization (e.g., autofocus (AF), auto white balance (AWB), and auto exposure control (AEC)), to generate video files via the output frames, to configure frames for display, to configure frames for storage, to transmit frames via a network connection, etc. Generally, an image signal processor (ISP) can obtain incoming frames from one or more image sensors, generate an output frame stream, and output the output frame stream to various output destinations.

[0017] In some aspects, output image frames can be generated by combining various aspects of the image correction disclosed herein with other computational photography techniques such as high dynamic range (HDR) photography or multi-frame noise reduction (MFNR). In the case of HDR photography, the first and second image frames are captured using different exposure times, different apertures, different lenses, and / or other characteristics that can result in improved dynamic range of the fused image when combining the two image frames. In some aspects, the method can be performed for MFNR photography, wherein the first and second image frames are captured using the same or different exposure times, and the first and second image frames are fused to generate a corrected first image frame that has reduced noise compared to the captured first image frame.

[0018] In some aspects, the device may include an image signal processor or a processor (e.g., an application processor) that includes specific functionalities for camera control and / or processing, such as enabling or disabling the merging module or otherwise controlling aspects of image correction. The methods and techniques described herein may be performed entirely by an image signal processor or a processor, or the various operations may be separated between an image signal processor and a processor, and in some aspects across additional processors.

[0019] The device may include one, two, or more image sensors, such as a first image sensor. When multiple image sensors are present, their configurations may differ. For example, the first image sensor may have a larger field of view (FOV) than the second image sensor, or the first image sensor may have a different sensitivity or a different dynamic range than the second image sensor. In one example, the first image sensor may be a wide-angle image sensor, and the second image sensor may be a telephoto image sensor. In another example, the first sensor is configured to acquire an image through a first lens having a first optical axis, and the second sensor is configured to acquire an image through a second lens having a second optical axis different from the first optical axis. Additionally or alternatively, the first lens may have a first magnification, and the second lens may have a second magnification different from the first magnification. Any of these or other configurations may be part of a lens cluster on a mobile device, such as where multiple image sensors and associated lenses are located at offset positions on the front or rear of the mobile device. Additional image sensors with larger, smaller, or the same field of view may be included. The image processing techniques described herein can be applied to image frames captured from any of the image sensors in a multi-sensor device.

[0020] In an additional aspect of this disclosure, an apparatus configured for image processing and / or image capture is disclosed. The apparatus includes components for capturing image frames. The apparatus also includes one or more components for capturing data representing a scene, such as image sensors (including charge-coupled device (CCD), Bayer filter sensors, infrared (IR) detectors, ultraviolet (UV) detectors, complementary metal-oxide-semiconductor (CMOS) sensors) and time-of-flight detectors. The apparatus may further include components for focusing and / or directing light onto one or more image sensors (including simple lenses, compound lenses, spherical lenses, and aspherical lenses). These components can be controlled to capture a first image frame and / or a second image frame input to the image processing techniques described herein.

[0021] Other aspects, features, and specific embodiments will become apparent to those skilled in the art upon reviewing the following description of particular exemplary aspects in conjunction with the accompanying drawings. Although features may be discussed hereinafter with reference to certain aspects and drawings, various aspects may include one or more of the advantageous features discussed herein. In other words, while one or more aspects may be discussed as having certain advantageous features, one or more of such features may also be used depending on the various aspects. Similarly, although exemplary aspects may be discussed hereinafter as aspects of an apparatus, system, or method, exemplary aspects may be implemented in various apparatuses, systems, and methods.

[0022] This method can be embedded as computer program code in a computer-readable medium, the computer program code including instructions to cause a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including: a first network adapter configured to transmit data, such as recorded images or videos or streaming data, via a first network connection among a plurality of network connections; and a processor coupled to the first network adapter and memory. The processor enables the output image frames described herein to be transmitted via a wireless communication network, such as a 5G NR communication network.

[0023] The features and technical advantages of the examples according to this disclosure have been summarized rather extensively above in order to better understand the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily used as the basis for modifying or designing other structures for achieving the same purpose of this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein (both their organization and manner of operation) and their associated advantages will be better understood from the following description when considered in conjunction with the accompanying drawings. Each figure in the drawings is provided for illustrative and descriptive purposes and not as a definition of limitation of the claims.

[0024] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, aspects and / or devices may be implemented via integrated chip implementations and other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically point to a use case or application, broad applicability of the described innovations is possible. The scope of implementations ranges from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily involve multiple components (e.g., hardware components, including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.) for analog and digital purposes. The innovations described herein are intended to be implemented in a variety of devices, chip-level components, systems, distributed arrangements, end-user equipment, etc., with different sizes, shapes, and constructions. Attached Figure Description

[0025] A further understanding of the nature and advantages of this disclosure can be achieved by referring to the following figures. In the figures, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numerals and a second reference numeral for differentiation between similar components. If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, regardless of the second reference numerals.

[0026] Figure 1 A block diagram of an example device for performing image capture from one or more image sensors is shown.

[0027] Figure 2 This is a block diagram illustrating an example data flow path for image data processing in an image capture device according to one or more embodiments of the present disclosure.

[0028] Figure 3A This is a block diagram illustrating, according to some embodiments of the present disclosure, the compression and expansion of image data for representation in two image frames.

[0029] Figure 3B This is a block diagram illustrating, according to some embodiments of the present disclosure, the compression and expansion of 14-bit image data into two image frames with 12-bit data.

[0030] Figure 3C This is a block diagram illustrating, according to some embodiments of the present disclosure, the compression and expansion of 18-bit image data into three image frames with 12-bit data.

[0031] Figure 4 This is a block diagram illustrating some embodiments of the present disclosure of decompressing and expanding image data to obtain a higher bit-width image representation.

[0032] Figure 5 A flowchart is shown of an example method for processing image data to perform data decompression expansion according to some embodiments of the present disclosure.

[0033] Figure 6 This is a block diagram illustrating an example image capture device configuration for image data processing in an image capture device according to one or more embodiments of the present disclosure.

[0034] The same reference numerals and names in the various figures indicate the same elements. Detailed Implementation

[0035] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to limit the scope of this disclosure. Rather, the detailed description includes specific details for providing a thorough understanding of the subject matter of the invention. It will be apparent to those skilled in the art that these specific details are not necessary in every situation, and in some cases, well-known structures and components are shown in block diagram form for clarity of presentation.

[0036] This disclosure provides systems, apparatus, methods, and computer-readable media supporting image processing, including techniques for processing higher bit-width images using lower bit-width logic. The techniques may include compressing and expanding data by changing the bit width, such that multiple lower bit-width image frames can represent a single higher bit-width image frame. The techniques may also include decompressing and expanding data to create a higher bit-width original representation from multiple lower bit-width image frames.

[0037] Specific embodiments of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages or benefits. In some aspects, this disclosure provides techniques for improving image quality by supporting the processing of higher bit-width image data, which can be used to support high dynamic range (HDR) photography with a wider color gamut. A wider color gamut allows for a more accurate representation of the scene, particularly scenes with significant differences in brightness between dark and bright areas.

[0038] In the description of the embodiments herein, numerous specific details (such as examples of specific components, circuits, and processes) are set forth to provide a thorough understanding of this disclosure. As used herein, the term "coupled" means a direct connection or a connection via one or more intermediate components or circuits. Additionally, specific terminology is set forth in the following description and for purposes of explanation in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that practicing the teachings disclosed herein may not require these specific details. In other instances, well-known circuits and devices are illustrated in block diagram form to avoid obscuring the teachings of this disclosure.

[0039] Certain portions of the following detailed description are presented using other symbolic representations of procedures, logic blocks, processes, and data bit operations within computer memory. In this disclosure, procedures, logic blocks, processes, etc., are conceived as a self-consistent sequence of steps or instructions that lead to a desired result. These steps are those that require physical manipulation of physical quantities. Although not strictly necessary, these physical quantities typically take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated within a computer system.

[0040] Example devices (such as smartphones) for capturing image frames using one or more image sensors may include a configuration of one, two, three, four, or more camera modules on the rear (e.g., the side opposite the main user display) and / or front (e.g., the same side as the main user display) of the device. These devices may include one or more image signal processors (ISPs), computer vision processors (CVPs) (e.g., AI engines), or other suitable circuitry for processing the images captured by the image sensors. The one or more image signal processors (ISPs) may store output image frames (e.g., via a bus) in memory and / or provide output image frames to processing circuitry (e.g., an application processor). The processing circuitry may perform further processing, such as encoding, storing, transmitting, or other manipulations of the output image frames.

[0041] As used herein, a camera module may include an image sensor and certain other components coupled to the image sensor for acquiring a representation of a scene in image data comprising image frames. For example, the camera module may include other components of the camera, including a shutter, buffer, or other readout circuitry for accessing individual pixels of the image sensor. In some embodiments, the camera module may include one or more components, including an image sensor, which is included in a single package having an interface configured to couple the camera module to an image signal processor or other processor via a bus.

[0042] Figure 1 A block diagram of a device 100 for performing image capture from one or more image sensors is shown. Device 100 may include or be otherwise coupled to an image signal processor (e.g., ISP 112) for processing image frames from one or more image sensors, such as a first image sensor 101, a second image sensor 102, and a depth sensor 140. In some specific embodiments, device 100 may also include or be coupled to a processor 104 and a memory 106 storing instructions 108 (e.g., memory storing processor-readable code or a non-transitory computer-readable medium storing instructions). Device 100 may also include or be coupled to a display 114 and component 116. Component 116 may be used for user interaction, such as a touchscreen interface and / or physical buttons.

[0043] Component 116 may also include network interfaces for communicating with other devices, including a wide area network (WAN) adapter (e.g., WAN adapter 152), a local area network (LAN) adapter (e.g., LAN adapter 153), and / or a personal area network (PAN) adapter (e.g., PAN adapter 154). WAN adapter 152 may be a 4G LTE or 5G NR wireless network adapter. LAN adapter 153 may be an IEEE 802.11 WiFi wireless network adapter. PAN adapter 154 may be a Bluetooth wireless network adapter. Each of WAN adapter 152, LAN adapter 153, and / or PAN adapter 154 may be coupled to an antenna comprising multiple antennas configured for main and diversity reception and / or configured to receive a specific frequency band. In some embodiments, the antennas may be shared by WAN adapter 152, LAN adapter 153, and / or PAN adapter 154 for communication on different networks. In some implementations, WAN adapter 152, LAN adapter 153 and / or PAN adapter 154 may share circuitry and / or be packaged together, such as when LAN adapter 153 and PAN adapter 154 are packaged as a single integrated circuit (IC).

[0044] Device 100 may also include or be coupled to a power supply 118 for device 100, such as a battery or an adapter that couples device 100 to an energy source. Device 100 may also include or be coupled to... Figure 1Additional features or components not shown. In one example, a wireless interface that may include multiple transceivers and baseband processors in the radio frequency front-end (RFFE) may be coupled to or included in the WAN adapter 152 for use in a wireless communication device. In another example, an analog front-end (AFE) for converting analog image data to digital image data may be coupled between the first image sensor 101 or the second image sensor 102 and the processing circuitry in the device 100. In some embodiments, the AFE may be embedded in the ISP 112.

[0045] The device may include or be coupled to sensor hub 150, which is used to interface with sensors to receive data about the movement of device 100, data about the environment surrounding device 100, and / or other non-camera sensor data. One example non-camera sensor is a gyroscope, a device configured to measure rotation, orientation, and / or angular velocity to generate motion data. Another example non-camera sensor is an accelerometer, a device configured to measure acceleration, which can also be used to determine the speed and distance of travel by appropriately integrating the measured acceleration. In some aspects, a gyroscope in an electronic image stabilization system (EIS) may be coupled to the sensor hub. In another example, the non-camera sensor may be a Global Positioning System (GPS) receiver, a device used to process satellite signals, such as through triangulation and other techniques, to determine the position of device 100. Position can be tracked over time to determine additional motion information, such as velocity and acceleration. Data from one or more sensors may be accumulated by sensor hub 150 into motion data. One or more of acceleration, velocity, and / or distance may be included in the motion data provided by sensor hub 150 to other components of device 100 (including ISP 112 and / or processor 104).

[0046] The ISP 112 can receive captured image data. In one embodiment, a local bus connection couples the ISP 112 to the first image sensor 101 and the second image sensor 102 of the first camera 103 and the second camera 105, respectively. In another embodiment, a wired interface couples the ISP 112 to an external image sensor. In yet another embodiment, a wireless interface couples the ISP 112 to either the first image sensor 101 or the second image sensor 102.

[0047] First image sensor 101 and second image sensor 102 are configured to capture image data representing scenes within the fields of view of first camera 103 and second camera 105, respectively. In some embodiments, first camera 103 and / or second camera 105 output analog data, which is converted by an analog front-end (AFE) and / or analog-to-digital converter (ADC) in device 100 or embedded in ISP 112. In some embodiments, first camera 103 and / or second camera 105 output digital data. The digital image data may be formatted into one or more image frames, whether received from first camera 103 and / or second camera 105 or converted from analog data received from first camera 103 and / or second camera 105.

[0048] The first camera 103 may include a first image sensor 101 and a first lens 131. The second camera may include a second image sensor 102 and a second lens 132. Each of the first lens 131 and the second lens 132 may be controlled by an associated autofocus (AF) algorithm (e.g., AF 133) executed in the ISP 112, which adjusts the first lens 131 and the second lens 132 to focus on a specific focal plane located at a certain depth of a scene. AF 133 may be assisted by depth data received from the depth sensor 140. The first lens 131 and the second lens 132 focus light onto the first image sensor 101 and the second image sensor 102 respectively through one or more apertures for receiving light, one or more shutters for blocking light outside the exposure window, and / or one or more color filter arrays (CFAs) for filtering light outside a specific frequency range. The first lens 131 and the second lens 132 may have different fields of view to capture different representations of the scene. For example, the first lens 131 may be an ultra-wide-angle (UW) lens, and the second lens 132 may be a wide-angle (W) lens. Multiple image sensors may include a combination of ultra-wide-angle (high field of view (FOV)) sensors, wide-angle sensors, telephoto sensors, and super-telephoto (low FOV) sensors.

[0049] Each of the first camera 103 and the second camera 105 can be configured via hardware configuration and / or software settings to obtain different but overlapping fields of view. In some configurations, the cameras are configured with different lenses with different magnifications, which produce different fields of view for capturing different representations of the scene. The cameras can be configured such that the UW camera has a larger FOV than the W camera, the W camera has a larger FOV than the T camera, and the T camera has a larger FOV than the UT camera. For example, a camera configured for wide-angle FOV can capture a field of view in the range of 64 to 84 degrees, a camera configured for ultra-wide-angle FOV can capture a field of view in the range of 100 to 140 degrees, a camera configured for telephoto FOV can capture a field of view in the range of 10 to 30 degrees, and a camera configured for super telephoto FOV can capture a field of view in the range of 1 to 8 degrees.

[0050] In some implementations, one or more of the first camera 103 and / or the second camera 105 may be variable aperture (VA) cameras, wherein the aperture can be adjusted to set a specific aperture size. Example aperture sizes include f / 2.0, f / 2.8, f / 3.2, f / 8.0, etc. Larger aperture values ​​correspond to smaller aperture sizes, and smaller aperture values ​​correspond to larger aperture sizes. Variable aperture (VA) cameras may have different characteristics that produce different representations of the scene based on the current aperture size. For example, a VA camera may capture image data with a depth of focus (DOF) corresponding to the current aperture size set for the VA camera.

[0051] The ISP 112 processes image frames captured by the first camera 103 and the second camera 105. Although Figure 1 Device 100 is exemplified as including a first camera 103 and a second camera 105, but any number of cameras (e.g., one, two, three, four, five, six, etc.) may be coupled to ISP 112. In some aspects, depth sensors such as depth sensor 140 may be coupled to ISP 112. The output from depth sensor 140 may be processed in a manner similar to that of the first camera 103 and the second camera 105. Examples of depth sensors 140 include active sensors, including one or more of the following: indirect time-of-flight (iToF), direct time-of-flight (dToF), light detection and ranging (Lidar), mmWave, radio detection and ranging (Radar), and / or hybrid depth sensors (such as structured light sensors). In embodiments without depth sensor 140, similar information about the depth of an object or a depth map may be determined from the parallax between the first camera 103 and the second camera 105, such as by using a parallax depth measurement algorithm, a stereo depth measurement algorithm, a phase detection autofocus (PDAF) sensor, etc. Furthermore, any number of additional image sensors or image signal processors may be present for device 100.

[0052] In some embodiments, ISP 112 may execute instructions from memory, such as instructions 108 from memory 106, instructions stored in a separate memory coupled to or included in ISP 112, or instructions provided by processor 104. Additionally or alternatively, ISP 112 may include specific hardware (such as one or more integrated circuits (ICs)) configured to perform one or more operations described in this disclosure. For example, ISP 112 may include an image front-end (e.g., IFE 135), an image post-processing engine (e.g., IPE 136), an automatic exposure compensation (AEC) engine (e.g., AEC 134), and / or one or more engines for video analysis (e.g., EVA 137). The image pipeline may be formed by a sequence of one or more of IFE 135, IPE 136, and / or EVA 137. In some embodiments, the image pipeline in ISP 112 may be reconfigured by changing the connections between IFE 135, IPE 136, and / or EVA 137. AF 133, AEC 134, IFE 135, IPE136 and EVA 137 may each include dedicated circuitry, which may be embodied as software or firmware executed by ISP 112 and / or a combination of hardware and software or firmware executed on ISP 112.

[0053] Memory 106 may include a non-transient or non-transitory computer-readable medium storing computer-executable instructions (such as instruction 108) for performing all or part of one or more of the operations described in this disclosure. Instruction 108 may include a camera application (or other suitable application, such as a messaging application) to be executed by device 100 for taking pictures or videos. Instruction 108 may also include other applications or programs to be executed by device 100, such as an operating system and applications other than those for image or video generation. Executing a camera application, such as by processor 104, may enable device 100 to record images using the first camera 103 and / or the second camera 105 and the ISP 112.

[0054] In addition to instruction 108, memory 106 may also store image frames. The image frames may be output image frames stored by ISP 112. The output image frames may be accessed by processor 104 for further operation. In some embodiments, device 100 does not include memory 106. For example, device 100 may be circuitry including ISP 112, and the memory may be external to device 100. Device 100 may be coupled to external memory and configured to access that memory to write output image frames for display or long-term storage. In some embodiments, device 100 is a system-on-a-chip (SoC) that integrates ISP 112, processor 104, sensor hub 150, memory 106, and / or component 116 into a single package.

[0055] In some embodiments, at least one of the ISP 112 or processor 104 executes instructions to perform various operations described herein, including decompressing and expanding data. This may include combining image frames captured using lower bit-width values ​​from a single exposure to obtain a higher dynamic range representation of the scene. For example, the execution of instructions may instruct the ISP 112 to begin or end capturing image frames or sequences of image frames, wherein the capture includes corrections as described in the embodiments herein. In some embodiments, processor 104 may include one or more general-purpose processor cores 104A to 104N capable of executing instructions to control the operation of the ISP 112. For example, cores 104A to 104N may execute a camera application (or other suitable application for generating images or videos) stored in memory 106 that activates or deactivates the ISP 112 to capture image frames and / or controls the ISP 112 when applying compression or decompression expansion to the image frames. The operation of cores 104A to 104N and the ISP 112 may be based on user input. For example, a camera application executing on processor 104 may receive a user command to start a video preview display. Upon receiving the user command, it may capture and process video, including a sequence of image frames, from a first camera 103 and / or a second camera 105 via ISP 112 for display and / or storage. Image processing, such as that described herein, for determining “output” or “corrected” image frames, may be applied to one or more image frames in the sequence.

[0056] In some implementations, processor 104 may include an IC or other hardware (e.g., an artificial intelligence (AI) engine such as AI engine 124 or other coprocessors) to offload certain tasks from cores 104A through 104N. AI engine 124 may be used to offload tasks related to face detection and / or object recognition, performed, for example, using machine learning (ML) or artificial intelligence (AI). AI engine 124 may refer to an artificial intelligence processing unit (AI PU). AI engine 124 may include hardware configured to perform and accelerate convolutional operations involved in executing machine learning algorithms, such as by executing predictive models such as artificial neural networks (ANNs) (including multilayer feedforward neural networks (MLFFNNs), recurrent neural networks (RNNs), and / or radial basis functions (RBFs)). The ANN executed by AI engine 124 has access to predefined training weights to perform operations on user data. The ANN may optionally be trained during operation of image capture device 100, such as through reinforcement training, supervised training, and / or unsupervised training. In some other implementations, device 100 does not include processor 104, such as when all the described functionality is configured in ISP 112.

[0057] In some embodiments, display 114 may include one or more suitable displays or screens that allow the user to interact and / or present a preview of an item (such as the output of the first camera 103 and / or the second camera 105) to the user. In some embodiments, display 114 is a touch-sensitive display. Input / output (I / O) components (such as component 116) may be or include any suitable mechanism, interface, or device to receive input (such as commands) from the user and provide output to the user via display 114. For example, component 116 may include (but is not limited to) a graphical user interface (GUI), a keyboard, a mouse, a microphone, a speaker, a squeezable bezel, one or more buttons (such as a power button), a slider, a toggle, or a switch.

[0058] Although shown as coupled to each other via processor 104, components (such as processor 104, memory 106, ISP 112, display 114, and component 116) may be coupled to each other in various other arrangements, such as via one or more local buses, which are not shown for simplicity. An example of a bus used to interconnect components is the Peripheral Component Interface (PCI) Fast (PCIe) bus.

[0059] Although ISP 112 is illustrated as separate from processor 104, ISP 112 may be the core of processor 104, which is an application processor unit (APU) included in a system-on-a-chip (SoC), or otherwise included in processor 104. While device 100 is referenced in the examples herein to perform aspects of this disclosure, some device components may not be included. Figure 1 The details are shown to prevent obscuring aspects of this disclosure. Additionally, other components, the number of components, or combinations of components may be included in suitable equipment for performing aspects of this disclosure. Therefore, this disclosure is not limited to the configuration of a particular device or component, including device 100.

[0060] Operable Figure 1 An exemplary image capture device is used to obtain an improved image by processing image frames obtained from an image sensor with in-sensor compression expansion or image frames with data from other sources with compression expansion. Figure 2 An example method of operating one or more cameras (such as a first camera 103 and / or a second camera 105) is shown and described below.

[0061] Figure 2 This is a block diagram illustrating an example data flow path for image data processing in an image capture device according to one or more embodiments of the present disclosure. The processor 104 of system 200 communicates with ISP 112 via a bidirectional bus and / or separate control and data lines. The processor 104 can control a first camera 103 via camera control 210. Camera control 210 may be a camera driver executed by processor 104 for configuring the first camera 103, such as activating or deactivating image capture, configuring exposure settings, and / or configuring aperture size. Camera control 210 may be managed by a camera application 204 executing on processor 104. Camera application 204 provides user-accessible settings, allowing a user to specify individual camera settings or select a profile with corresponding camera settings. Camera control 210 communicates with the first camera 103 to configure the first camera 103 according to commands received from camera application 204. Camera application 204 may be, for example, a photography application, a document scanning application, a messaging application, or other applications that process image data acquired from the first camera 103.

[0062] Camera configuration may include specifying, for example, image compression extension configurations (such as those referenced below). Figure 3A , Figure 3B or Figure 3CThe parameters described include image compression and expansion configuration, frame rate, image resolution, readout duration, exposure level, aspect ratio, and / or aperture size. The first camera 103 can apply a camera configuration and use that configuration to obtain image data representing a scene. In some embodiments, the camera configuration can be adjusted to obtain different representations of the scene. For example, the processor 104 can execute camera application 204 to instruct the first camera 103 via camera control 210 to set a first camera configuration for the first camera 103, obtain first image data from the first camera 103 operating with the first camera configuration, instruct the first camera 103 to set a second camera configuration for the first camera 103, and obtain second image data from the first camera 103 operating with the second camera configuration.

[0063] In some embodiments where the first camera 103 is a variable aperture (VA) camera system, the processor 104 can execute camera application 204 to instruct the first camera 103 to configure to a first aperture size, acquire first image data from the first camera 103, instruct the first camera 103 to configure to a second aperture size, and acquire second image data from the first camera 103. The aperture reconfiguration and the acquisition of the first and second image data can occur with little or no change in the scene captured at the first and second aperture sizes. Example aperture sizes are f / 2.0, f / 2.8, f / 3.2, f / 8.0, etc. Larger aperture values ​​correspond to smaller aperture sizes, and smaller aperture values ​​correspond to larger aperture sizes. That is, f / 2.0 corresponds to an aperture size larger than f / 8.0.

[0064] Image data received from the first camera 103 can be processed in one or more blocks of the ISP 112 to determine output image frames 230 that can be stored in memory 106 and / or otherwise provided to the processor 104. The processor 104 can further process the image data to apply effects to the image frames 230. Effects may include background blur, lighting, color cast, and / or high dynamic range (HDR) blending. In some embodiments, the effects may be applied to the ISP 112.

[0065] Image frames 230 output by ISP 112 may include an improved representation of the scene through various aspects of this disclosure, such as by providing images with image data having a higher dynamic range. Images with a higher dynamic range may be obtained using image signal processing circuitry with a bit width smaller than the bit width of the image sensor output, but still resulting in output image frames with a bit width corresponding to the image sensor output. Processor 104 may display these output image frames 230 to a user, and the improvements provided by the processing described in ISP 112 and / or processor 104 improve image quality and user experience by allowing the capture, viewing, and / or editing of images with a high dynamic range, which results in more vivid colors and better representation of bright and dark areas in the scene. For example, camera 103 may output compressed and expanded data in multiple image frames, and decompression expander 212 in ISP 112 may combine the compressed and expanded data to obtain a high dynamic range (HDR) representation of the image scene, which corresponds to the high dynamic range (HDR) representation of the image scene captured by image sensor 101 before the data is compressed and expanded for transmission to parts of image signal processor 112 and / or processed in parts of image signal processor.

[0066] Figure 3A , Figure 3B , Figure 3C The example implementation of compressed expansion of data within system 200 (such as within image sensor 101) is shown. Figure 3A This is a block diagram illustrating, according to some embodiments of the present disclosure, the compression and expansion of image data for representation in two image frames. First image data 350 with a first bit width can be compressed and expanded into second image data 352 and third image data 354 having corresponding second and third bit widths. The second image data 352 and third image data 354, combined, can represent the first image data. A first operation 356 generates second image data 352, whose bit width may be equal to or less than that of the first image data 350. A second operation 358 generates third image data 354, whose bit width may be equal to or less than that of the first image data 350. The first operation 356 and / or the second operation 358 may each include one or more bit shifting operations, such that data is shifted and the resulting data occupies only a subset of bits. The first operation 356 and the second operation 358 may further include a truncation operation that eliminates the same number of bits that are shifted in the bit shifting operation, thereby reducing the bit width from the bit width of image data 350 to different bit widths of second image data 352 and third image data 354. The second image data 352 and the third image data 354 may be second and third image frames representing the same scene as that represented by the first image data 350.

[0067] The first image data 350 may have been captured by a single exposure of an image sensor. In some embodiments, the first image data may be the result of a combination of exposures from an image sensor to obtain high dynamic range (HDR) image data represented by a single image frame corresponding to the single exposure. The HDR image data may have a higher bit width to represent a wider range of colors and / or brightness. The higher bit width HDR image data may be represented by second image data 352 and third image data 354, each having a lower bit width, to allow processing in circuitry that does not support the higher bit width of the first image data 350.

[0068] Figure 3B The image shows the use of Figure 3A An example bit-width arrangement of a compressed extended arrangement. Figure 3B This is a block diagram illustrating, according to some embodiments of the present disclosure, the compression and expansion of 14-bit image data into two image frames with 12-bit data. First image data 310 may include a value represented by 14 bits, such that the bit width of first image data 310 is 14 bits. A first bit shift operation 316 performs a rounding operation that captures the most significant bit of the 14-bit value. The 12 bits that are the most significant bits become second image data 312 with a bit width of 12 bits. A second bit shift operation 318 performs a clamping operation that captures the least significant bit of the 14-bit value. The 12 bits that are the least significant bits become third image data 314 with a bit width of 12 bits.

[0069] The compression extension example described above involves representing a single image frame using two image frames with a lower bit width; however, it is also possible to use more than two image frames to represent a single image frame. For example, a single image frame can be represented using three, four, five, or more image frames. Figure 3C The image shows an example of compression extended to three image frames.

[0070] Figure 3CThis is a block diagram illustrating, according to some embodiments of the present disclosure, the compression and expansion of 18-bit image data into three image frames with 12-bit data. First image data 320 may include a value represented by 18 bits, such that the bit width of first image data 320 is 18 bits. A first bit shift operation 332 may perform a rounding operation that captures the most significant bit of the 18-bit value. The 12 bits that are the most significant bits become second image data 312 with a 12-bit bit width. A second bit shift operation 334 may perform a combined rounding and clamping operation, resulting in a 12-bit value that becomes third image data 324 with a 12-bit bit width. The second bit shift operation 334 may include left shift and right shift operations to perform rounding and clamping. For example, the second bit shift operation 334 may include a 3-bit left shift followed by a 6-bit right shift, which results in the loss of 3 most significant bits (MSB) and 3 least significant bits (LSB) to obtain a 12-bit value from the 18-bit value. The third bit shift operation 336 can perform a clamping operation that captures the least significant bit of the 18-bit value. The 12 bits that are the least significant bits become the fourth image data 314 with a width of 12 bits.

[0071] Despite about Figure 3A , Figure 3B and Figure 3C Some example implementations of compression extensions are described, but additional compression extension examples are provided in the table below:

[0072]

[0073] Compressed and expanded image data can be combined with high dynamic range (HDR) image data captured from the image sensor (which is... Figure 3A The first image data (350) is represented in a similar or identical High Dynamic Range (HDR) format. Figure 4 The example implementation of decompression expansion of data within system 200 (such as within image signal processor 112) is shown. Figure 4 This is a block diagram illustrating decompression and expansion of image data to obtain a higher bit-width image representation according to some embodiments of the present disclosure. Second image data 402 and third image data 404 may be input to a combination operation 406, which produces an output image frame 408. Second image data 402 and third image data 404 may correspond to second image data 352 and third image data 354. For example, both second image data 402 and third image data 404 may represent the same scene captured as part of a single exposure of an image sensor.

[0074] Figure 5 This describes a method for processing compressed and expanded image data in an image capture device or image processing device. Figure 2System 200 can be configured to execute the reference. Figure 5 The described operation determines the output image frame 230. Figure 5 A flowchart is shown of an example method for processing image data to perform data decompression expansion according to some embodiments of the present disclosure. Figure 5 Capturing images in this way allows for an improved digital representation of the scene, resulting in photos or videos with higher image quality (IQ). (Reference) Figure 5 Each of the operations described can be performed by one or a combination of processor 104 (including cores 104A to 104N or AI engine 124) and / or ISP 112.

[0075] At block 502, first image data is received from the image sensor, such as when the image sensor is configured with a camera configuration. The first image data received at block 502 may include multiple image frames, which include at least a first image frame and a second image frame, wherein the multiple image frames represent the same scene and / or were captured during a single exposure. For example, the image data received at block 502 may include multiple image frames whose combined representation of the scene has a higher dynamic range than any single image frame individually represents. The multiple image frames may have the same bit width or different bit widths, but the bit width of any one of the image frames is lower than the bit width of the captured image data as an HDR representation of the scene.

[0076] The first image data may be received, for example, from a bus coupled to the first camera 103 or from an analog front-end (AFE) coupled to the first camera 103. When the bit width of the analog front-end (AFE) is smaller than the bit width of the image data captured by the first camera 103, the AFE may also be referred to as a thin front-end (TFE). The first image data may alternatively be received from a wireless camera, wherein the image data is received via one or more of a WAN adapter 152, a LAN adapter 153, and / or a PAN adapter 154. The first image data may alternatively be received from a memory location or a network storage location, such as when image data was previously captured and is now retrieved from memory 106 and / or a remote location via one or more of a WAN adapter 152, a LAN adapter 153, and / or a PAN adapter 154.

[0077] In some embodiments, image data capture may be initiated by a camera application executing on processor 104, which causes camera control 210 to activate the first camera 103 to capture image data. The image data retrieved at box 302 may then be processed by ISP 112 and / or processor 104 or other components for processing the image data according to the operations described in one or more of the following boxes. In some embodiments, the camera application may provide a camera configuration to the first camera 103 specifying whether to compress and expand data to a smaller bit width and / or activate a high dynamic range (HDR) operating mode. For example, camera control 210 may cause the camera configuration to be transmitted to the first camera 103 to initiate HDR image capture, and the first camera 103 may be configured according to... Figure 3A , Figure 3B or Figure 3C One example implementation of the example implementation compresses and expands HDR images. Although the camera configuration is shown as being sent from processor 104 to first camera 103, the camera configuration may also be provided from processor 104 to ISP 112 and then output to first camera 103.

[0078] At box 504, the image frame to be processed is determined from the plurality of image frames received at box 502. For example, it can be determined according to reference. Figure 4 The described technique combines images. The processed image frame has an output bit width higher than the bit width of any one of the plurality of image frames received at block 502. Determining block 504 may include combining the plurality of image frames, which may include padding values ​​to increase the bit width of one of the image frames. Padding zeros may be added as either the most significant bit or the least significant bit, depending on whether the bit shift operation used to obtain the image frame shifts the most significant bit or the least significant bit. Corresponding values ​​of the plurality of image frames may be added after padding the values ​​of the plurality of image frames to obtain values ​​with a bit width corresponding to the output bit width of the original HDR representation. In some embodiments, the HDR fusion logic of the ISP may be used to perform the combination. Sharing this fusion logic may reduce the amount of circuitry in the ISP die.

[0079] Figure 6 This is a block diagram illustrating an example image capture device configuration for image data processing in an image capture device according to one or more embodiments of the present disclosure. Image capture device 600 may include an image sensor with in-sensor compression extension and an image signal processor with front-end decompression extension. Image capture device 600 allows the image sensor to capture images with a higher dynamic range than supported by the narrowest processing path bit width of ISP 112. This improves user experience. Figure 6 The image quality (IQ) of photos and videos captured by an image capture device.

[0080] Image sensor 101 includes a pixel element array 602 that converts light captured by, for example, a lens into values ​​representing a scene within the field of view of image sensor 101. In high dynamic range (HDR) operating mode, the output of pixel element 602 can be an 18-bit value (e.g., a value with an 18-bit width). An in-sensor compression extension 604 can determine image frames with a lower bit width than the 18-bit width output of pixel element array 602. For example, compression extension 604 can perform… Figure 3A , Figure 3B or Figure 3C One example of compression extension is shown below. Lower bit-width image frames are sent to ISP 112 via a bus, which may have the same or a different bit width as the output of compression extension 604 within the sensor.

[0081] Image signal processor 112 or other processing circuitry may be configured to operate on image data to perform... Figure 5 One or more operations of the method determine one or more output image frames 230. ISP 112 includes a front-end decompression extension 606 that applies a non-linear curve to change a 14-bit non-linear signal to an 18-bit linear signal. The front-end decompression extension 606 can be configured to perform decompression extension to recover the higher bit-width signal of the pixel element array 602. For example, an in-sensor compression extension 604 may apply a compression extension curve that performs a square root operation to reduce the bit width from 18 bits to 14 bits, and the front-end decompression extension 606 may apply a decompression extension curve that performs a square operation to increase the bit width from 14 bits to 18 bits. In some embodiments, the higher bit-width signal may be an 18-bit Bayer signal. The decompressed data may be processed by a format converter 608 that converts the Bayer format output into two sets of RAW data. The output of the format converter 608 can be two sets of RAW data, corresponding to the least significant bit (LSB) and most significant bit (MSB) of a bit-splitting operation from the 18-bit Bayer signal output from the front-end compression extension 606. The two sets of RAW data can be processed by HDR fusion logic 610 to produce a high dynamic range image frame 230. The fusion logic 610 can perform [reference missing]. Figure 4 and / or Figure 5 The described operation yields a decompressed and expanded result. For example, the fusion logic 610 can use LSB RAW data and MSB RAW data to perform tone mapping operations. In some implementations, the output of the fusion logic 610 can be 10-bit YUV data.

[0082] In one or more aspects, the technology for supporting image processing may include additional aspects, such as any single aspect or any combination of aspects described below or in conjunction with one or more other processes or devices described elsewhere herein. In a first aspect, supporting image processing may include an apparatus, such as an image capture device or a mobile phone, having at least one processor configured to perform operations including: receiving by the processor first image data comprising a plurality of image frames, the plurality of image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the plurality of image frames represent the same scene; and determining a processed image frame having an output bit width greater than the first bit width and greater than the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0083] Additionally, the apparatus may perform or operate according to one or more aspects described below. In some embodiments, the apparatus includes a wireless device, such as a UE. In some embodiments, the apparatus includes a remote server (such as a cloud-based computing solution) that receives image data, processes it, and determines output image frames. In some embodiments, the apparatus may include at least one processor and memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the apparatus. In some other embodiments, the apparatus may include a non-transitory computer-readable medium having program code recorded thereon, and the program code being executable by a computer to cause the computer to perform the operations described herein with reference to the apparatus. In some embodiments, the apparatus may include one or more components configured to perform the operations described herein. In some embodiments, a method of wireless communication may include one or more operations described herein with reference to the apparatus.

[0084] In a second aspect, in conjunction with the first aspect, receiving the first image data includes receiving compressed and expanded image data from an image sensor, and wherein determining the image frame to process includes decompressing and expanding the compressed and expanded image data.

[0085] In a third aspect, in conjunction with one or more of the first or second aspects, the apparatus is further configured to receive camera configuration information indicating that the image sensor is configured to perform intra-sensor compression expansion to generate compressed and expanded image data, and to decompress and expand the compressed and expanded image data based on the camera configuration information indicating that the image sensor is configured to perform intra-sensor compression expansion.

[0086] In the fourth aspect, in conjunction with one or more of the first to third aspects, the first bit width and the second bit width are the same bit width.

[0087] In the fifth aspect, in conjunction with one or more of the first to fourth aspects, the first bit width is 12 bits, the second bit width is 12 bits, and the output bit width is 14 bits.

[0088] In a sixth aspect, in conjunction with one or more of the first to fifth aspects, the plurality of image frames further includes a third image frame having a third bit width, wherein the first bit width is 12 bits, the second bit width is 12 bits, the third bit width is 12 bits, and the output bit width is 18 bits.

[0089] In the seventh aspect, in conjunction with one or more of the first to sixth aspects, combining multiple image frames includes applying a high dynamic range (HDR) fusion operation to the multiple image frames by inputting the multiple image frames as multiple different exposures of the same scene.

[0090] In the eighth aspect, in conjunction with one or more of the first to seventh aspects, multiple image frames include different displacement bit representations of the same scene.

[0091] In the ninth aspect, in conjunction with one or more of the first to eighth aspects, the first image frame includes a value consisting of a first subset of the most significant bits of the representation of the scene, and wherein the second image frame includes a value consisting of a second subset of the least significant bits of the representation of the scene.

[0092] In the tenth aspect, in conjunction with one or more of the first to ninth aspects, it is determined that the image frames being processed are performed without aligning multiple image frames for combination.

[0093] In an eleventh aspect, a method for processing image data includes: receiving by a processor first image data comprising a plurality of image frames, the plurality of image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the plurality of image frames represent the same scene; and determining a processed image frame having an output bit width greater than the first bit width and greater than the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0094] In the twelfth aspect, in conjunction with the eleventh aspect, receiving the first image data includes receiving compressed and expanded image data from an image sensor, and wherein determining the image frame to process includes decompressing and expanding the compressed and expanded image data.

[0095] In a thirteenth aspect, in conjunction with one or more of aspects eleven to twelfth, the method further includes receiving camera configuration information indicating that an image sensor is configured to perform intrasensor compression expansion to produce compressed expanded image data, and decompressing the compressed expanded image data based on the camera configuration information.

[0096] In aspect fourteen, in conjunction with one or more of aspects eleven to thirteen, the first width and the second width are the same width.

[0097] In the fifteenth aspect, in conjunction with one or more of aspects eleven through fourteen, the first bit width is 12 bits, the second bit width is 12 bits, and the output bit width is 14 bits.

[0098] In the sixteenth aspect, in conjunction with one or more of aspects eleven to fifteen, the plurality of image frames further includes a third image frame having a third bit width, wherein the first bit width is 12 bits, the second bit width is 12 bits, the third bit width is 12 bits, and the output bit width is 18 bits.

[0099] In the seventeenth aspect, in conjunction with one or more of aspects eleven to sixteen, combining multiple image frames includes applying a high dynamic range (HDR) fusion operation to the multiple image frames by inputting the multiple image frames as multiple different exposures of the same scene.

[0100] In the eighteenth aspect, in conjunction with one or more of aspects eleven through seventeen, multiple image frames include different displacement bit representations of the same scene.

[0101] In the nineteenth aspect, in conjunction with one or more of aspects eleven to eighteen, the first image frame includes a value consisting of a first subset of the most significant bits of the representation of the scene, and wherein the second image frame includes a value consisting of a second subset of the least significant bits of the representation of the scene.

[0102] In the twentieth aspect, in combination with one or more of the eleventh to nineteenth aspects, it is determined that the image frames being processed are performed without aligning multiple image frames for combination.

[0103] In a twenty-first aspect, a non-transitory computer-readable medium storing instructions for image processing includes instructions that, when executed by a processor, cause the processor to perform operations including: receiving by the processor first image data comprising a plurality of image frames, the plurality of image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the plurality of image frames represent the same scene; and determining a processed image frame having an output bit width greater than the first bit width and greater than the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0104] In the twenty-second aspect, in conjunction with the twenty-first aspect, multiple image frames include different displacement bit representations of the same scene.

[0105] In the twenty-third aspect, in combination with one or more of the twenty-first and twenty-second aspects, receiving the first image data includes receiving compressed and expanded image data from an image sensor, and wherein determining the processing of the image frame includes decompressing and expanding the compressed and expanded image data, and wherein the operation further includes receiving camera configuration information indicating that the image sensor is configured to perform intra-sensor compression and expansion to produce compressed and expanded image data, and decompressing and expanding the compressed and expanded image data based on the camera configuration information indicating that the image sensor is configured to perform intra-sensor compression and expansion.

[0106] In aspect 24, in conjunction with one or more of aspects 21 to 23, the first bit width is 12 bits, the second bit width is 12 bits, and the output bit width is 14 bits.

[0107] In the twenty-fifth aspect, in conjunction with one or more of the twenty-first to twenty-fourth aspects, the plurality of image frames further includes a third image frame having a third bit width, wherein the first bit width is 12 bits, the second bit width is 12 bits, the third bit width is 12 bits, and the output bit width is 18 bits.

[0108] In a twenty-sixth aspect, an image capture device includes: an image sensor configured to output a single exposure of a scene as a first image frame having a first width and a second image frame having a second bit width, wherein the first width and the second bit width are each lower than a sensor bit width captured by the image sensor; a memory storing processor-readable code; and at least one processor coupled to the memory and the image sensor, the at least one processor configured to execute the processor-readable code to cause the at least one processor to perform an operation including: receiving first image data comprising a plurality of image frames, the plurality of image frames including the first image frame and the second image frame; and determining a processed image frame having an output bit width higher than the first width and higher than the second bit width, the processed image frame being obtained based on the plurality of image frames by combining the plurality of image frames to obtain the output bit width.

[0109] In the twentieth aspect, in conjunction with the twentieth aspect, the at least one processor includes at least one image signal processor, the at least one image signal processor including an image front-end (IFE) coupled to an image sensor and an image processing engine (IPE) coupled to the image front-end (IFE), wherein the image processing engine (IPE) includes a high dynamic range (HDR) fusion module configured to perform combining multiple image frames.

[0110] In the twenty-eighth aspect, in combination with one or more of the twenty-sixth to twenty-seventh aspects, multiple image frames include different displacement bit representations of the scene.

[0111] In aspect 29, in conjunction with one or more of aspects 26 to 28, the first bit width is 12 bits, the second bit width is 12 bits, and the output bit width is 14 bits.

[0112] In the thirtieth aspect, in conjunction with one or more of the twenty-sixth to twenty-ninth aspects, the plurality of image frames further include a third image frame having a third bit width, wherein the first bit width is 12 bits, the second bit width is 12 bits, the third bit width is 12 bits, and the output bit width is 18 bits.

[0113] In the accompanying drawings, a single block can be described as performing one or more functions. The one or more functions performed by this block can be performed in a single component or across multiple components, and / or can be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps are described below in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Moreover, the example device may include components other than those shown, including well-known components such as processors, memory, etc.

[0114] The aspects of this disclosure are applicable to any electronic device that includes, is coupled to, or otherwise processes data from one, two, or more image sensors capable of capturing image frames (or “frames”). The terms “output image frame,” “modified image frame,” and “corrected image frame” can refer to an image frame that has been processed by any of the techniques disclosed to adjust raw image data received from an image sensor. Additionally, aspects of the disclosed techniques can be implemented for processing image data received from image sensors having the same or different capabilities and characteristics, such as resolution, shutter speed, or sensor type. Furthermore, aspects of the disclosed techniques can be implemented in devices for processing image data, whether or not the device includes or is coupled to an image sensor. For example, the disclosed techniques can include operations performed by processing devices in a cloud computing system that retrieve image data to be processed previously recorded by a separate device having an image sensor.

[0115] Unless explicitly stated otherwise in the following discussion, it should be understood that throughout this application, the use of terms such as “access,” “receive,” “transmit,” “use,” “select,” “determine,” “normalize,” “multiply,” “average,” “monitor,” “compare,” “apply,” “update,” “measure,” “derive,” “set,” “generate,” etc., refers to the actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities in the registers and memories of the computer system and transform them into other data similarly represented as physical quantities in the registers, memories, or other such information storage, transmission, or display devices of the computer system. The use of different terms to refer to actions or processes of a computer system does not necessarily indicate different operations. For example, “determining” data can refer to “generating” data. Similarly, “determining” data can refer to “retrieving” data.

[0116] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (such as a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some parts of this disclosure. Although the description and examples herein use the term "device" to describe various aspects of this disclosure, the term "device" is not limited to a particular configuration, type, or number of objects. As used herein, an apparatus can include a device or part of a device for performing the described operations.

[0117] Certain components in a device or apparatus described as “component for access,” “component for receiving,” “component for transmitting,” “component for use,” “component for selection,” “component for determination,” “component for normalization,” “component for multiplication,” or other similarly named terms referring to one or more operations on data (such as image data) may refer to processing circuitry (e.g., application-specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), central processing unit (CPU), computer vision processor (CVP), or neural signal processor (NSP)) configured to perform the described function by means of hardware, software, or a combination of hardware configured by software.

[0118] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0119] The components, functional blocks, and modules described herein with respect to the accompanying figures cited above include processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, and so on, or any combination thereof. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, and / or functions, whether referred to as software, firmware, middleware, microcode, hardware description languages, or other terms. Furthermore, the features discussed herein may be implemented via dedicated processor circuitry, via executable instructions, or a combination thereof.

[0120] Those skilled in the art should understand that, with reference to Figures 3 to 4, Figure 5 One or more boxes (or operations) described may be combined with one or more boxes (or operations) described in another figure referring to the figures. For example, Figures 3A to 3C One or more boxes (or operations) can be connected with Figures 1 to 2 A combination of one or more boxes (or operations). For example, with... Figure 4 One or more associated boxes can be combined with Figures 1 to 2 A combination of one or more associated boxes (or operations).

[0121] Those skilled in the art will also recognize that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described herein are merely examples, and that components, methods, or interactions of various aspects of this disclosure can be combined or performed in ways other than those illustrated and described herein.

[0122] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the specific implementations disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been broadly described in terms of functionality and illustrated in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0123] Hardware and data processing means for implementing the various exemplary logic, logic blocks, modules, and circuits described herein can be implemented or executed using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some embodiments, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some embodiments, specific processes and methods may be performed by circuitry specific to a given function.

[0124] In one or more aspects, the described functionality may be implemented in hardware, digital electronic circuits, computer software, firmware, including the structures disclosed in this specification and their structural equivalents or any combination thereof. Specific implementations of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing apparatus or for controlling the operation of a data processing apparatus.

[0125] If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted through a computer-readable medium. The processes of the methods or algorithms disclosed herein can be implemented in a processor-executable software module that can reside on a computer-readable medium. Computer-readable media include both computer storage media and communication media, including any medium that can be implemented to transfer a computer program from one location to another. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible to a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operation of a method or algorithm may reside as a set of code and instructions or any combination of code and instructions on a machine-readable medium and a computer-readable medium that may be incorporated into a computer program product.

[0126] Various modifications to the specific embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific embodiments without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific embodiments shown herein, but are to be granted the broadest scope consistent with this disclosure, the principles disclosed herein, and the novel features.

[0127] Additionally, those skilled in the art will readily recognize that, for the convenience of describing the figures, opposite terms such as “upper” and “lower” or “front” and “back” or “top” and “bottom” or “forward” and “backward” are sometimes used, indicating relative positioning on a correctly oriented page corresponding to the orientation of the figures, and may not reflect the correct orientation of any device as implemented.

[0128] Certain features described in this specification in the context of a single embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations and even originally claimed in this way, one or more features from the claimed combination may be removed from that combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0129] Similarly, although operations are depicted in a specific order in the figures, this should not be construed as requiring such operations to be performed in the indicated specific order or sequential order, or to perform all illustrated operations to achieve the desired result. Furthermore, the figures may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be combined with the schematically illustrated example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any illustrated operation. In some environments, multitasking and parallel processing are advantageous. Moreover, the separation of the various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products. Additionally, several other embodiments also fall within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired result.

[0130] As used herein (including the claims), the term "or" in a list of two or more items means that any one of the listed items may be used alone, or any combination of two or more of the listed items may be used. For example, if a composition is described as containing component A, B, or C, the composition may contain A alone; B alone; C alone; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Furthermore, as used herein (including the claims), "or" in a list of items ending with "at least one of" indicates a disjunctive list, such that a list such as "at least one of A, B, or C" refers to A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination of any of these items.

[0131] The term “substantially” is defined as being largely, but not necessarily entirely, of the specified content (and includes the specified content; for example, substantially 90 degrees includes 90 degrees and substantially parallel includes parallel), as understood by one of ordinary skill in the art. In any specific implementation of the disclosure, the term “substantially” may be used in place of “[percentage]” of the specified content, where percentage includes 0.1%, 1%, 5%, or 10%.

[0132] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, the method comprising: The processor receives first image data comprising multiple image frames, the multiple image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the multiple image frames represent the same scene; as well as A processed image frame is determined to have an output bit width that is higher than the first bit width and higher than the second bit width, the processed image frame being obtained by combining the plurality of image frames to obtain the output bit width.

2. The method of claim 1, wherein receiving the first image data includes receiving compressed and expanded image data from an image sensor, and wherein determining to process the image frame includes decompressing and expanding the compressed and expanded image data.

3. The method of claim 2, further comprising receiving camera configuration information indicating that the image sensor is configured to perform intra-sensor compression expansion to generate compressed and expanded image data, and decompressing and expanding the compressed and expanded image data based on the camera configuration information indicating that the image sensor is configured to perform intra-sensor compression expansion.

4. The method according to claim 1, wherein the first bit width and the second bit width are the same bit width.

5. The method according to claim 1, wherein the first bit width is 12 bits, the second bit width is 12 bits, and the output bit width is 14 bits.

6. The method according to claim 1, wherein the plurality of image frames further comprises a third image frame having a third bit width, wherein the first bit width is 12 bits, the second bit width is 12 bits, the third bit width is 12 bits, and the output bit width is 18 bits.

7. The method of claim 1, wherein combining the plurality of image frames comprises applying a high dynamic range (HDR) fusion operation to the plurality of image frames by inputting the plurality of image frames as multiple different exposures of the same scene.

8. The method according to claim 1, wherein the plurality of image frames include different displacement bit representations of the same scene.

9. The method of claim 1, wherein the first image frame comprises a value consisting of a first subset of the most significant bits of the representation of the scene, and wherein the second image frame comprises a value consisting of a second subset of the least significant bits of the representation of the scene.

10. The method of claim 1, wherein determining the image frames to be processed is performed without aligning the plurality of image frames for combination.

11. An apparatus comprising: Memory, the memory storing processor-readable code; and At least one processor, coupled to the memory, is configured to execute processor-readable code to cause the at least one processor to perform operations, the operations including: The processor receives first image data comprising multiple image frames, the multiple image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the multiple image frames represent the same scene; as well as A processed image frame is determined to have an output bit width that is higher than the first bit width and higher than the second bit width, the processed image frame being obtained by combining the plurality of image frames to obtain the output bit width.

12. The apparatus of claim 11, wherein receiving the first image data includes receiving compressed and expanded image data from an image sensor, and wherein determining to process the image frame includes decompressing and expanding the compressed and expanded image data.

13. The apparatus of claim 12, further comprising receiving camera configuration information indicating that the image sensor is configured to perform intra-sensor compression expansion to generate compressed image data, and decompressing the compressed image data based on the camera configuration information indicating that the image sensor is configured to perform intra-sensor compression expansion.

14. The apparatus of claim 11, wherein the first bit width and the second bit width are the same bit width.

15. The apparatus of claim 11, wherein the first bit width is 12 bits, the second bit width is 12 bits, and the output bit width is 14 bits.

16. The apparatus of claim 11, wherein the plurality of image frames further comprises a third image frame having a third bit width, wherein the first bit width is 12 bits, the second bit width is 12 bits, the third bit width is 12 bits, and the output bit width is 18 bits.

17. The apparatus of claim 11, wherein combining the plurality of image frames includes applying a high dynamic range (HDR) fusion operation to the plurality of image frames by inputting the plurality of image frames as multiple different exposures of the same scene.

18. The apparatus of claim 11, wherein the plurality of image frames include different displacement bit representations of the same scene.

19. The apparatus of claim 11, wherein the first image frame comprises a value consisting of a first subset of the most significant bits of the representation of the scene, and wherein the second image frame comprises a value consisting of a second subset of the least significant bits of the representation of the scene.

20. The apparatus of claim 11, wherein determining the image frames to be processed is performed without aligning the plurality of image frames for combination.

21. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations, the operations including: The processor receives first image data comprising multiple image frames, the multiple image frames including at least a first image frame having a first bit width and a second image frame having a second bit width, wherein the multiple image frames represent the same scene; as well as A processed image frame is determined to have an output bit width that is higher than the first bit width and higher than the second bit width, the processed image frame being obtained by combining the plurality of image frames to obtain the output bit width.

22. The non-transitory computer-readable medium of claim 21, wherein the plurality of image frames include different displacement bit representations of the same scene.

23. The non-transitory computer-readable medium of claim 21, wherein receiving the first image data includes receiving compressed and expanded image data from an image sensor, and wherein determining that processing an image frame includes decompressing and expanding the compressed and expanded image data, and wherein the operation further includes receiving camera configuration information indicating that the image sensor is configured to perform intra-sensor compression and expansion to produce the compressed and expanded image data, and decompressing and expanding the compressed and expanded image data based on the camera configuration information indicating that the image sensor is configured to perform intra-sensor compression and expansion.

24. The non-transitory computer-readable medium of claim 21, wherein the first bit width is 12 bits, the second bit width is 12 bits, and the output bit width is 14 bits.

25. The non-transitory computer-readable medium of claim 21, wherein the plurality of image frames further comprises a third image frame having a third bit width, wherein the first bit width is 12 bits, wherein the second bit width is 12 bits, wherein the third bit width is 12 bits, and wherein the output bit width is 18 bits.

26. An image capturing device, the image capturing device comprising: An image sensor configured to output a single exposure of a scene as a first image frame having a first bit width and a second image frame having a second bit width, wherein the first bit width and the second bit width are each lower than the sensor bit width captured by the image sensor; Memory, the memory storing processor-readable code; and At least one processor, coupled to the memory and the image sensor, is configured to execute processor-readable code to cause the at least one processor to perform operations, said operations including: Receive first image data comprising multiple image frames, wherein the multiple image frames include the first image frame and the second image frame; as well as A processed image frame is determined to have an output bit width that is higher than the first bit width and higher than the second bit width, the processed image frame being obtained by combining the plurality of image frames to obtain the output bit width.

27. The image capture apparatus of claim 26, wherein the at least one processor comprises at least one image signal processor, the at least one image signal processor comprising an image front-end (IFE) coupled to the image sensor and an image processing engine (IPE) coupled to the image front-end (IFE), wherein the image processing engine (IPE) includes a high dynamic range (HDR) fusion module configured to perform combining the plurality of image frames.

28. The image capture device of claim 26, wherein the plurality of image frames include different displacement bit representations of the scene.

29. The image capture device of claim 26, wherein the first bit width is 12 bits, the second bit width is 12 bits, and the output bit width is 14 bits.

30. The image capture device of claim 26, wherein the plurality of image frames further comprises a third image frame having a third bit width, wherein the first bit width is 12 bits, wherein the second bit width is 12 bits, wherein the third bit width is 12 bits, and wherein the output bit width is 18 bits.

Images