Automatic IO test method and system applied to FPGA chip

Abstract

The application relates to the field of integrated circuit technology, and relates to an automatic IO test method and system applied to an FPGA chip, which comprises the following steps: acquiring a pin layout corresponding to a packaging type and an electrical standard corresponding to an IO type, referencing the IO information, generating an engineering file and a constraint file of a test type according to the pin layout and the electrical standard, setting a chip model according to an FPGA chip model and a packaging type in an EDA tool environment, referencing the engineering file and the constraint file to synthesize and realize, obtaining a log log, judging whether code points can be correctly generated according to the log log, debugging the test type if an error or a serious warning occurs during generation, until the code points can be correctly generated, converting the correct code points into a machine test AVC file, generating a test vector file according to the constraint file, and performing ATE machine test according to the machine test AVC file, the test vector file and test port information. The application can improve the IO test efficiency of the current FPGA chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to an automatic IO test method and system applied to an FPGA chip. BACKGROUND

[0002] In an integrated circuit, the IO interface circuit of an FPGA (Field Programmable Gate Array) is a key physical interface for data interaction between the FPGA chip and external circuits. In an FPGA chip, ComboIO (combined input and output interface) mainly includes HRIO (High Range I / O) and HPIO (High Performance I / O), each of which has its own unique interface standard and characteristics. In order to adapt to various application scenarios, ComboIO is compatible with dozens of level standards and more than a dozen characteristics, which brings great challenges to the production testing of chips.

[0003] After searching, the closest prior art invention with the invention disclosure number CN111338326B has the invention name of "a device and method for testing FPGA general IO interface", but this invention does not disclose an automatic code stream and vector file generation system for ComboIO testing of an FPGA chip.

[0004] In a traditional manual or semi-automatic process test, in order to fully cover each level standard and port characteristic, it is necessary to build a test project for each level standard and the corresponding test vector, which is a time-consuming and error-prone large project. Therefore, the current IO test method for an FPGA chip has the problem of low test efficiency. SUMMARY

[0005] The present application provides an automatic IO test method and system applied to an FPGA chip, which mainly aims to improve the IO test efficiency of the current FPGA chip.

[0006] To achieve the above purpose, the present application provides an automatic IO test method applied to an FPGA chip, which comprises:

[0007] receiving the FPGA chip model, package type, IO type and test type input by the user, obtaining IO information, wherein the IO information includes the number of banks, the number of IOs and the number of IO classifications;

[0008] obtaining the pin layout corresponding to the package type and the electrical standard corresponding to the IO type, referencing the IO information, and generating the engineering file and the constraint file of the test type according to the pin layout and the electrical standard;

[0009] The pre-built TCL script is used to run the pre-built EDA tool to obtain an EDA tool environment, in which a chip model is set according to the FPGA chip model and the package type, and synthesis and implementation are performed by referring to the engineering file and the constraint file to obtain a log;

[0010] According to the log, it is judged whether the preset code point can be correctly generated;

[0011] If the code point cannot be correctly generated, the test type is debugged according to the EDA tool until the correct code point is obtained;

[0012] If the code point can be correctly generated, the correct code point is obtained;

[0013] The correct code point is converted into a preset machine test AVC file by using a preset conversion environment, a test vector file is generated according to a constraint file, and test port information is output;

[0014] The ATE machine test is performed according to the machine test AVC file, the test vector file and the test port information, and the automatic IO test applied to the FPGA chip is completed.

[0015] Optionally, the test type includes an HRIO type test and an HPIO type test, wherein the HRIO type test includes an IO_DC test, an IO_TERM test, an IO_LEAKAGE test, an IO_FUNC test and an IO_PULLTYPE test; and the HPIO type test includes an IO_DC test, an IO_TERM test, an IO_LEAKAGE test, an IO_FUNC test, an IO_PULLTYPE test and an IO_DCI test.

[0016] Optionally, the IO information is referred to, and the engineering file and the constraint file of the test type are generated according to the pin layout and the electrical standard, including:

[0017] The IO information is referred to, and the RTL engineering corresponding to the test type is established according to the pin layout and the electrical standard to obtain an engineering file, wherein the RTL engineering calls a source language of ComboIO to build;

[0018] The RTL engineering test content corresponding to the RTL engineering is obtained, and the constraint file is added according to the RTL engineering test content, ComboIO, IO level standard, ComboIO attribute, bit stream compression attribute and preset other attributes, to obtain a constraint file, wherein the ComboIO attribute includes a pull-up attribute and a pull-down attribute, and the other attributes include an internal reference configuration.

[0019] Optionally, the determining whether the preset code point can be correctly generated according to the log file includes:

[0020] The ERROR information and the CRITICAL WARNING information in the log file are extracted by using a pre-built log error warning extraction program in a TCL script, and it is determined whether the ERROR information or the CRITICAL WARNING information exists in the log file.

[0021] If the ERROR information or the CRITICAL WARNING information exists in the log file, the code point cannot be correctly generated.

[0022] If the ERROR information or the CRITICAL WARNING information does not exist in the log file, the code point can be correctly generated.

[0023] Optionally, the debugging the test type according to the EDA tool until the correct code point is obtained includes:

[0024] According to the log file, the EDA tool is run to perform fault diagnosis and fault positioning on the test type until the correct code point is obtained.

[0025] Optionally, the generating the test vector file according to the constraint file and outputting the test port information includes:

[0026] When the test type is an IO_DC test or an IO_FUNC test, the test vector verification is performed on the test type to obtain a test vector file of the IO_DC test or a test vector file of the IO_FUNC test, wherein the test vector file of the IO_DC test is divided into a test vector of a single-ended IO, a test vector of an IO with an external reference voltage, and a test vector of a differential level IO according to a preset level standard.

[0027] The test port information is output according to the test type.

[0028] Optionally, after the generating the test vector file according to the constraint file and outputting the test port information, the method further includes:

[0029] When the test type is an IO_TERM test, an IO_LEAKAGE test, an IO_PULLTYPE test, or an IO_DCI test, the test port and a Limit value are set in a pre-built ATE machine according to the test port information.

[0030] Optionally, the test vector of the single-ended IO includes a test vector of an LVCMOS12 level standard, a test vector of an LVCMOS15 level standard, and a test vector of an LVCMOS18 level standard.

[0031] The IO test vector with external reference voltage includes: a test vector of SSTL level standard, a test vector of HSTL level standard and a test vector of HSUL level standard.

[0032] The IO test vector of differential level includes: a test vector of DIFF_SSTL level standard, a test vector of DIFF_HSTL level standard and a test vector of LVDS level standard.

[0033] Optionally, the IO_DC test includes: LVCMOS12 level standard test.

[0034] The IO_TERM test includes: terminal resistance test and differential resistance test, wherein the level configuration standard of the terminal resistance test is SSTL_18 level standard, and the level configuration standard of the differential resistance test is LVDS25 level standard.

[0035] The IO_LEAKAGE test includes: high-voltage leakage test, and the level configuration standard of the high-voltage leakage test is LVCMOS33.

[0036] The IO_FUNC test includes: IBUFDISABLE test.

[0037] The IO_PULLTYPE test includes: weak pull-up current test of LVCMOS33.

[0038] The IO_DCI test includes: source matching resistance test.

[0039] To achieve the above object, the application further provides an automatic IO test system applied to an FPGA chip, comprising:

[0040] An engineering file and constraint file generation module is configured to receive a FPGA chip model, a package type, an IO type and a test type input by a user, acquire IO information, wherein the IO information includes a number of banks, a number of IOs and a number of IO classifications, acquire a pin layout corresponding to the package type and an electrical standard corresponding to the IO type, reference the IO information, generate an engineering file and a constraint file of the test type according to the pin layout and the electrical standard, and generate a log.

[0041] A log acquisition module is configured to run a pre-constructed EDA tool by using a pre-constructed TCL script to obtain an EDA tool environment, set a chip model in the EDA tool environment according to the FPGA chip model and the package type, perform synthesis and implementation by referencing the engineering file and the constraint file to obtain a log.

[0042] The correct code point acquisition module is configured to determine whether the preset code point can be correctly generated according to the log, debug the test type according to the EDA tool until the correct code point is obtained if the code point cannot be correctly generated, and obtain the correct code point if the code point can be correctly generated.

[0043] The ATE machine test module is configured to convert the correct code point into a preset machine test AVC file by using a preset transcoding environment, generate a test vector file according to a constraint file, and output test port information; and perform ATE machine test according to the machine test AVC file, the test vector file, and the test port information.

[0044] To solve the above problems, the application further provides an electronic device, which comprises:

[0045] The memory stores at least one instruction, and the processor executes the instruction stored in the memory to realize the automatic IO test method for the FPGA chip.

[0046] To solve the above problems, the application further provides a computer readable storage medium, which stores at least one instruction, and the at least one instruction is executed by a processor in an electronic device to realize the automatic IO test method for the FPGA chip.

[0047] The application is to solve the problems described in the background art. First, the engineering files and constraint files of each test type need to be generated. When generating the engineering files and constraint files, the FPGA chip model, package type, IO type and test type input by the user need to be received, and the IO information needs to be obtained, wherein the IO information includes the number of banks, the number of IOs and the number of IO classifications. Then, the pin layout corresponding to the package type and the electrical standard corresponding to the IO type are obtained. At this time, the IO information can be referenced, and the engineering files and constraint files of each test type are generated according to the pin layout and electrical standard. Since the correct code points need to be generated, which can be judged according to the log log, the EDA tool environment is obtained by running the EDA tool using the TCL script. Then, in the EDA tool environment, the chip model is set according to the FPGA chip model and the package type. Finally, the synthesis and implementation are performed by referencing the engineering files and constraint files, and the log log is obtained. At this time, it is necessary to determine whether the code points can be correctly generated according to the log log. If the code points cannot be correctly generated, the test type can be debugged according to the EDA tool until the correct code points are obtained. If the code points can be correctly generated, the correct code points are directly obtained. When the correct code points are obtained, ATE machine testing needs to be performed. Specifically, the correct code points are converted into a preset machine testing AVC file by using a conversion environment. Then, the test vector file is generated according to the constraint file, and the test port information is output. Finally, the ATE machine testing is performed according to the machine testing AVC file, the test vector file and the test port information. Therefore, the application can improve the IO test efficiency of the current FPGA chip. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 The flowchart of the automatic IO test method applied to the FPGA chip provided by an embodiment of the application is shown.

[0049] Figure 2 The automatic code point and test vector file generation flowchart provided by an embodiment of the application is shown.

[0050] Figure 3 The user demand receiving schematic diagram provided by an embodiment of the application is shown.

[0051] Figure 4 The function module diagram of the automatic IO test system applied to the FPGA chip provided by an embodiment of the application is shown.

[0052] Figure 5 The structure schematic diagram of the electronic device for implementing the automatic IO test method applied to the FPGA chip provided by an embodiment of the application is shown.

[0053] Explanation of reference numerals in the attached figures:

[0054] 10. Electronic device; 11. Processor; 12. Memory; 13. Bus.

[0055] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0056] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0057] This application provides an automated I / O testing method for FPGA chips. The executing entity of the automated I / O testing method for FPGA chips includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the automated I / O testing method for FPGA chips can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0058] Reference Figure 1 The diagram shown is a flowchart illustrating an automated I / O testing method for FPGA chips according to an embodiment of the present invention. In this embodiment, the automated I / O testing method for FPGA chips includes:

[0059] S1. Receive the FPGA chip model, package type, IO type and test type input by the user, and obtain IO information, wherein the IO information includes: number of banks, number of IOs and number of IO categories.

[0060] Understandably, the FPGA chip model refers to a standardized device identifier used to precisely describe the intrinsic logic characteristics of the FPGA chip. The package type refers to a standardized device identifier that uniquely identifies the package form, number of pins, physical size, and pin layout of the FPGA chip. The I / O type refers to a predefined electrical specification used to define a series of electrical characteristics of the FPGA chip's physical pins when used as inputs or outputs, including signal voltage, current, reference level, and termination method.

[0061] Further, the test type refers to a structured command for specifying one or more IO function characteristics or electrical parameters that need to be verified, which determines the RTL design, constraint file and ATE test program that should be automatically generated by the system. The IO information refers to a set of statistical data about the number and distribution of physical IO resources of the chip after the FPGA chip model and package type are determined, which is automatically extracted by the system. The Bank number refers to the total number of independent power groups into which the user IO pins are physically divided under the FPGA chip model and package type. The IO number refers to the total number of input / output pins that can be freely configured and used by the user under the FPGA chip model and package type. The IO classification number refers to the specific number of each category after the total IO pins are classified according to physical capabilities and supported signal types.

[0062] For example, the IO information of a certain chip model is as follows:

[0063] IO_Bank = 5 # a total of 5 Banks;

[0064] IO_BANK = 5 # a total of 5 Banks;

[0065] IO_ALL = 250 # a total of 250 IO ports in 5 Banks;

[0066] IO_EXVREF = 10 # a total of 10 external reference IO ports in 5 Banks;

[0067] IO_TOPSING = 5 # the top IO in each Bank is a single-ended IO, so there are 5 top single-ended IOs;

[0068] IO_BOTSING = 5 # the bottom IO in each Bank is a single-ended IO, so there are 5 bottom single-ended IOs;

[0069] IO_SING = $((IO_ALL)) # all IOs can be used as single-ended IOs;

[0070] IO_SING_VREF = $(((IO_ALL-IO_EXVREF))) # if an external reference voltage input is used, the total number of reference IOs that can be used = the total number of IOs - the number of external reference IOs.

[0071] IO_DIFF = $(((IO_ALL-IO_TOPSING-IO_BOTSING))) # the number of IOs that can be used as differential IOs = the total number of IOs - the number of top single-ended IOs - the number of bottom single-ended IOs.

[0072] In the embodiment of the present application, the test types include HRIO type test and HPIO type test, wherein the HRIO type test includes IO_DC test, IO_TERM test, IO_LEAKAGE test, IO_FUNC test and IO_PULLTYPE test; the HPIO type test includes IO_DC test, IO_TERM test, IO_LEAKAGE test, IO_FUNC test, IO_PULLTYPE test and IO_DCI test.

[0073] In detail, the user requirement receiving schematic diagram can refer to Figure 3 The HRIO type test refers to the electrical characteristic and functional compliance verification of the specific IO Bank of the high range IO (HRIO). The IO Bank refers to the basic unit of grouping management of the physical input / output (IO) pin on the FPGA chip. The high range IO refers to the IO pin of the IO Bank power supply supporting the wide working voltage range from 1.2V-3.3V, internally containing high voltage detection, voltage protection and other modules. The HPIO type test refers to the electrical characteristic and functional compliance verification of the specific IO Bank of the high performance IO (HPIO). The high performance IO refers to the high performance ComboIO pin optimized for high-speed applications, the working voltage range of the IO Bank is 1.2V-1.8V, internally containing digital impedance, voltage equalization module. The ComboIO refers to the combined input / output interface, that is, the IO resource that can be combined and configured on the FPGA chip. ComboIO is the key interface for the chip to interact with external devices, responsible for the input, output and processing of signals, and the IO configuration directly affects the performance, signal integrity and reliability of the system.

[0074] Further, the IO_DC test (IO direct current characteristic test) refers to a comprehensive test of whether the basic and static direct current electrical parameters of the IO pin of the FPGA chip comply with the JEDEC (Solid State Technology Association) specification when complying with a specific level standard (such as LVCMOS12), the level standard referring to a rule of defining the voltage range of high and low levels in a circuit, which is used for distinguishing the logic state (0 / 1) of a digital signal and is the basis for compatibility between chips, interfaces, and communication protocols. The level standards that can be compatible in the FPGA include LVCMOS, SSTL, HSTL, DIFF_SSTL, DIFF_HSTL, LVDS, TMDS, and the like. The IO_DC test includes an input buffer IBUF test and an output buffer OBUF test. When the input buffer IBUF test is performed, the input low voltage VIL and the input high voltage VIH need to be tested to ensure the correctness of the input signal recognition. When the output buffer OBUF test is performed, the output low voltage VOL and the output high voltage VOH are measured under the condition of meeting the specified output drive current (output low current IOL and output high current IOH) load.

[0075] In detail, the IO_TERM test (IO termination resistance test) refers to a test of the resistance accuracy parameter of the programmable on-chip termination resistance integrated in the IO module of the FPGA chip. The IO_TERM test only tests the termination characteristics of the input end of the chip. The IO_TERM test is used to test the terminal resistance or differential resistance of the ComboIO.

[0076] As can be explained, the IO_LEAKAGE test (IO leakage current test) refers to a test of the non-expected and tiny direct current flowing in or out of the IO pin of the FPGA chip in a static (non-switching) mode. The IO_LEAKAGE test is used to test the leakage current of the ComboIO pad when pulled up or pulled down.

[0077] Further, the IO_FUNC test (IO functional characteristic test) refers to a digital function test for verifying whether the special control function or logic characteristic possessed by the FPGA IO module works as expected. The IO_FUNC test is used to test the functions of the IO, including IBUFDISABLE (configuration attribute of controlling the enable / disable state of the input buffer IBUF), KEEPER (holding attribute of the IO port), INTERVREF (internal reference voltage attribute), OBUFT (tri-state attribute of the OBUF), and the like.

[0078] It should be understood that the IO_PULLTYPE test (IO pull-up and pull-down function test) refers to a digital function and parameter mixed test for verifying whether the programmable weak pull-up / pull-down resistance function integrated inside the FPGA IO module is normal. The IO_PULLTYPE test is used for testing the current value of the ComboIO when the weak pull-up or weak pull-down is configured.

[0079] It can be understood that the IO_DCI test (digitally controlled impedance test) refers to a comprehensive test specially used for verifying the accuracy and synergy of the Digitally Controlled Impedance (DCI) advanced function in the Xilinx FPGA. The IO_DCI test is used for testing the matching resistance value of the DCI matching in the IO.

[0080] In the embodiment of the application, the IO_DC test comprises: an LVCMOS12 level standard test.

[0081] The IO_TERM test comprises: a termination resistance test and a differential resistance test, wherein the level configuration standard of the termination resistance test is SSTL_18 level standard, and the level configuration standard of the differential resistance test is LVDS25 level standard.

[0082] The IO_LEAKAGE test comprises: a high-voltage leakage test, and the level configuration standard of the high-voltage leakage test is LVCMOS33.

[0083] The IO_FUNC test comprises: an IBUFDISABLE test.

[0084] The IO_PULLTYPE test comprises: a weak pull-up current test of LVCMOS33.

[0085] The IO_DCI test comprises: a source-end matching resistance test.

[0086] Further, the terminal resistance test is used to verify whether the on-chip parallel terminal resistance provided by the FPGA IO module for single-ended signal standard meets the nominal value. The differential resistance test is used to verify whether the on-chip differential terminal resistance provided by the FPGA IO module for differential signal standard and connected across the differential pair (P / N) pin meets the nominal value. The LVCMOS12 level standard test refers to a test for verifying whether the IO pin of the FPGA chip meets the specification defined by JEDEC when configured as the LVCMOS12 level standard. The SSTL_18 level standard refers to a reference voltage type single-ended signal IO standard specially designed for high-speed memory interfaces such as DDR2 SDRAM, and its working power supply voltage is 1.8V. The LVDS25 level standard refers to a low-voltage differential signal interface technology using 2.5V power supply defined by ANSI / TIA / EIA-644 standard, which transmits data at high speed, low power consumption and high anti-interference through a pair of inverted transmission lines.

[0087] In detail, the high-voltage leakage test refers to a test for measuring the direct current leakage current by applying a direct current higher than the normal rated working voltage to the IO pin. The LVCMOS33 refers to a low-voltage CMOS digital signal interface standard using 3.3V power supply defined by JEDEC. The IBUFDISABLE test refers to a test for verifying the IBUFDISABLE configurable attribute of the FPGA IO module. The weak pull-up current test of the LVCMOS33 refers to a test for verifying whether the weak pull-up resistor function inside the IO pin configured as the LVCMOS33 standard is enabled and can work normally and generate a pull-up current within the specification range. The source-end matching resistance test refers to a direct current parameter characterization test for verifying whether the actual resistance value of the programmable series terminal resistance integrated inside the FPGA output driver meets the nominal value.

[0088] S2, acquiring the pin layout corresponding to the packaging type and the electrical standard corresponding to the IO type, referencing the IO information, and generating the engineering file and the constraint file of the test type according to the pin layout and the electrical standard.

[0089] It can be understood that the pin layout refers to a physical mapping layout of the logical function port on the FPGA chip and the physical pin. The electrical standard refers to the voltage, current and other electrical standards of the IO pin during signal transmission. The engineering file refers to a file created and managed by an EDA tool to organize, manage and track the related source files, configuration information and tool settings included in a specific FPGA design project. The constraint file refers to a text file conveying the specific requirements of the FPGA physical implementation and performance timing to the EDA tool.

[0090] In the embodiment of the present application, the IO information is referenced to generate the engineering file and the constraint file of the test type according to the pin layout and the electrical standard, comprising:

[0091] The IO information is referenced to establish the RTL engineering corresponding to the test type according to the pin layout and the electrical standard, to obtain an engineering file, wherein the RTL engineering calls the source language of ComboIO to build;

[0092] The RTL engineering test content corresponding to the RTL engineering is obtained, and the constraint file is added according to the ComboIO, the IO level standard, the ComboIO attribute, the bit stream compression attribute and the other preset attributes of the RTL engineering test content, to obtain a constraint file, wherein the ComboIO attribute comprises a pull-up attribute and a pull-down attribute, and the other attributes comprise an internal reference configuration.

[0093] It can be understood that the RTL (Register Transfer Level) engineering refers to a source code collection for constructing the logic function of a digital system by describing the transmission and processing behavior of data between registers in a digital circuit using a hardware description language. The engineering file refers to a project index file created by an EDA tool, recording and managing the resources required by each test type. The RTL engineering test content refers to key information generated by parsing the RTL engineering to guide the generation of a constraint file. The ComboIO of the constraint file refers to the file part of the constraint file allocated to the physical position of the IO port, used to represent the pin allocation constraint. The IO level standard refers to the electrical behavior specification of the IO port in the constraint file. The ComboIO attribute refers to the additional attribute set for the IO port in the constraint file, used to control its internal advanced function or specific behavior. The bit stream compression attribute refers to the engineering setting for optimizing the size of the generated code point file. The internal reference configuration refers to a specific attribute for enabling and setting the internal reference voltage generator of the FPGA chip. The source language refers to the most basic and indivisible hardware functional unit in the FPGA design library.

[0094] It can be understood that when generating the engineering file of each test type by referencing the IO information, a script is used to establish an RTL engineering for each test type, to ensure that the generated test scheme can verify each available user IO pin on the FPGA chip.

[0095] Further, when the test type is IO_DC test, the RTL engineering can be: when performing LVCMOS12 level standard test, to achieve efficient parallel test, 250 IOs packaged out are divided into two groups, and 125 independent input / output pairs (I / O Pairs) are constructed, each of which is composed of an IO from the first group (configured as input) and an IO from the second group (configured as output), so as to realize parallel driving and measurement on AET (automatic test equipment).

[0096] Specifically, all 250 IOs packaged out are divided into input[124:0] and output[124:0], and then input[i] and output[i] are combined into a pair of input / output pairs, a total of 125 input / output pairs, at this time, the input low level VIL of each input is tested, the input high level VIH is tested, and the output low level VOL of each output is tested, the output high level VOH is tested, the output low current IOL is tested, and the output high current IOH is tested.

[0097] In detail, when performing LVCMOS12 level standard test, it is divided into forward test mode and reverse test mode, wherein when performing forward test mode, in each I / O pair, one pin is configured as input and the other is configured as output, ATE performs VIL / VIH parameter test on the pin configured as input, and at the same time, performs VOL / VOH parameter test on the pin configured as output under specified IOL / IOH load condition. When performing reverse test mode, it is necessary to reverse the I / O pair in the forward test mode and re-perform the parameter test in the forward test mode. It can be understood that the LVCMOS12 level standard test is divided into two kinds, the first kind is liuo (lower input and upper output) test, that is, in each input / output pair, the lower pad is configured as input and the upper pad is configured as output, and the second kind is uilo (upper input and lower output) test, that is, in each input / output pair, the upper pad is configured as input and the lower pad is configured as output. The pad refers to the last physical metal interface on the FPGA chip which can be directly contacted by the probe or socket of ATE.

[0098] In detail, when the test type is IO_TERM test, the RTL engineering refers to the following: the IO_TERM test is divided into terminal resistance test and differential resistance test. In the terminal resistance test, taking SSTL_18 level standard as an example, all single-ended IO (IO_SING) needs to be configured to use 250 input ports of the SSTL_18 level standard of the internal reference voltage, which can be represented as input[249:0], and different internal terminal resistance attributes are applied to all single-ended IOs under test, which can be INTERM_40 / 50 / 60 attributes corresponding to 40 / 50 / 60 ohm nominal values (i.e. internal terminal resistance 40 / 50 / 60 ohm), and the terminal resistance of all IOs is tested in each engineering. In the differential resistance test, taking LVDS25 level standard as an example, all 240 IO_DIFF (differential pair IO) need to be configured to LVDS25 level standard, and 240 IO_DIFF can be represented as inputn[119:0] and inputp[119:0], and the terminal resistance of all DIFF IOs can be tested.

[0099] Further, when the test type is IO_LEAKAGE test, the RTL engineering can refer to the following: taking high-voltage leakage test as an example, during the test, first, two independent test projects are created through an automatic process, and the 250 IO pins under test are configured to be in input (IBUF) mode or high-impedance output (OBUF Tri-stated) mode under LVCMOS33 standard. Subsequently, for each configuration, the ATE will apply 3.465V (high-voltage stress) and 0V direct current to all IO pads in turn, and accurately measure the direct current leakage current flowing through the pad under each voltage condition to ensure that the value is within the specification range.

[0100] It can be understood that when the test type is IO FUNC test, the RTL engineering can refer to the following: taking IBUFDISABLE test as an example, 250 IOs are tested twice, in the first test, 247 IOs of the IOs are configured as SSTL 18 level standard input with ibufdisable function, i.e. input [246:0]; one ibufdisable port is configured; one and logic output port out_and is configured, i.e. and output of all input ports; one or logic output port out_or is configured, i.e. or output of all input ports. In the second test, the ibufdisable port, the out_and port and the out_or port verified in the first test are configured as SSTL 18 level standard input with ibufdisable function, and three of the other ports are configured as ibufdisable port, out_and port and out_or port.

[0101] In detail, when the test type is IO_PULLTYPE test, the RTL engineering can refer to the following: taking weak pull-up current test of LVCMOS33 as an example, 250 ComboIOs need to be configured as tri-state input ports of LVCMOS33 level standard, and pull-up function is configured, pad is grounded during test, and pad current is measured.

[0102] Further, when the test type is IO_DCI test, the RTL engineering can refer to the following: taking source-end matching resistance test as an example, 247 ports of 250 IOs are configured as output ports of LVDCI 18 level, two of the remaining three IOs are top and bottom IO calibration ports, and one is an input port, and the values of 247 output ports output [246:0] are equal to the value of the input port. During measurement, calibration resistance needs to be connected to the IO calibration port, VCCO / 2 voltage is applied to the pads of 247 output ports output [246:0], 0 and 1 are input to the input port input respectively, and the currents when the output high level and low level are measured, and then the resistance value is calculated through voltage / current.

[0103] In detail, when the test type is IO_DC test, the constraint file can refer to the following: in the IO_DC test of the LVCMOS12 level standard, the physical position of the port needs to be allocated first, and 125 input ports and 125 output ports defined in the RTL project are mapped to the physical pins of the FPGA, specifically, the constraint ports of input[124:0] and output[124:0] are added in turn, and then the voltage standards of the constraint ports are set to the LVCMOS12 level standard, specifically, the voltage standards of input[124:0] and output[124:0] are set to LVCMOS12, and it needs to be noted that the test ports of liuo and uilo are reversed in the construction process of the constraint file.

[0104] When the test type is IO_TERM test, the constraint file can refer to the following: when generating the constraint file for IO_TERM test, different rules are applied according to different test sub-items, specifically, when the test sub-item is terminal resistance test, first, the pins of 250 input ports are allocated, and the level standard is set to SSTL_18 level, then the internal reference voltage (INTERNAL_VREF) is enabled, and the corresponding INTERM attribute is iteratively added according to the test target (such as 40 / 50 / 60 ohms), specifically, the constraint ports of input[249:0] are added in turn, then the level standard of input[i] is set to SSTL_18 level, and finally the internal reference voltage is added, and the INTERM_40 / 50 / 60 attribute is added; when the test sub-item is differential resistance test, the pins of 120 pairs of differential ports need to be allocated, and the level standard is set to LVDS25, and the built-in ohmic terminal resistance of each pair of differential input is enabled by adding the DIFF_TERM=“TRUE” attribute. Specifically, the constraint ports of inputn[119:0] and inputp[119:0] are added in turn, then the level standard of inputn[119:0] and inputp[119:0] is set to LVDS25, and finally the DIFF_TERM attribute is added.

[0105] Further, when the test type is IO_LEAKAGE test, the constraint file can refer to the following: when generating the constraint file for IO_LEAKAGE test, first, all logical ports are mapped to the physical pins of the FPGA through port physical position allocation, and then the voltage standards of the logical ports are uniformly set to LVCMOS33, specifically, the constraint ports of input[249:0] are added in turn, and then the voltage standards of input[249:0] are added in turn as LVCMOS33.

[0106] It should be understood that when the test type is IO_FUNC test, the constraint file can refer to the following: When generating the constraint file for IO_FUNC test, the first test requires physical pin assignment to the ports in the RTL project (e.g., input[246:0], ibufdisable port, out_and / out_or port), then setting the port voltage standard to SSTL_18, automatically adding the corresponding internal reference voltage configuration, and adding the IBUFDISABLE attribute. Specifically, the first test requires adding the constraint ports for input[246:0], ibufdisable, out_and, and out_or in sequence; then adding the voltage standard to SSTL_18 in sequence; finally adding the internal reference voltage and adding the IBUFDISABLE attribute. The second test will repeat the same constraint logic, only rotating the port roles during the physical pin assignment stage.

[0107] In detail, when the test type is IO_PULLTYPE test, the constraint file can refer to the following: When generating the constraint file for IO_PULLTYPE test, it is necessary to first perform physical pin assignment on the 250 input ports under test, then set the voltage standard of these input ports under test to LVCMOS33, and finally add the PULLTYPE=PULL_UP attribute. Specifically, it is necessary to add the constraint ports of input[249:0] in sequence, then add the voltage standard of LVCMOS33 in sequence, and finally add the PULLTYPE=PULL_UP attribute.

[0108] It should be explained that when the test type is IO_DCI test, the constraint file can refer to the following: When generating the constraint file for IO_DCI test, it is necessary to first assign physical pins to different ports: including 247 output ports under test, 1 driver input port, and reserve two reference pins for DCI calibration. In terms of electrical standard settings, the voltage standard of the output port under test is configured as LVDCI_18, while the level standard of the driver input port is configured as LVCMOS18. Specifically, in the IO_DCI test of LVCMOS12: first add the constraint ports of output[246:0] and input in sequence, then add the voltage standard of output[246:0] as LVDCI_18 and the level standard of input as LVCMOS18 in sequence, the reference IO is not configured, and finally configure the DCI cascading attribute to cascade the DCI of each bank.

[0109] S3, running the pre-built EDA tool by using the pre-built TCL script to obtain an EDA tool environment, in which a chip model is set according to the FPGA chip model and the packaging type, and the engineering file and the constraint file are referenced for synthesis and implementation to obtain a log.

[0110] In the embodiment of the present application, the TCL (Tool Command Language) script refers to a TCL language command text file containing the whole automation construction and verification process. The EDA tool refers to a software suite for FPGA design, synthesis, implementation and verification, which is a kind of FPGA adaptive SoC design suite. The EDA tool is a highly integrated development environment covering the whole hardware development process from design input, synthesis, implementation (layout and wiring) to verification and debugging. The EDA tool environment refers to a working environment created in the computer memory after the EDA tool is started by the TCL script, which contains the complete project context and can execute subsequent commands. The synthesis refers to the conversion of the hardware description language into a logic connection graph composed of FPGA underlying logic units. Specifically, it is to translate the abstract RTL code into the basic hardware resource connection netlist of the corresponding device, only solve the function mapping, and do not care about the physical location, which is a "logical level translation". The implementation refers to the allocation of a specific physical location for each logic unit according to the logic connection graph, and the connection of the logic units by physical wiring resources. Through the actual placement of the netlist output by the synthesis into the physical units of the FPGA / chip, the layout+wiring is completed, the physical landing is solved, and the timing convergence is ensured, which is a "physical level landing". The log refers to a text file automatically generated during the execution of the synthesis and implementation of the EDA tool, which records the operation, state information, warnings and errors.

[0111] In detail, for each test type, the following steps can be completed by using the TCL script: opening the EDA tool, setting the FPGA chip model, referencing the RTL engineering file, referencing the RTL constraint file, synthesizing, implementing, and generating the corresponding code point.

[0112] S4, judging whether the preset code point can be correctly generated according to the log.

[0113] As can be explained, the code point refers to a final binary bit stream configuration file carrying complete FPGA design information and capable of being directly used for configuring a physical chip, which contains a binary data set required for configuring the FPGA into a specific hardware function.

[0114] In the embodiment of the present application, the judging whether the preset code point can be correctly generated according to the log comprises:

[0115] The ERROR information and the CRITICAL WARNING information in the log log are captured by using a pre-built log error warning capture program in a TCL script, and it is judged whether the ERROR information or the CRITICAL WARNING information exists in the log log.

[0116] If the ERROR information or the CRITICAL WARNING information exists in the log log, the code point cannot be correctly generated.

[0117] If the ERROR information or the CRITICAL WARNING information does not exist in the log log, the code point can be correctly generated.

[0118] The log error warning capture program refers to a subprogram code for text processing and pattern matching specially written in a TCL script, and the core function thereof is to automatically and programmatically check a log log file and search and extract predefined keywords indicating problems in a construction process from the log log file. The ERROR information refers to a highest priority error report information printed in a log log when an EDA tool encounters a problem that cannot be processed or recovered during execution. The CRITICAL WARNING information refers to a second highest priority warning report information printed in a log log when the EDA tool finds a very serious design problem that is extremely likely to cause a failure of a final hardware function or a performance failure.

[0119] Further, the TCL script can be built-in with a simulation code, and the log error warning capture program for capturing the ERROR information and the CRITICAL WARNING information in the log log can be written in the TCL script, so as to judge whether a program runs normally during generation of a code point.

[0120] If the code point cannot be correctly generated, S5 is executed, and the EDA tool is debugged according to the test type until a correct code point is obtained.

[0121] The correct code point refers to a code point whose generation process and final result completely meet all preset quality standards.

[0122] In the embodiment of the application, the EDA tool is debugged according to the test type until a correct code point is obtained, and the method comprises the following steps.

[0123] According to the log log, the EDA tool is run to perform fault diagnosis and fault positioning on the test type until a correct code point is obtained.

[0124] It can be understood that after the code point generation of all test projects is completed, whether there is error information and critical warning information (ERROR information and CRITICAL WARNING information) in the code point generation process can be checked by capturing the log information captured by the log error warning capture program, if there is error information and critical warning information, the error test type is diagnosed by viewing the log file and running the EDA tool, if there is no error information and critical warning information, the subsequent step is continued.

[0125] If the code point can be correctly generated, S6 is executed to obtain the correct code point.

[0126] It can be understood that if the code point can be correctly generated, that is, the log file has no error information and critical warning information, the generated code point can be used as the correct code point.

[0127] S7, the correct code point is converted into a preset machine test AVC file by using a preset conversion environment, a test vector file is generated according to a constraint file, and test port information is output.

[0128] It can be understood that the conversion environment refers to a set of software tools, scripts and pre-defined libraries for parsing FPGA design products and translating them into a format recognizable by ATE (automatic test equipment). The machine test AVC file (AutoVoltage Calibration File, automatic voltage calibration file) refers to a test vector file in ASCII text format specific to ATE test machine. The input files required in ATE machine testing include the AVC file of the correct code point and the vector AVC file. The test vector file refers to a file containing test excitation and expected response information captured from RTL function simulation for verifying the logic function of the circuit. The test port information refers to a mapping file that establishes the connection relationship between the logical signal name and the physical channel (Channel) on the ATE test head (Test Head) and the physical pin (Pin) of the device under test (DUT), also known as PINMAP file.

[0129] In the embodiment of the application, the test vector file is generated according to the constraint file, and the test port information is output, comprising:

[0130] When the test type is IO_DC test or IO_FUNC test, the test type is verified to obtain the test vector file of IO_DC test or the test vector file of IO_FUNC test, wherein the test vector file of IO_DC test is divided into single-ended IO test vector, IO test vector with external reference voltage and differential level IO test vector according to a preset level standard.

[0131] Output test port information according to the test type.

[0132] It can be understood that the test vector verification refers to a test method based on test excitation and expected response information. The specific process is as follows: the ATE drives a series of dynamically changing digital signals (test excitation) to the input pins of the FPGA according to the timing and code type in the AVC file of the machine test, at the same time or later, the ATE samples on the output pins of the FPGA, and compares the signal captured by it with the expected response defined in the test vector file. When the ATE machine is tested, the response output of the test chip is tested by applying the test vector (vector signal) to the FPGA chip, and the response output is compared with the expected result, so as to judge whether the chip meets the specification requirements.

[0133] Further, the test vector file of the IO_DC test is a set of ATE test procedures specially designed for verifying IO direct current characteristics (such as VIL / VIH, VOL / VOH), and the test vector file of the IO_FUNC test refers to a set of ATE test procedures specially designed for verifying specific digital logic functions (such as IBUFDISABLE) of IO.

[0134] In detail, the test vector of the single-ended IO refers to a general test vector template specially designed for LVCMOS and other single-ended, rail-to-rail IO standards. The test vector of the IO with external reference voltage refers to a test vector template specially designed for reference voltage type IO standards such as SSTL, HSTL and HSUL. The test vector of the differential level IO refers to a test vector template specially designed for differential IO standards such as LVDS and DIFF_SSTL.

[0135] In the embodiment of the application, the test vector of the single-ended IO includes: a test vector of the LVCMOS12 level standard, a test vector of the LVCMOS15 level standard and a test vector of the LVCMOS18 level standard;

[0136] The test vector of the IO with external reference voltage includes: a test vector of the SSTL level standard, a test vector of the HSTL level standard and a test vector of the HSUL level standard;

[0137] The test vector of the differential level IO includes: a test vector of the DIFF_SSTL level standard, a test vector of the DIFF_HSTL level standard and a test vector of the LVDS level standard.

[0138] In detail, the test vector of LVCMOS12 level standard refers to an ATE test program whose internal voltage parameters are set to comply with LVCMOS12 specification. The test vector of LVCMOS15 level standard refers to an ATE test program whose internal voltage parameters are set to comply with LVCMOS15 specification. The test vector of LVCMOS18 level standard refers to an ATE test program specially designed for LVCMOS18 specification. The test vector of SSTL level standard refers to an ATE test program specially designed for SSTL (Stub Series Terminated Logic) series standards (such as SSTL_18, SSTL_15). The test vector of HSTL level standard refers to an ATE test program specially designed for HSTL (High-Speed Transceiver Logic) series standards, which is commonly used in high-performance communications. The test vector of HSUL level standard refers to an ATE test program specially designed for HSUL (High-Speed Unterminated Logic) series standards. The test vector of DIFF_SSTL level standard refers to a differential version of the test vector of SSTL level standard, which is specially designed for clock, gating and other signals of DDR memory. The test vector of DIFF_HSTL level standard refers to a differential version of the test vector of HSTL level standard. The test vector of LVDS level standard refers to an ATE test program specially designed for LVDS (Low-Voltage Differential Signaling) standard, which is the most widely used differential standard.

[0139] In the embodiment of the present application, after the test vector file is generated according to the constraint file and the test port information is output, the method further comprises:

[0140] When the test type is IO_TERM test, IO_LEAKAGE test, IO_PULLTYPE test or IO_DCI test, the test port and Limit value are set according to the test port information in the pre-built ATE machine.

[0141] It can be understood that the ATE machine (Automatic Test Equipment) is a highly complex, computer-controlled automated test equipment specially used for quickly and accurately detecting whether the function, performance and electrical characteristics of a semiconductor chip are qualified in the large-scale production process of the chip. The test port refers to one or more physical pins designated as a specific measurement task object in the ATE test program. The Limit value refers to a pre-set specification upper and lower limit for each parameter measurement in the ATE test program, which is used to determine Pass or Fail.

[0142] S8, performing ATE machine test according to the machine test AVC file, test vector file and test port information, completing the automatic IO test applied to the FPGA chip.

[0143] It can be understood that the ATE (Automatic Test Equipment) machine test refers to a process of performing a series of automatic electrical and functional inspections on a semiconductor chip according to a machine test AVC file, a test vector file and test port information by using ATE, so as to screen out defective products and ensure product quality. The essence is an "automatic quality inspection tool" for the whole process from chip research and development to mass production, which replaces manual work to complete comprehensive detection of chip functions, performance and reliability, and is an essential link for chip mass production landing. The code point and test vector file automatic generation process diagram of FPGA chip ComboIO test can be referred to as shown in Figure 2

[0144] The embodiment of the application can realize flexible generation of test files of ComboIO of different FPGA chip models by inputting the FPGA chip model, IO type, test type and packaging type, reduce the manual input time, improve the test efficiency, and generate log logs to extract error information. By using the automatic IO test system to generate the code points and test vector files of hundreds of projects, the automatic IO test system can be adapted to FPGA chip tests of different FPGA chip models, different packaging types, different IO types and different test types, and can effectively cover all test items of IO. Further, since ComboIO has more devices externally connected to the EVB Board in the hand screening test stage, the IO state cannot be tested correctly, therefore, debugging needs to be performed on the machine in the FT stage (Final Test Phase, product test stage), and the code points and test vector files generated by using the automatic IO test system not only save the labor cost and time cost, but also reduce the probability of human error.

[0145] ​The application is to solve the problems described in the background art. First, the engineering files and constraint files of each test type need to be generated. When generating the engineering files and constraint files, the FPGA chip model, package type, IO type and test type input by the user are received, and the IO information is obtained, wherein the IO information includes the number of banks, the number of IOs and the number of IO classifications. Then, the pin layout corresponding to the package type and the electrical standard corresponding to the IO type are obtained. At this time, the IO information can be referenced to generate the engineering files and constraint files of each test type according to the pin layout and electrical standard. Since the correct code point needs to be generated, which can be judged according to the log log, the EDA tool environment is obtained by running the EDA tool using the TCL script. Then, in the EDA tool environment, the chip model is set according to the FPGA chip model and the package type. Finally, the synthesis and implementation are performed by referencing the engineering files and constraint files to obtain the log log. At this time, it is necessary to determine whether the code point can be correctly generated according to the log log. If the code point cannot be correctly generated, the test type can be debugged according to the EDA tool until the correct code point is obtained. If the code point can be correctly generated, the correct code point is directly obtained. After obtaining the correct code point, ATE machine testing needs to be performed. Specifically, the correct code point is converted into a preset machine testing AVC file using the conversion environment. Then, the test vector file is generated according to the constraint file, and the test port information is output. Finally, the ATE machine testing is performed according to the machine testing AVC file, the test vector file and the test port information. Therefore, the application can improve the IO test efficiency of the current FPGA chip.

[0146] As Figure 4 shown is a functional module diagram of an automatic IO test system applied to an FPGA chip according to an embodiment of the application.

[0147] The automatic IO test system 100 applied to the FPGA chip according to the application can be installed in an electronic device. According to the implemented functions, the automatic IO test system 100 applied to the FPGA chip can include an engineering file and constraint file generation module 101, a log log acquisition module 102, a correct code point acquisition module 103 and an ATE machine testing module 104. The modules according to the application can also be referred to as units, which refer to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0148] The engineering file and constraint file generation module 101 is configured to receive an FPGA chip model, a package type, an IO type and a test type input by a user, acquire IO information, wherein the IO information comprises a number of banks, a number of IOs and a number of IO classifications, acquire a pin layout corresponding to the package type and an electrical standard corresponding to the IO type, reference the IO information, and generate the engineering file and the constraint file of the test type according to the pin layout and the electrical standard.

[0149] The log acquisition module 102 is configured to run a pre-built EDA tool by using a pre-built TCL script to obtain an EDA tool environment, in which a chip model is set according to the FPGA chip model and the package type, and synthesis and implementation are performed by referencing the engineering file and the constraint file to obtain a log.

[0150] The correct code point acquisition module 103 is configured to determine whether a preset code point can be correctly generated according to the log, debug the test type according to the EDA tool until a correct code point is obtained if the code point cannot be correctly generated, and acquire the correct code point if the code point can be correctly generated.

[0151] The ATE machine test module 104 is configured to convert the correct code point into a preset machine test AVC file by using a preset conversion environment, generate a test vector file according to the constraint file, and output test port information, and perform ATE machine test according to the machine test AVC file, the test vector file and the test port information.

[0152] In detail, the modules in the automatic IO test system 100 for FPGA chips in the embodiment of the present application adopt the same technical means as the automatic IO test method for FPGA chips in the embodiment of the present application described above when in use, and can produce the same technical effects, which will not be described herein again. Figure 1

[0153] As shown in FIG. 1, it is a structure schematic diagram of an electronic device for implementing the automatic IO test method for FPGA chips provided by an embodiment of the present application. Figure 5

[0154] The electronic device 1 can comprise a processor 10, a memory 11 and a bus 12, and can further comprise a computer program stored in the memory 11 and executable on the processor 10, such as an automatic IO test method for FPGA chips program.

[0155] ​​The memory 11 includes at least one type of readable storage medium, such as a flash memory, a mobile hard disk, a multimedia card, a card-type memory (e.g., an SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 11 can also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Further, the memory 11 includes both an internal storage unit and an external storage device of the electronic device 1. The memory 11 can be used to store application software and various data installed in the electronic device 1, such as a code of the automated IO test method program for an FPGA chip, and can also be used to temporarily store data that has been output or will be output.

[0156] The processor 10 can be composed of an integrated circuit in some embodiments, such as a single packaged integrated circuit or a plurality of packaged integrated circuits with the same or different functions, including one or more combinations of a central processing unit (CPU), a microprocessor, a digital processing chip, a graphics processor, and various control chips, etc. The processor 10 is a control unit of the electronic device, which connects various components of the electronic device through various interfaces and lines, executes programs or modules stored in the memory 11 (such as the automated IO test method program for an FPGA chip), and calls data stored in the memory 11 to perform various functions and process data of the electronic device 1.

[0157] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0158] Figure 5 Only the electronic device with components is shown, and those skilled in the art can understand that, Figure 5The illustrated structure does not constitute a limitation on the electronic device 1, and can include fewer or more components than illustrated, or combine certain components, or different component arrangements.

[0159] For example, although not shown, the electronic device 1 can also include a power supply (such as a battery) to power the various components, and preferably the power supply can be logically connected to the at least one processor 10 through a power management device, so that the power management device can implement functions such as charge management, discharge management, and power consumption management. The power supply can also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and any other components. The electronic device 1 can also include various sensors, Bluetooth modules, Wi-Fi modules, and the like, which are not described here.

[0160] Further, the electronic device 1 can also include a network interface, which can optionally include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), and is typically used to establish a communication connection between the electronic device 1 and other electronic devices.

[0161] Optionally, the electronic device 1 can also include a user interface, which can be a display (Display), an input unit (such as a keyboard (Keyboard)), and optionally a standard wired interface, a wireless interface. Optionally, in some embodiments, the display can be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch, etc. The display can also be appropriately referred to as a display screen or a display unit, and is used to display information processed in the electronic device 1 and to display a visualized user interface.

[0162] The application program stored in the memory 11 of the electronic device 1 is a combination of a plurality of instructions, which, when executed in the processor 10, can achieve:

[0163] Receiving a user input FPGA chip model, package type, IO type and test type, obtaining IO information, wherein the IO information includes: Bank number, IO number and IO classification number;

[0164] Obtaining the pin layout corresponding to the package type and the electrical standard corresponding to the IO type, referencing the IO information, and generating the test type engineering file and the constraint file according to the pin layout and the electrical standard;

[0165] The pre-built TCL script is used to run the pre-built EDA tool to obtain an EDA tool environment, in which, according to the FPGA chip model and the package type, the chip model is set, the engineering file and the constraint file are referenced for synthesis and implementation, and a log is obtained;

[0166] According to the log, it is judged whether the preset code point can be correctly generated or not;

[0167] If the code point cannot be correctly generated, the test type is debugged according to the EDA tool until the correct code point is obtained;

[0168] If the code point can be correctly generated, the correct code point is obtained;

[0169] The correct code point is converted into a preset machine test AVC file by using a preset conversion environment, a test vector file is generated according to a constraint file, and test port information is outputted;

[0170] The ATE machine test is performed according to the machine test AVC file, the test vector file and the test port information, and the automatic IO test applied to the FPGA chip is completed.

[0171] Specifically, the specific implementation method of the processor 10 to the above instructions can refer to Figures 1 to 5 The description of related steps in the corresponding embodiments is not repeated here.

[0172] Further, the modules / units integrated in the electronic device 1 are implemented in the form of software function units and sold or used as independent products, which can be stored in a computer readable storage medium. The computer readable storage medium can be volatile or non-volatile. For example, the computer readable medium can include any entity or device capable of carrying the computer program code, a recording medium, a U disk, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM, Read-Only Memory).

[0173] The application also provides a computer readable storage medium, which stores a computer program, and the computer program can realize the following when executed by a processor of an electronic device:

[0174] Receiving the FPGA chip model, the package type, the IO type and the test type inputted by a user, and obtaining IO information, wherein the IO information includes the number of banks, the number of IOs and the number of IO classifications;

[0175] Obtaining a pin layout corresponding to the packaging type and an electrical standard corresponding to the IO type, referencing the IO information, and generating an engineering file and a constraint file of the test type according to the pin layout and the electrical standard;

[0176] A pre-built TCL script is used to run a pre-built EDA tool to obtain an EDA tool environment, in which a chip model is set according to the FPGA chip model and the packaging type, and synthesis and implementation are performed by referencing the engineering file and the constraint file to obtain a log;

[0177] It is determined whether the preset code point can be correctly generated according to the log;

[0178] If the code point cannot be correctly generated, the test type is debugged according to the EDA tool until the correct code point is obtained;

[0179] If the code point can be correctly generated, the correct code point is obtained;

[0180] The correct code point is converted into a preset machine test AVC file by using a preset conversion environment, a test vector file is generated according to the constraint file, and test port information is output;

[0181] ATE machine test is performed according to the machine test AVC file, the test vector file and the test port information, and the automatic IO test applied to the FPGA chip is completed.

[0182] In several embodiments provided in the present application, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the above-described system embodiments are only illustrative, and actual implementation can have another division method.

[0183] The modules described as separate components can or can not be physically separated, and the components shown as modules can or can not be physical units, that is, they can be located in one place, or they can be distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment.

[0184] In addition, each functional module in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of hardware plus software functional modules.

[0185] It is apparent for a person skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, but that the present application can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit the present application, and although the present application has been described in detail with reference to the preferred embodiments, those ordinarily skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced without departing from the spirit and scope of the present application.

Claims

1. An automated IO test method applied to an FPGA chip, characterized in that, The method comprises: receiving user input FPGA chip model, package type, IO type and test type, obtaining IO information, wherein the IO information includes: Bank number, IO number and IO classification number; obtaining the pinout corresponding to the package type and the electrical standard corresponding to the IO type, referencing the IO information, and generating the engineering file and the constraint file of the test type according to the pinout and the electrical standard; running the pre-built EDA tool using the pre-built TCL script to obtain an EDA tool environment, in which, according to the FPGA chip model and the package type, the chip model is set, and the engineering file and the constraint file are referenced for synthesis and implementation to obtain a log log; determining whether the preset code point can be correctly generated according to the log log; if the code point cannot be correctly generated, debugging the test type according to the EDA tool until the correct code point is obtained; if the code point can be correctly generated, obtaining the correct code point; using a preset transcoding environment to transcode the correct code point into a preset machine test AVC file, generating a test vector file according to the constraint file, and outputting test port information; according to the machine test AVC file, the test vector file and the test port information, performing ATE machine test to complete the automatic IO test applied to the FPGA chip.

2. The automated IO test method for FPGA chip according to claim 1, wherein, The test type includes: HRIO type test and HPIO type test, wherein the HRIO type test includes: IO_DC test, IO_TERM test, IO_LEAKAGE test, IO_FUNC test and IO_PULLTYPE test; HPIO type test includes: IO_DC test, IO_TERM test, IO_LEAKAGE test, IO_FUNC test, IO_PULLTYPE test and IO_DCI test.

3. The automated IO testing method for FPGA chip of claim 1, wherein, The referencing the IO information, generating the engineering file and the constraint file of the test type according to the pinout and the electrical standard, comprises: referencing the IO information, establishing the RTL engineering corresponding to the test type according to the pinout and the electrical standard, obtaining the engineering file, wherein the RTL engineering calls the source language of ComboIO to build; obtaining the RTL engineering test content corresponding to the RTL engineering, adding the ComboIO, IO level standard, ComboIO attribute, bit stream compression attribute and preset other attributes of the constraint file according to the RTL engineering test content, obtaining the constraint file, wherein the ComboIO attribute includes: pull-up attribute and pull-down attribute, and the other attributes include: internal reference configuration.

4. The automated IO test method for FPGA chip of claim 3, wherein, The determining whether the preset code point can be correctly generated according to the log log, comprises: The ERROR information and the CRITICAL WARNING information in the log are captured by using a pre-built log error warning grabbing program in a TCL script, and it is determined whether the ERROR information or the CRITICAL WARNING information exists in the log; If the ERROR information or the CRITICAL WARNING information exists in the log, the code point cannot be correctly generated; If the ERROR information or the CRITICAL WARNING information does not exist in the log, the code point can be correctly generated.

5. The automated IO test method for FPGA chip of claim 1, wherein, The debugging of the test type according to the EDA tool until the correct code point is obtained, comprises: According to the log, the EDA tool is run to diagnose and locate faults of the test type until the correct code point is obtained.

6. The automated IO test method for FPGA chip of claim 5, wherein, The test vector file is generated according to the constraint file, and the test port information is output, comprising: When the test type is IO_DC test or IO_FUNC test, the test vector of the test type is verified to obtain the test vector file of the IO_DC test or the test vector file of the IO_FUNC test, wherein the test vector file of the IO_DC test is divided into a test vector of a single-ended IO, an IO test vector with an external reference voltage and an IO test vector of a differential level according to a preset level standard. The test port information is output according to the test type.

7. The automated IO test method for FPGA chip of claim 6, wherein, After the test vector file is generated according to the constraint file and the test port information is output, the method further comprises: When the test type is IO_TERM test, IO_LEAKAGE test, IO_PULLTYPE test or IO_DCI test, the test port and the Limit value are set in a pre-built ATE machine according to the test port information.

8. The automated IO test method for FPGA chip according to claim 6, wherein, The test vector of the single-ended IO comprises a test vector of an LVCMOS12 level standard, a test vector of an LVCMOS15 level standard and a test vector of an LVCMOS18 level standard; The IO test vector with the external reference voltage comprises a test vector of an SSTL level standard, a test vector of an HSTL level standard and a test vector of an HSUL level standard; The IO test vector of the differential level comprises a test vector of a DIFF_SSTL level standard, a test vector of a DIFF_HSTL level standard and a test vector of an LVDS level standard.

9. The automated IO testing method for FPGA chip according to claim 2, wherein, The IO_DC test comprises an LVCMOS12 level standard test; The IO_TERM test comprises a terminal resistance test and a differential resistance test, wherein the level configuration standard of the terminal resistance test is an SSTL_18 level standard, and the level configuration standard of the differential resistance test is an LVDS25 level standard; The IO_LEAKAGE test comprises a high-voltage leakage test, and the level configuration standard of the high-voltage leakage test is an LVCMOS33; The IO_FUNC test comprises an IBUFDISABLE test. The IO_PULLTYPE test comprises a weak pull-up current test of LVCMOS33; The IO_DCI test comprises a source-end matching resistance test.

10. An automated IO test system applied to an FPGA chip, characterized in that, The system comprises: An engineering file and constraint file generation module, configured to receive a user input of an FPGA chip model, a package type, an IO type and a test type, acquire IO information, wherein the IO information comprises a number of banks, a number of IOs and a number of IO classifications, acquire a pin layout corresponding to the package type and an electrical standard corresponding to the IO type, reference the IO information, and generate the engineering file and the constraint file of the test type according to the pin layout and the electrical standard; A log acquisition module, configured to run a pre-built EDA tool by using a pre-built TCL script to obtain an EDA tool environment, set a chip model in the EDA tool environment according to the FPGA chip model and the package type, and synthesize and implement by referencing the engineering file and the constraint file to obtain a log; A correct code point acquisition module, configured to determine whether a preset code point can be correctly generated according to the log; if the code point cannot be correctly generated, debug the test type according to the EDA tool until a correct code point is obtained; and if the code point can be correctly generated, acquire the correct code point; An ATE machine test module, configured to convert the correct code point into a preset machine test AVC file by using a preset conversion environment, generate a test vector file according to the constraint file, and output test port information; and perform ATE machine test according to the machine test AVC file, the test vector file and the test port information.

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