Low-dropout linear regulator circuit with soft start, low-dropout linear regulator, power supply unit and electronic equipment

Abstract

This application belongs to the field of electronic circuit technology and provides a low-dropout linear regulator circuit with soft start, a low-dropout linear regulator, a power supply device, and an electronic device. The low-dropout linear regulator circuit with soft start includes a capacitor module, a bias module, an input module, an intermediate stage module, and an output module. The capacitor module is connected to both the bias module and the input module. The input module is connected to the bias module, the intermediate stage module, and the output module. The intermediate stage module is connected to both the bias module and the output module. This application achieves the soft-start function of the low-dropout linear regulator circuit using NMOS input pairs through the synergistic effect between the capacitor module, bias module, input module, intermediate stage module, and output module, ensuring no overshoot in the output voltage during soft start, thereby achieving a stable output voltage establishment. This solves the problem that traditional soft-start schemes are not applicable to LDOs using NMOS input pairs.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and particularly relates to a low dropout linear regulator circuit with soft start, a low dropout linear regulator, a power supply device, and an electronic device. Background Technology

[0002] LDO stands for Low Dropout Regulator, a power management module that provides stable voltage. At power-on, before the loop reaches stable operation, the power transistor is in an uncontrolled state. The large capacitor at the load end acts as a short circuit during startup, absorbing a large current. This resulting peak current flows through the power transistor. If this peak current exceeds the power transistor's rated current capacity, it can burn out the transistor and cause related reliability issues. Simultaneously, this peak current causes a rapid rise in output voltage, easily exceeding the loop's regulation target value, leading to voltage overshoot. If this overshoot voltage is large, exceeding the withstand voltage of subsequent MOSFETs, it can damage them. Generally, the function of a soft-start circuit is to avoid large current surges and voltage overshoots, thereby protecting subsequent components and improving their reliability and lifespan. A soft-start circuit uses specific timing control to slowly turn on the power transistor and slowly charge the output capacitor, allowing the current and voltage to rise smoothly to the loop's target value.

[0003] Traditional soft-start schemes use a slowly increasing signal from zero to short-circuit the reference voltage path during the startup setup phase, thereby achieving a smooth establishment of output voltage and current, thus achieving soft start. However, this scheme is only applicable to LDOs using PMOS input pairs and not to LDOs using NMOS input pairs. Therefore, this problem urgently needs to be solved. Summary of the Invention

[0004] This application provides a low-dropout linear regulator circuit with soft start, a low-dropout linear regulator, a power supply device, and an electronic device, which can solve the problem that traditional soft-start solutions cannot be applied to LDOs using NMOS input pairs.

[0005] In a first aspect, embodiments of this application provide a low-dropout linear regulator circuit with soft-start, including a capacitor module, a bias module, an input module, an intermediate stage module, and an output module. The capacitor module is connected to the bias module and the input module, respectively. The input module is connected to the bias module, the intermediate stage module, and the output module, respectively. The intermediate stage module is connected to the bias module and the output module, respectively.

[0006] When the circuit is powered on, the bias module provides a charging current, a first bias current, and a second bias current; the capacitor module responds to an enable control signal and outputs a first voltage signal that slowly rises from zero based on the charging current; the input module outputs a second voltage signal that slowly rises from zero based on the first voltage signal, the first bias current, the power supply voltage, the reference voltage, and the feedback voltage; the intermediate stage module outputs a third voltage signal that slowly decreases from a preset initial voltage based on the second voltage signal and the second bias current; the output module outputs an output voltage that slowly rises from zero based on the third voltage signal until the output voltage reaches a preset target voltage, while simultaneously outputting a feedback voltage that varies with the output voltage; the input module is a module using NMOS type input pairs.

[0007] In one possible implementation of the first aspect, the capacitor module includes a first transistor and a first capacitor, the gate of the first transistor is used to receive an enable control signal, the drain of the first transistor is connected to a first terminal of the first capacitor, the bias module and the input module, respectively, and the source of the first transistor and the second terminal of the first capacitor are grounded.

[0008] In one possible implementation of the first aspect, the input module includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The gate of the second transistor is used to receive a reference voltage. The drain of the second transistor is connected to the source of the fourth transistor. The gate of the fourth transistor is connected to the capacitor module and the bias module. The drain of the fourth transistor is connected to the drain of the sixth transistor, the gate of the sixth transistor, and the gate of the seventh transistor. The sources of the sixth transistor and the seventh transistor receive a power supply voltage. The drain of the seventh transistor is connected to the intermediate stage module and the drain of the fifth transistor. The gate of the fifth transistor receives a power supply voltage. The source of the fifth transistor is connected to the drain of the third transistor. The gate of the third transistor is connected to the output module. The source of the second transistor is connected to the source of the third transistor and the bias module.

[0009] In one possible implementation of the first aspect, the fourth transistor and the fifth transistor are of the same size.

[0010] In one possible implementation of the first aspect, the bias module includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a first current source. A first terminal of the first current source receives a power supply voltage. A second terminal of the first current source is connected to the gate of the eighth transistor, the drain of the ninth transistor, the gate of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor, respectively. The drain of the tenth transistor is connected to the input module. The drain of the eleventh transistor is connected to the intermediate stage module. The sources of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor are grounded. The drain of the eighth transistor is connected to the drain of the twelfth transistor, the gate of the twelfth transistor, and the gate of the thirteenth transistor, respectively. The drain of the thirteenth transistor is connected to the capacitor module and the input module, respectively. The sources of the twelfth transistor and the thirteenth transistor receive a power supply voltage.

[0011] In one possible implementation of the first aspect, the intermediate stage module includes a thirteenth transistor, the drain of which is connected to both the output module and the bias module, the source of which receives a power supply voltage, and the gate of which is connected to the input module.

[0012] In one possible implementation of the first aspect, the output module includes a fourteenth transistor, a first resistor, a second resistor, and a second capacitor. The gate of the fourteenth transistor is connected to the intermediate stage module and the bias module, respectively. The source of the fourteenth transistor receives a power supply voltage. The drain of the fourteenth transistor is connected to the first terminal of the first resistor and the first terminal of the second capacitor, respectively. The second terminal of the first resistor is connected to the first terminal of the second resistor and the input module, respectively. The second terminal of the second resistor and the second terminal of the second capacitor are grounded.

[0013] Secondly, embodiments of this application provide a low-dropout linear regulator, including the low-dropout linear regulator circuit described in any one of the first aspects.

[0014] Thirdly, embodiments of this application provide a power supply device including the low-dropout linear regulator described in any one of the second aspects.

[0015] Fourthly, embodiments of this application provide an electronic device including the power supply device described in any one of the third aspects.

[0016] The beneficial effects of the embodiments in this application compared with the prior art are:

[0017] This application provides a low-dropout linear regulator circuit with soft-start, including a capacitor module, a bias module, an input module, an intermediate stage module, and an output module. The capacitor module is connected to the bias module and the input module, the input module is connected to the bias module, the intermediate stage module, and the output module, and the intermediate stage module is connected to the bias module and the output module.

[0018] When the circuit powers on, the bias module provides the charging current, the first bias current, and the second bias current. The capacitor module responds to the enable control signal and outputs a first voltage signal that slowly rises from zero based on the charging current. The input module outputs a second voltage signal that slowly rises from zero based on the first voltage signal, the first bias current, the power supply voltage, the reference voltage, and the feedback voltage. The intermediate stage module outputs a third voltage signal that slowly decreases from a preset initial voltage based on the second voltage signal and the second bias current. The output module outputs an output voltage that slowly rises from zero based on the third voltage signal until the output voltage reaches a preset target voltage, while simultaneously outputting a feedback voltage that varies with the output voltage. The input module uses NMOS type input pairs.

[0019] This application achieves a soft-start function for a low-dropout linear regulator circuit using NMOS input pairs through the synergistic interaction of the capacitor module, bias module, input module, intermediate stage module, and output module. This ensures that there is no overshoot in the output voltage during the soft-start process, thereby achieving a stable output voltage build-up. Compared to traditional soft-start solutions, this application can achieve a soft-start function for low-dropout linear regulator circuits using NMOS input pairs, solving the problem that traditional soft-start solutions are not applicable to LDOs using NMOS input pairs.

[0020] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a circuit connection diagram of a low dropout linear regulator circuit that uses PMOS input pairs and is based on a traditional soft-start scheme.

[0023] Figure 2This is a schematic diagram of a low-dropout linear regulator circuit with soft start provided in an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of a low-dropout linear regulator circuit with soft start provided in another embodiment of this application;

[0025] Figure 4 This is a circuit connection diagram of a low-dropout linear regulator circuit with soft start provided in an embodiment of this application.

[0026] In the diagram: 101, Capacitor module; 102, Bias module; 103, Input module; 104, Intermediate stage module; 105, Output module; 106, Frequency compensation module. Detailed Implementation

[0027] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0028] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0029] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0030] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0031] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0032] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0033] Figure 1 A circuit connection diagram is shown for a low-dropout linear regulator circuit using a PMOS input pair and based on a traditional soft-start scheme. (See diagram for reference.) Figure 1 As shown, PM0~PM3 It is a PMOS device, and its function is to provide bias current to the loop by current mirroring. PM4~PM5 It is an input pair transistor. PM4 The gate receives the reference voltage. VREF , PM5 The gate receives feedback voltage VFB . NM3 It is a power transistor (because it needs to provide a large load circuit, its size is very large, and its width can reach tens of thousands of μm). C102 It is an external load capacitor with a relatively large capacitance, reaching the uF level. PM6 , PM3 , NM4 , C101 Used to implement the soft-start function of the circuit. When the circuit is powered on, the enable control signal... ENN From high level to low level, NM4 When it is in the off state, the current flows through PM3 Give capacitor C101 Charging is achieved by setting a mirror ratio to ensure that the flow is maintained through... PM3 The current is very small, so the capacitor C101 voltage on VSTP It will slowly increase to near the power supply voltage. VDD And it ended. PM6 The gate voltage is voltage VSTP When the circuit is powered on, the voltage VSTP Very small (close to zero), so it flows through at this time PM1 The current was almost entirely... PM6 Steal ( PM4 This is equivalent to a short-circuit state, which is equivalent to providing a very small reference voltage to the loop. Because of this... C101 The charging current is very small (typically in the nA range), resulting in a low voltage. VSTP It will rise to the power supply voltage very slowly. VDD Therefore, the output voltage VOUT It builds up slowly from zero without voltage overshoot. The essence of this method is to short-circuit the reference voltage path during the build-up phase using a signal that gradually increases from zero, thereby achieving the desired output voltage. VOUT This allows for a smooth establishment of the current, thus achieving the purpose of soft start.

[0034] However, this method only applies to LDOs with PMOS input pairs, because in step 1... PM4 The source voltage (i.e.) Figure 1 The voltage at node A1 is generally quite high, and its expression is: V A1 = V gspm4 + VREF , V gspm4 represent PM4 The absolute value of the gate-source voltage difference. VREF This is the reference voltage (usually around 1V), because PM6 and PM4 Having the same dimensions, the gate-source voltage difference between the two is relatively close, therefore, when the voltage... VSTP At a lower voltage, the voltage at node A1 V A1 Definitely higher PM6 The voltage difference between the gate and source, PM6 It will be easy to conduct, thus enabling PM4 Short-circuiting is used to achieve soft-start. However, this method cannot achieve soft-start for an LDO with an NMOS input pair, so this problem urgently needs to be solved.

[0035] To address the aforementioned problems, this application provides a low-dropout linear regulator circuit with soft-start capability, comprising a capacitor module, a bias module, an input module, an intermediate stage module, and an output module. The capacitor module is connected to both the bias module and the input module. The input module is connected to the bias module, the intermediate stage module, and the output module. The intermediate stage module is connected to both the bias module and the output module. This application achieves soft-start functionality for the low-dropout linear regulator circuit using NMOS input pairs through the synergistic effect of the capacitor module, bias module, input module, intermediate stage module, and output module, ensuring no overshoot in the output voltage during soft-start and thus achieving a stable output voltage establishment. Compared to traditional soft-start solutions, this application can achieve soft-start functionality for low-dropout linear regulator circuits using NMOS input pairs, solving the problem that traditional soft-start solutions are not applicable to LDOs using NMOS input pairs.

[0036] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0037] Figure 2 A schematic diagram of the low-dropout linear regulator circuit with soft-start provided in this application is shown. Figure 2 As shown, the low-dropout linear regulator circuit with soft start includes a capacitor module 101, a bias module 102, an input module 103, an intermediate stage module 104, and an output module 105. The capacitor module 101 is connected to the bias module 102 and the input module 103. The input module 103 is connected to the bias module 102, the intermediate stage module 104, and the output module 105. The intermediate stage module 104 is connected to the bias module 102 and the output module 105.

[0038] Specifically, when the circuit is powered on, the bias module 102 provides a charging current, a first bias current, and a second bias current. It should be noted that the charging current provided by the bias module 102 is very small. The capacitor module 101 is used in response to the enable control signal. ENN Based on the charging current, the output voltage signal slowly rises from zero. VSTN In this embodiment, when the circuit is powered on, the enable control signal is activated. ENN The enable control signal changes from high to low. ENN Enable signal provided by the chip containing the circuit EN The result is obtained by inverting the first voltage signal. Input module 103 is used to determine the voltage signal based on the first voltage signal. VSTN First bias current, power supply voltage VDD Reference voltage VREF and feedback voltage VFB The output module 105 outputs a second voltage signal that rises slowly from zero. The intermediate stage module 104 outputs a third voltage signal that falls slowly from a preset initial voltage, based on the second voltage signal and the second bias current. VOUT until the output voltage VOUT The voltage is increased to the preset target voltage, and the output voltage follows the preset target voltage. VOUT Changing feedback voltage VFB The input module 103 is a module that uses NMOS type input transistors.

[0039] This application achieves a soft-start function for a low-dropout linear regulator circuit using NMOS input transistors through the synergistic effect of capacitor module 101, bias module 102, input module 103, intermediate stage module 104, and output module 105, ensuring that the output voltage remains constant during the soft-start process. VOUT No overshoot phenomenon, thus achieving output voltage VOUTAnd the smooth establishment of current. Compared with the traditional soft-start scheme, this application can realize the soft-start function of the low dropout linear regulator circuit using NMOS type input pair transistors, and solve the problem that the traditional soft-start scheme cannot be applied to LDOs using NMOS type input pair transistors.

[0040] In one embodiment of this application, such as Figure 3 As shown, a low-dropout linear regulator circuit with soft-start also includes a frequency compensation module 106, which is connected to the input module 103, the intermediate stage module 104, the bias module 102, and the output module 105. Specifically, the frequency compensation module 106 is used to achieve stable operation of the circuit, and its specific structure is not limited in this application, as long as it can achieve the function of frequency compensation.

[0041] In one embodiment of this application, such as Figure 4 As shown, the bias module 102 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a first current source Ib1. The first terminal of the first current source Ib1 receives the power supply voltage. VDD The second terminal of the first current source Ib1 is connected to the gate of the eighth transistor M8, the drain of the ninth transistor M9, the gate of the tenth transistor M10, and the gate of the eleventh transistor M11, respectively. The drain of the tenth transistor M10 is connected to the input module 103, and the drain of the eleventh transistor M11 is connected to the intermediate stage module 104. The sources of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are grounded. The drain of the eighth transistor M8 is connected to the drain of the twelfth transistor M12, the gate of the twelfth transistor M12, and the gate of the thirteenth transistor M13, respectively. The drain of the thirteenth transistor M13 is connected to the capacitor module 101 and the input module 103, respectively. The sources of the twelfth transistor M12 and the thirteenth transistor M13 receive the power supply voltage. VDD .

[0042] Specifically, the current provided by the first current source Ib1 generates a first bias current through a current mirror structure composed of the ninth transistor M9 and the tenth transistor M10, a second bias current through a current mirror structure composed of the ninth transistor M9 and the eleventh transistor M11, and a third bias current through a current mirror structure composed of the ninth transistor M9 and the eighth transistor M8. This third bias current then generates a charging current through a current mirror structure composed of the twelfth transistor M12 and the thirteenth transistor M13. To ensure a very small charging current, the mirror ratio between the thirteenth transistor M13 and the twelfth transistor M12 should be set very small.

[0043] In one embodiment of this application, such as Figure 4 As shown, the intermediate stage module 104 includes a thirteenth transistor M13. The drain of the thirteenth transistor M13 is connected to the output module 105 and the bias module 102, respectively, and the source of the thirteenth transistor M13 receives the power supply voltage. VDD The gate of the thirteenth transistor M13 is connected to the input module 103.

[0044] Specifically, the second voltage signal output by the input module 103 is a signal that slowly rises from zero. The thirteenth transistor M13, based on the second voltage signal and the second bias current, outputs a third voltage signal to the output module 105 that slowly decreases from a preset initial voltage. It should be noted that the preset initial voltage is the power supply voltage. VDD .

[0045] In one embodiment of this application, such as Figure 4 As shown, the output module 105 includes a fourteenth transistor M14, a first resistor R1, a second resistor R2, and a second capacitor C2. The gate of the fourteenth transistor M14 is connected to the intermediate stage module 104 and the bias module 102, respectively, and the source of the fourteenth transistor M14 receives the power supply voltage. VDD The drain of the fourteenth transistor M14 is connected to the first terminal of the first resistor R1 and the first terminal of the second capacitor C2. The second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and the input module 103. The second terminal of the second resistor R2 and the second terminal of the second capacitor C2 are grounded. The second capacitor C2 is an off-chip load capacitor.

[0046] Specifically, the third voltage signal output by the intermediate stage module 104 is a signal that slowly decreases from a preset initial voltage, and the fourteenth transistor M14 outputs an output voltage that slowly increases from zero based on the third voltage signal. VOUT Output voltage VOUT The feedback voltage is obtained after voltage division by the voltage divider network composed of the first resistor R1 and the second resistor R2. VFB, Feedback voltage VFB Feedback is sent to input module 103.

[0047] In one embodiment of this application, such as Figure 4 As shown, the capacitor module 101 includes a first transistor M1 and a first capacitor C1. The gate of the first transistor M1 is used to receive an enable control signal. ENN The drain of the first transistor M1 is connected to the first terminal of the first capacitor C1, the bias module 102 and the input module 103 respectively, and the source of the first transistor M1 and the second terminal of the first capacitor C1 are grounded.

[0048] Specifically, when the circuit is powered on, the enable control signal... ENNWhen the voltage level changes from high to low, the first transistor M1 is turned off, and the first capacitor C1 outputs a first voltage signal that slowly rises from zero based on the charging current. It should be noted that the function of the enable control signal ENN is to control the first transistor M1 to turn on before it goes low, so as to discharge the first capacitor C1, thereby ensuring that the initial state of the first capacitor C1 is zero when the circuit is powered on.

[0049] In one embodiment of this application, such as Figure 4 As shown, the input module 103 includes a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The gate of the second transistor M2 is used to receive a reference voltage. VREF The drain of the second transistor M2 is connected to the source of the fourth transistor M4. The gate of the fourth transistor M4 is connected to the capacitor module 101 and the bias module 102, respectively. The drain of the fourth transistor M4 is connected to the drain of the sixth transistor M6, the gate of the sixth transistor M6, and the gate of the seventh transistor M7, respectively. The sources of the sixth transistor M6 and the seventh transistor M7 receive the power supply voltage. VDD The drain of the seventh transistor M7 is connected to the drain of the intermediate stage module 104 and the drain of the fifth transistor M5, respectively. The gate of the fifth transistor M5 receives the power supply voltage. VDD The source of the fifth transistor M5 is connected to the drain of the third transistor M3, the gate of the third transistor M3 is connected to the output module 105, and the source of the second transistor M2 is connected to the source of the third transistor M3 and the bias module 102, respectively.

[0050] Specifically, when the circuit is powered on, the enable control signal... ENN When the voltage level changes from high to low, the first transistor M1 is turned off. At this time, the charging current flows through the thirteenth transistor M13 to charge the first capacitor C1. Since the charging current is very small, the first voltage signal on the first capacitor C1 is... VSTN It will start from zero and rise slowly until it approaches the power supply voltage. VDD And then it terminates. The gate voltage of the fourth transistor M4 is the first voltage signal. VSTN The gate voltage of the fifth transistor M5 is the power supply voltage. VDD Therefore, the fifth transistor M5 is in the normally on state. Because at the start of power-on in the circuit, the first voltage signal... VSTN The voltage is very small (close to zero), so the fourth transistor M4 is off, causing the sixth transistor M6 and the seventh transistor M7 to also be off. Therefore, the first bias current flowing through the tenth transistor M10 is almost entirely diverted by the third transistor M3 and the fifth transistor M5, pulling node B1 low. It should be noted that at the start of power-on in the circuit, the first voltage signal... VSTN The voltage is very small, so the fourth transistor M4 is in a weak conducting state, which in turn causes the sixth transistor M6 and the seventh transistor M7 to also be in a weak conducting state, thus pulling up the voltage at node B1. As the voltage at node B1 increases, the voltage at node B2 is pulled down, therefore the output voltage... VOUT Not zero. Output voltage VOUT The feedback voltage is obtained after voltage division by the voltage divider network composed of the first resistor R1 and the second resistor R2. VFB Greater than 0 ， Therefore, the third transistor M3 is in the ON state. It should be noted that the first voltage signal... VSTN The rate of change is very slow, while the response speed of the circuit feedback loop is very fast. This is the key condition for the stable conduction of the third transistor M3.

[0051] The thirteenth transistor M13 and the fourteenth transistor M14 are configured as a common-source structure, and the input-to-output gain of the common-source structure is... A v Its expression is ,in g m For the small-signal transconductance of the thirteenth transistor M13, r o The small-signal impedance at node B2, V B2 This is the voltage at node B2 (i.e., the third voltage signal). V B1 The voltage at node B1 (i.e., the second voltage signal) is indicated by the negative sign in the formula. V B2 The direction of change and V B1 The direction of change is opposite. Therefore, it can be concluded that the downward movement... V B1 It will inevitably lead to V B2 The voltage is pulled high, so the fourteenth transistor M14 (i.e., the power transistor) is almost turned off, and the output voltage... VOUT It is close to zero. Because the charging current is very small (typically in the nA range), the first voltage signal... VSTN It gradually increases at a very slow rate until it reaches the power supply voltage. VDD According to the analysis above, V B1 It will rise slowly, at the same time V B2 It will decrease slowly, eventually causing the output voltage to... VOUT The voltage is gradually increased from zero until the preset target voltage of the loop is reached, thereby avoiding voltage overshoot and achieving the desired output voltage. VOUThe smooth establishment of the circuit ultimately achieves the purpose of soft start. The fifth transistor M5 is in a normally conducting state, and its size is the same as the fourth transistor M4. This ensures that after the soft start is completed, the fourth transistor M4 and the fifth transistor M5 operate in the same state, thus ensuring that the two branches containing the second transistor M2 and the third transistor M3 are in the same working environment. Ultimately, this ensures that the matching performance of the circuit is not affected under normal operating conditions.

[0052] In summary, this application achieves the soft-start function of a low-dropout linear regulator circuit using NMOS input transistors through the synergistic effect of capacitor module 101, bias module 102, input module 103, intermediate stage module 104, and output module 105, ensuring that the output voltage remains constant during the soft-start process. VOUT No overshoot phenomenon, thus achieving output voltage VOUT This invention achieves a smooth current build-up without affecting the matching performance under normal circuit operation. Compared to traditional soft-start solutions, this application enables soft-start functionality for low-dropout linear regulator circuits using NMOS input pairs, solving the problem that traditional soft-start solutions are unsuitable for LDOs using NMOS input pairs.

[0053] It should be noted that this application is not only applicable to the field of LDOs, but also to all circuit structures with NMOS input pairs, such as DC-DC error amplifiers or operational amplifiers that require soft start, and the technical solutions of this application can be applied. All of the above application scenarios fall within the protection scope of this application.

[0054] This application also provides a low-dropout linear regulator, including the low-dropout linear regulator circuit with soft-start described above. Since the low-dropout linear regulator provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0055] This application also provides a power supply device, including the low-dropout linear regulator described above. Since the power supply device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0056] This application also provides an electronic device, including the power supply device described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0057] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0058] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A low-dropout linear regulator circuit with soft-start, characterized in that, It includes a capacitor module, a bias module, an input module, an intermediate stage module, and an output module. The capacitor module is connected to the bias module and the input module, the input module is connected to the bias module, the intermediate stage module, and the output module, and the intermediate stage module is connected to the bias module and the output module. When the circuit is powered on, the bias module provides a charging current, a first bias current, and a second bias current; the capacitor module responds to an enable control signal and outputs a first voltage signal that slowly rises from zero based on the charging current; the input module outputs a second voltage signal that slowly rises from zero based on the first voltage signal, the first bias current, the power supply voltage, the reference voltage, and the feedback voltage; the intermediate stage module outputs a third voltage signal that slowly decreases from a preset initial voltage based on the second voltage signal and the second bias current; the output module outputs an output voltage that slowly rises from zero based on the third voltage signal until the output voltage reaches a preset target voltage, while simultaneously outputting a feedback voltage that varies with the output voltage; the input module is a module using NMOS type input pairs. The input module includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The gate of the second transistor receives a reference voltage. The drain of the second transistor is connected to the source of the fourth transistor. The gate of the fourth transistor is connected to the capacitor module and the bias module. The drain of the fourth transistor is connected to the drain, gate, and gate of the sixth transistor. The sources of the sixth and seventh transistors receive a power supply voltage. The drain of the seventh transistor is connected to the intermediate stage module and the drain of the fifth transistor. The gate of the fifth transistor receives a power supply voltage. The source of the fifth transistor is connected to the drain of the third transistor. The gate of the third transistor is connected to the output module. The source of the second transistor is connected to the source of the third transistor and the bias module.

2. The low-dropout linear regulator circuit with soft start according to claim 1, characterized in that, The capacitor module includes a first transistor and a first capacitor. The gate of the first transistor is used to receive an enable control signal. The drain of the first transistor is connected to the first terminal of the first capacitor, the bias module, and the input module, respectively. The source of the first transistor and the second terminal of the first capacitor are grounded.

3. The low-dropout linear regulator circuit with soft start according to claim 1, characterized in that, The fourth transistor and the fifth transistor are the same size.

4. The low-dropout linear regulator circuit with soft start according to claim 1 or 2, characterized in that, The bias module includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a first current source. The first terminal of the first current source receives a power supply voltage. The second terminal of the first current source is connected to the gate of the eighth transistor, the drain of the ninth transistor, the gate of the ninth transistor, the gate of the tenth transistor, and the gate of the eleventh transistor, respectively. The drain of the tenth transistor is connected to the input module. The drain of the eleventh transistor is connected to the intermediate stage module. The sources of the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor are grounded. The drain of the eighth transistor is connected to the drain of the twelfth transistor, the gate of the twelfth transistor, and the gate of the thirteenth transistor, respectively. The drain of the thirteenth transistor is connected to the capacitor module and the input module, respectively. The sources of the twelfth transistor and the thirteenth transistor receive a power supply voltage.

5. The low-dropout linear regulator circuit with soft start according to claim 1 or 2, characterized in that, The intermediate stage module includes a thirteenth transistor, the drain of which is connected to both the output module and the bias module, the source of which receives the power supply voltage, and the gate of which is connected to the input module.

6. The low-dropout linear regulator circuit with soft start according to claim 1 or 2, characterized in that, The output module includes a fourteenth transistor, a first resistor, a second resistor, and a second capacitor. The gate of the fourteenth transistor is connected to the intermediate stage module and the bias module, respectively. The source of the fourteenth transistor receives the power supply voltage. The drain of the fourteenth transistor is connected to the first end of the first resistor and the first end of the second capacitor, respectively. The second end of the first resistor is connected to the first end of the second resistor and the input module, respectively. The second end of the second resistor and the second end of the second capacitor are grounded.

7. A low-dropout linear voltage regulator, characterized in that, Includes the low dropout linear regulator circuit as described in any one of claims 1-6.

8. A power supply device, characterized in that, Includes the low-dropout linear regulator as described in claim 7.

9. An electronic device, characterized in that, Includes the power supply device as described in claim 8.

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