A low-power scheduling method and system for edge heterogeneous computing units

Abstract

This invention provides a low-power scheduling method and system for edge heterogeneous computing units. The method includes constructing a resource-aware model for heterogeneous hardware and collecting performance parameters of processing units in real time; establishing a task priority evaluation model, calculating task priorities based on the resource-aware model, the task priority evaluation model, and using the analytic hierarchy process (AHP); designing a collaborative optimization model; solving for the optimal task allocation scheme on the heterogeneous hardware based on the collaborative optimization model and using an improved particle swarm optimization algorithm, and dynamically adjusting the operating frequency of the heterogeneous hardware; monitoring the status of task execution and the heterogeneous hardware in real time, and determining whether there is a risk of resource overload or task timeout. If so, the scheduling scheme is updated. This invention effectively avoids getting trapped in local optima, significantly improves solution efficiency and solution quality, and achieves a closed-loop dynamic power consumption control system that links frequency to voltage by triggering scheduling scheme updates.

Description

Technical Field

[0001] This invention relates to the field of edge computing and embedded systems technology, and in particular to a low-power scheduling method and system for edge heterogeneous computing units. Background Technology

[0002] With the development of the Internet of Things (IoT) and artificial intelligence (AI), edge computing moves data processing from the cloud to edge nodes closer to the data source, effectively reducing latency and bandwidth pressure. However, edge nodes generally face problems such as weak computing power, limited storage, and power supply constraints.

[0003] To enhance computing power, modern edge devices widely adopt heterogeneous hardware architectures (such as CPU+GPU+FPGA+NPU), but this brings scheduling challenges: different hardwares vary greatly in performance, power consumption, and programming models, making it difficult for traditional scheduling methods to achieve efficient coordination.

[0004] Most existing technologies only target CPU scheduling, failing to utilize the acceleration potential of GPUs / FPGAs / NPUs; they rely on offloading tasks to the cloud to reduce power consumption, making them unsuitable for weak network conditions or privacy-sensitive scenarios; and most scheduling strategies are statically fixed, unable to cope with fluctuations in task load and changes in hardware state. Therefore, there is an urgent need for a heterogeneous hardware collaborative scheduling method that balances low power consumption, high real-time performance, and strong adaptability. Summary of the Invention

[0005] Therefore, the purpose of this invention is to provide a low-power scheduling method and system for edge heterogeneous computing units to address the shortcomings of the prior art.

[0006] In a first aspect, the present invention provides a low-power scheduling method for edge heterogeneous computing units, the method comprising:

[0007] Construct a resource-aware model for heterogeneous hardware and collect performance parameters of processing units in real time;

[0008] A task priority evaluation model is established, based on the resource awareness model, the task priority evaluation model, task type, deadline, data volume, and computational complexity, and the analytic hierarchy process is used to calculate task priority.

[0009] Design a collaborative optimization model that aims to minimize total power consumption while satisfying task latency and hardware resource constraints;

[0010] Based on the aforementioned collaborative optimization model, an improved particle swarm optimization algorithm is used to solve the optimal allocation scheme of tasks on the heterogeneous hardware, and the operating frequency of the heterogeneous hardware is dynamically adjusted.

[0011] The system monitors the execution of tasks and the status of the heterogeneous hardware in real time, and determines whether there is a risk of resource overload or task timeout. If so, it triggers an update to the scheduling scheme.

[0012] Compared with existing technologies, the beneficial effects of this invention are as follows: By generating dynamic task priorities through a resource-aware model, a priority evaluation model, and the four original features of the task, a precise match between task requirements and hardware status is achieved, overcoming the limitations of traditional scheduling that emphasizes performance over energy consumption or static over dynamic aspects. Furthermore, by using a collaborative optimization model and an improved particle swarm optimization algorithm to transform continuous velocity into allocation probability, continuous velocity is effectively avoided from getting trapped in local optima, significantly improving solution efficiency and solution quality. Moreover, by triggering scheduling scheme updates, a three-level energy-saving control chain is achieved, from task allocation to frequency adjustment to voltage adaptation, realizing a dynamic power consumption control closed loop that links frequency to voltage.

[0013] Furthermore, prior to the step of constructing the resource-aware model for heterogeneous hardware, the method further includes:

[0014] Obtain the arriving tasks and extract the task features, which include task type, task data volume, task deadline, and task computational complexity.

[0015] Furthermore, the step of acquiring and processing unit performance parameters in real time includes:

[0016] The computing power utilization, memory usage, and power consumption of CPU, GPU, FPGA, and NPU are collected in real time at preset intervals, wherein the preset interval is 50ms to 200ms.

[0017] The computing power utilization, memory occupancy, and power consumption are normalized using range standardization. The expression for range standardization is:

[0018] ;

[0019] In the formula, Indicates hardware resource utilization. This represents the normalized resource status value. Indicates at time No. The first type of hardware Original resource status value, Indicates the first The first type of hardware The minimum value of the resource indicator within the historical observation window. Indicates the first The first type of hardware The maximum value of each resource indicator within the historical observation window, among which, These correspond to CPU, GPU, FPGA, and NPU, respectively. These correspond to utilization rate, memory occupancy rate, and power consumption value, respectively.

[0020] Furthermore, the expression for calculating the task priority is:

[0021] ;

[0022] in, Indicates task priority. , Indicates the first The weighting coefficients of each evaluation dimension, The first character representing the task features One evaluation dimension This represents the standardized value of each indicator.

[0023] Furthermore, the expression for the collaborative optimization model is:

[0024] ;

[0025] In the formula, This represents the objective of minimizing the total energy consumption of the system. This indicates the total number of tasks to be processed within the current scheduling period. Indicates the task and task index. Indicates the task Assigned to hardware The estimated energy consumed during execution can be estimated through historical measurement analysis or power consumption models. Indicates the task allocation relationship. These correspond to CPU, GPU, FPGA, and NPU, respectively.

[0026] Furthermore, after the step of solving the optimal allocation scheme of the task on the heterogeneous hardware based on the cooperative optimization model and using an improved particle swarm optimization algorithm, the method further includes:

[0027] The tasks are allocated to the corresponding heterogeneous hardware according to the optimal allocation scheme;

[0028] The required power supply voltage at the target frequency is found or calculated based on the characteristic curve of the heterogeneous hardware, and voltage and frequency adjustment commands are synchronously issued through power management.

[0029] Furthermore, after the step of determining whether the state indicates a risk of resource overload or task timeout, the method further includes:

[0030] If no resource overload or task timeout risk is detected in the aforementioned state, the resource-aware model for constructing heterogeneous hardware is repeatedly executed, and the performance parameters of the processing units are collected in real time. A task priority evaluation model is established, and task priorities are calculated using the analytic hierarchy process (AHP) based on the task priority evaluation model, task type, deadline, data volume, and computational complexity. A collaborative optimization model is designed to minimize total power consumption while satisfying task latency and hardware resource constraints. An improved particle swarm optimization algorithm is used to solve for the optimal allocation scheme of tasks on the heterogeneous hardware, and the operating frequency of the heterogeneous hardware is dynamically adjusted. The execution of tasks and the status of the heterogeneous hardware are monitored in real time, and it is determined whether the status indicates resource overload or task timeout risk, until the scheduling scheme is updated.

[0031] Secondly, the present invention also provides a low-power scheduling system for edge heterogeneous computing units, the system comprising:

[0032] A data acquisition module is built to construct a resource awareness model for heterogeneous hardware and to collect performance parameters of the processing unit in real time.

[0033] A calculation module is established to build a task priority evaluation model. Based on the resource awareness model, the task priority evaluation model, task type, deadline, data volume, and computational complexity, the task priority is calculated using the analytic hierarchy process (AHP).

[0034] The design module is used to design a collaborative optimization model that aims to minimize total power consumption while satisfying task latency and hardware resource constraints.

[0035] The allocation and adjustment module is used to solve the optimal allocation scheme of tasks on the heterogeneous hardware based on the cooperative optimization model and using an improved particle swarm optimization algorithm, and to dynamically adjust the operating frequency of the heterogeneous hardware.

[0036] The monitoring and judgment module is used to monitor the status of task execution and the heterogeneous hardware in real time, and to determine whether there is a risk of resource overload or task timeout. If so, the scheduling scheme is updated.

[0037] Thirdly, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described low-power scheduling method for edge heterogeneous computing units.

[0038] Fourthly, the present invention also provides a storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described low-power scheduling method for edge heterogeneous computing units. Attached Figure Description

[0039] Figure 1This is a flowchart of the low-power scheduling method for edge heterogeneous computing units in the first embodiment of the present invention;

[0040] Figure 2 This is a flowchart of the improved PSO algorithm scheduling solution in the first embodiment of the present invention;

[0041] Figure 3 This is a hardware architecture design diagram of the edge device in the first embodiment of the present invention;

[0042] Figure 4 This is a structural block diagram of the low-power scheduling system for edge heterogeneous computing units in the second embodiment of the present invention;

[0043] Figure 5 This is a structural block diagram of the electronic device in the third embodiment of the present invention.

[0044] Explanation of key component symbols:

[0045] 10. Construct the data acquisition module; 20. Establish the calculation module; 30. Design the module; 40. Allocate and adjust the module; 50. Monitor and judge the module;

[0046] 60. Bus; 61. Processor; 62. Memory; 63. Communication interface.

[0047] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0048] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0049] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0051] Example 1

[0052] Please see Figure 1 The figure shows a low-power scheduling method for edge heterogeneous computing units in the first embodiment of the present invention, the method comprising steps S1 to S5:

[0053] S1, construct a resource-aware model for heterogeneous hardware and collect performance parameters of processing units in real time;

[0054] It should be noted that step S01 precedes step S1:

[0055] S01, obtain the arriving task and extract the task features, the task features including task type, task data volume, task deadline and task computational complexity;

[0056] Specifically, step S1 includes steps S11 to S12:

[0057] S11, Real-time collection of computing power utilization, memory usage and power consumption values ​​of CPU, GPU, FPGA and NPU at preset intervals, wherein the preset interval is 50ms~200ms;

[0058] S12, the computing power utilization rate, the memory occupancy rate, and the power consumption value are normalized by range standardization. The expression for range standardization is:

[0059] ;

[0060] In the formula, Indicates hardware resource utilization. This represents the normalized resource status value. Indicates at time No. The first type of hardware Original resource status value, Indicates the first The first type of hardware The minimum value of the resource indicator within the historical observation window. Indicates the first The first type of hardware The maximum value of each resource indicator within the historical observation window, among which, These correspond to CPU, GPU, FPGA, and NPU, respectively. These correspond to utilization rate, memory occupancy rate, and power consumption value, respectively. ;

[0061] It should be noted that, in order to eliminate the difference in dimensions, the range standardization method is adopted to provide a unified and comparable input basis for subsequent scheduling decisions, and to solve the problem of difficulty in comparison across hardware types.

[0062] S2, Establish a task priority evaluation model, based on the resource awareness model, the task priority evaluation model, task type, deadline, data volume and computational complexity, and use the analytic hierarchy process to calculate task priority;

[0063] It should be noted that the task characteristics extracted include: task type, data volume, deadline, and computational complexity; a priority model is constructed using the analytic hierarchy process (AHP).

[0064] Among them, the weights of the criterion layer are: (Task type) (Deadline) (Data volume) (Computational complexity), satisfies ;

[0065] Quantification of deadlines:

[0066] ;

[0067] In the formula, Indicates the deadline. Indicates the current system time, Indicates the time it takes for the task to reach the edge node. Indicates task The deadline for completion, if Take 1; if The timeout has been determined.

[0068] It is worth noting that the Analytic Hierarchy Process (AHP) was used to determine the weights of each criterion in the task priority evaluation model. First, task priority was set as the target layer, while task type, deadline urgency, data volume, and computational complexity were set as the criterion layers. Second, pairwise comparison matrices were constructed using expert scoring or historical operational data. Then, the weight vectors were calculated and a consistency check (CR < 0.1) was performed, ultimately yielding the weight allocation: task type weight. Deadline weight Data volume weight Calculation complexity weights This weight combination is embedded in the scheduling engine and can also be dynamically updated based on application scenarios.

[0069] In this embodiment, the expression for calculating the task priority is:

[0070] ;

[0071] in, This indicates the overall priority score of the current task. , Indicates the first The weighting coefficients of each evaluation dimension, The first character representing the task features One evaluation dimension Indicates the first The standardized scores for each dimension, among which... The larger the value, the higher the priority.

[0072] S3 is designed as a collaborative optimization model that aims to minimize total power consumption while satisfying task latency and hardware resource constraints.

[0073] In this embodiment, the expression for the collaborative optimization model is:

[0074] ;

[0075] In the formula, This represents the objective of minimizing the total energy consumption of the system. This indicates the total number of tasks to be processed within the current scheduling period. Indicates the task and task index. Indicates the task Assigned to hardware The estimated energy consumed during execution (in joules) can be estimated through historical measurement analysis or power consumption models. Indicates the task allocation relationship. :Task m Assigned to hardware i ; Unassigned These correspond to CPU, GPU, FPGA, and NPU, respectively.

[0076] It should be noted that the constraints are as follows:

[0077] The task is uniquely assigned, expressed as:

[0078] ;

[0079] Delay constraints:

[0080] ;

[0081] In the formula, Indicates task In hardware The estimated execution latency is as follows. This indicates all tasks to be scheduled. Established;

[0082] Resource capacity constraints:

[0083] ;

[0084] In the formula, Indicates task In hardware When the above is executed, the first The demand for such resources Hardware The Total limit of resource quantity.

[0085] S4. Based on the cooperative optimization model and using an improved particle swarm optimization algorithm, solve for the optimal allocation scheme of tasks on the heterogeneous hardware, and dynamically adjust the operating frequency of the heterogeneous hardware.

[0086] Specifically, step S4 includes steps S41 to S42:

[0087] S41, The task is allocated to the corresponding heterogeneous hardware according to the optimal allocation scheme;

[0088] S42, find or calculate the required power supply voltage at the target frequency based on the characteristic curve of the heterogeneous hardware, and send voltage and frequency adjustment commands synchronously through power management;

[0089] It should be noted that the proposed improved PSO (Particle Swarm Optimization) dynamic scheduling algorithm first involves particle encoding: each particle represents a... The task assignment probability matrix :particle At any moment For task sub Assigned to hardware The velocity variable; : The corresponding positional variable, Indicates task Assigned to hardware The probability of;

[0090] Please refer to [link / reference needed] for further explanation. Figure 2 The improved PSO dynamic scheduling algorithm includes an initialization phase, an iterative optimization phase, a termination condition determination, and loop control.

[0091] Initialization phase: Set particle swarm parameters, including the number of particles (particle swarm size) N and the maximum number of iterations. Inertia weight acceleration coefficient etc.; randomly initialize the position vector of each particle. and velocity vector ,in Let be the dimension of the search space, representing the dimension of each particle in the search space. The number of variables in the real number space. The encoding length corresponds to the task scheduling problem; a fitness function is also defined. This is used to evaluate the overall performance of each particle (i.e., the scheduling scheme);

[0092] Iterative optimization phase: By updating the individual optimal position, the global optimal position, and the particle's velocity and position, the optimal scheduling strategy is gradually approximated; in the k-th iteration, for each particle... Compare its current fitness value Its historical best fitness value If the current value is better, then update its individual optimal position:

[0093] ;

[0094] Simultaneously, the optimal fitness value is found among all particles, and the global optimal position is updated:

[0095] ;

[0096] Subsequently, the particle states are adjusted according to the standard PSO velocity-position update formula to guide the population to search for high-fitness regions. Indicates the first The individual historical best position of a particle, that is, the solution with the best fitness in each iteration (a task allocation scheme). Indicates the first The particle in the first Current position at the next iteration This represents the globally optimal solution. Indicates the first The optimal scheduling strategy for each individual particle, and the solution with the best fitness among all particles, is the optimal scheduling strategy found in the current population. Is to make The smallest index;

[0097] Termination condition determination: Determine if any of the following termination conditions are met: current iteration number The range of change in the global optimal fitness value over several consecutive generations (Preset threshold); if any condition is met, the algorithm is considered to have converged and the iteration stops;

[0098] Loop control: If the maximum number of iterations has not been reached and the fitness value changes by more than a set threshold... If the solution is found to be correct, return to the iterative optimization phase and continue execution; otherwise, exit the loop and output the final solution.

[0099] Output: After the algorithm terminates, it outputs the global optimal solution. After decoding, the solution generates an optimal task scheduling strategy, which includes the target execution hardware unit (such as CPU, GPU, FPGA, NPU), execution order, and corresponding DVFS running parameters (frequency / voltage level) for each task, thereby achieving low latency, low power consumption, and high reliability edge computing resource scheduling.

[0100] Improve the fitness function in the PSO dynamic scheduling algorithm:

[0101] ;

[0102] In the formula, This represents the fitness value. This represents the power consumption weighting coefficient. This reflects the principle of prioritizing power consumption. This indicates the total number of tasks to be processed within the current scheduling period. Indicates task The deadline;

[0103] Particle Update:

[0104] ;

[0105] ;

[0106] In the formula, Indicates the first Each particle at time , for the task Assigned to hardware velocity variable, The inertia weight controls the degree to which a particle maintains its original velocity; it typically decreases with iteration. This represents the iteration time step (not the actual time, but the number of algorithm iterations). , These represent acceleration coefficient one and acceleration coefficient two, respectively. , Let these represent two random numbers, one from the interval [0,1] and the other from the interval [0,1]. This represents the individual's historical best position. Represents the global historical optimal position, the overall optimal solution found so far among all particles (i.e., the task assignment scheme with the highest fitness across the entire swarm), and each particle... The best solution I found in each iteration (i.e. the task allocation scheme with the highest fitness). Indicates the probability of allocation. This represents the scaling parameter in the Sigmoid function (usually set to 1 or tuned empirically), used to control the steepness of the mapping. Indicates continuous velocity. Indicates the particle number; uses the Sigmoid function to represent continuous velocity. Mapped to Assignment Probability This makes the algorithm applicable to discrete task allocation problems;

[0107] The expression for adjusting the operating frequency is:

[0108] ;

[0109] In the formula, Indicates allocation to hardware Target operating frequency, Hardware The lowest configurable frequency, Indicates task The computational requirements, Hardware Maximum computing resource capacity Hardware The highest configurable frequency;

[0110] Understandably, the optimal task allocation scheme and the operating frequency of the heterogeneous hardware are output to allocate tasks to the corresponding heterogeneous hardware. At the same time, based on the DVFS (Dynamic Voltage and Frequency Scaling) characteristic curve of each heterogeneous hardware unit, the required power supply voltage at the target operating frequency of the heterogeneous hardware is found or calculated, and voltage and frequency adjustment commands are synchronously issued through the power management interface (such as PMIC, ACPI or register writing) to achieve fine control of power consumption.

[0111] It's worth noting that the DVFS characteristic curve shows that increasing the clock frequency requires increasing the voltage to ensure circuit stability, as transistor switching speed depends on voltage; power consumption... With the square of the voltage and clock frequency Proportional ( ), This represents the equivalent dynamic capacitance of a hardware unit. Therefore, adjusting the frequency and voltage can significantly reduce energy consumption and achieve energy efficiency optimization. The Dynamic Voltage Frequency Adjustment (DVFS) characteristic curve defines the optimal supply voltage for each hardware unit at different frequencies within its operating range.

[0112] S5. Monitor the status of task execution and heterogeneous hardware in real time, and determine whether there is a risk of resource overload or task timeout. If so, trigger the scheduling scheme update.

[0113] It should be noted that during task execution, the system monitors the utilization rate of heterogeneous hardware resources in real time. Actual task execution delay Hardware health Status parameters, including hardware health. The overall reliability of hardware operation can be comprehensively reflected by indicators such as temperature, aging degree, and error rate. The calculation formula is as follows:

[0114] ;

[0115] In the formula, Hardware At any moment Real-time temperature, Hardware Maximum allowable operating temperature Hardware The safe temperature threshold Indicates aging factors, Represents the normalized error rate, where, ;

[0116] It should be noted that in this embodiment, rescheduling is triggered when any of the following conditions are met: hardware resource utilization. The monitoring lasted for two consecutive monitoring cycles; the actual task latency was [not specified]. Hardware health .

[0117] Furthermore, if no resource overload or task timeout risk is detected in the stated state, the resource-aware model for heterogeneous hardware is repeatedly executed, and the performance parameters of the processing units are collected in real time. A task priority evaluation model is established, and task priorities are calculated using the analytic hierarchy process (AHP) based on the task priority evaluation model, task type, deadline, data volume, and computational complexity. A collaborative optimization model is designed to minimize total power consumption while satisfying task latency and hardware resource constraints. An improved particle swarm optimization algorithm is used to solve for the optimal allocation scheme of tasks on the heterogeneous hardware, and the operating frequency of the heterogeneous hardware is dynamically adjusted. The execution of tasks and the state of the heterogeneous hardware are monitored in real time, and it is determined whether resource overload or task timeout risk is detected, until a scheduling scheme update is triggered. A new scheduling scheme is generated, forming a closed-loop feedback control, which improves the robustness and energy efficiency of the entire system.

[0118] For specific implementation details, please refer to [link / reference]. Figure 3This is a schematic diagram of the edge device hardware architecture, including a task input interface, a task scheduling engine, heterogeneous computing units (CPU / GPU / FPGA / NPU), a power management unit (PMU), a system bus and memory, and a status monitoring sensor group. The task scheduling engine dynamically schedules tasks based on task characteristics and hardware status, and adjusts the operating frequency and power supply voltage of each hardware component through the PMU. It also receives sensor feedback to achieve closed-loop control, as shown in Table 1.

[0119] Table 1

[0120]

[0121] In summary, the low-power scheduling method for edge heterogeneous computing units in the above embodiments of the present invention significantly reduces system power consumption (measured reduction of over 20%); improves the overall utilization rate of heterogeneous hardware (reducing idleness and overload); possesses dynamic adaptability and is suitable for complex edge environments; the method is engineerable and the device has complete hardware support; dynamic task priorities are generated through a resource-aware model, a priority evaluation model, and the four original features of the task, thereby achieving precise matching between task requirements and hardware status, overcoming the limitations of traditional scheduling that emphasizes performance over energy consumption or static over dynamic aspects. Furthermore, by using a collaborative optimization model and an improved particle swarm optimization algorithm to transform continuous velocity into allocation probability, it effectively avoids getting trapped in local optima, significantly improving solution efficiency and solution quality. By triggering scheduling scheme updates, it realizes a three-level energy-saving control chain from task allocation to frequency adjustment to voltage adaptation, achieving a dynamic power consumption control closed loop that links frequency and voltage.

[0122] Example 2

[0123] The second embodiment of the present invention also provides a low-power scheduling system for edge heterogeneous computing units. Please refer to [link to relevant documentation]. Figure 4 The figure shows a low-power scheduling system for edge heterogeneous computing units in a second embodiment of the present invention. The system includes:

[0124] A data acquisition module 10 is constructed to build a resource awareness model for heterogeneous hardware and collect the performance parameters of the processing unit in real time.

[0125] A calculation module 20 is established to build a task priority evaluation model. Based on the resource awareness model, the task priority evaluation model, task type, deadline, data volume, and computational complexity, the task priority is calculated using the analytic hierarchy process (AHP). The expression for calculating the task priority is as follows:

[0126] ;

[0127] in, Indicates task priority. , Indicates the first The weighting coefficients of each evaluation dimension, The first character representing the task features One evaluation dimension This represents the standardized value of each indicator;

[0128] Design module 30 is used to design a collaborative optimization model that aims to minimize total power consumption while satisfying task latency and hardware resource constraints. The expression of the collaborative optimization model is:

[0129] ;

[0130] In the formula, This represents the objective of minimizing the total energy consumption of the system. This indicates the total number of tasks to be processed within the current scheduling period. Indicates the task and task index. Indicates the task Assigned to hardware The estimated energy consumed during execution can be estimated through historical measurement analysis or power consumption models. Indicates the task allocation relationship. These correspond to CPU, GPU, FPGA, and NPU, respectively.

[0131] The allocation adjustment module 40 is used to solve the optimal allocation scheme of tasks on the heterogeneous hardware based on the cooperative optimization model and using an improved particle swarm optimization algorithm, and to dynamically adjust the operating frequency of the heterogeneous hardware.

[0132] The monitoring and judgment module 50 is used to monitor the status of task execution and the heterogeneous hardware in real time, and to determine whether the status indicates resource overload or task timeout risk. If so, the scheduling scheme is updated.

[0133] In some alternative embodiments, the construction acquisition module 10 includes:

[0134] The acquisition and extraction unit is used to acquire the arriving task and extract the task features, which include task type, task data volume, task deadline and task computational complexity.

[0135] The acquisition unit is used to collect the computing power utilization, memory usage and power consumption of CPU, GPU, FPGA and NPU in real time at a preset interval period, wherein the preset interval period is 50ms~200ms;

[0136] The processing unit is used to normalize the computing power utilization, the memory occupancy rate, and the power consumption value through range normalization. The expression for range normalization is:

[0137] ;

[0138] In the formula, Indicates hardware resource utilization. This represents the normalized resource status value. Indicates at time No. The first type of hardware Original resource status value, Indicates the first The first type of hardware The minimum value of the resource indicator within the historical observation window. Indicates the first The first type of hardware The maximum value of each resource indicator within the historical observation window, among which, These correspond to CPU, GPU, FPGA, and NPU, respectively. These correspond to utilization rate, memory occupancy rate, and power consumption value, respectively.

[0139] In some alternative embodiments, the allocation adjustment module 40 includes:

[0140] The allocation unit is used to allocate tasks to corresponding heterogeneous hardware according to the optimal allocation scheme;

[0141] The lookup unit is used to find or calculate the required power supply voltage at the target frequency based on the characteristic curve of the heterogeneous hardware, and to synchronously issue voltage and frequency adjustment commands through power management.

[0142] In some optional embodiments, the monitoring and judgment module 50 includes:

[0143] The execution unit is used to determine whether there is a risk of resource overload or task timeout in the stated state. If so, it repeatedly executes the resource-aware model for constructing heterogeneous hardware and collects the performance parameters of the processing unit in real time. It establishes a task priority evaluation model, and calculates task priorities based on the task priority evaluation model, task type, deadline, data volume, and computational complexity using the analytic hierarchy process (AHP). It designs a collaborative optimization model that minimizes total power consumption while satisfying task latency and hardware resource constraints. It uses an improved particle swarm optimization algorithm to solve for the optimal allocation scheme of tasks on the heterogeneous hardware and dynamically adjusts the operating frequency of the heterogeneous hardware. It monitors the task execution and the state of the heterogeneous hardware in real time and determines whether there is a risk of resource overload or task timeout, until a scheduling scheme update is triggered.

[0144] The functions or operation steps implemented by the above modules and units are largely the same as those in the above method embodiments, and will not be repeated here.

[0145] The low-power scheduling system for edge heterogeneous computing units provided in this embodiment of the invention has the same implementation principle and technical effects as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0146] Example 3

[0147] The third embodiment of the present invention also proposes an electronic device, please refer to [link / reference]. Figure 5 The image shows an electronic device according to a third embodiment of the present invention.

[0148] The electronic device may include a processor 61 and a memory 62 storing computer program instructions.

[0149] Specifically, the processor 61 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the present application.

[0150] The memory 62 may include a large-capacity storage device for data or instructions. For example, and not limitingly, the memory 62 may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), flash memory, an optical disk drive, a magneto-optical disk drive, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 62 may include removable or non-removable (or fixed) media. Where appropriate, the memory 62 may be internal or external to a data processing device. In a particular embodiment, the memory 62 is non-volatile memory. In a particular embodiment, the memory 62 includes read-only memory (ROM) and random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), an electrically alterable read-only memory (EAROM), or flash memory, or a combination of two or more of these. Where appropriate, the RAM can be Static Random-Access Memory (SRAM) or Dynamic Random-Access Memory (DRAM). DRAM can be Fast Page Mode Dynamic Random-Access Memory (FPMDRAM), Extended Data Out Dynamic Random-Access Memory (EDODRAM), Synchronous Dynamic Random-Access Memory (SDRAM), etc.

[0151] The memory 62 can be used to store or cache various data files that need to be processed and / or communicated, as well as possible computer program instructions executed by the processor 61.

[0152] The processor 61 implements the low-power scheduling method for edge heterogeneous computing units described in Embodiment 1 by reading and executing computer program instructions stored in the memory 62.

[0153] In some embodiments, the electronic device may further include a communication interface 63 and a bus 60. For example, Figure 5 As shown, the processor 61, memory 62, and communication interface 63 are connected through bus 60 and complete communication with each other.

[0154] The communication interface 63 is used to enable communication between the various modules, devices, units, and / or equipment in this application. The communication interface 63 can also enable data communication with other components such as external devices, image / data acquisition devices, databases, external storage, and image / data processing workstations.

[0155] Bus 60 includes hardware, software, or both, that couples components of a device together. Bus 60 includes, but is not limited to, at least one of the following: data bus, address bus, control bus, expansion bus, and local bus. For example, and not as a limitation, bus 60 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 60 may include one or more buses. Although this application describes and illustrates a specific bus, this application considers any suitable bus or interconnection.

[0156] The electronic device can acquire the edge heterogeneous computing unit low-power scheduling system and execute the edge heterogeneous computing unit low-power scheduling method of this embodiment.

[0157] Furthermore, in conjunction with the low-power scheduling method for edge heterogeneous computing units in Embodiment 1 above, this application can provide a storage medium for implementation. This storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement the low-power scheduling method for edge heterogeneous computing units in Embodiment 1 above.

[0158] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0159] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A low-power scheduling method for edge heterogeneous computing units, characterized in that, The method includes: Constructing a resource-aware model for heterogeneous hardware and collecting performance parameters of processing units in real time, this step specifically includes: The computing power utilization, memory usage, and power consumption of CPU, GPU, FPGA, and NPU are collected in real time at preset intervals, wherein the preset interval is 50ms to 200ms. The computing power utilization, memory occupancy, and power consumption are normalized using range standardization. The expression for range standardization is: ； In the formula, Indicates hardware resource utilization. This represents the normalized resource status value. Indicates at time No. The first type of hardware Original resource status value, Indicates the first The first type of hardware The minimum value of the resource indicator within the historical observation window. Indicates the first The first type of hardware The maximum value of each resource indicator within the historical observation window, among which, These correspond to CPU, GPU, FPGA, and NPU, respectively. These correspond to utilization rate, memory occupancy rate, and power consumption value, respectively. A task priority evaluation model is established, based on the resource awareness model, the task priority evaluation model, task type, deadline, data volume, and computational complexity, and the analytic hierarchy process is used to calculate task priority. Design a collaborative optimization model that aims to minimize total power consumption while satisfying task latency and hardware resource constraints. The expression for the collaborative optimization model is as follows: ； In the formula, This represents the objective of minimizing the total energy consumption of the system. This indicates the total number of tasks to be processed within the current scheduling period. Indicates the task and task index. Indicates the task Assigned to hardware The estimated energy consumed during execution can be estimated through historical measurement analysis or power consumption models. Indicates the task allocation relationship. These correspond to CPU, GPU, FPGA, and NPU, respectively. Based on the aforementioned collaborative optimization model, an improved particle swarm optimization algorithm is used to solve the optimal allocation scheme of tasks on the heterogeneous hardware, and the operating frequency of the heterogeneous hardware is dynamically adjusted. The system monitors the execution of tasks and the status of the heterogeneous hardware in real time, and determines whether there is a risk of resource overload or task timeout. If so, it triggers an update to the scheduling scheme.

2. The low-power scheduling method for edge heterogeneous computing units according to claim 1, characterized in that, Before the step of constructing a resource-aware model for heterogeneous hardware, the method further includes: The system acquires the arriving tasks and extracts task features, including task type, task data volume, task deadline, and task computational complexity.

3. The low-power scheduling method for edge heterogeneous computing units according to claim 1, characterized in that, The expression for calculating the priority of the task is: ； in, Indicates task priority. , Indicates the first The weighting coefficients of each evaluation dimension, The first character representing the task features One evaluation dimension This represents the standardized value of each indicator.

4. The low-power scheduling method for edge heterogeneous computing units according to claim 1, characterized in that, Following the step of solving the optimal allocation scheme for the task on the heterogeneous hardware based on the cooperative optimization model and using an improved particle swarm optimization algorithm, the method further includes: The tasks are allocated to the corresponding heterogeneous hardware according to the optimal allocation scheme; The required power supply voltage at the target frequency is found or calculated based on the characteristic curve of the heterogeneous hardware, and voltage and frequency adjustment commands are synchronously issued through power management.

5. The low-power scheduling method for edge heterogeneous computing units according to claim 1, characterized in that, After the step of determining whether the state indicates a risk of resource overload or task timeout, the method further includes: If no resource overload or task timeout risk is detected in the aforementioned state, the resource-aware model for constructing heterogeneous hardware is repeatedly executed, and the performance parameters of the processing units are collected in real time. A task priority evaluation model is established, and task priorities are calculated using the analytic hierarchy process (AHP) based on the task priority evaluation model, task type, deadline, data volume, and computational complexity. A collaborative optimization model is designed to minimize total power consumption while satisfying task latency and hardware resource constraints. An improved particle swarm optimization algorithm is used to solve for the optimal allocation scheme of tasks on the heterogeneous hardware, and the operating frequency of the heterogeneous hardware is dynamically adjusted. The execution of tasks and the status of the heterogeneous hardware are monitored in real time, and it is determined whether the status indicates resource overload or task timeout risk, until the scheduling scheme is updated.

6. A low-power scheduling system for edge heterogeneous computing units, characterized in that, The system includes: A data acquisition module is built to construct a resource awareness model for heterogeneous hardware and to collect performance parameters of the processing unit in real time. The data acquisition module includes: The acquisition unit is used to collect the computing power utilization, memory usage and power consumption of CPU, GPU, FPGA and NPU in real time at a preset interval period, wherein the preset interval period is 50ms~200ms; The processing unit is used to normalize the computing power utilization, the memory occupancy rate, and the power consumption value through range normalization. The expression for range normalization is: ； In the formula, Indicates hardware resource utilization. This represents the normalized resource status value. Indicates at time No. The first type of hardware Original resource status value, Indicates the first The first type of hardware The minimum value of the resource indicator within the historical observation window. Indicates the first The first type of hardware The maximum value of each resource indicator within the historical observation window, among which, These correspond to CPU, GPU, FPGA, and NPU, respectively. These correspond to utilization rate, memory occupancy rate, and power consumption value, respectively. A calculation module is established to build a task priority evaluation model. Based on the resource awareness model, the task priority evaluation model, task type, deadline, data volume, and computational complexity, the task priority is calculated using the analytic hierarchy process (AHP). The design module is used to design a collaborative optimization model that aims to minimize total power consumption while satisfying task latency and hardware resource constraints. The expression for the collaborative optimization model is: ； In the formula, This represents the objective of minimizing the total energy consumption of the system. This indicates the total number of tasks to be processed within the current scheduling period. Indicates the task and task index. Indicates the task Assigned to hardware The estimated energy consumed during execution can be estimated through historical measurement analysis or power consumption models. Indicates the task allocation relationship. These correspond to CPU, GPU, FPGA, and NPU, respectively. The allocation and adjustment module is used to solve the optimal allocation scheme of tasks on the heterogeneous hardware based on the cooperative optimization model and using an improved particle swarm optimization algorithm, and to dynamically adjust the operating frequency of the heterogeneous hardware. The monitoring and judgment module is used to monitor the status of task execution and the heterogeneous hardware in real time, and to determine whether there is a risk of resource overload or task timeout. If so, the scheduling scheme is updated.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the low-power scheduling method for edge heterogeneous computing units as described in any one of claims 1 to 5.

8. A storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the low-power scheduling method for edge heterogeneous computing units as described in any one of claims 1 to 5.

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