A mixed test system and method of a multi-core heterogeneous system-on-chip, electronic equipment and storage medium

Abstract

The application provides a mixed test system, method, electronic equipment and storage medium of a multi-core heterogeneous system-level chip, the mixed test system comprising: a serial control network component, at least one protocol conversion gateway device, a local test distribution network controller and a plurality of data network encapsulators; the protocol conversion gateway device comprising a bus slave interface, a storage buffer unit and a flow control state machine. Through the mixed test system architecture of the serial control network component configuration, the protocol conversion gateway device multiplexing and the local test distribution dedicated network, the inherent contradictions of the prior art in time, cost and contention are cooperatively solved in the multi-core heterogeneous system-level chip, the flexibility and scalability of testing the multi-core heterogeneous system-level chip are improved, the hardware cost and wiring congestion are significantly reduced, the bus contention is eliminated, the test efficiency is improved and the time cost of parallel testing is reduced.

Description

Technical Field

[0001] This application relates to the field of multi-core heterogeneous system-on-a-chip (SoC) testing technology, and in particular to a hybrid testing system, method, electronic device, and storage medium for multi-core heterogeneous SoCs. Background Technology

[0002] As modern system-on-a-chip (SoC) evolves towards multi-core, heterogeneous, and chiplet-based architectures, the amount of test data, test application time, and test power consumption all face significant physical bottlenecks. Traditional serial test access mechanisms can no longer effectively scale to cope with this complexity. Existing SoC test architectures include those based on dedicated test buses, those based on traditional JTAG daisy-chain architectures, and those based on fully multiplexed functional buses. However, each of these architectures has obvious limitations and cannot simultaneously balance test time, hardware overhead, and test efficiency.

[0003] Among these, architectures based on dedicated test buses lay out dedicated buses to achieve parallel testing, resulting in high wiring resources and chip area costs; in traditional JTAG daisy-chain architectures, the serial nature leads to uncontrollable test time issues, causing the test time complexity of the architecture to not increase linearly with the number of cores; in architectures based on fully multiplexed functional buses, when the test data stream occupies the functional system bus, in order to avoid or eliminate its competition for bus bandwidth with the CPU or other functional modules, it will lead to test pauses and unpredictable timing issues. Therefore, existing technologies based on static topologies cannot be dynamically configured and are difficult to meet different test requirements. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a hybrid test system, method, electronic device and storage medium for multi-core heterogeneous system-on-a-chip (SoC). Through a hybrid test system architecture of serial control network component configuration, protocol conversion gateway device multiplexing and local test distribution dedicated network, the inherent contradictions of the prior art in terms of time, overhead and contention are solved in multi-core heterogeneous SoC, improving the flexibility and scalability of testing multi-core heterogeneous SoC, and significantly reducing hardware overhead and wiring congestion. While eliminating bus contention, it improves test efficiency and reduces the time overhead of parallel testing.

[0005] This application provides a hybrid test system for a multi-core heterogeneous system-on-a-chip. The hybrid test system includes: a serial control network component, at least one protocol conversion gateway device, a local test distribution network controller, and multiple data network encapsulators; wherein, the protocol conversion gateway device includes: a bus slave interface, a storage buffer unit, and a flow control state machine.

[0006] The serial control network component is used to send configuration instruction information to each of the protocol conversion gateway devices to perform static configuration on each node in the hybrid test system;

[0007] The protocol conversion gateway device is used to respond to the addressing request of the functional system bus master device by the bus slave interface and receive the burst write transaction packet sent by the functional system bus master device, write the target data corresponding to the burst write transaction packet to the storage buffer unit and send it to the local test distributed network controller and / or the data network encapsulator;

[0008] The flow control state machine is used to monitor the data filling level of the storage buffer unit and dynamically generate a synchronous scan clock signal based on the data filling level, so as to convert the asynchronous burst data in the burst write transaction packet into the target data that is represented as a synchronous continuous bit stream.

[0009] The local test distribution network controller is used to send the target data to the corresponding data network encapsulator;

[0010] The data network encapsulator is used to send the target data to the target core group under test corresponding to the data network encapsulator according to the test mode corresponding to the configuration instruction information, and to receive the status flag data sent by the target core group under test, and send the status flag data to the storage buffer unit.

[0011] When the protocol conversion gateway device receives the status flag data, the protocol conversion gateway device is further configured to perform logical OR aggregation on the status flag data to generate the test results corresponding to the target tested core group.

[0012] Furthermore, the serial control network component includes a test subsystem access layer, a protocol conversion gateway configuration layer, and a core encapsulation access layer; when the serial control network component issues configuration command information to each of the protocol conversion gateway devices to perform static configuration on each node in the hybrid test system, the serial control network component is used for:

[0013] The protocol conversion gateway configuration layer accesses the configuration register of each protocol conversion gateway device through a preset first configuration instruction to dynamically group the target core group under test and send the first configuration parameter in the configuration instruction information to each protocol conversion gateway device.

[0014] The test subsystem access layer uses a preset second configuration instruction to write the second configuration parameter in the configuration instruction information to each node in the hybrid test system;

[0015] In response to the configuration of each node in the hybrid test system taking effect, the test subsystem access layer uses a preset third configuration instruction to drive the switching of physical paths within the local test distribution network controller to establish a physical connection.

[0016] The target core group under test is accessed through the core encapsulation access layer via the first configuration instruction, and the scan chain mode inside the target core group under test is configured through the second configuration instruction.

[0017] Furthermore, the bus slave interface is used to respond to the addressing request of the functional system bus master device, and to process the address handshake, data handshake and response handshake signals of the functional system bus master device;

[0018] The storage buffer unit decouples the clock difference between the burst transmission of the functional system bus master device and the streaming transmission of the local test distributed network controller through asynchronous first-in-first-out, in order to absorb protocol jitter.

[0019] The storage buffer unit includes a vector buffer and a response buffer; the vector buffer is used to receive the burst write transaction packet sent by the functional system bus master device, and send the target data corresponding to the burst write transaction packet to the local test distribution network controller and / or the data network encapsulator; the response buffer is used to receive the status flag bit data sent by the data network encapsulator for the functional system bus read channel to read.

[0020] Furthermore, when monitoring the data fill level of the storage buffer unit, the flow control state machine is used to:

[0021] The data consumption rate of the scan chain of the target tested core group and the target pause time of the functional system bus are collected respectively.

[0022] Based on the data consumption rate, the target pause time, and the preset safety margin coefficient, the target depth value of the storage buffer unit is determined to determine the data filling level of the storage buffer unit.

[0023] Furthermore, the flow control state corresponding to the flow control state machine can be jump-controlled based on the data filling level, scan chain length counter and configuration instruction information; the flow control state includes idle state, configuration check state, pre-charge state, flow transmission state, pause state and empty state.

[0024] Furthermore, the local test distribution network corresponding to the local test distribution network controller is a dedicated distribution network without routing, arbitration, or flow control handshake; the local test distribution network controller includes physical connections, multiplexers, and fan-out buffers; the local test distribution network controller is specifically used to broadcast the target data in parallel to the corresponding data network encapsulator.

[0025] Furthermore, the test modes include parallel testing with the same core, parallel testing with different cores, serial testing with the same core, and parallel testing with a single core and multiple modules.

[0026] This application also provides a hybrid testing method for multi-core heterogeneous system-on-a-chip, the hybrid testing method including:

[0027] The serial control network component sends configuration instructions to each protocol conversion gateway device to perform static configuration on each node in the hybrid test system.

[0028] The protocol conversion gateway device responds to the addressing request of the functional system bus master device via its bus slave interface and receives a burst write transaction packet sent by the functional system bus master device. It then writes the target data corresponding to the burst write transaction packet to a storage buffer unit and sends it to a local test distributed network controller and / or a data network encapsulator. The protocol conversion gateway device includes a bus slave interface, a storage buffer unit, and a flow control state machine. The flow control state machine monitors the data fill level of the storage buffer unit and, based on the data fill level, dynamically generates a synchronous scan clock signal to convert the asynchronous burst data in the burst write transaction packet into the target data, which appears as a synchronous continuous bit stream.

[0029] The target data is sent by the local test distribution network controller to the corresponding data network encapsulator;

[0030] The data network encapsulator sends the target data to the target core group under test corresponding to the data network encapsulator according to the test mode corresponding to the configuration instruction information, and receives the status flag data sent by the target core group under test, and sends the status flag data to the storage buffer unit.

[0031] When the protocol conversion gateway device receives the status flag data, it performs logical OR aggregation on the status flag data to generate the test result corresponding to the target core group under test.

[0032] This application also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the hybrid testing method for multi-core heterogeneous system-on-a-chip described above are performed.

[0033] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the hybrid testing method for multi-core heterogeneous system-on-a-chip described above.

[0034] This application provides a hybrid testing system, method, electronic device, and storage medium for multi-core heterogeneous system-on-a-chip (SoC). The hybrid testing system includes: a serial control network component, at least one protocol conversion gateway device, a local test distribution network controller, and multiple data network encapsulators. The protocol conversion gateway device includes: a bus slave interface, a storage buffer unit, and a flow control state machine. The serial control network component is used to issue configuration instructions to each protocol conversion gateway device to statically configure each node in the hybrid testing system. The protocol conversion gateway device is used to respond to an addressing request from a functional system bus master device via the bus slave interface and receive a burst write transaction packet sent by the functional system bus master device, write the target data corresponding to the burst write transaction packet to the storage buffer unit, and send it to the local test distribution network controller and / or the data network encapsulators. The flow control state machine is used to monitor the data fill level of the storage buffer unit and dynamically generate a synchronous scan clock signal based on the data fill level to convert the asynchronous burst data in the burst-written transaction packet into the target data that appears as a synchronous continuous bit stream. The local test distribution network controller is used to send the target data to the corresponding data network encapsulator. The data network encapsulator is used to send the target data to the target core group under test corresponding to the data network encapsulator according to the test mode corresponding to the configuration instruction information, and receive the status flag data sent by the target core group under test, and send the status flag data to the storage buffer unit. When the protocol conversion gateway device receives the status flag data, the protocol conversion gateway device is also used to perform logical OR aggregation on the status flag data to generate the test result corresponding to the target core group under test.

[0035] Compared with existing system architectures such as dedicated test bus-based architecture, traditional JTAG daisy-chain-based architecture, and fully multiplexed functional bus-based architecture, this hybrid test system architecture, which combines serial control network component configuration, protocol conversion gateway device multiplexing, and local test distribution dedicated network, collaboratively resolves the inherent contradictions in time, overhead, and contention in multi-core heterogeneous system-on-a-chip (SoC) architectures. It improves the flexibility and scalability of testing multi-core heterogeneous SoCs, significantly reduces hardware overhead and wiring congestion, and improves test efficiency and reduces the time overhead of parallel testing while eliminating bus contention.

[0036] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic diagram of the structure of a hybrid test system for a multi-core heterogeneous system-on-a-chip provided in an embodiment of this application;

[0039] Figure 2 This is a flowchart illustrating the operation of a protocol conversion gateway device provided in an embodiment of this application.

[0040] Figure 3 A flowchart illustrating a parallel testing process using the same core, provided as an embodiment of this application;

[0041] Figure 4 A flowchart illustrating a parallel testing process using different cores, provided as an embodiment of this application;

[0042] Figure 5 A flowchart illustrating a serial testing process with identical cores, provided as an embodiment of this application;

[0043] Figure 6 A flowchart illustrating a single-core, multi-module parallel testing process provided in this application embodiment;

[0044] Figure 7 A flowchart illustrating a hybrid testing method for a multi-core heterogeneous system-on-a-chip provided in this application embodiment;

[0045] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0047] Research has revealed that modern system-on-a-chip (SoC) evolution towards multi-core, heterogeneous, and chiplet-based architectures has led to a significant increase in physical bottlenecks in test data volume, test application time, and test power consumption. Traditional serial test access mechanisms are no longer sufficient to effectively scale to cope with this complexity. Existing SoC test architectures include those based on dedicated test buses, traditional JTAG daisy-chain architectures, and fully reused functional buses. However, each of these architectures has significant limitations and cannot simultaneously balance test time, hardware overhead, and test efficiency.

[0048] The architecture based on a dedicated test bus is a classic architecture advocated by the "IEEE 1500" standard. It designs a dedicated test package for each (or group of) cores and transmits test data from chip pins to each (or group of) cores through one or more dedicated on-chip test buses. The shortcomings of this architecture include: the need to lay multiple physical buses from the top layer of the chip to every corner of the system-on-a-chip (SoC), which consumes a huge amount of chip area and routing resources in complex SoCs with multiple cores, leading to severe routing congestion and potentially affecting the chip's timing; furthermore, it has poor flexibility and is difficult to adapt to later IP additions or deletions or changes in the testing process.

[0049] Based on the traditional JTAG daisy-chain architecture and the "IEEE 1149.1 (JTAG)" standard, all cores' JTAG interfaces (or scan chains) on the chip are daisy-chained together. The automated test system accesses the entire long chain through a single TDI and TDO pin. The shortcomings of this architecture include: test time increases linearly, as the daisy-chain architecture is inherently serial, and the total scan chain length is the sum of the scan chain lengths of all cores; as the number of cores increases, the test time increases linearly. Furthermore, it lacks flexibility and robustness; the daisy-chain architecture has extremely poor flexibility. A failure in the JTAG interface of any core in the chain, or in the connections between them, will cause the entire test chain to collapse, making all other healthy cores inaccessible and untestable.

[0050] Architectures based on fully reused functional buses utilize existing functional buses within the system-on-a-chip (SoC) to transmit test data, such as AMBA and AXI buses. However, this architecture has several drawbacks: bus contention and performance bottlenecks. The AXI bus is designed for high-performance, bursty access in functional modes. In test mode, continuous long sequences of scan vector data streams occupy the AXI bus for extended periods with high bandwidth, leading to severe resource contention with other critical on-chip activities that require the bus. Furthermore, it is unsuitable for broadcast testing. AXI is a point-to-point or multi-point-to-multipoint protocol, and its architecture does not support efficiently broadcasting the same test vectors simultaneously to a large number of cores (e.g., AI accelerator arrays).

[0051] Based on the analysis of the existing architectures above, it is evident that architectures based on dedicated test buses, which require dedicated buses to achieve parallel testing, result in high wiring resources and chip area costs. In traditional JTAG daisy-chain architectures, the serial nature leads to uncontrollable test time issues, causing the test time complexity of the architecture to not increase linearly with the number of cores. In architectures based on fully multiplexed functional buses, when the test data stream occupies the functional system bus, in order to avoid or eliminate its competition for bus bandwidth with the CPU or other functional modules, it will lead to test pauses and unpredictable timing issues. Therefore, existing technologies based on static topologies cannot be dynamically configured and are difficult to meet different test requirements.

[0052] Based on this, embodiments of this application provide a hybrid testing system for multi-core heterogeneous system-on-a-chip (SoC). Through a hybrid testing system architecture that combines serial control network component configuration, protocol conversion gateway device multiplexing, and a local test distribution dedicated network, the inherent contradictions in time, overhead, and contention in existing technologies are resolved in a coordinated manner within multi-core heterogeneous SoCs. This improves the flexibility and scalability of testing multi-core heterogeneous SoCs, significantly reduces hardware overhead and wiring congestion, and improves testing efficiency and reduces the time overhead of parallel testing while eliminating bus contention.

[0053] Please see Figure 1 , Figure 1 This application provides a schematic diagram of the structure of a hybrid test system for a multi-core heterogeneous system-on-a-chip. (See attached diagram.) Figure 1 As shown in the figure, the hybrid test system 10 for multi-core heterogeneous system-on-a-chip provided in this application embodiment includes: a serial control network component 110, at least one protocol conversion gateway device 120, a local test distribution network controller 130, and multiple data network encapsulators 140.

[0054] The protocol conversion gateway device 120 includes a bus slave interface 121, a storage buffer unit 122, and a flow control state machine 123.

[0055] The serial control network component 110 is used to send configuration instruction information to each of the protocol conversion gateway devices 120 to perform static configuration on each node in the hybrid test system 10.

[0056] In this embodiment of the application, the configuration instruction information includes a first configuration parameter and a second configuration parameter; the configuration instruction information includes, but is not limited to, the operating mode, scan chain length, local bus clock rate, and expected data packet size of the protocol conversion gateway device.

[0057] In this embodiment, the serial control network component 110 includes a test subsystem access layer, a protocol conversion gateway configuration layer, and a core encapsulation access layer.

[0058] Here, the serial control network component 110 may include an IJTAG (Internal Joint TestAction Group) network, which is an architecture defined by the "IEEE 1687" standard for managing on-chip testability and accessibility.

[0059] Specifically, the serial control network component 110 may include a standard "IEEE 1687" serial network and be connected out-of-band to all components within the system-on-a-chip that need to be tested. When the chip enters test mode, the functional system bus master device 20 remains silent, and the serial control network component 110 is activated.

[0060] In one possible implementation of this application, when the serial control network component 110 issues configuration instruction information to each of the protocol conversion gateway devices 120 to perform static configuration on each node in the hybrid test system 10, the serial control network component 110 is used to:

[0061] The protocol conversion gateway configuration layer accesses the configuration register of each protocol conversion gateway device 120 through a preset first configuration instruction to dynamically group the target core group 30 under test, and sends the first configuration parameter in the configuration instruction information to each protocol conversion gateway device 120.

[0062] In this embodiment of the application, the target core group 30 under test can be dynamically grouped through the configuration register of the protocol conversion gateway device 120 to realize a software-defined test topology. Although the hardware is fixed, the effective test topology can be reconstructed in milliseconds through software instructions. This allows the same chip to adapt to different parallelism requirements at different stages such as wafer testing (CP), packaging testing (FT), and system-level testing (SLT).

[0063] For example, in scenario A, the full chip power consumption test can enable broadcasting for all cores in the target tested core group 30; in scenario B, the local hotspot test only enables broadcasting for Core 1, Core 3, and Core 5 in the target tested core group 30.

[0064] The test subsystem access layer uses a preset second configuration instruction to write the second configuration parameter in the configuration instruction information to each node in the hybrid test system 10.

[0065] In response to the configuration taking effect of each node in the hybrid test system 10, the test subsystem access layer uses a preset third configuration instruction to drive the switching of physical paths within the local test distribution network controller 130 to establish a physical connection.

[0066] The target core group under test 30 is accessed through the core encapsulation access layer via the first configuration instruction, and the scan chain mode inside the target core group under test 30 is configured via the second configuration instruction.

[0067] For example, the serial control network component 110 is a multi-level IJTAG network. The test subsystem access layer controls the access of the entire test subsystem, the protocol conversion gateway configuration layer controls the access of the configuration port of the protocol conversion gateway device 120, and the core encapsulation access layer controls the access of each encapsulation core. For example, the following typical configuration sequence can emphasize the role of static configuration in the testing process.

[0068] For example, a typical configuration sequence includes: ShiftIR (first configuration instruction), used to control the configuration register of the access protocol conversion gateway device 120; ShiftDR (second configuration instruction), used to set "MODE = BROADCAST; DIV_RATIO = 4 (AXI clock / 4 = scan clock); BROADCAST_MASK = 0xFF00 (test only the first 8 cores)"; UpdateDR (third configuration instruction), used to establish a physical connection by locally testing the MUX switching path within the distributed network controller 130 when the configuration takes effect; ShiftIR (first configuration instruction), used to access the Core Wrapper; ShiftDR (second configuration instruction), used to configure the scan chain mode (e.g., Bypass mode or Intest mode) within the target core group under test 30.

[0069] like Figure 1 As shown, the protocol conversion gateway device 120 is configured to, in response to receiving a burst write transaction packet sent by the functional system bus master device 20, write the target data corresponding to the burst write transaction packet to the storage buffer unit 122 and send it to the local test distribution network controller 130 and / or the data network encapsulator 140.

[0070] Here, the functional system bus corresponding to the functional system bus master device 20 may include an AXI (Advanced deXtensible Interface) bus. The functional system bus master device 20 is equipped with an AXI bus interconnect matrix, and the top layer of the system-on-a-chip initiates bus transactions through the standard AXI interconnect bus.

[0071] Furthermore, the bus slave interface 121 is used to respond to the addressing request of the functional system bus master device 20, and to process the address handshake, data handshake and response handshake signals of the functional system bus master device 20.

[0072] Here, the logic of the bus slave interface 121 is the "throat" of the protocol conversion gateway device 120 connecting to the top-level bus of the system-on-a-chip. This interface is mainly composed of complex combinational logic and register files, in which a flow control backpressure design is added. This is a key circuit to prevent data overflow. It receives the "Programmable Full" signal from the storage buffer unit 122. Once the water level of the storage buffer unit 122 reaches the threshold, the logic circuit immediately pulls down the "WREADY" signal, which forces the functional system bus master device to suspend transmission until the data network encapsulator consumes some data. This hardware-level automatic flow control is the basis for realizing the "contention-free feature".

[0073] The storage buffer unit 122 decouples the clock difference between the burst transmission of the functional system bus master device 20 and the streaming transmission of the local test distribution network controller 130 through asynchronous first-in-first-out decoupling, in order to absorb protocol jitter.

[0074] Here, the storage buffer unit 122 may include an internally heterogeneous first-in-first-out buffer medium, which is responsible for decoupling the irregular, high-speed burst data writing of the functional system bus and the constant, streaming data consumption of the local test distributed network controller 130.

[0075] When the storage buffer unit 122 is not empty, the protocol conversion gateway device 120 starts reading data from the storage buffer unit 122 and streams it as a "pure payload" to the local data network encapsulator 140.

[0076] For example, the storage buffer unit 122 is not only used for cross-clock domain (CDC), but also for absorbing protocol jitter. The input of the storage buffer unit 122 is connected to the functional system bus, the frequency of which can be set to 2GHz, and the behavior is "burst, pause, burst". The output is connected to the local test distributed network controller 130, the frequency of which can be set to 50-100MHz, and the behavior is "constant current".

[0077] In this embodiment of the application, the storage buffer unit 122 includes a vector buffer 1221 and a response buffer 1222.

[0078] The vector buffer 1221 is used to receive the burst write transaction packet sent by the functional system bus master device, and send the target data corresponding to the burst write transaction packet to the local test distribution network controller 130 and / or the data network encapsulator 140.

[0079] Here, the input of vector buffer 1221 is connected to the write data bus in the functional system bus master device 20 and is driven by a high-frequency system clock; the output is connected to the master control logic of data network encapsulator 140 and is driven by a configurable test clock to mask bus access latency jitter through a reasonable first-in-first-out buffer depth.

[0080] The response buffer 1222 is used to receive the status flag data sent by the data network encapsulator for the read channel of the functional system bus to read.

[0081] Here, the input of the response buffer 1222 is driven by TCLK to receive data from the comparator or deserializer; the output is driven by ACLK to be read by the read channel in the functional system bus master device 20. Since the data network encapsulator 140 is usually a serial data stream, while the functional system bus side is a wide bus, the input of the response buffer 1222 is usually equipped with serial-to-parallel conversion logic (SIPO) to pack the single-byte scan output data into multiple bytes before writing it into the response buffer 1222.

[0082] Furthermore, the flow control state machine 123 is used to monitor the data filling level of the storage buffer unit 122, and dynamically generate a synchronous scan clock signal based on the data filling level, so as to convert the asynchronous burst data written into the burst transaction packet into the target data that is represented as a synchronous continuous bit stream.

[0083] Here, after detecting that the storage buffer unit 122 is not empty, the flow control state machine 123 immediately begins to read data from the storage buffer unit 122 and streams it to the output port of the N-bit local test distribution network controller 130 at a constant clock rate configured by the serial control network component 110. It does not add any address or opcode, but only transmits the pure payload.

[0084] The flow control state machine 123 monitors the data level of the storage buffer unit 122 in real time using an elastic flow control method based on water level prediction. When the data level is higher than the high threshold, the back-end scanning clock is started and full-speed testing begins. When the water level is lower than the low threshold, the flow control state machine 123 performs a "safe pause" operation. That is, during the low-level phase of the scanning clock, the clock is cut off without glitches through the gating circuit, and a high-priority bandwidth request is sent to the functional system bus. This mechanism ensures that even when the functional system bus is extremely busy and data flow is interrupted, the back-end core under test will not experience illegal clock glitches or metastability.

[0085] Here, the standard AXI bus can only generate standard read and write transactions. The protocol conversion gateway device 120 unpacks the address data packets of the AXI bus, strips away all routing information, extracts only the pure payload, and reassembles it into a continuous bit stream. This is a "protocol reduction" technique. The usual trend inside a system-on-a-chip is to package simple protocols into complex protocols (e.g., AHB to AXI). However, the system described in this application restores the complex protocol to the most original bit stream at the end of the test path. This "reverse protocol conversion" greatly reduces the hardware overhead of the end network.

[0086] In one possible embodiment of this application, when the flow control state machine 123 is used to monitor the data fill level of the storage buffer unit 122, the flow control state machine 123 is used to:

[0087] The data consumption rate of the scan chain of the target tested core group and the target pause time of the functional system bus are collected respectively.

[0088] Based on the data consumption rate, the target pause time, and the preset safety margin coefficient, the target depth value of the storage buffer unit is determined to determine the data filling level of the storage buffer unit.

[0089] In this embodiment of the application, the target depth value of the storage buffer unit is calculated using the following formula.

[0090] .

[0091] in, This represents the target depth value (i.e., the minimum depth value). Indicates the data consumption rate (data consumption rate of the scan chain, unit: bps); Indicates the target pause time (the maximum possible pause time on the system bus, in seconds); This represents the safety margin factor.

[0092] Furthermore, the flow control state corresponding to the flow control state machine 123 can be jump-controlled based on the data filling level, scan chain length counter and configuration instruction information; the flow control state includes idle state, configuration check state, pre-charge state, flow transmission state, pause state and empty state.

[0093] For example, the idle state (IDLE) is the default state after reset, with the scan clock (Scan_Clk) held low, waiting for the serial control network component 110 to configure the feasible bit; the configuration check state (CONFIG_CHECK) is used to check if the scan chain length register (LEN_REG) is non-zero. If it is zero, an error is reported or the configuration check state is maintained; the precharge state (PRE_FILL) receives functional system bus data and writes it to the storage buffer unit 122, while the scan clock remains off; the stream transmission state (STREAMING) is used to turn on the scan clock, reading one data word from the storage buffer unit 122 each cycle, serializing it, and then sending it; the pause state (PAUSE) is used to immediately pull the scan clock signal low and gate the scan clock on the next clock edge, keeping the "WREADY" signal of the AXI interface high to receive data at full capacity; the drain state (DRAIN) no longer receives new data from the functional system bus master device 20 (or discards new data), draining the remaining data in the storage buffer unit 122 to the scan chain to finally capture the response.

[0094] For example, please refer to Figure 2 , Figure 2This is a flowchart illustrating the operation of a protocol conversion gateway device provided in an embodiment of this application. Figure 2 As shown, the workflow of the protocol conversion gateway device 120 can be summarized as: configuration, vector loading, test distribution, response processing, and result feedback. Specifically, the upper layer configures the configuration register via the AXI interface through the bus from interface 121. The configuration register sends control signals to the flow control state machine 123 to complete the initialization of test parameters. The "ScanIn Vector" (test instruction) is transmitted to the flow control state machine 123 via Scan-in, and at the same time, the vector buffer 1221 provides data to the flow control state machine 123 to complete the preparation of the test vector. The flow control state machine 123 sends the test vector to the data network encapsulator 140 via Scan-in, and then the data network encapsulator 140 passes it to the target core under test to start the test. The test response of the core is transmitted back to the flow control state machine 123 via the data network encapsulator 140 via Scan-Out. The flow control state machine 123 stores the response in the response buffer 1222, and can also send the response to the comparator for on-chip comparison. The comparison result is fed back to the response buffer 1222. The test data (and comparison result) in the response buffer is transmitted back via the bus from interface 121 to feed back the test result to the upper layer.

[0095] Furthermore, the local test distribution network controller 130 is used to send the target data to the corresponding data network encapsulator 140.

[0096] The local test distribution network corresponding to the local test distribution network controller 130 is a dedicated distribution network without routing, arbitration, or flow control handshake; the local test distribution network controller 130 includes physical connections, a multiplexer, and a fan-out buffer; the local test distribution network controller 130 is specifically used to broadcast the target data in parallel to the corresponding data network encapsulator.

[0097] In this embodiment of the application, the local test distributed network controller 130 is essentially a set of physical connections connected by multiplexers and fan-out buffers. The data flow direction is not determined by the packet header, but entirely by the previous configuration phase.

[0098] Thus, based on the idea of ​​simplifying logical design by utilizing physical determinism, since the local test distributed network controller 130 has no arbitration and queuing, its transmission delay is physically fixed. This means that the protocol conversion gateway device 120 can accurately calculate when the data arrives at the end of the scan chain of the target core group 30 under test, thereby achieving precise periodic control.

[0099] Furthermore, the data network encapsulator 140 is used to send the target data to the target core group 30 under test corresponding to the data network encapsulator 140 according to the test mode corresponding to the configuration instruction information, and to receive the status flag data sent by the target core group under test 30, and send the status flag data to the storage buffer unit 122.

[0100] In the serial operation of multiple data network encapsulators 140, the bus connection bit width between the data network encapsulators 140 can be configured to meet different scan rate requirements.

[0101] In this application embodiment, the test modes include parallel testing with the same core, parallel testing with different cores, serial testing with the same core, and parallel testing with a single core and multiple modules.

[0102] Furthermore, when the protocol conversion gateway device 120 receives the status flag data, the protocol conversion gateway device 120 is also used to perform logic or aggregation on the status flag data to generate the test result corresponding to the target tested core group 30.

[0103] Here, to further reduce bandwidth requirements, the protocol conversion gateway device 120 integrates hardware comparison logic. In comparison mode, the data stream in the storage buffer unit 122 typically uses an interleaved format, i.e., "excitation bit, expected bit, excitation bit, expected bit, etc." The flow control state machine 123 is responsible for sending the excitation bit to Scan_In and the expected bit to the comparator. Then, the actual value of Scan_Out read back from the target core group under test 30 is compared bit by bit with the extracted expected value. The comparison result is usually not stored in its entirety, but is recorded through a "sticky fault bit." Once any mismatch occurs, this bit is set to 1 and held until reset. Finally, only this status bit needs to be read to determine whether the test passed or failed.

[0104] For details, please refer to Figure 3 , Figure 3 This is a flowchart illustrating a parallel testing process using the same core, as provided in an embodiment of this application. Figure 3As shown, the test configuration is sent to the protocol conversion gateway device 120 via IJTAG configuration, and then synchronized to the local test distribution network controller 130; the broadcast test vector (Scan In) is transmitted to the local test distribution network controller 130, and the local test distribution network controller 130 distributes the vector in parallel to multiple data network encapsulators 140 via DN_Broadcast; each data network encapsulator 140 injects the test vector and collects the test response simultaneously to the corresponding AI Core (5 / 6 / 7) through the Scan In / Out interface; the data network encapsulator 140 sends the response back to the local test distribution network controller 130, and the local test distribution network controller 130 performs a consistency comparison on the responses of the same core, and finally feeds back the comparison result to the protocol conversion gateway device 120.

[0105] For details, please refer to Figure 4 , Figure 4 This is a flowchart illustrating a parallel testing process using different cores, provided as an embodiment of this application. Figure 4 As shown, the two protocol conversion gateway devices 120 are synchronized through IJTAG configuration to complete test initialization; each protocol conversion gateway device 120 independently controls the corresponding data network encapsulator 140. The data network encapsulator 140 injects test vectors in parallel to its different cores (CPU Core2, GPU Core1) through the Scan In / Out interface; CPU Core2 and GPU Core1 execute tests simultaneously, and the data network encapsulator 140 collects the test responses of the corresponding cores respectively; the data network encapsulator 140 sends the responses of its respective cores back to the corresponding protocol conversion gateway device 120, and the upper layer obtains the test results of different cores through AXI read and write.

[0106] For details, please refer to Figure 5 , Figure 5 This is a flowchart illustrating a serial testing process using the same core, as provided in an embodiment of this application. Figure 5As shown, the protocol conversion gateway device 120 is initialized via IJTAG configuration and synchronously configured with the local test distributed network controller 130. The protocol conversion gateway device 120 sends a broadcast vector (Scan In) to the local test distributed network controller 130. The local test distributed network controller 130 serially transmits the test vector to multiple data network encapsulators 140 connected in series via DN_Broadcast. The data network encapsulators 140 cooperate with Bypass through links to realize the sequential transmission of vectors. The test vectors are sequentially injected into AI Core1-4 through the Scan In / Out interface of the data network encapsulators 140 (performing tests on the same core one by one). At the same time, the data network encapsulators 140 sequentially collect the test response of each core. The test response of each core is serially returned to the local test distributed network controller 130 through the connected data network encapsulators 140. The local test distributed network controller 130 performs a consistency comparison on the responses of the same core and finally feeds back the comparison result to the protocol conversion gateway device 120. The upper layer obtains the test results through AXI read and write.

[0107] For details, please refer to Figure 6 , Figure 6 This is a flowchart illustrating a single-core, multi-module parallel testing process provided in an embodiment of this application. Figure 6 As shown, the upper layer completes the test initialization of the protocol conversion gateway device 120 through IJTAG configuration; the protocol conversion gateway device 120 simultaneously sends test vectors to two data network encapsulators 140 to achieve parallel transmission of test commands; the two data network encapsulators 140 interact with different modules inside CPU Core1 through Scan In / Out interfaces to simultaneously inject test vectors into each module and collect the test responses of each module in parallel; the two data network encapsulators 140 send the module responses they have collected back to the gateway, and the upper layer obtains the test results through AXI read and write.

[0108] Based on this, the hybrid test system described in this application firstly employs a system-on-a-chip test architecture where the control plane and data plane are completely orthogonal. The control plane uses an Inter-Jet Serial Interface (IJTAG) to focus on the static configuration and mode switching of the network topology; the data plane uses a parallel high-speed bus (AXI) to focus on the transparent transmission of massive test vectors. This architecture achieves zero configuration overhead. During the high-speed data transmission phase, the bus bandwidth is entirely used for the payload, with no protocol overhead used for transmitting instructions, thereby breaking through the efficiency limits of traditional test buses.

[0109] Then, a protocol conversion gateway device with clock domain isolation and flow shaping, embedded between the function bus and the test network, includes a flow control state machine based on water level monitoring. This flow control state machine dynamically modulates the phase and enable state of the backend test clock according to the real-time occupancy rate of the receive buffer, realizing a lossless conversion from asynchronous burst transmission to synchronous streaming transmission. This solves the noise and timing violation problems caused by directly multiplexing the function bus. In the prior art, the FIFO buffer is only used for buffering, while the embodiment of this application uses the FIFO buffer water level and the clock generator to form a closed-loop feedback control system.

[0110] Subsequently, a method for distributing multicast test data on a unicast function bus was used to write data to a specific single address of the protocol conversion gateway device. The protocol conversion gateway device used the masking logic of a pre-configured local test distribution network to concurrently distribute the data to multiple cores under test in the target test core group, thus realizing a complex multicast function. This is a "protocol spoofing" mechanism. For the function system bus master device, it thinks it is writing data to a slave device, but in fact, the data is physically broadcast to multiple nodes. This idea of ​​using standard protocols to implement non-standard functions has extremely high practical value and avoids design difficulties.

[0111] Finally, to address the bandwidth bottleneck caused by response data backhaul in parallel testing, an edge computing-based test response processing mechanism is adopted. Real-time comparison of expected values ​​is performed at the end of the local test distribution network, and only a single bit of the test result is backhauled to the protocol conversion gateway device for logical OR aggregation. This solves the problems of traditional test systems needing to store massive amounts of expected response data and insufficient bus read bandwidth. By pushing the comparison logic down to the end under test, the uplink bandwidth requirement is compressed by several orders of magnitude. This asymmetric bandwidth utilization design perfectly matches the "write-strong, read-weak" characteristics of the AXI bus.

[0112] The hybrid test system for multi-core heterogeneous system-on-a-chip provided in this application, through a hybrid test system architecture of serial control network component configuration, protocol conversion gateway device multiplexing, and local test distribution dedicated network, collaboratively solves the inherent contradictions of the prior art in terms of time, overhead, and contention in multi-core heterogeneous system-on-a-chip, improves the flexibility and scalability of testing multi-core heterogeneous system-on-a-chip, and significantly reduces hardware overhead and wiring congestion. While eliminating bus contention, it improves test efficiency and reduces the time overhead of parallel testing.

[0113] Please see Figure 7 , Figure 7 This is a flowchart illustrating a hybrid testing method for a multi-core heterogeneous system-on-a-chip (SoC) provided in an embodiment of this application. Figure 7As shown in the embodiments of this application, the hybrid testing method for multi-core heterogeneous system-on-a-chip includes:

[0114] S101. The serial control network component sends configuration command information to each protocol conversion gateway device to perform static configuration on each node in the hybrid test system.

[0115] S102. In response to receiving a burst write transaction packet sent by the functional system bus master device, the protocol conversion gateway device writes the target data corresponding to the burst write transaction packet to the storage buffer unit and sends it to the local test distributed network controller and / or data network encapsulator.

[0116] The protocol conversion gateway device includes a bus slave interface, a storage buffer unit, and a flow control state machine. The flow control state machine is used to monitor the data filling level of the storage buffer unit and dynamically generate a synchronous scan clock signal based on the data filling level to convert the asynchronous burst data written into the burst transaction packet into the target data that appears as a synchronous continuous bit stream.

[0117] S103, The local test distribution network controller sends the target data to the corresponding data network encapsulator.

[0118] S104. The data network encapsulator sends the target data to the target core group under test corresponding to the data network encapsulator according to the test mode corresponding to the configuration instruction information, and receives the status flag data sent by the target core group under test, and sends the status flag data to the storage buffer unit.

[0119] S105. When the protocol conversion gateway device receives the status flag data, the protocol conversion gateway device performs logical OR aggregation on the status flag data to generate the test result corresponding to the target tested core group.

[0120] The hybrid testing method for multi-core heterogeneous system-on-a-chip (SoC) provided in this application, through a hybrid testing system architecture of serial control network component configuration, protocol conversion gateway device multiplexing, and local test distribution dedicated network, collaboratively solves the inherent contradictions in time, overhead, and contention in existing technologies for multi-core heterogeneous SoCs. It improves the flexibility and scalability of testing multi-core heterogeneous SoCs, and significantly reduces hardware overhead and wiring congestion. While eliminating bus contention, it improves testing efficiency and reduces the time overhead of parallel testing.

[0121] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 8As shown, the electronic device 800 includes a processor 810, a memory 820, and a bus 830.

[0122] The memory 820 stores machine-readable instructions executable by the processor 810. When the electronic device 800 is running, the processor 810 and the memory 820 communicate via the bus 830. When the machine-readable instructions are executed by the processor 810, they can perform the operations described above. Figure 7 The steps of the hybrid testing method for multi-core heterogeneous system-on-a-chip in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0123] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 7 The steps of the hybrid testing method for multi-core heterogeneous system-on-a-chip in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0124] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0125] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0126] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0127] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0128] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0129] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A hybrid testing system for a multi-core heterogeneous system-on-a-chip, characterized in that, The hybrid test system includes: a serial control network component, at least one protocol conversion gateway device, a local test distribution network controller, and multiple data network encapsulators; wherein, the protocol conversion gateway device includes: a bus slave interface, a storage buffer unit, and a flow control state machine; The serial control network component is used to send configuration instruction information to each of the protocol conversion gateway devices to perform static configuration on each node in the hybrid test system; The protocol conversion gateway device is used to respond to the addressing request of the functional system bus master device by the bus slave interface and receive the burst write transaction packet sent by the functional system bus master device, write the target data corresponding to the burst write transaction packet to the storage buffer unit and send it to the local test distributed network controller and / or the data network encapsulator; The flow control state machine is used to monitor the data filling level of the storage buffer unit and dynamically generate a synchronous scan clock signal based on the data filling level, so as to convert the asynchronous burst data in the burst write transaction packet into the target data that is represented as a synchronous continuous bit stream. The local test distribution network controller is used to send the target data to the corresponding data network encapsulator; The data network encapsulator is used to send the target data to the target core group under test corresponding to the data network encapsulator according to the test mode corresponding to the configuration instruction information, and to receive the status flag data sent by the target core group under test, and send the status flag data to the storage buffer unit. When the protocol conversion gateway device receives the status flag data, the protocol conversion gateway device is further configured to perform logical OR aggregation on the status flag data to generate the test results corresponding to the target tested core group.

2. The hybrid testing system according to claim 1, characterized in that, The serial control network component includes a test subsystem access layer, a protocol conversion gateway configuration layer, and a core encapsulation access layer. When the serial control network component issues configuration instructions to each protocol conversion gateway device to perform static configuration on each node in the hybrid test system, the serial control network component is used for: The protocol conversion gateway configuration layer accesses the configuration register of each protocol conversion gateway device through a preset first configuration instruction to dynamically group the target core group under test and send the first configuration parameter in the configuration instruction information to each protocol conversion gateway device. The test subsystem access layer uses a preset second configuration instruction to write the second configuration parameter in the configuration instruction information to each node in the hybrid test system; In response to the configuration of each node in the hybrid test system taking effect, the test subsystem access layer uses a preset third configuration instruction to drive the switching of physical paths within the local test distribution network controller to establish a physical connection. The target core group under test is accessed through the core encapsulation access layer via the first configuration instruction, and the scan chain mode inside the target core group under test is configured through the second configuration instruction.

3. The hybrid testing system according to claim 1, characterized in that, The bus slave interface is used to respond to the addressing request of the functional system bus master device and to process the address handshake, data handshake and response handshake signals of the functional system bus master device; The storage buffer unit decouples the clock difference between the burst transmission of the functional system bus master device and the streaming transmission of the local test distributed network controller through asynchronous first-in-first-out, in order to absorb protocol jitter. The storage buffer unit includes a vector buffer and a response buffer; the vector buffer is used to receive the burst write transaction packet sent by the functional system bus master device, and send the target data corresponding to the burst write transaction packet to the local test distribution network controller and / or the data network encapsulator; The response buffer is used to receive the status flag data sent by the data network encapsulator for the read channel of the functional system bus to read.

4. The hybrid testing system according to claim 1, characterized in that, When monitoring the data fill level of the storage buffer unit, the flow control state machine is used to: The data consumption rate of the scan chain of the target tested core group and the target pause time of the functional system bus are collected respectively. Based on the data consumption rate, the target pause time, and the preset safety margin coefficient, the target depth value of the storage buffer unit is determined to determine the data filling level of the storage buffer unit.

5. The hybrid testing system according to claim 1, characterized in that, The flow control state corresponding to the flow control state machine can be jump-controlled based on the data filling level, scan chain length counter and configuration instruction information; the flow control state includes idle state, configuration check state, pre-fill state, stream transmission state, pause state and empty state.

6. The hybrid testing system according to claim 1, characterized in that, The local test distribution network corresponding to the local test distribution network controller is a dedicated distribution network without routing, arbitration, or flow control handshake; the local test distribution network controller includes physical connections, multiplexers, and fan-out buffers; the local test distribution network controller is specifically used to broadcast the target data in parallel to the corresponding data network encapsulator.

7. The hybrid testing system according to claim 1, characterized in that, The test modes include parallel testing with the same core, parallel testing with different cores, serial testing with the same core, and parallel testing with a single core and multiple modules.

8. A hybrid testing method for a multi-core heterogeneous system-on-a-chip, characterized in that, The hybrid testing method includes: The serial control network component sends configuration instructions to each protocol conversion gateway device to perform static configuration on each node in the hybrid test system. The protocol conversion gateway device responds to the addressing request of the functional system bus master device via its bus slave interface and receives a burst write transaction packet sent by the functional system bus master device. It then writes the target data corresponding to the burst write transaction packet to a storage buffer unit and sends it to a local test distributed network controller and / or a data network encapsulator. The protocol conversion gateway device includes a bus slave interface, a storage buffer unit, and a flow control state machine. The flow control state machine monitors the data fill level of the storage buffer unit and, based on the data fill level, dynamically generates a synchronous scan clock signal to convert the asynchronous burst data in the burst write transaction packet into the target data, which appears as a synchronous continuous bit stream. The target data is sent by the local test distribution network controller to the corresponding data network encapsulator; The data network encapsulator sends the target data to the target core group under test corresponding to the data network encapsulator according to the test mode corresponding to the configuration instruction information, and receives the status flag data sent by the target core group under test, and sends the status flag data to the storage buffer unit. When the protocol conversion gateway device receives the status flag data, it performs logical OR aggregation on the status flag data to generate the test result corresponding to the target core group under test.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the hybrid testing method for a multi-core heterogeneous system-on-a-chip as described in claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the hybrid testing method for multi-core heterogeneous system-on-a-chip as described in claim 8.

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