FPGA (Field Programmable Gate Array) method for increasing communication distance and stability of communication data

Abstract

The invention relates to a field programmable gate array (FPGA) method for increasing communication distance and communication data stability, which relates to the technical field of communication and comprises the following steps: firstly, acquiring a clock signal and a data signal corresponding to serial data; then, according to a plurality of clock sampling points corresponding to the clock signal, obtaining a filtered clock signal; in response to the detected rising edge of the filtered clock signal, starting data latching, and determining a plurality of data sampling points corresponding to the rising edge in the data signal; obtaining filtered data signals according to the numerical values corresponding to the plurality of data sampling points; and finally, carrying out self-synchronization coding on the filtered clock signal and the filtered data signal to obtain coded serial data. According to the scheme, the data signals are filtered through the data sampling points corresponding to the rising edges in the clock signals, the coded serial data are obtained through self-synchronization coding, interference in the serial data is reduced, and the reliability of the serial data is improved.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and more specifically to an FPGA method for increasing communication distance and communication data stability. Background Technology

[0002] In an industrial distributed control system (DCS), the link layer between control units and cards typically uses asynchronous serial ports or High-Level Data Link Control (HDLC) for data exchange, while the application layer uses different protocol packet formats depending on the function.

[0003] Currently, with the increase in communication distance and the number of cards, the resistance and capacitance characteristics and interference on the communication bus are constantly changing, which can lead to some symbol transmission errors during communication and affect the reliability of information transmission. Summary of the Invention

[0004] In view of this, this disclosure provides a field-programmable gate array (FPGA) method for increasing communication distance and communication data stability. The main purpose is to solve the technical problem that as the communication distance and the number of cards increase, the resistance and capacitance characteristics and interference on the communication bus are constantly changing, which leads to some symbol transmission errors during the communication process and affects the reliability of information transmission.

[0005] According to a first aspect of this disclosure, an FPGA method for increasing communication distance and communication data stability is provided, the method comprising: Obtain the clock signal and data signal corresponding to the serial data; Based on the multiple clock sampling points corresponding to the clock signal, the filtered clock signal is obtained; In response to detecting the rising edge of the filtered clock signal, data latching is initiated, and multiple data sampling points corresponding to the rising edge are determined in the data signal; Based on the values ​​corresponding to the multiple data sampling points, the filtered data signal is obtained; The filtered clock signal and the filtered data signal are self-synchronized and encoded to obtain the encoded serial data.

[0006] According to a second aspect of this disclosure, an FPGA device for increasing communication distance and communication data stability is provided, the device comprising: The acquisition module is used to acquire the clock signal and data signal corresponding to the serial data; and to acquire the filtered clock signal based on multiple clock sampling points corresponding to the clock signal. The determination module is used to initiate data latching in response to detecting the rising edge of the filtered clock signal, and to determine multiple data sampling points corresponding to the rising edge in the data signal; The acquisition module is used to acquire the filtered data signal based on the values ​​corresponding to the plurality of data sampling points; The encoding module is used to perform self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain encoded serial data.

[0007] According to a third aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to said at least one processor; wherein the memory stores instructions executable by said at least one processor, said instructions being executed by said at least one processor to enable said at least one processor to perform the method of the first aspect described above.

[0008] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause a computer to perform the method of the first aspect described above.

[0009] This disclosure provides an FPGA method for increasing communication distance and communication data stability. Compared with related technologies, this disclosure first acquires a clock signal and a data signal corresponding to serial data; then, based on multiple clock sampling points corresponding to the clock signal, it acquires a filtered clock signal; in response to detecting the rising edge of the filtered clock signal, it initiates data latching and determines multiple data sampling points corresponding to the rising edge in the data signal; then, based on the values ​​corresponding to the multiple data sampling points, it acquires a filtered data signal; finally, it performs self-synchronization encoding on the filtered clock signal and the filtered data signal to acquire encoded serial data. Through the scheme of this disclosure, this embodiment can acquire multiple clock sampling points of the clock signal corresponding to serial data, filter the clock signal, initiate data latching in response to detecting the rising edge of the filtered clock signal, use multiple data sampling points corresponding to the rising edge in the clock signal to filter the data signal, and finally perform self-synchronization encoding on the filtered clock signal and the filtered data signal to acquire encoded serial data. This achieves filtering of the clock signal and data signal, reduces symbol transmission errors during communication, effectively suppresses noise and interference in the serial data, and thus significantly improves the stability and reliability of data transmission. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating an FPGA method for increasing communication distance and communication data stability provided in an embodiment of this disclosure. Figure 2 This is a flowchart illustrating another FPGA method for increasing communication distance and communication data stability provided in an embodiment of this disclosure. Figure 3 A flowchart illustrating an example provided in an embodiment of this application is shown; Figure 4 A flowchart illustrating an example provided in an embodiment of this application is shown; Figure 5 A flowchart illustrating an example provided in an embodiment of this application is shown; Figure 6 This is a schematic diagram of the structure of an FPGA device for increasing communication distance and communication data stability, provided as an embodiment of the present disclosure. Detailed Implementation

[0013] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments of this disclosure and the features described therein can be combined with each other.

[0014] The following describes an embodiment of the FPGA method for increasing communication distance and communication data stability, with reference to the accompanying drawings.

[0015] This disclosure provides an FPGA method for increasing communication distance and communication data stability. The main purpose is to solve the technical problem that as the communication distance and the number of cards increase, the RC characteristics and interference on the communication bus also change, which leads to some symbol transmission errors during the communication process and affects the reliability of information transmission.

[0016] like Figure 1 As shown, embodiments of this disclosure provide an FPGA method for increasing communication distance and communication data stability, including: Step 101: Obtain the clock signal and data signal corresponding to the serial data.

[0017] In digital communication systems, especially in scenarios involving serial communication, it is necessary to correctly receive and parse serial data. Clock signals can be used to provide a time reference and determine when to sample data. Data signals can be used to carry the actual transmitted bit stream (0 and 1). The clock and data signals corresponding to serial data can be obtained directly through independent clock lines, such as through clock pins and data pins. When there are no independent clock lines, clock beats can also be simulated through the system clock and baud rate generator, and sampled from the data pins, combined with edge detection to recover bits.

[0018] Step 102: Obtain the filtered clock signal based on the multiple clock sampling points corresponding to the clock signal.

[0019] In industrial settings (such as DCS systems), externally input clock signals (such as HDLC clocks) may be affected by electromagnetic interference, signal jitter, glitches, and transitions caused by poor contact. Directly using such clock signals may lead to false edge triggering, ultimately resulting in serial data errors. Therefore, the original clock signal can be sampled at multiple points using the system clock and filtered using filtering algorithms (such as majority decision, median method, averaging, weighted, threshold decision, etc.) to remove noise and glitches, generating a stable, reliable, and clean clock signal that can be used for subsequent edge detection and data sampling. This can be widely applied in anti-interference scenarios such as industrial DCS and HDLC communication to reduce communication interference to serial data and achieve long-distance anti-interference communication.

[0020] Step 103: In response to the detection of the rising edge of the filtered clock signal, start data latching and determine multiple data sampling points corresponding to the rising edge in the data signal.

[0021] In some embodiments, an edge detection can trigger a sampling control logic that, in response to the rising edge of the filtered clock signal, samples the data signal multiple times under the drive of the system clock to obtain multiple data sampling points corresponding to the clock cycle. Data latching is then completed through majority decision or intermediate value selection, thereby using multiple data sampling points to lock the data value under the clock cycle and collect it, achieving accurate sampling and anti-interference, and thus realizing highly reliable and anti-interference serial data transmission.

[0022] Step 104: Obtain the filtered data signal based on the values ​​corresponding to multiple data sampling points.

[0023] In some embodiments, the values ​​of multiple data sampling points can be obtained first. Specifically, multiple data sampling points can be determined before and after the rising edge of the clock signal, and multiple samplings can be performed to obtain multiple point values. Combined with filtering algorithms, the effects of noise, jitter, or glitches can be eliminated to restore the most likely true data value of the data signal and generate a filtered data signal. This reduces the occurrence of symbol transmission errors during communication, thereby obtaining a data signal with strong anti-interference ability and high stability.

[0024] Step 105: Perform self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain the encoded serial data.

[0025] In some embodiments, a self-synchronizing encoding method (such as Manchester encoding) can be used to combine the filtered data signal with clock information to generate an encoded serial data signal. The encoded serial data may include data information and clock information, allowing the receiving end to simultaneously recover the data and clock from the signal. For example, Manchester encoding can be used, where each bit has a transition in the middle, making synchronization easy. The receiver can recover the clock accordingly. This method has strong anti-interference capabilities and is suitable for long-distance communication. Through self-synchronizing encoding, an encoded serial signal containing both data and implicit clock information can be generated, reducing the possibility of symbol transmission errors during communication and improving communication reliability.

[0026] Compared with related technologies, this embodiment first acquires the clock signal and data signal corresponding to the serial data; then, based on multiple clock sampling points corresponding to the clock signal, it acquires the filtered clock signal; in response to the detection of the rising edge of the filtered clock signal, it initiates data latching and determines multiple data sampling points corresponding to the rising edge in the data signal; then, based on the values ​​corresponding to the multiple data sampling points, it acquires the filtered data signal; finally, it performs self-synchronization encoding on the filtered clock signal and the filtered data signal to acquire the encoded serial data. Through the scheme disclosed herein, this embodiment can acquire multiple clock sampling points of the clock signal corresponding to the serial data, filter the clock signal, initiate data latching in response to the detection of the rising edge of the filtered clock signal, use multiple data sampling points corresponding to the rising edge in the clock signal to filter the data signal, and finally perform self-synchronization encoding on the filtered clock signal and the filtered data signal to acquire the encoded serial data. This achieves filtering of the clock signal and data signal, reduces symbol transmission errors during communication, effectively suppresses noise and interference in the serial data, and thus significantly improves the stability and reliability of data transmission.

[0027] Based on the technical implementation described in the above embodiments, in order to further illustrate the specific implementation process of the method in this embodiment, this embodiment provides the following: Figure 2 The specific method shown includes: Step 201: Obtain the clock signal and data signal corresponding to the serial data.

[0028] In specific application scenarios, the execution entity of this embodiment can be a receiving end, used to receive the clock signal and then the data signal corresponding to the serial data.

[0029] Optionally, the method in this embodiment further includes: performing delay processing on the clock signal and the data signal; and obtaining the delayed clock signal and the data signal.

[0030] Optionally, the filtered clock signal can be obtained based on multiple clock sampling points corresponding to the clock signal. Specifically, it may also include: acquiring multiple clock sampling points in the delayed clock signal, filtering the delayed clock signal, and obtaining the filtered clock signal.

[0031] In some embodiments, such as Figure 3 As shown, in the FPGA system solution, a clock of F=48MHz can be used as the system clock. This clock is used to filter the clock signal on the HDLC bus, and then the data bus data is acquired using the edge of the filtered clock signal (the falling edge of the clock indicates data inversion). Before acquiring the data, a delay module can be used to delay the clock signal and data signal on the bus. The clock signal i_clk and the data signal i_data can be input from outside the system, or through other modules or communication interfaces, to facilitate subsequent data extraction. After DIY using the delay module, the delayed clock signal clk_dly and data signal data_dly can be output. This delay processing of the input signals helps to eliminate metastability, glitches, and other noise, ensuring that the clock and data signals have a stable timing relationship in subsequent processing.

[0032] Correspondingly, the delayed clock signal clk_dly can enter the clock signal filtering module for further noise reduction, removing jitter, glitches, and other interference. Possible methods include debouncing counters and low-pass filters, outputting a clean, filtered clock signal o_clk. Then, the data signal acquisition module can sample the delayed data signal data_dly based on the rising edge (clk_posedge) of the filtered clock signal o_clk, ensuring that the data is correctly latched at a stable clock edge, and obtain the filtered data signal o_data. This delay and filtering process on the input clock and data signals helps improve the stability and reliability of data transmission.

[0033] Step 202: Obtain multiple clock sampling points corresponding to the current time.

[0034] Among them, multiple clock sampling points may include, but are not limited to, the sampling point corresponding to the current time, the sampling point of the first time, the sampling point of the second time, etc. The sampling point of the first time may include, but is not limited to, a first preset number of time sampling points before the current time, and the sampling point of the second time may include, but is not limited to, a second preset number of time sampling points after the current time.

[0035] Optionally, the first preset number and the second preset number can be configured as parameters to better filter interference, depending on the specific on-site interference and hardware environment.

[0036] For example, the sampling point corresponding to the current time, the sampling points of N clock times after the current time can be obtained as the first time sampling point, and the sampling points of M clock times before the current time can be obtained as the second time sampling point, thereby obtaining multiple clock sampling points corresponding to the current time.

[0037] Step 203: Using preset clock filtering conditions, obtain the filtered clock signal based on the point values ​​corresponding to multiple clock sampling points.

[0038] Optionally, step 203 may specifically include: using preset clock filtering conditions, determining the clock edge corresponding to the clock signal based on the point value corresponding to the sampling point at the first time and the point value corresponding to the sampling point at the second time, wherein the preset clock filtering conditions are used to identify glitches in the clock signal and determine the rising and falling edges of the clock signal; and obtaining the filtered clock signal based on the clock edge.

[0039] For example, mean filtering can be used to eliminate glitches and interference. The preset clock filtering condition can be expressed as: ; In the formula, The value can represent the point value corresponding to the k-th clock sampling point, N can represent the N clock moments after the current moment, and M can represent the M clock sampling points before the current moment. Specifically, if at least N / 2 of the sampling points at the current moment and the N clock moments after it have a value of 1, and the values ​​of the M clock sampling points before the current moment are all 0, then the current point is determined to be the rising edge of the clock, and data latching is initiated.

[0040] For example, without considering overall latency, such as Figure 4 As shown, the timing diagrams before and after clock and data filtering are illustrated, including the original clock with clock glitches, the original data with data glitches, the filtered clock, and the filtered data.

[0041] In this way, the rising edge of the clock signal can be determined by using preset clock filtering conditions, and glitches in the signal can be removed to obtain the filtered clock signal.

[0042] Optionally, multiple clock sampling points can be determined from the delayed clock signal, and then the rising edge in the delayed clock signal can be determined using preset clock filtering conditions. The delayed clock signal can be filtered to obtain the filtered clock signal, which reduces the occurrence of symbol transmission errors during communication and further improves the accuracy of the clock signal.

[0043] Step 204: Trigger data latching at the rising edge of the filtered clock signal, and determine multiple data sampling points from the data signal based on the rising edge time.

[0044] The multiple data sampling points may include, but are not limited to, a first data sampling point and a second data sampling point. The first data sampling point may include, but is not limited to, a third preset number of data sampling points before the rising edge time, and the second data sampling point may include, but is not limited to, a fourth preset number of data sampling points after the rising edge time.

[0045] Optionally, the third and fourth preset numbers can be configured as parameters to better filter interference, depending on specific on-site interference and hardware environment.

[0046] For example, L sampling points can be taken before each rising edge of the bus clock as the first data sampling points, and L sampling points can be taken after the rising edge of the clock as the second data sampling points, thereby obtaining multiple data sampling points corresponding to the rising edge, which facilitates the filtering of the data signal.

[0047] Step 205: Obtain the filtered data signal based on the values ​​corresponding to multiple data sampling points.

[0048] Optionally, step 205 may specifically include: obtaining the filtered data signal based on preset data filtering conditions and the values ​​corresponding to multiple data sampling points. The preset data filtering conditions are used to identify glitches in the data signal and determine the data value corresponding to the data signal.

[0049] In some embodiments, the preset data filtering condition can be expressed as: ; In the formula, The value can be represented by the k-th data sampling point, and l can represent the L sampling points taken before the rising edge of each bus clock.

[0050] Specifically, data latching is triggered at each rising edge of the bus clock. A multiple sampling and averaging scheme is adopted. L sampling points are taken before each rising edge of the bus clock and L sampling points are taken after the rising edge of the clock. If the sum of the values ​​of the L sampling points before the rising edge and the L sampling points after the rising edge is greater than L, the current data value can be determined to be 1; if the sum of the values ​​of the L sampling points before the rising edge and the L sampling points after the rising edge is less than or equal to L, the current data value can be determined to be 0.

[0051] In this way, the rising edge of the clock, determined by the preset clock filtering conditions, can be used to start data latching. By using multiple data sampling points corresponding to the rising edge and the preset data filtering conditions, the data value can be determined, data glitches in the data signal can be removed, and thus the filtered data signal can be obtained, improving the anti-interference ability of the data signal and improving the accuracy of data transmission.

[0052] Optionally, multiple data sampling points can be determined from the delayed data signal based on the rising edge of the delayed clock signal. Then, the delayed data signal can be filtered using preset data filtering conditions to obtain the filtered data signal. This reduces the occurrence of symbol transmission errors during communication and further improves the accuracy of the data signal.

[0053] Step 206: Perform self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain the encoded serial data.

[0054] Optionally, step 206 may specifically include: using preset level conversion conditions to perform self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain the encoded serial data. The preset level conversion conditions include the correspondence between level and data symbols.

[0055] In some embodiments, the preset level conversion conditions may include: using high-low level conversion to represent "0" or "1", where the level conversion in the middle of each bit represents both a data symbol and a timing signal, using a 1->0 conversion to represent "0" and a 0->1 level change to represent "1", and sending the encoded serial data to the receiving end helps to reduce symbol transmission errors during communication.

[0056] For example, such as Figure 5As shown, the signal timing diagram before and after encoding is displayed. The signal clock (NHz) and the original data signal can be self-synchronized and encoded according to the preset level conversion conditions to obtain the encoded signal and the encoded clock (2NHz). After encoding, the data communication no longer uses a dedicated clock channel, and the data rate can be increased from the original Nbps to 2Nbps. In this way, the bit stream can be filtered and encoded without involving the application layer protocol, occupying less FPGA resources, and the data transmission delay is smaller, which effectively improves the real-time performance of communication.

[0057] Correspondingly, for the receiving end, a data stream that has undergone self-synchronization coding (such as Manchester) has the following characteristics: (1) Under an encoding clock of f=2N Hz, the longest level width is 1 / N; (2) The end edge of the wide level must be the original clock fixed edge.

[0058] Decoding utilizes these two characteristics. When the encoded symbol length L = 1 / N, it is the falling edge of the bus clock. At this point, the initial phase of the bus recovery clock is found. Subsequently, the bus recovery clock reverses once every F / 2N clock cycles. When the symbol length L = 1 / N is encountered again, it is the falling edge of the bus clock, and the bus recovery clock can be phase aligned again. In this way, the recovery clock in the decoding stage performs phase alignment at any time during the data stream reception process in order to maintain the phase relationship of the clock data.

[0059] In this way, after filtering, the self-synchronized encoded data can be used as a high-speed serial data stream, carrying clock information for long-distance transmission via optical fiber or a more stable transmission medium. The receiving end can use the Manchester encoding characteristics to recover the clock and data of the original signal, ultimately improving the security and reliability of data interaction.

[0060] Compared with related technologies, this embodiment can collect multiple clock sampling points of the clock signal corresponding to the serial data, filter the clock signal, and start data latching in response to the detection of the rising edge of the filtered clock signal. It can also use multiple data sampling points corresponding to the rising edge of the clock signal to filter the data signal. Finally, it can perform self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain the encoded serial data. This reduces the occurrence of symbol transmission errors during communication, effectively suppresses noise and interference in the serial data, and thus significantly improves the stability and reliability of data transmission. Specifically, a certain delay processing can be applied to the clock signal and data signal to ensure a stable time relationship between them in subsequent processing. Data latching is initiated using the rising edge of the clock determined by preset clock filtering conditions. Multiple data sampling points corresponding to the rising edge and preset data filtering conditions are used to determine the data value, removing data glitches from the data signal to obtain a filtered data signal. This improves the anti-interference capability of the data signal and enhances data transmission accuracy. Furthermore, filtering and encoding processing is performed on the bitstream. This process does not involve application layer protocols, consumes relatively few FPGA resources, and has a low data transmission delay, improving real-time communication performance, enhancing the stability and reliability of industrial field communication, and enabling longer communication distances.

[0061] Based on the above Figure 1 and Figure 2 The specific implementation of the method shown in this embodiment provides an FPGA device for increasing communication distance and communication data stability, such as... Figure 6 As shown, the device includes: an acquisition module 31, a determination module 32, and an encoding module 33; The acquisition module 31 is used to acquire the clock signal and data signal corresponding to the serial data; and to acquire the filtered clock signal based on multiple clock sampling points corresponding to the clock signal. The determination module 32 is used to start data latching in response to the detection of the rising edge of the filtered clock signal, and determine multiple data sampling points corresponding to the rising edge in the data signal; The acquisition module 31 is used to acquire the filtered data signal based on the values ​​corresponding to multiple data sampling points; The encoding module 33 is used to perform self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain the encoded serial data.

[0062] In some examples of this embodiment, the acquisition module 31 is specifically configured to acquire multiple clock sampling points corresponding to the current time; and to acquire a filtered clock signal based on the point values ​​corresponding to the multiple clock sampling points using preset clock filtering conditions. The multiple clock sampling points include the sampling point corresponding to the current time, the sampling point at the first time, and the sampling point at the second time. The sampling point at the first time includes a first preset number of time sampling points before the current time, and the sampling point at the second time includes a second preset number of time sampling points after the current time.

[0063] In some examples of this embodiment, the acquisition module 31 is specifically configured to use a preset clock filtering condition to determine the clock edge corresponding to the clock signal based on the point value corresponding to the sampling point at the first time and the point value corresponding to the sampling point at the second time. The preset clock filtering condition is used to identify glitches in the clock signal and determine the rising and falling edges of the clock signal; and to acquire the filtered clock signal based on the clock edge.

[0064] In some examples of this embodiment, the determining module 32 is specifically configured to trigger data latching at the rising edge of the filtered clock signal and determine multiple data sampling points from the data signal based on the rising edge time. The multiple data sampling points include a first data sampling point and a second data sampling point. The first data sampling point includes a third preset number of data sampling points before the rising edge time, and the second data sampling point includes a fourth preset number of data sampling points after the rising edge time.

[0065] In some examples of this embodiment, the acquisition module 31 is specifically configured to acquire the filtered data signal based on preset data filtering conditions and the values ​​corresponding to multiple data sampling points. The preset data filtering conditions are used to identify glitches in the data signal and determine the data value corresponding to the data signal.

[0066] In some examples of this embodiment, the encoding module 33 is specifically configured to perform self-synchronization encoding on the filtered clock signal and the filtered data signal using preset level conversion conditions to obtain encoded serial data. The preset level conversion conditions include the correspondence between level and data symbols.

[0067] In some examples of this embodiment, the acquisition module 31 is further configured to perform delay processing on the clock signal and the data signal; and acquire the delayed clock signal and the data signal.

[0068] In some examples of this embodiment, the acquisition module 31 is further configured to acquire multiple clock sampling points in the delayed clock signal, perform filtering processing on the delayed clock signal, and acquire the filtered clock signal.

[0069] Based on the above, Figure 1 and Figure 2Accordingly, this embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. Figure 1 and Figure 2 The method shown.

[0070] Based on this understanding, the technical solution disclosed herein can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, or portable hard drive) and includes several instructions to cause a computer device (such as a personal computer, server, or network device) to execute the methods of various implementation scenarios of this disclosure.

[0071] Based on the above, Figure 1 and Figure 2 The method shown, and Figure 6 To achieve the above objectives, this disclosure also provides an electronic device, comprising a storage medium and a processor; the storage medium for storing a computer program; and the processor for executing the computer program to implement the above-described virtual device embodiments. Figure 1 and Figure 2 The method shown.

[0072] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0073] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0074] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the aforementioned physical device, supporting the operation of information processing programs and other software and / or programs. The network communication module is used to enable communication between the various components within the storage medium, as well as communication with other hardware and software in the information processing physical device.

[0075] Through the above description of the embodiments, those skilled in the art can clearly understand that this disclosure can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. Through the scheme of this disclosure, this embodiment can collect multiple clock sampling points of the clock signal corresponding to the serial data, filter the clock signal, and in response to the detection of the rising edge of the filtered clock signal, start data latching, use multiple data sampling points corresponding to the rising edge of the clock signal to filter the data signal, and finally perform self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain the encoded serial data. This achieves filtering of the clock signal and the data signal, reduces the occurrence of symbol transmission errors during communication, effectively suppresses noise and interference in the serial data, and thus significantly improves the stability and reliability of data transmission. Specifically, a certain delay processing can be applied to the clock signal and data signal to ensure a stable time relationship between them in subsequent processing. Data latching is initiated using the rising edge of the clock determined by preset clock filtering conditions. Multiple data sampling points corresponding to the rising edge and preset data filtering conditions are used to determine the data value, removing data glitches from the data signal to obtain a filtered data signal. This improves the anti-interference capability of the data signal and enhances data transmission accuracy. Furthermore, filtering and encoding processing is performed on the bitstream. This process does not involve application layer protocols, consumes relatively few FPGA resources, and has a low data transmission delay, improving real-time communication performance, enhancing the stability and reliability of industrial field communication, and enabling longer communication distances.

[0076] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0077] The above are merely specific embodiments of this disclosure, enabling those skilled in the art to understand or implement this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. An FPGA method for increasing communication distance and communication data stability, characterized in that, include: Obtain the clock signal and data signal corresponding to the serial data; Based on the multiple clock sampling points corresponding to the clock signal, the filtered clock signal is obtained; In response to detecting the rising edge of the filtered clock signal, data latching is initiated, and multiple data sampling points corresponding to the rising edge are determined in the data signal; Based on the values ​​corresponding to the multiple data sampling points, the filtered data signal is obtained; The filtered clock signal and the filtered data signal are self-synchronized and encoded to obtain the encoded serial data.

2. The method according to claim 1, characterized in that, The step of obtaining the filtered clock signal based on multiple clock sampling points corresponding to the clock signal includes: Obtain multiple clock sampling points corresponding to the current time; Using preset clock filtering conditions, the filtered clock signal is obtained based on the point values ​​corresponding to the multiple clock sampling points.

3. The method according to claim 2, characterized in that, The plurality of clock sampling points include the sampling point corresponding to the current time, the sampling point at the first time, and the sampling point at the second time. The sampling point at the first time includes a first preset number of sampling points before the current time, and the sampling point at the second time includes a second preset number of sampling points after the current time.

4. The method according to claim 3, characterized in that, The step of obtaining the filtered clock signal based on the point values ​​corresponding to the multiple clock sampling points using preset clock filtering conditions includes: Using a preset clock filtering condition, the clock edge corresponding to the clock signal is determined based on the point value corresponding to the sampling point at the first time and the point value corresponding to the sampling point at the second time. The preset clock filtering condition is used to identify glitches in the clock signal and determine the rising and falling edges of the clock signal. The filtered clock signal is obtained based on the clock edge.

5. The method according to claim 1, characterized in that, In response to detecting the rising edge of the filtered clock signal, data latching is initiated, and multiple data sampling points corresponding to the rising edge are determined in the data signal, including: Data latching is triggered at the rising edge of the filtered clock signal, and the plurality of data sampling points are determined from the data signal based on the rising edge time; The plurality of data sampling points include a first data sampling point and a second data sampling point. The first data sampling point includes a third preset number of data sampling points before the rising edge time, and the second data sampling point includes a fourth preset number of data sampling points after the rising edge time.

6. The method according to claim 5, characterized in that, The step of obtaining the filtered data signal based on the values ​​corresponding to the plurality of data sampling points includes: Based on preset data filtering conditions and the values ​​corresponding to the multiple data sampling points, a filtered data signal is obtained. The preset data filtering conditions are used to identify glitches in the data signal and determine the data value corresponding to the data signal.

7. The method according to claim 1, characterized in that, The step of performing self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain encoded serial data includes: Using preset level conversion conditions, the filtered clock signal and the filtered data signal are self-synchronized and encoded to obtain encoded serial data. The preset level conversion conditions include the correspondence between level and data symbols.

8. The method according to claim 1, characterized in that, After acquiring the clock signal and data signal corresponding to the serial data, the method further includes: The clock signal and the data signal are delayed. Obtain the clock signal and data signal after delay processing.

9. The method according to claim 8, characterized in that, The step of obtaining the filtered clock signal based on multiple clock sampling points corresponding to the clock signal further includes: Multiple clock sampling points are collected from the delayed clock signal, and the delayed clock signal is filtered to obtain the filtered clock signal.

10. An FPGA device for increasing communication distance and communication data stability, characterized in that, include: The acquisition module is used to acquire the clock signal and data signal corresponding to the serial data; Based on the multiple clock sampling points corresponding to the clock signal, the filtered clock signal is obtained; The determination module is used to initiate data latching in response to detecting the rising edge of the filtered clock signal, and to determine multiple data sampling points corresponding to the rising edge in the data signal; The acquisition module is used to acquire the filtered data signal based on the values ​​corresponding to the multiple data sampling points; The encoding module is used to perform self-synchronization encoding on the filtered clock signal and the filtered data signal to obtain encoded serial data.

11. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-9.

12. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-9.

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