Fast-SSCF decoding method and device
By employing Bartholomew's parameter pre-computation and hierarchical caching strategies in Fast-SSCF decoding, the caching conditions for flipped bits are optimized, the redundant computation problem of decoding restart is solved, hardware resource consumption and decoding latency are reduced, and error correction performance is improved.
Patent Information
- Application Number
- CN202511650216.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-12
- Publication Date
- 2026-02-24
AI Technical Summary
Existing Fast-SSCF decoding algorithms suffer from limited bit error rate performance in low signal-to-noise ratio scenarios, excessive hardware resource consumption and latency, and existing optimization strategies struggle to find a balance between improving error correction capabilities and reducing complexity.
By recursively pre-calculating the channel error probability based on the Parseltongue parameter during the first decoding, caching the LLR sequence, partial sum, and decision results, and employing a hierarchical caching and low-level fast recovery algorithm, the cache activation conditions for flipped bits are optimized, thereby reducing the decoding restart latency.
While significantly saving storage resources, it reduces restart decoding latency and achieves an efficient balance between hardware resource consumption and error correction performance, especially in high signal-to-noise ratio scenarios where its performance is close to that of the CA-SCL algorithm.
Smart Images
Figure CN121567136A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of communication technology, specifically relating to a Fast-SSCF decoding method and apparatus. Background Technology
[0002] With the increasing demands for high reliability and low latency in communication systems, polar codes, as a core channel coding scheme in the 5G standard, have seen their decoding algorithms optimized, becoming a research hotspot. The traditional Fast Simplified Continuous Elimination (Fast-SSC) algorithm reduces recursion depth through code tree pruning, significantly improving decoding speed. However, it still belongs to the continuous elimination framework, limiting its bit error rate performance in low signal-to-noise ratio scenarios. Based on this, researchers proposed the Fast-SSC algorithm (Fast-SSCF) based on a flip mechanism, which enhances error correction capabilities by identifying key error bits and restarting decoding. However, existing flip mechanisms have significant drawbacks: restarting decoding requires recalculating the log-likelihood ratio (LLR) and partial sums of the entire code tree, leading to a significant increase in computational complexity, especially in high code length or multi-round flip scenarios, resulting in a sharp increase in hardware resource consumption and latency.
[0003] On the other hand, while existing research attempts to optimize the flip mechanism through dynamic path selection or local update strategies, it generally faces a dilemma between performance and complexity: simply increasing the number of flips to improve error correction capability will lead to an exponential increase in hardware resource consumption; while oversimplifying the control logic will result in limited improvement in bit error rate. For example, in the decoding of typical polar codes (N=1024), the traditional continuous elimination flip (SC-Flip) algorithm requires more than 30% additional logic resources, but the bit error rate gain is only about 0.2dB. Although the CRC (Cyclic Redundancy Check)-assisted early termination strategy can reduce invalid decoding, its synergistic optimization with the flip mechanism is still insufficient, and redundant calculations during the restart process have not been systematically resolved. Summary of the Invention
[0004] To address the aforementioned problems in the existing technology, this invention proposes a Fast-SSCF decoding method and apparatus to improve error correction performance, reduce hardware resource consumption, and reduce decoding latency.
[0005] A Fast-SSCF decoding method of the present invention includes:
[0006] Step 1: The decoder obtains the codeword sequence to be decoded and the level 1 log-likelihood ratio (LLR) sequence from the channel;
[0007] Step Two: Utilize functions and The function computes the LLR sequence required to determine the current node. ;
[0008] Step 3: Based on the node type of the current decoding node, perform decoding decisions on the current decoding node to obtain the decision results for each bit of the current decoding node;
[0009] Step 4: Select the quantization bit width;
[0010] Step 5: If the conditional probability that the flipped bit is located in the second half of the codeword to be decoded is greater than the preset threshold value, cache the LLR sequence of each level, the partial sum, and the decision results from the 1st bit to the N / 2nd bit to the BRAM storage module.
[0011] Step 6: If the decoding CRC check fails, flip the bit corresponding to the flipped bit position index;
[0012] Step 7: If the BRAM storage module has cached the decoded data and the flipped bit position index is not less than N / 2, perform fast decoding;
[0013] Where N is the length of the codeword to be decoded.
[0014] Furthermore, step three includes:
[0015] If the current decoding node type is R0, set the decision result of each bit of the current decoding node to 0;
[0016] If the current decoding node type is R1, for Perform a hard decision to obtain the decision result for each bit;
[0017]
[0018] If the current decoding node type is SPC, set the decision result of the first frozen bit of the previous decoding node to 0; perform hard decision on the LLR value of the information bits to obtain the decision result of each bit.
[0019]
[0020] The parity of the decision result is checked. If the parity is incorrect, the bit with the smallest absolute value of LLR in the information bits is selected and the decision result of that bit is flipped.
[0021] If the current decoding node type is REP, set the decision result of the frozen bits of the previous decoding node to 0; perform a weighted summation of the LLR of the frozen bits to obtain the weighted summation value. ;right Perform a hard decision to obtain the decision result for the information bits;
[0022]
[0023]
[0024] in, For the decision result of the k-th bit, The decision result for the Nth bit; for The k-th LLR value in the equation; the parity correctness means that the sum of all bit decision results is even.
[0025] Preferably, the quantization bit width in step four is set to 6 bits.
[0026] Furthermore, step five includes:
[0027] During the initial decoding, the channel error probability is recursively pre-calculated based on the Parseltongue parameters. ;
[0028]
[0029]
[0030]
[0031] Calculate the error probability of the k-th bit;
[0032]
[0033] Pre-calculate the conditional probability that the flipped bit is located in the second half of the codeword to be decoded. ;
[0034]
[0035] like Greater than the preset threshold value The LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit are cached in the BRAM storage module.
[0036] in, Let k be the error probability of the k-th bit. Let be the index of the flipped bit position in the t-th flip operation. This is the set of flipped bit indices for the current decoding node; For noise power spectral density, Let be the bit energy, and Q be the Q-function.
[0037] Furthermore, step seven includes:
[0038] If the BRAM storage module has already cached the decoded data, and Not less than N / 2, read the cached LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit from the BRAM storage module;
[0039] Perform Fast-SSC algorithm decoding on bits N / 2 to N;
[0040] right Perform a hard decision on the corresponding bit and obtain the hard decision result for that bit.
[0041] .
[0042] A Fast-SSCF decoding device of the present invention includes:
[0043] The codeword information acquisition module is used to obtain the codeword sequence A to be translated and the LLR sequence of level 1 from the channel;
[0044] The LLR sequence calculation module is used to utilize functions and Function computation decision Required LLR sequence ;
[0045] The node decoding module is used to perform decoding decisions on the current decoding node according to the node type of the current decoding node, and obtain the decision results of each bit of the current decoding node.
[0046] The quantization bit width selection module is used to select the quantization bit width;
[0047] The decoding data caching module is used to perform decoding data caching based on the pre-calculated conditional probability that the flipped bit is located in the second half of the codeword to be decoded; if the conditional probability that the flipped bit is located in the second half of the codeword to be decoded is greater than the preset threshold value, the LLR sequence, partial sum and decision results of each level from the 1st bit to the N / 2nd bit are cached to the BRAM storage module.
[0048] The bit-flipping module is used to flip the bit corresponding to the bit position index when the decoding CRC check fails.
[0049] The fast decoding module is used to select whether to perform fast decoding or full decoding based on the data caching status in the BRAM storage module and the position of the bit corresponding to the flipped bit position index; if the BRAM storage module has cached the decoded data and the flipped bit position index is not less than N / 2, fast decoding is performed.
[0050] The decoding result output module is used to output the decoding result when decoding is complete. If the preset maximum number of flips has been reached or the CRC check is successful, decoding is completed and the decoding result is output. Otherwise, the number of flips t is incremented by 1, the bit flipping module is selected, and bit flipping is performed.
[0051] Where N is the length of the codeword to be decoded.
[0052] Furthermore, the node decoding module includes:
[0053] The node type determination unit is used to determine the node type of the current decoding node and select the corresponding node decoding unit to perform the decoding operation according to the node type.
[0054] The R0 node decoding unit is used to perform decoding decisions on nodes of type R0; it sets the decision result of each bit of the current decoding node to 0.
[0055] The R1 node decoding unit is used to perform decoding decisions on nodes of type R1; Perform a hard decision to obtain the decision result for each bit;
[0056]
[0057] The SPC node decoding unit is used to perform decoding decisions on nodes of type SPC; set the decision result of the first frozen bit of the current decoding node to 0; and perform hard decision on the LLR value of the information bits to obtain the decision result of each bit.
[0058]
[0059] The parity of the decision result is checked. If the parity is incorrect, the bit with the smallest absolute value of LLR in the information bits is selected and the decision result of that bit is flipped.
[0060] The REP node decoding unit is used to perform decoding decisions on nodes of type SPC; [Settings are missing from the original text] The decision result for the frozen bits is 0; the LLR of the frozen bits is weighted and accumulated to obtain the weighted accumulated value. ;right Perform a hard decision to obtain the decision result for the information bits;
[0061]
[0062]
[0063] in, For the decision result of the k-th bit, The decision result for the Nth bit; for The k-th LLR value in the equation; the parity correctness means that the sum of all bit decision results is even.
[0064] Preferably, the quantization bit width selection module is set to a quantization bit width of 6 bits.
[0065] Furthermore, the decoded data caching module includes:
[0066] The channel error probability calculation unit is used to recursively pre-calculate the channel error probability based on the Parseltongue parameters during the first decoding.
[0067]
[0068]
[0069]
[0070] Bit error probability calculation unit, used to calculate the error probability of the k-th bit;
[0071]
[0072] The conditional probability calculation unit is used to pre-calculate the conditional probability that the flipped bit is located in the second half of the codeword to be decoded. ;
[0073]
[0074] Decoding data buffer unit, used in the Greater than the preset threshold value At that time, the LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit are cached in the BRAM storage module.
[0075] in, Let k be the error probability of the k-th bit. Let be the index of the flipped bit position in the t-th flip operation. This is the set of flipped bit indices for the current decoding node; For noise power spectral density, Let be the bit energy, and Q be the Q-function.
[0076] Furthermore, the fast decoding module includes:
[0077] The decoding mode selection unit is used to select whether to perform fast decoding or full decoding;
[0078] If the BRAM storage module has already cached the decoded data, and If the value is not less than N / 2, select the fast decoding unit to perform fast decoding; otherwise, select the LLR sequence calculation module to perform full decoding.
[0079] A fast decoding unit, used to perform fast decoding operations, includes:
[0080] Read the cached LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit from the BRAM storage module;
[0081] Perform Fast-SSC algorithm decoding on bits N / 2 to N;
[0082] right Perform a hard decision on the corresponding bit and obtain the hard decision result for that bit;
[0083] .
[0084] This invention addresses the redundant computation problem in decoding restart by proposing an intermediate data reuse strategy. During the initial decoding, the channel error probability is recursively pre-calculated based on the Parseltongue parameter to accurately determine the buffer activation condition; the LLR sequence, partial sum, and the decision results from the 1st bit to the N / 2th bit are buffered. During decoding restart, if the subsequent flip position is located in the latter half of the code length and meets the conditional probability, the restart decoding latency is reduced through the coordinated optimization of hierarchical data buffering and a low-level fast recovery algorithm, significantly saving storage resources. Attached Figure Description
[0085] Figure 1 This is a flowchart of the method in specific embodiment 1 of the present invention;
[0086] Figure 2 This is a flowchart of the decoding data caching steps in a specific embodiment of the present invention;
[0087] Figure 3 This is a flowchart of the steps for selecting between fast decoding and full decoding in a specific embodiment 1 of the present invention;
[0088] Figure 4 This is a schematic diagram of the device structure in specific embodiment 2 of the present invention;
[0089] Figure 5 This is a schematic diagram of the decoding data caching module structure in specific embodiment 2 of the present invention;
[0090] Figure 6 This is a schematic diagram of the fast decoding module structure in specific embodiment 2 of the present invention. Detailed Implementation
[0091] To better illustrate the technical solution of the present invention, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0092] In the following specific embodiments of the present invention, the length of the codeword to be decoded from the polar code obtained from the channel is N. The codeword to be decoded consists of information bits and frozen bits, wherein the frozen bits are directly determined to be 0 according to a preset position sequence; the information bits need to be determined by calculating the corresponding LLR. The calculation of the LLR value is performed in stages, and the stage is determined by the length of the codeword to be decoded, which is N. The polar codes have a total of The LLR value sequence is a hierarchical sequence, with the hierarchical numbers numbered from top to bottom in ascending order. The LLR sequence of the top-level layer is... The codeword to be decoded contains four special nodes: R0 node, a node with all frozen bits; R1 node, a node with all information bits; REP node, a node where the last bit is an information bit and the rest are frozen bits; and SPC node, a node where the first bit is a frozen bit and the rest are information bits. Specific Implementation Example 1
[0094] This embodiment is a preferred implementation of the Fast-SSCF decoding method of the present invention.
[0095] See Figure 1 ,like Figure 1 As shown, the method in this specific embodiment includes:
[0096] S1, The decoder obtains the codeword sequence to be decoded, A, and the LLR sequence of level 1 from the channel. ;
[0097]
[0098]
[0099] in, Indicates the first A special node, for Node type, for The node length; for The set of flipped bit indices, in which elements Indicates the position information for bit flipping. for The number of nodes it contains.
[0100] S2, Utilization functions and Function computation decision Required LLR sequence ;
[0101] In this specific embodiment, this step may further include:
[0102] S201. Judgment If the j-th bit is 0, proceed to step S202; otherwise, proceed to step S203.
[0103] S202. Utilization The function and the current level's LLR sequence are used to calculate the next level's LLR sequence; step S204 is executed;
[0104]
[0105] S203. Utilization The function and the current level's LLR sequence are used to calculate the next level's LLR sequence;
[0106]
[0107] in, for of and Control signals for the operation For level j+1, the first One LLR value; For level j, the first One LLR value; For level j, the first One LLR value; For level j, the first The partial sum corresponding to each LLR value.
[0108] S204. Set the level of the LLR sequence obtained in step S202 or S203 to the current level, and repeat steps S202 to S203 until the LLR sequence is obtained. LLR sequence at the corresponding level ;
[0109] S3, based on the current decoding node The node type, for Perform decoding judgment and obtain Each bit The verdict ;
[0110] Where k is The number of each bit;
[0111] In this specific embodiment, this step may further include:
[0112] S301. Judgment If the node type is R0, proceed to step S302; if the node type is R1, proceed to step S303; if the node type is SPC, proceed to step S304; if the node type is REP, proceed to step S305.
[0113] S302, Settings Each bit is determined to be 0; proceed to step S4.
[0114] S303, to Make a hard judgment and obtain The judgment result; execution step S4;
[0115]
[0116] in, for The k-th LLR value in;
[0117] S304, Settings The decision result for the first frozen bit is 0; a hard decision is made on the LLR value of the information bits to obtain... The verdict;
[0118]
[0119] Perform parity check on the decision result. If the parity is incorrect, select the bit with the smallest absolute value of LLR in the information bits and flip its decision result; proceed to step S4.
[0120]
[0121] in, This is a bit-flipping operation; the correct parity means that the sum of all bit decisions is even, i.e.:
[0122]
[0123] S305, Settings The decision result for the frozen bits is 0; the LLR of the frozen bits is weighted and accumulated to obtain the weighted accumulated value. ;right Perform a hard decision to obtain the decision result for the information bits;
[0124]
[0125]
[0126] S4. Select the quantization bit width;
[0127] In this specific embodiment, the quantization bit width is set to 4 to 6 bits, preferably 6 bits.
[0128] S5. Based on the pre-calculated conditional probability that the flipped bit is located in the second half of the codeword to be decoded, perform decoding data buffering;
[0129] See Figure 2 ,like Figure 2 As shown in this specific embodiment, this step may further include:
[0130] S501. During the first decoding, the channel error probability is recursively pre-calculated based on the Parseltongue parameters.
[0131]
[0132]
[0133]
[0134] S502, Calculate the error probability of the k-th bit;
[0135]
[0136] S503. Pre-calculate the conditional probability that the flipped bit is located in the second half of the codeword to be decoded. ;
[0137]
[0138] in, Let k be the error probability of the k-th bit. Let be the index of the flipped bit position in the t-th flip operation. for The set of flipped bit indices; For noise power spectral density, Let be the bit energy; Q is the Q function, Q(x) = (1 / 2)[1 - erf(x / √2)].
[0139] S504, such as Greater than the preset threshold value Cache the LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit at each level. To the BRAM storage module.
[0140] in, In this specific embodiment, based on a preset threshold value for the signal-to-noise ratio, the... The optimal dynamic setting can be selected based on the signal-to-noise ratio:
[0141]
[0142] S6. If the decoding CRC check fails, The corresponding bits are flipped;
[0143] S7. Based on the data caching status in the BRAM storage module and For the corresponding bit position, choose to perform fast decoding or full decoding;
[0144] In this specific embodiment, this step may further include:
[0145] S701, if the BRAM storage module has already cached the decoded data, and If the value is not less than N / 2, proceed to step S702; otherwise, proceed to step S705.
[0146] S702. Read the cached LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit from the BRAM storage module. ;
[0147] S703, to ~ Perform Fast-SSC algorithm decoding;
[0148] In this specific embodiment, the decoding in this step uses a decoding method similar to that in steps S2 and S3, which will not be described again here.
[0149] S704, to Perform a hard decision on the corresponding bit, obtain the hard decision result for that bit, and proceed to step S8.
[0150]
[0151] S705, Execute step S2, for Perform full decoding;
[0152] S8. If the preset maximum number of flips has been reached or the CRC check is successful, the decoding is completed and the decoding result is output; otherwise, set t=t+1 and execute step S6. Specific Implementation Example 2
[0154] This embodiment is a preferred implementation of the Fast-SSCF decoding device of the present invention.
[0155] See Figure 4 ,like Figure 4 As shown, the apparatus in this specific embodiment includes:
[0156] The codeword information acquisition module is used to obtain the codeword sequence A to be translated and the LLR sequence of level 1 from the channel. ;
[0157]
[0158]
[0159] in, Indicates the first A special node, for Node type, for The node length; for The set of flipped bit indices, in which elements Indicates the position information for bit flipping. for The number of nodes it contains.
[0160] The LLR sequence calculation module is used to utilize functions and Function computation decision Required LLR sequence ;
[0161] In this specific embodiment, this module may further include:
[0162] The calculation function selects the unit, used to determine the function based on... The j-th bit selection Function computation unit or The function computation unit performs LLR sequence computation;
[0163] if The j-th bit is 0, so choose Function calculation unit; otherwise, select Function computation unit;
[0164] Function computation unit, used to utilize The function and the current level's LLR sequence are used to calculate the next level's LLR sequence;
[0165]
[0166] Function computation unit, used to utilize The function and the current level's LLR sequence are used to calculate the next level's LLR sequence;
[0167]
[0168] in, for of and Control signals for the operation For level j+1, the first One LLR value; For level j, the first One LLR value; For level j, the first One LLR value; For level j, the first The partial sum corresponding to each LLR value.
[0169] The node decoding module is used to determine the current decoding node. The node type, for Perform decoding judgment and obtain Each bit The verdict ;
[0170] In this specific embodiment, this module may further include:
[0171] Node type determination unit, used to determine The node type is determined, and the corresponding node decoding unit is selected to perform the decoding operation according to the node type; if the node type is R0, the R0 node decoding unit is selected; if the node type is R1, the R1 node decoding unit is selected; if the node type is SPC, the SPC node decoding unit is selected; if the node type is REP, the REP node decoding unit is selected.
[0172] The R0 node decoding unit is used to perform decoding decisions on nodes of type R0.
[0173] set up The result of each bit decision is 0;
[0174] The R1 node decoding unit is used to make decoding decisions for nodes of type R1.
[0175] right Make a hard judgment and obtain The verdict;
[0176]
[0177] The SPC node decoding unit is used to perform decoding decisions on nodes of type SPC.
[0178] set up The decision result for the first frozen bit is 0; a hard decision is made on the LLR value of the information bits to obtain... The verdict;
[0179]
[0180] Perform parity check on the decision result. If the parity is incorrect, select the bit with the smallest absolute value of LLR in the information bits and flip its decision result.
[0181]
[0182] The parity test being correct means that the sum of all bit decisions is even, i.e.:
[0183]
[0184] REP node decoding unit is used to perform decoding decisions on nodes of type SPC.
[0185] set up The decision result for the frozen bits is 0; the LLR of the frozen bits is weighted and accumulated to obtain the weighted accumulated value. ;right Perform a hard decision to obtain the decision result for the information bits;
[0186]
[0187]
[0188] in, for The k-th LLR value in; This is a bit flipping operation; k is... The number of each bit;
[0189] The quantization bit width selection module is used to select the quantization bit width;
[0190] In this specific embodiment, the quantization bit width is set to 4 to 6 bits, preferably 6 bits.
[0191] The decoding data caching module is used to perform decoding data caching based on the pre-calculated conditional probability that the flipped bit is located in the second half of the codeword to be decoded;
[0192] See Figure 5 ,like Figure 5 As shown in this specific embodiment, this module may further include:
[0193] The channel error probability calculation unit is used to recursively pre-calculate the channel error probability based on the Parseltongue parameters during the first decoding.
[0194]
[0195]
[0196]
[0197] Bit error probability calculation unit, used to calculate the error probability of the k-th bit;
[0198]
[0199] The conditional probability calculation unit is used to pre-calculate the conditional probability that the flipped bit is located in the second half of the codeword to be decoded. ;
[0200]
[0201] Decoding data buffer unit, used in the Greater than the preset threshold value At that time, cache the LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit at each level. To the BRAM storage module.
[0202] in, Let k be the error probability of the k-th bit. Let be the index of the flipped bit position in the t-th flip operation. for The set of flipped bit indices; For noise power spectral density, Bit energy; The threshold value is preset based on the signal-to-noise ratio; Q is the Q function, Q(x) = (1 / 2)[1 - erf(x / √2)].
[0203] In this specific embodiment, the The optimal dynamic setting can be selected based on the signal-to-noise ratio:
[0204]
[0205] The bit-flipping module is used to reverse the CRC check if decoding fails. The corresponding bits are flipped;
[0206] The fast decoding module is used to determine the data cache status in the BRAM storage module and For the corresponding bit position, choose to perform fast decoding or full decoding;
[0207] See Figure 6 ,like Figure 6 As shown in this specific embodiment, this module may further include:
[0208] The decoding mode selection unit is used to select whether to perform fast decoding or full decoding;
[0209] If the BRAM storage module has already cached the decoded data, and If the value is not less than N / 2, select the fast decoding unit to perform fast decoding; otherwise, select the LLR sequence calculation module to perform full decoding.
[0210] A fast decoding unit, used to perform fast decoding operations, includes:
[0211] From the BRAM storage module, read the cached LLR sequences at each level, partial sums, and the decision results from the 1st bit to the N / 2th bit. ;
[0212] right Perform Fast-SSC algorithm decoding;
[0213] In this specific embodiment, the Fast-SSC algorithm decoding performed by this module is similar to the decoding method of the node decoding module, and will not be described again here;
[0214] right Perform a hard decision on the corresponding bit and obtain the hard decision result for that bit;
[0215]
[0216] The decoding result output module is used to output the decoding result when decoding is complete;
[0217] If the preset maximum number of flips has been reached or the CRC check is successful, the decoding is completed and the decoding result is output; otherwise, set t=t+1, select the bit flipping module, and perform bit flipping.
[0218] In the specific embodiments of the present invention described above, an innovative intermediate data reuse strategy is proposed to address the redundant computation problem in decoding restart. This strategy involves recursively pre-calculating the channel error probability based on the Parseltongue parameter during the first decoding iteration, and then dynamically mapping the SNR threshold. The system accurately determines the cache activation conditions. Only the LLR sequence, partial sum, and the decision results from the 1st bit to the N / 2th bit are cached, forming a hierarchical importance-aware storage strategy. During decoding restart, if the subsequent flip position is located in the latter half of the code length and meets the conditional probability, the restart decoding latency is reduced by 38% through the collaborative optimization of hierarchical cached data and low-level fast recovery algorithms, significantly saving storage resources. This invention achieves an efficient balance between hardware resource consumption, decoding latency, and error correction performance, especially in high signal-to-noise ratio scenarios, achieving performance close to the CA-SCL algorithm with significantly reduced hardware overhead. Simultaneously, based on the LLR quantization bit width optimization strategy, a suitable quantization bit width is selected, simplifying the operation logic of the f / g function and reducing the bit width requirements of the multiplier and adder.
[0219] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A Fast-SSCF decoding method, characterized in that, include: Step 1: The decoder obtains the codeword sequence to be decoded and the level 1 log-likelihood ratio (LLR) sequence from the channel; Step Two: Utilize functions and The function computes the LLR sequence required to determine the current node. ; Step 3: Based on the node type of the current decoding node, perform decoding decisions on the current decoding node to obtain the decision results for each bit of the current decoding node; Step 4: Select the quantization bit width; Step 5: If the conditional probability that the flipped bit is located in the second half of the codeword to be decoded is greater than the preset threshold, cache the LLR sequence of each level, the partial sum, and the decision results from the 1st bit to the N / 2nd bit to the storage module. Step 6: If the decoding CRC check fails, flip the bit corresponding to the flipped bit position index; Step 7: If the decoded data is already cached in the storage module, and the index of the flipped bit position is not less than N / 2, perform fast decoding; Where N is the length of the codeword to be decoded.
2. The method according to claim 1, characterized in that, Step three includes: If the current decoding node type is R0, set the decision result of each bit of the current decoding node to 0; If the current decoding node type is R1, for Perform a hard decision to obtain the decision result for each bit; ； If the current decoding node type is SPC, set the decision result of the first frozen bit of the previous decoding node to 0; perform hard decision on the LLR value of the information bits to obtain the decision result of each bit. ； The parity of the decision result is checked. If the parity is incorrect, the bit with the smallest absolute value of LLR in the information bits is selected and the decision result of that bit is flipped. If the current decoding node type is REP, set the decision result of the frozen bits of the previous decoding node to 0; perform a weighted summation of the LLR of the frozen bits to obtain the weighted summation value. ;right Perform a hard decision to obtain the decision result for the information bits; ； ； in, For the decision result of the k-th bit, The decision result for the Nth bit; for The k-th LLR value in the equation; the parity correctness means that the sum of all bit decision results is even.
3. The method according to claim 1, characterized in that, Step four includes: The quantization bit width is set to 6 bits.
4. The method according to claim 1, characterized in that, Step five includes: During the initial decoding, the channel error probability is recursively pre-calculated based on the Parseltongue parameters. ; ； ； ； Calculate the error probability of the k-th bit; ； Pre-calculate the conditional probability that the flipped bit is located in the second half of the codeword to be decoded. ; ； like Greater than the preset threshold value The LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit at each level are cached in the storage module. in, Let k be the error probability of the k-th bit. Let be the index of the flipped bit position in the t-th flip operation. This is the set of flipped bit indices for the current decoding node; For noise power spectral density, Let be the bit energy, and Q be the Q-function.
5. The method according to claim 4, characterized in that, Step seven includes: If the decoded data is already cached in the storage module, and Not less than N / 2, read the cached LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit from the BRAM storage module; Perform Fast-SSC algorithm decoding on bits N / 2 to N; right Perform a hard decision on the corresponding bit and obtain the hard decision result for that bit; 。 6. A Fast-SSCF decoding device, characterized in that, include: The codeword information acquisition module is used to obtain the codeword sequence A to be translated and the LLR sequence of level 1 from the channel; The LLR sequence calculation module is used to utilize... functions and Function computation decision Required LLR sequence ; The node decoding module is used to perform decoding decisions on the current decoding node according to the node type of the current decoding node, and obtain the decision results of each bit of the current decoding node. The quantization bit width selection module is used to select the quantization bit width; The decoding data caching module is used to perform decoding data caching based on the pre-calculated conditional probability that the flipped bit is located in the second half of the codeword to be decoded; if the conditional probability that the flipped bit is located in the second half of the codeword to be decoded is greater than the preset threshold value, the LLR sequence, partial sum and decision results of each level from the 1st bit to the N / 2nd bit are cached to the storage module. The bit-flipping module is used to flip the bit corresponding to the bit position index when the decoding CRC check fails. The fast decoding module is used to select between fast decoding and full decoding based on the data caching status in the storage module and the position of the bit corresponding to the flipped bit position index. If the decoding data is already cached in the storage module and the flipped bit position index is not less than N / 2, fast decoding is performed. The decoding result output module is used to output the decoding result when decoding is complete; if the preset maximum number of flips has been reached or the CRC check is successful, decoding is complete and the decoding result is output. Otherwise, increment the number of flips t by 1, select the bit flipping module, and perform the bit flipping. Where N is the length of the codeword to be decoded.
7. The apparatus according to claim 6, characterized in that, The node decoding module includes: The node type determination unit is used to determine the node type of the current decoding node and select the corresponding node decoding unit to perform the decoding operation according to the node type. The R0 node decoding unit is used to perform decoding decisions on nodes of type R0; it sets the decision result of each bit of the current decoding node to 0. The R1 node decoding unit is used to perform decoding decisions on nodes of type R1; Perform a hard decision to obtain the decision result for each bit; ； The SPC node decoding unit is used to perform decoding decisions on nodes of type SPC; set the decision result of the first frozen bit of the current decoding node to 0; and perform hard decision on the LLR value of the information bits to obtain the decision result of each bit. ； The parity of the decision result is checked. If the parity is incorrect, the bit with the smallest absolute value of LLR in the information bits is selected and the decision result of that bit is flipped. The REP node decoding unit is used to perform decoding decisions on nodes of type SPC; [Settings are missing from the original text] The decision result for the frozen bits is 0; the LLR of the frozen bits is weighted and accumulated to obtain the weighted accumulated value. ;right Perform a hard decision to obtain the decision result for the information bits; ； ； in, For the decision result of the k-th bit, The decision result for the Nth bit; for The k-th LLR value in the equation; the parity correctness means that the sum of all bit decision results is even.
8. The apparatus according to claim 6, characterized in that, The quantization bit width selection module sets the quantization bit width to 6 bits.
9. The apparatus according to claim 6, characterized in that, The decoding data caching module includes: The channel error probability calculation unit is used to recursively pre-calculate the channel error probability based on the Parseltongue parameters during the first decoding. ； ； ； Bit error probability calculation unit, used to calculate the error probability of the k-th bit; ； The conditional probability calculation unit is used to pre-calculate the conditional probability that the flipped bit is located in the second half of the codeword to be decoded. ; ； Decoding data buffer unit, used in the Greater than the preset threshold value At that time, the LLR sequence, partial sum, and decision results from the first bit to the N / 2th bit of each level are cached in the storage module; in, Let k be the error probability of the k-th bit. Let be the index of the flipped bit position in the t-th flip operation. This is the set of flipped bit indices for the current decoding node; For noise power spectral density, Let be the bit energy, and Q be the Q-function.
10. The apparatus according to claim 9, characterized in that, The fast decoding module includes: The decoding mode selection unit is used to select whether to perform fast decoding or full decoding; If the decoded data is already cached in the storage module, and If the value is not less than N / 2, select the fast decoding unit to perform fast decoding; otherwise, select the LLR sequence calculation module to perform full decoding. A fast decoding unit, used to perform fast decoding operations, includes: Read the cached LLR sequences, partial sums, and decision results from the first bit to the N / 2th bit from the storage module; Perform Fast-SSC algorithm decoding on bits N / 2 to N; right Perform a hard decision on the corresponding bit and obtain the hard decision result for that bit; 。