Transmitter, chip and signal transmission equipment

Abstract

The invention relates to a transmitter, a chip and a signal transmission device, the transmitter comprises a controllable current module and an output module, the controllable current module is used for generating a synthesis current according to a control signal, the synthesis current comprises a main current and an additional current, and the output module is used for outputting the synthesis current according to the synthesis current and an original signal received by the transmitter. Generating and outputting an output signal; wherein the output signal comprises an additional signal, the amplitude and the duration of the additional signal are adjusted according to the control signal, and the additional current is flexibly adjusted through the control signal, so that the additional signal with the controllable amplitude and the controllable duration is generated in the output signal; the additional signal can specifically pre-compensate attenuation caused by a channel at the beginning of transmission of the output signal, so that the risk of amplitude reduction and waveform distortion of the signal received by the receiver can be remarkably reduced, the signal quality of the receiver can be effectively improved, and the effective transmission distance of a transmitter can be remarkably prolonged.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a transmitter, chip, and signal transmission device. Background Technology

[0002] In various electronic devices and systems, such as data communication, audio and video transmission, or autonomous driving, signal transmission is often required through transmission channels.

[0003] As application scenarios expand, signals sometimes need to be transmitted through long-distance or high-loss channels. For example, when transmitting through long cables, the signal will attenuate due to the distributed parameters such as resistance, capacitance, and inductance inherent in the cable itself, especially the significant attenuation of high-frequency components. In wireless transmission scenarios, the signal will also be distorted due to spatial path loss and multipath effects. The common feature of these channel effects is that they all cause the signal, especially the high-frequency components, to experience severe amplitude reduction and waveform distortion during transmission. This not only seriously affects the signal quality of the receiver, but also fundamentally limits the effective transmission distance of the transmitter. Summary of the Invention

[0004] To address the aforementioned technical problems, the purpose of this application is to provide a transmitter, a chip, and a signal transmission device. The transmitter, chip, and signal transmission device provided by this application can significantly reduce the risk of amplitude reduction and waveform distortion in the signal received by the receiver, thereby effectively improving the signal quality of the receiver and significantly extending the effective transmission distance of the transmitter.

[0005] The technical solution provided in this application is as follows: A transmitter includes: a controllable current module and an output module; The control terminal of the controllable current module is used to receive control signals, and the output terminal is connected to the input terminal of the output module, with the common terminal of the connection serving as the output terminal of the transmitter. The controllable current module is used to generate a composite current according to the control signal, the composite current including a main current and an additional current; The output module is used to generate and output an output signal based on the synthesized current and the original signal received by the transmitter; wherein the output signal includes an additional signal, the amplitude and duration of which are adjusted according to the control signal.

[0006] Optionally, the controllable current module includes a main current module and an auxiliary current module, and the control signal includes a main control signal and an auxiliary control signal; The main current module is used to generate main current according to the main control signal; The additional current module is used to generate additional current according to the additional control signal.

[0007] Optionally, the transmitter further includes a control module; The input terminal of the control module receives a control signal, the control terminal of the control module receives a delayed control signal, and the output terminal of the control module is connected to the control terminal of the additional current module. The control module is used to generate the additional control signal based on the slave control signal and the delay control signal.

[0008] Optionally, the slave control signal includes multiple slave control sub-signals, the control module includes multiple control units connected in parallel, and the additional current module includes multiple additional current units connected in parallel. Each of the aforementioned control units is configured in a one-to-one correspondence with one of the aforementioned additional current units; The input terminal of the control unit receives the slave control sub-signal, the control terminal of the control unit receives the delay control signal, and the output terminal of the control unit is connected to the control terminal of the corresponding additional current unit. The control unit is configured to generate an additional control sub-signal based on the slave control sub-signal and the delay control signal; The additional current unit is used to generate a first sub-current according to the additional control sub-signal; The additional current is synthesized from multiple first sub-currents, the amplitude of the additional signal is positively correlated with the number of first sub-currents, and the duration of the additional signal is positively correlated with the delay time of the additional control sub-signal.

[0009] Optionally, the control unit includes a delay unit, an inverter, and logic gates; The input terminal of the delay unit receives the slave control sub-signal, the control terminal of the delay unit receives the delay control signal, the output terminal of the delay unit is connected to the input terminal of the inverter, the output terminal of the inverter is connected to one input terminal of the logic gate, the other input terminal of the logic gate receives the slave control sub-signal, and the output terminal of the logic gate is connected to the control terminal of the corresponding additional current unit. The delay unit is used to perform delay processing on the slave control sub-signal according to the delay control signal to generate a delay signal; The logic gate is used to perform logical operations on the slave control sub-signal and the inverted delayed signal to generate an additional control sub-signal.

[0010] Optionally, the additional current unit includes a first current source and a first switching unit; The control terminal of the first switching unit receives the additional control sub-signal, the input terminal of the first switching unit is connected to the output terminal of the first current source, and the output terminal of the first switching unit is connected to the input terminal of the output module. The first switching unit is used to turn on or off according to the additional control sub-signal to control the output current of the first current source.

[0011] Optionally, the output signal further includes a main signal, the main control signal includes multiple main control sub-signals, and the main current module includes multiple main current units connected in parallel. The main current unit is used to generate a second sub-current according to the main control sub-signal; The main current is synthesized from multiple second sub-currents, and the amplitude of the main signal is positively correlated with the number of second sub-currents.

[0012] Optionally, the output module includes an adjustable load, the first end of which is connected to the output end of the controllable current module, and the common end of the connection serves as the output end of the transmitter. The control end of the adjustable load receives an impedance control signal, and the second end of the adjustable load is grounded.

[0013] This application also provides a chip including the transmitter described in any of the above claims.

[0014] This application also provides a signal transmission device, including a transmitter, a transmission medium and a receiver, wherein the transmitter is configured as described in any of the preceding claims; The transmission medium is used to transmit the output signal and form a target signal to be sent to the receiver. The attenuation value of the target signal compared to the original signal is less than a preset threshold.

[0015] Compared with the prior art, this application provides a transmitter, a chip, and a signal transmission device. The transmitter includes a controllable current module and an output module. The control terminal of the controllable current module is used to receive a control signal, and the output terminal is connected to the input terminal of the output module. The common terminal of the connection serves as the output terminal of the transmitter. The controllable current module is used to generate a composite current according to the control signal. The composite current includes a main current and an additional current. The output module is used to generate an output signal and output it according to the composite current and the original signal received by the transmitter. The output signal includes an additional signal. The amplitude and duration of the additional signal are adjusted according to the control signal. This application flexibly adjusts the additional current through the control signal, so that an additional signal with controllable amplitude and duration is generated in the output signal. This additional signal can pre-compensate for attenuation caused by the channel at the beginning of the output signal transmission, thereby significantly reducing the risk of amplitude drop and waveform distortion in the signal received by the receiver. This can effectively improve the signal quality of the receiver and significantly extend the effective transmission distance of the transmitter. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the first structure of a transmitter provided in an embodiment of this application; Figure 2 This is a schematic diagram of the second structure of a transmitter provided in an embodiment of this application; Figure 3 This is a circuit diagram of a transmitter provided in an embodiment of this application; Figure 4 This is a schematic diagram of the signal processing process from the control sub-signal through the delay unit, inverter, and logic gate provided in the embodiments of this application; Figure 5-1 This is an ideal waveform diagram of the output signal sent by the transmitter when the main control sub-signals received by the control terminals of the eight second switch units provided in this embodiment are all at high level; Figure 5-2 The ideal waveform diagram of the output signal sent by the transmitter when the control terminals of the eight second switching units provided in this embodiment of the application receive the main control sub-signals at high level, the control terminals of the three first switching units receive the additional control sub-signals at high level, and the duration of the additional signals is configured to 620ps by the delay control signal. Figure 6-1This is a waveform diagram of the actual output signal sent by the transmitter when the main control sub-signals received by the control terminals of the eight second switch units provided in this embodiment are all at high level. Figure 6-2 This is a waveform diagram of the actual signal received by the receiver when the main control sub-signals received by the control terminals of the eight second switch units provided in this embodiment are all at high level. Figure 6-3 The waveform diagram of the output signal sent by the transmitter when the control terminals of the eight second switching units provided in this embodiment of the application receive the main control sub-signals at high level, the control terminals of the three first switching units receive the additional control sub-signals at high level, and the duration of the additional signals is configured to 620ps by the delay control signal. Figure 6-4 The waveform diagram of the signal received by the receiver when the main control sub-signals received by the control terminals of the eight second switch units provided in this embodiment are all at high level, the additional control sub-signals received by the control terminals of the three first switch units are at high level, and the duration of the additional signals is configured to 620ps by the delay control signal; Figure 7 This is an eye diagram of the positive and negative polarity signals received by the receiver provided in this embodiment of the application; Figure 8 This is a circuit diagram of a delay unit provided in an embodiment of this application; Figure 9 This is a circuit diagram of another delay unit provided in the embodiments of this application; Figure 10 This is a schematic diagram of the structure of a signal transmission device provided in an embodiment of this application; Reference numerals: 100 - Transmitter; 200 - Transmission medium; 300 - Receiver; 110 - Controllable current module; 120 - Output module; 130 - Control module; 111 - Main current module; 1111 - Main current unit; I2 - Second current source; M2 - Second switching unit; 112 - Additional current module; 1121 - Additional current unit; I1 - First current source; M1 - First switching unit; 131-Control unit; 1311-Delay unit; 1312-Logic gate; INV1-Inverter; 121 - Adjustable load; 1211 - Load unit; M3 - Third switching transistor; R - Load subunit; 13111 - First delay sub-unit; M4 - Fourth switch; M5 - Fifth switch; INV2 - Second inverter; INV3 - Third inverter; 13112 - Second delay sub-unit; INV4 - Fourth inverter; INV5 - Fifth inverter; M6 - Sixth switch; C - Capacitor. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly set on the other component; when a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to the other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" or "several" means two or more, unless otherwise explicitly specified.

[0022] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0023] like Figure 1As shown in the figure, this application embodiment provides a transmitter, including: a controllable current module 110 and an output module 120; the control terminal of the controllable current module 110 is used to receive a control signal, and the output terminal is connected to the input terminal of the output module 120, and the common terminal of the connection serves as the output terminal of the transmitter; the controllable current module 110 is used to generate a composite current according to the control signal, the composite current including a main current and an additional current; the output module 120 is used to generate an output signal and output it according to the composite current and the original signal received by the transmitter; wherein, the output signal includes an additional signal, and the amplitude and duration of the additional signal are adjusted according to the control signal.

[0024] In this embodiment, the transmitter can be a transmitter that conforms to the USB 2.0 protocol, but the technical solution of the present invention is not limited to this, and its core concept can also be applied to the physical layer design of other high-speed serial interfaces.

[0025] The raw signal can be image data of road signs, pedestrians, etc., collected by image acquisition devices (such as camera modules or vision sensors) in the field of autonomous driving, or sound data such as road broadcasts and car horns collected by sound acquisition devices (such as microphones or microphone arrays).

[0026] The control signal received by the control terminal of the controllable current module 110 can be a configuration signal generated by the current regulation inside the transmitter. The configuration signal is not fixed and can be dynamically configured or statically preset according to the actual transmission channel characteristics. By configuring the control signal, the amplitude and duration of the additional current in the synthetic current output by the controllable current module 110 can be adjusted, thereby making the amplitude and duration of the additional signal in the output signal output by the output module 120 adjustable by the control signal. This additional signal, whose amplitude and duration are adjustable, can specifically compensate for the attenuation and amplitude reduction caused by long-distance transmission channels at the beginning of the output signal transmission, so that the receiver can obtain a signal with a lower bit error rate and significantly improve the integrity of the signal after long-distance transmission.

[0027] Compared with the prior art, this application provides a transmitter, a chip, and a signal transmission device. The transmitter includes a controllable current module 110 and an output module 120. The control terminal of the controllable current module 110 is used to receive control signals, and its output terminal is connected to the input terminal of the output module 120, with the common terminal serving as the output terminal of the transmitter. The controllable current module 110 is used to generate a composite current according to the control signal. The composite current includes a main current and an additional current. The output module 120 is used to generate and output an output signal according to the composite current and the original signal received by the transmitter. The output signal includes an additional signal, the amplitude and duration of which are adjusted according to the control signal. In this application, the additional current is flexibly adjusted by the control signal to generate an additional signal with controllable amplitude and duration in the output signal. This additional signal can pre-compensate for attenuation caused by the channel at the beginning of the output signal transmission, thereby significantly reducing the risk of amplitude drop and waveform distortion in the signal received by the receiver. This effectively improves the signal quality of the receiver and significantly extends the effective transmission distance of the transmitter.

[0028] like Figure 2 As shown, in one embodiment of this application, the controllable current module 110 includes a main current module 111 and an auxiliary current module 112, and the control signals include a main control signal and an auxiliary control signal; the main current module 111 is used to generate a main current according to the main control signal; the auxiliary current module 112 is used to generate an auxiliary current according to the auxiliary control signal.

[0029] In this embodiment, by dividing the controllable current module 110 into a main current module 111 and an auxiliary current module 112, and correspondingly using a main control signal and an auxiliary control signal for independent control, independent control of the basic drive and the auxiliary drive is achieved. The main control signal is used to drive the main current module 111, so that the main current module 111 generates a basic drive current. The auxiliary control signal can be configured to adjust the superposition amplitude of the auxiliary current by setting the number of its effective signals, and to adjust the duration of the auxiliary current by setting the pulse width of its effective signals. Thus, an auxiliary drive current with adjustable amplitude and duration can be dynamically superimposed on the basic drive current. This synthesized current flows through the output module 120, so that the amplitude and duration of the auxiliary signal in the output signal output by the output module 120 are controlled. This auxiliary signal with adjustable amplitude and duration can specifically compensate for the attenuation and amplitude reduction caused by long-distance transmission channels at the beginning of the output signal transmission.

[0030] like Figure 2As shown, in one embodiment of this application, the transmitter further includes a control module 130; the input terminal of the control module 130 receives a slave control signal, the control terminal of the control module 130 receives a delay control signal, and the output terminal of the control module 130 is connected to the control terminal of the additional current module 112; the control module 130 is used to generate an additional control signal based on the slave control signal and the delay control signal.

[0031] In this embodiment, the control module 130 is used to perform delay processing on the slave control signal received at the input terminal according to the delay control signal received at the control terminal and combine it with logical operations to generate an additional control signal with adjustable pulse width, so as to precisely control the duration of the additional current. Combined with the amplitude of the additional current determined by the number of slave control signals, the coordinated control of the duration and amplitude of the additional signal in the output signal is realized.

[0032] like Figure 3 As shown, in one embodiment of this application, the control signal includes multiple control sub-signals, the control module 130 includes multiple control units 131 connected in parallel, and the additional current module 112 includes multiple additional current units 1121 connected in parallel. The multiple control units 131 and the multiple additional current units 1121 are configured in a one-to-one correspondence. The input terminal of the control unit 131 receives the control sub-signals, the control terminal of the control unit 131 receives the delayed control signal, and the output terminal of the control unit 131 is connected to the control terminal of the corresponding additional current unit 1121. The control unit 131 is used to generate additional control sub-signals based on the control sub-signals and the delayed control signal. The additional current unit 1121 is used to generate a first sub-current based on the additional control sub-signals. The additional current is synthesized from multiple first sub-currents, the amplitude of the additional signal is positively correlated with the number of first sub-currents, and the duration of the additional signal is positively correlated with the delay time of the additional control sub-signals.

[0033] In this embodiment, a parallel control channel architecture consisting of multiple control units 131 connected one-to-one with multiple additional current units 1121 achieves refined and scalable control of the additional current. Each control unit 131 and its corresponding additional current unit 1121 constitute an independent control channel. The final amplitude of the additional current is determined by the number of additional current units 1121 that receive valid additional control sub-signals. That is, the more channels are activated, the more superimposed first sub-currents there are, and the larger the amplitude of the additional current, thereby achieving precise control of the magnitude of the additional current and, consequently, precise control of the amplitude of the additional signal. At the same time, the duration of the additional signal is positively correlated with the delay time of the additional control sub-signal, and the delay time of the additional control sub-signal is determined by the number of additional current units 1121 that receive valid additional control sub-signals. The delay control signal received by unit 131 controls the signal. Furthermore, in this embodiment, by controlling the delay control signal received by control unit 131, the pulse width of each additional control sub-signal is adjusted, thereby adjusting the duration of the additional signal. For example, by allowing all control units 131 to share the same delay control signal, each additional control sub-signal has the same or cooperatively adjustable pulse width, thereby ensuring that all activated additional current units 1121 synchronously inject a current pulse of consistent duration to output module 120. This design decouples amplitude control (through the number of channels) from duration control (through a unified delay), enabling the flexible and independent adjustment of these two key parameters of the additional signal to optimally compensate for signal attenuation caused by different channels.

[0034] like Figure 3 As shown, in one embodiment of this application, the control unit 131 includes a delay unit 1311, an inverter INV1, and a logic gate 1312. The input terminal of the delay unit 1311 receives a slave control sub-signal, the control terminal of the delay unit 1311 receives a delay control signal, the output terminal of the delay unit 1311 is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to one input terminal of the logic gate 1312, the other input terminal of the logic gate 1312 receives the slave control sub-signal, and the output terminal of the logic gate 1312 is connected to the control terminal of the corresponding additional current unit 1121. The delay unit 1311 is used to delay the slave control sub-signal according to the delay control signal to generate a delayed signal. The logic gate 1312 is used to perform logical operations on the slave control sub-signal and the inverted delayed signal to generate an additional control sub-signal.

[0035] In this embodiment, inverter INV1 is the first inverter INV1, and delay unit 1311 can be a digital delay line circuit (DDL circuit) or other circuits capable of signal delay. The control unit 131, through the synergistic effect of delay unit 1311, inverter INV1, and logic gate 1312 (preferably an AND gate), achieves a precise pulse generation mechanism. Figure 4 As shown, the signal processing procedure is as follows: The first signal (i.e., a positive pulse arriving from the edge of a control sub-signal, such as a flag signal) is input to the first input terminals of the delay unit 1311 and the logic gate 1312. The delay unit 1311 delays the first signal according to the delay control signal, and generates a second signal at the output terminal of the delay unit 1311. The second signal is inverted by the inverter INV1 to generate a third signal, which is then input to the second input terminal of the logic gate 1312. The logic gate 1312 then performs a bitwise AND operation on the first and third signals, and generates a fourth signal at the output terminal of the logic gate 1312. The fourth signal is a pulse signal whose rising edge is synchronously triggered by the rising edge of the first signal, and whose falling edge is determined by the rising edge of the second signal (i.e., the rising edge of the first signal after the delay). Therefore, the pulse width of the fourth signal depends on the delay time set by the delay unit 1311. By adjusting the delay control signal to change this delay time, the pulse width of the fourth signal (i.e., the additional control sub-signal) can be directly and linearly controlled, thereby accurately controlling the on-time of the corresponding additional current unit 1121, thereby adjusting the duration of the additional signal and compensating for the signal attenuation caused by different channels.

[0036] like Figure 3 As shown, in one embodiment of this application, the additional current unit 1121 includes a first current source I1 and a first switching unit M1; the control terminal of the first switching unit M1 receives an additional control sub-signal, the input terminal of the first switching unit M1 is connected to the output terminal of the first current source I1, and the output terminal of the first switching unit M1 is connected to the input terminal of the output module 120; the first switching unit M1 is used to turn on or off according to the additional control sub-signal to control the output current of the first current source I1.

[0037] In this embodiment, the first switching unit M1 includes a first switching transistor, which can specifically be a MOS transistor. By designing each additional current unit 1121 as a series connection of a first current source I1 and a first switching unit M1, refined and digital control of the additional current is achieved. The first switching unit M1 can specifically be a high-speed, controllable electronic switch, whose on and off states are controlled by the logic level of the additional control sub-signal. When the additional control sub-signal is valid, the first switching unit M1 quickly turns on, accurately connecting its corresponding first current source I1 to the output circuit to generate a first sub-current; conversely, the first switching unit M1 turns off. This unitized design of "one source and one switch" makes the final additional current amplitude appear as a linear superposition of the first sub-currents generated by all activated additional current units 1121. Thus, by controlling the number of activated units, the amplitude of the additional current can be precisely adjusted, thereby adjusting the amplitude of the additional signal. This structure not only has a fast response speed and precise control, but also has good scalability, making it easy to adapt to different additional signal requirements by increasing or decreasing the number of parallel units.

[0038] like Figure 3 As shown, in one embodiment of this application, the output signal further includes a main signal, the main control signal includes multiple main control sub-signals, and the main current module 111 includes multiple main current units 1111 connected in parallel; the main current unit 1111 is used to generate a second sub-current according to the main control sub-signal; wherein, the main current is synthesized from multiple second sub-currents, and the amplitude of the main signal is positively correlated with the number of second sub-currents.

[0039] In this embodiment, the main current module 111 adopts a parallel, modular architecture similar to the additional current module 112, which improves the driving capability flexibility and configurability of the transmitter output signal. Each main current unit 1111 is an independent current driving unit, and its on / off state is independently controlled by the corresponding main control sub-signal. By setting the number of effective main control sub-signals, the total number of activated main current units 1111 can be precisely controlled, thereby adjusting the main current to the target value. This allows the same transmitter circuit to be configured to adapt to different driving strength requirements. The stability and predictability of the main current are the basis for generating a main signal that conforms to the standard voltage swing of the protocol, while the additional current is dynamically enhanced on this stable basis. This architecture that separates the basic drive from the dynamic enhancement ensures that the additional signal in the output signal can be accurately generated on a stable and controllable reference.

[0040] like Figure 3As shown, in one specific implementation, the main current unit 1111 may include a second current source I2 and a second switching unit M2; the control terminal of the second switching unit M2 receives the main control sub-signal, the input terminal of the second switching unit M2 is connected to the output terminal of the second current source I2, and the output terminal of the second switching unit M2 is connected to the input terminal of the output module 120; the second switching unit M2 is used to turn on or off according to the main control sub-signal to control the output current of the second current source I2.

[0041] In this embodiment, the second switching unit M2 includes a second switching transistor, which can specifically be a MOSFET. The main current unit 1111 adopts the same modular design of "current source + switching unit" as the auxiliary current unit 1121. This provides a unified, symmetrical and easily integrated circuit structure for the entire transmitter. The second switching unit M2 quickly turns on and off according to the main control sub-signal, realizing precise control over whether the output of the second current source I2 is connected to the output module. The second sub-currents output by all activated main current units 1111 are linearly superimposed at the input of the output module 120 to generate the final main current. This highly symmetrical unit structure allows the main current module 111 and the auxiliary current module 112 to share similar designs, layouts and timing control strategies, greatly reducing the complexity and risk of chip design. At the same time, it ensures that the main current and auxiliary current have good consistency and matching degree when synthesized, thereby ensuring the overall quality and stability of the output signal waveform.

[0042] It should be noted that the above embodiments use single-ended signals as an example to describe the principle of the additional signals in the control output signals of this application. For differential transmission scenarios common in the art (such as the D+ and D- signal lines of USB 2.0), the receiver determines the logic state by calculating the voltage difference between the differential P terminal and the differential N terminal. Specifically, the transmitter in the differential transmission scenario adopts the transmitter and the method for controlling the additional signals described in any of the above embodiments. When the signal transitions, for the signal edge transitioning from low level to high level (whether it is the P terminal or the N terminal), the additional signals are controlled by the above method. Through this symmetrical processing, the signal loss during the transition process of the differential signal from 0 to 1 and from 1 to 0 can be completely compensated.

[0043] For example, in a specific configuration, the number of additional control sub-signals, first current source I1, and first switching unit M1 are all 4, and the number of main control sub-signals, second current source I2, and second switching unit M2 are all 8. If the main control sub-signals received by the control terminals of the 8 second switching units M2 are all high-level, causing the output current of the 8 second current sources I2 to be output to the output module, and the additional control sub-signals received by the control terminals of the 4 first switching units M1 are all low-level, then the ideal waveform of the output signal sent by the transmitter is as follows: Figure 5-1 As shown, the actual waveform of the output signal sent by the transmitter is as follows: Figure 6-1 As shown, the actual waveform of the signal received by the receiver is as follows: Figure 6-2 As shown, if the main control sub-signals received by the control terminals of the eight second switching units M2 are all high-level, causing the output currents of the eight second current sources I2 to be output to the output module 120, and the additional control sub-signals received by the control terminals of the three first switching units M1 are high-level, causing the output currents of the three first current sources I1 to be output to the output module 120, and the duration of the additional signals is configured to 620 ps through the delay control signal, then the ideal waveform of the output signal sent by the transmitter is as follows: Figure 5-2 As shown, the actual waveform of the output signal sent by the transmitter is as follows: Figure 6-3 As shown, the actual waveform of the signal received by the receiver is as follows: Figure 6-4 As shown, according to Figure 6-1 to Figure 6-4 As can be seen, by adding an additional signal with specific energy to the output signal, after transmission through the channel, the energy of the additional signal exactly compensates for the loss of high-frequency components of the signal itself by the channel, so that the signal waveform recovered by the receiver has a regular amplitude and steep edges, which significantly improves the signal quality. In this way, inter-symbol interference is significantly suppressed. It should be noted that the number of activated additional current units can be flexibly set according to the signal compensation requirements in the actual scenario, and this embodiment does not limit this.

[0044] like Figure 7 As shown, when no additional signal is added to the output signal (i.e., no de-emphasis is performed), the eye diagrams of the positive and negative polarity signals received by the receiver are almost closed due to severe inter-symbol interference (see the "EyeOpening reduced" label in the figure). When an additional signal is added to the output signal (i.e., with de-emphasis), the signal attenuation during transmission is effectively offset, significantly improving the eye diagram performance of the two differential signal paths. Specifically, this is manifested in the increase in eye height and the expansion of eye width (see the "Improved Eye Opening" label in the figure). This means that the amplitude margin and timing margin of the receiver signal are greatly improved, and the bit error rate is significantly reduced. Ultimately, this not only effectively improves the signal quality of the receiver but also significantly extends the effective transmission distance of the transmitter.

[0045] like Figure 3As shown, in one embodiment of this application, the output module 120 includes an adjustable load 121. The first end of the adjustable load 121 is connected to the output end of the controllable current module 110, and the common end of the connection serves as the output end of the transmitter. The control end of the adjustable load 121 receives an impedance control signal, and the second end of the adjustable load 121 is grounded.

[0046] As a specific implementation, the adjustable load 121 may include multiple load units 1211 connected in parallel. Each load unit 1211 includes a third switch M3 and a load subunit R. The input terminal of the third switch M3 is connected to the output terminal of the controllable current module 110, and the output terminal of the third switch M3 is connected to the first terminal of the load subunit R. The control terminal of the third switch M3 receives an impedance control signal, and the second terminal of the load subunit R is grounded.

[0047] In this embodiment, the third switch M3 can be a MOSFET. By introducing an adjustable load 121 composed of multiple parallel load units 1211, precise and dynamic control of the output impedance and signal amplitude is achieved. This design enables the transmitter to flexibly adapt to different channel characteristics and transmission standards by controlling the impedance signal. Under the condition of fixed drive current, the integrity of the output signal can be optimized by adjusting the load impedance alone, thereby ensuring the best signal quality in various application scenarios and significantly improving the adaptability and reliability of the system.

[0048] like Figure 8 As shown, in one specific implementation, the delay unit 1311 may include multiple first delay sub-units 13111 connected in series. The first delay sub-unit 13111 includes a fourth switch M4, a fifth switch M5, a second inverter INV2, and a third inverter INV3. The input terminal of the fourth switch M4 is connected to the input terminal of the second inverter INV2 and serves as the input terminal of the first delay sub-unit 13111. The output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3. The output terminal of the third inverter INV3 is connected to the input terminal of the fifth switch M5. The output terminal of the fourth switch M4 is connected to the output terminal of the fifth switch M5 and serves as the output terminal of the first delay sub-unit 13111. The control terminals of the fourth switch M4 and the fifth switch M5 are respectively used to input delay control signals.

[0049] In this embodiment, the fourth switch M4 and the fifth switch M5 can be specifically MOS transistors. The second inverter INV2 and the third inverter INV3 together constitute a basic delay circuit. Multiple of the above-mentioned first delay sub-units 13111 are connected in series to form a configurable delay chain. The delay control signal controls the on and off of the fourth switch M4 and the fifth switch M5 in each first delay sub-unit 13111 to determine whether the signal path bypasses the two inverters of the sub-unit (i.e., passes through the fourth switch M4) or passes through the two inverters of the sub-unit (i.e., the second inverter INV2 and the third inverter INV3) in sequence. In this way, the number of effective inverter pairs that the signal needs to pass through from the input terminal to the output terminal of the delay unit 1311 can be dynamically changed. Since each inverter pair introduces a fixed unit delay, the more inverter pairs connected in series, the greater the total delay time, thereby realizing digital and step-by-step adjustment of the delay time.

[0050] like Figure 9 As shown, as another specific implementation, the delay unit 1311 may also include multiple second delay sub-units 13112 connected in series. The second delay sub-unit 13112 includes a fourth inverter INV4, a fifth inverter INV5, a sixth switch M6, and a capacitor C. The input terminal of the fourth inverter INV4 serves as the input terminal of the second delay sub-unit 13112. The output terminal of the fourth inverter INV4 is connected to the input terminals of the fifth inverter INV5 and the sixth switch M6. The output terminal of the sixth switch M6 is connected to the first terminal of the capacitor C. The output terminal of the sixth switch M6 is used to input a delay control signal. The second terminal of the capacitor C is grounded. The output terminal of the fifth inverter INV5 serves as the output terminal of the second delay sub-unit 13112.

[0051] In this embodiment, the sixth switch M6 can be specifically a MOSFET. The sixth switch M6 acts as a switch for connecting capacitor C. When the sixth switch M6 is turned on, capacitor C is connected in parallel to the inverter INV1 node. When it is turned off, it is disconnected. By controlling the on and off of the sixth switch M6 in each of the second delay sub-units 13112 in the delay chain, the total value of the load capacitor C of each node in the series path can be dynamically changed. Since the node delay is proportional to the load capacitor C, the delay time of the entire delay unit 1311 can be adjusted in steps by controlling the total amount of connected capacitor C.

[0052] This application also provides a chip including a transmitter according to any of the above.

[0053] like Figure 10As shown, this application also provides a signal transmission device, including a transmitter 100, a transmission medium 200, and a receiver 300. The transmitter 100 is configured as a transmitter as described in any of the preceding claims. The transmission medium 200 is used to transmit an output signal and form a target signal to be sent to the receiver 300. The attenuation value of the target signal compared to the original signal is less than a preset threshold.

[0054] In this embodiment, the transmission medium 200 can be a wired medium such as twisted pair or coaxial cable, or it can be a wireless transmission medium 200. The preset threshold is a technical indicator determined based on the signal decision threshold of the receiver 300 and the system bit error rate requirement, to ensure that the target signal can be correctly decoded by the receiver 300. This embodiment does not restrict the selection of the preset threshold value, as long as it does not affect the subsequent processing of the original signal. For example, when the preset threshold is 0, the target signal does not attenuate relative to the original signal. At the same time, the preset threshold can be a value greater than 0 but does not affect the subsequent processing of the original signal.

[0055] The embodiments in this specification are described in a progressive manner, with each embodiment focusing on the related aspects. For any differences between the embodiments, or for the same or similar parts between the embodiments, please refer to each other.

[0056] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A transmitter, characterized in that, include: Controllable current module and output module; The control terminal of the controllable current module is used to receive control signals, and the output terminal is connected to the input terminal of the output module, with the common terminal of the connection serving as the output terminal of the transmitter. The controllable current module is used to generate a composite current according to the control signal, the composite current including a main current and an additional current; The output module is used to generate and output an output signal based on the synthesized current and the original signal received by the transmitter; wherein the output signal includes an additional signal, the amplitude and duration of which are adjusted according to the control signal.

2. The transmitter according to claim 1, characterized in that, The controllable current module includes a main current module and an auxiliary current module, and the control signal includes a main control signal and an auxiliary control signal; The main current module is used to generate main current according to the main control signal; The additional current module is used to generate additional current according to the additional control signal.

3. The transmitter according to claim 2, characterized in that, The transmitter also includes a control module; The input terminal of the control module receives a control signal, the control terminal of the control module receives a delayed control signal, and the output terminal of the control module is connected to the control terminal of the additional current module. The control module is used to generate the additional control signal based on the slave control signal and the delay control signal.

4. The transmitter according to claim 3, characterized in that, The slave control signal includes multiple slave control sub-signals, the control module includes multiple control units connected in parallel, and the additional current module includes multiple additional current units connected in parallel. Each of the aforementioned control units is configured in a one-to-one correspondence with one of the aforementioned additional current units; The input terminal of the control unit receives the slave control sub-signal, the control terminal of the control unit receives the delay control signal, and the output terminal of the control unit is connected to the control terminal of the corresponding additional current unit. The control unit is configured to generate an additional control sub-signal based on the slave control sub-signal and the delay control signal; The additional current unit is used to generate a first sub-current according to the additional control sub-signal; The additional current is synthesized from multiple first sub-currents, the amplitude of the additional signal is positively correlated with the number of first sub-currents, and the duration of the additional signal is positively correlated with the delay time of the additional control sub-signal.

5. The transmitter according to claim 4, characterized in that, The control unit includes a delay unit, an inverter, and logic gates; The input terminal of the delay unit receives the slave control sub-signal, the control terminal of the delay unit receives the delay control signal, the output terminal of the delay unit is connected to the input terminal of the inverter, the output terminal of the inverter is connected to one input terminal of the logic gate, the other input terminal of the logic gate receives the slave control sub-signal, and the output terminal of the logic gate is connected to the control terminal of the corresponding additional current unit. The delay unit is used to perform delay processing on the slave control sub-signal according to the delay control signal to generate a delay signal; The logic gate is used to perform logical operations on the slave control sub-signal and the inverted delayed signal to generate an additional control sub-signal.

6. The transmitter according to claim 4, characterized in that, The additional current unit includes a first current source and a first switching unit; The control terminal of the first switching unit receives the additional control sub-signal, the input terminal of the first switching unit is connected to the output terminal of the first current source, and the output terminal of the first switching unit is connected to the input terminal of the output module. The first switching unit is used to turn on or off according to the additional control sub-signal to control the output current of the first current source.

7. The transmitter according to claim 2, characterized in that, The output signal also includes a main signal, the main control signal includes multiple main control sub-signals, and the main current module includes multiple main current units connected in parallel. The main current unit is used to generate a second sub-current according to the main control sub-signal; The main current is synthesized from multiple second sub-currents, and the amplitude of the main signal is positively correlated with the number of second sub-currents.

8. The transmitter according to claim 1, characterized in that, The output module includes an adjustable load. The first end of the adjustable load is connected to the output end of the controllable current module, and the common end of the connection serves as the output end of the transmitter. The control end of the adjustable load receives an impedance control signal, and the second end of the adjustable load is grounded.

9. A chip, characterized in that, Includes the transmitter as described in any one of claims 1 to 8.

10. A signal transmission device, comprising a transmitter, a transmission medium, and a receiver, characterized in that, The transmitter is configured as a transmitter as described in any one of claims 1 to 8; The transmission medium is used to transmit the output signal and form a target signal to be sent to the receiver. The attenuation value of the target signal compared to the original signal is less than a preset threshold.

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