Reconfigurable intelligent imaging chip system

Abstract

The invention provides a reconfigurable intelligent imaging chip system, and the system is characterized in that a control and scheduling unit is used for determining a corresponding first target voltage signal and a first target structure of a reconfigurable super-structure chip based on a target task, and a first target neural network model; the on-chip optical sensing unit is used for regulating and controlling the reconfigurable super-structure chip of the first target structure through the first target voltage signal to perform in-situ modulation and compression coding of a high-dimensional light field to obtain a light field compression characteristic value image; the on-chip signal preprocessing unit is used for preprocessing the light field compression characteristic value image to obtain a target digital characteristic image; and the on-chip intelligent computing unit is used for processing the target digital feature image through the first target neural network model and outputting a task result. According to the system integrating optical perception and intelligent calculation, the complete process from on-chip light field collection to intelligent information processing is achieved, and the perception requirements of adapting to multiple tasks, multiple scenes and multiple modes are met.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic processing technology, and in particular to a reconfigurable intelligent imaging chip system. Background Technology

[0002] With the deep integration of artificial intelligence (AI) and the Internet of Things (IoT) technologies, the demand for real-time perception and intelligent processing of high-dimensional visual information is becoming increasingly urgent in edge computing scenarios such as intelligent transportation, industrial visual inspection, and augmented reality (AR). These applications require not only capturing the two-dimensional intensity information of targets but also acquiring and understanding their rich physical properties, such as angles, spectra, polarization, and other multi-dimensional light field features, in order to achieve low-latency scene understanding and task adaptation.

[0003] Currently, visual perception systems are built upon traditional digital CMOS image sensors. However, conventional CMOS image sensors are essentially intensity-response devices, capable of recording only the light intensity distribution in two-dimensional space. They cannot directly capture high-dimensional features such as spectrum, polarization, and angle, which carry crucial information about the target material, surface shape, and depth, at the optical front end. This results in a significant loss of valuable information at the sensing source. Furthermore, the process from optical acquisition to digital signal processing involves multiple photoelectric and analog-to-digital conversions, increasing system energy consumption and limiting end-to-end real-time performance and bandwidth efficiency. To address the aforementioned limitations, related technologies propose integrating "intelligent sensors + edge computing." This approach attempts to integrate lightweight computing units (such as analog computing circuits or in-memory computing arrays) within the sensor chip or near the sensing end, offloading some computational tasks to the hardware layer. While this approach alleviates the burden on the backend processor to some extent, the overall bandwidth bottleneck and power consumption issues remain unresolved because the output signal still requires pixel-by-pixel readout and conversion. Furthermore, this architecture still exhibits weak capabilities in feature fusion and collaborative processing of multidimensional information (such as spectral and polarization). Consequently, the aforementioned technical solutions struggle to simultaneously achieve efficient acquisition of high-dimensional information and flexible adaptation to intelligent tasks, resulting in poor versatility across different application scenarios. The rigid hardware architecture prevents adaptive reconstruction of optical structures or computational processes at the sensing source based on specific task requirements, severely limiting the system's versatility and robustness in complex application environments. Summary of the Invention

[0004] This disclosure aims to at least partially address one of the technical problems in the related art.

[0005] Therefore, the first objective of this disclosure is to propose a reconfigurable intelligent imaging chip system. Through a control and scheduling unit, an on-chip optical sensing unit, an on-chip signal preprocessing unit, and an on-chip intelligent computing unit, a complete end-to-end process from optical high-dimensional encoding to intelligent task execution is constructed. This proposes a system that integrates optical sensing and intelligent computing, realizing a complete process from on-chip light field acquisition to intelligent information processing, and meeting the sensing needs of adapting to multiple tasks, multiple scenarios, and multiple modalities.

[0006] To achieve the above objectives, a first aspect of this disclosure proposes a reconfigurable intelligent imaging chip system, the system comprising a control and scheduling unit, an on-chip optical sensing unit, an on-chip signal preprocessing unit, and an on-chip intelligent computing unit, wherein... The control and scheduling unit is connected to the on-chip optical sensing unit and the on-chip intelligent computing unit respectively, and is used to acquire the target task, and determine the corresponding first target voltage signal, the first target structure of the reconfigurable meta-chip, and the first target neural network model based on the target task; The on-chip optical sensing unit is connected to the control and scheduling unit and is used to regulate the reconfigurable metachip of the first target structure through the first target voltage signal to perform in-situ modulation and compression encoding of the high-dimensional light field to obtain a compressed feature value image of the light field. The on-chip signal preprocessing unit is connected to the on-chip optical sensing unit and is used to acquire the light field compression feature value image and preprocess the light field compression feature value image to obtain the target digital feature image. The on-chip intelligent computing unit is connected to the on-chip signal preprocessing unit and the control and scheduling unit, and is used to acquire the target digital feature image, process the target digital feature image through the first target neural network model, and output the task result.

[0007] Optionally, the reconfigurable metachip includes a metasurface image sensor to acquire an input light image, wherein the metasurface image sensor is a liquid crystal-wetted composite metasurface image sensor.

[0008] Optionally, the reconfigurable metachip uses upper and lower double-layer glass to encapsulate the liquid crystal cavity to form a liquid crystal cavity. Combining electrically tunable liquid crystal and static metasurface structure, it realizes the collaborative perception of light field control and multi-dimensional information extraction at the micro-nano scale. In this case, one side of the liquid crystal cavity has a nanostructure, and the other side is a flat glass surface.

[0009] Optionally, the metasurface units inside the reconfigurable metachip are composed of a subwavelength-scale array of nanopillars, and each nanopillar can be freely designed in terms of its contour and topology to achieve local encoding of the target light field in four dimensions: space, angle, spectrum and polarization.

[0010] Optionally, the on-chip signal preprocessing unit includes an image acquisition chip and an edge acceleration module; the step of acquiring the light field compression feature value image and preprocessing the light field compression feature value image to obtain the target digital feature image includes: The image acquisition chip performs photoelectric conversion on the light field compression feature value image to obtain an initial digital feature image; The edge acceleration module preprocesses the initial digital feature image to obtain the target digital feature image.

[0011] Optionally, the edge acceleration module preprocesses the initial digital feature image to obtain the target digital feature image, including: The edge acceleration module performs image reading, normalization, filtering, and enhancement on the initial digital feature image to obtain the target digital feature image.

[0012] Optionally, determining the corresponding first target voltage signal and the first target structure of the reconfigurable metachip, as well as the first target neural network model, based on the target task includes: Based on the target task, a first target voltage signal corresponding to the target task is determined from the voltage set through a first mapping relationship; Based on the target task, the first target structure of the reconfigurable metachip is determined from the set of reconfigurable metachip structures through a second mapping relationship; Based on the target task, the first target neural network model is determined from the set of neural network models through a third mapping relationship.

[0013] Optionally, the system further includes an adaptive adjustment unit; the adaptive adjustment unit is connected to both the on-chip optical sensing unit and the on-chip intelligent computing unit, wherein... The adaptive adjustment unit is used to acquire the task result and determine the corresponding second target voltage signal, the second target structure of the reconfigurable metachip, and the second target neural network model based on the task result.

[0014] Optionally, determining the corresponding second target voltage signal and the second target structure of the reconfigurable metachip, as well as the second target neural network model, based on the task results includes: Based on the task results, the corresponding second target voltage signal is determined from the voltage set through a first mapping relationship; Based on the task results, the second target structure of the reconfigurable metachip is determined from the set of reconfigurable metachip structures through a second mapping relationship; Based on the task results, a second target neural network model is determined from the set of neural network models through a third mapping relationship.

[0015] Optionally, the target task includes at least one of digit recognition, angle reconstruction, and spectral band selection.

[0016] In summary, the reconfigurable intelligent imaging chip system provided in this disclosure includes a control and scheduling unit, an on-chip optical sensing unit, an on-chip signal preprocessing unit, and an on-chip intelligent computing unit. The control and scheduling unit is connected to both the on-chip optical sensing unit and the on-chip intelligent computing unit, and is used to acquire a target task, and based on the target task, determine the corresponding first target voltage signal, the first target structure of the reconfigurable meta-chip, and a first target neural network model. The on-chip optical sensing unit is connected to the control and scheduling unit, and is used to modulate the reconfigurable meta-chip of the first target structure using the first target voltage signal to perform in-situ modulation and compression encoding of a high-dimensional light field, obtaining a compressed light field feature image. The on-chip signal preprocessing unit is connected to the on-chip optical sensing unit, and is used to acquire the compressed light field feature image and preprocess it to obtain a target digital feature image. The on-chip intelligent computing unit is connected to both the signal preprocessing unit and the control and scheduling unit, and is used to acquire the target digital feature image and process it using the first target neural network model to output the task result. This disclosure constructs a complete end-to-end process from optical high-dimensional encoding to intelligent task execution through a control and scheduling unit, an on-chip optical sensing unit, an on-chip signal preprocessing unit, and an on-chip intelligent computing unit. This proposes a system that integrates optical sensing and intelligent computing, realizing a complete process from on-chip light field acquisition to intelligent information processing, and meeting the sensing needs of adapting to multiple tasks, multiple scenarios, and multiple modalities.

[0017] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic diagram of the structure of a reconfigurable intelligent imaging chip system provided in an embodiment of this disclosure. Detailed Implementation

[0019] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0020] The reconfigurable intelligent imaging chip system of this disclosure will be described in detail below with reference to specific embodiments.

[0021] Figure 1 This disclosure provides a reconfigurable intelligent imaging chip system according to an embodiment of the present disclosure. For example... Figure 1 As shown, the reconfigurable intelligent imaging chip system may include a control and scheduling unit 101, an on-chip optical sensing unit 102, an on-chip signal preprocessing unit 103, and an on-chip intelligent computing unit 104, wherein... The control and scheduling unit 101 is connected to the on-chip optical sensing unit 102 and the on-chip intelligent computing unit 104 respectively, and is used to acquire the target task, and determine the corresponding first target voltage signal, the first target structure of the reconfigurable meta-chip, and the first target neural network model based on the target task. The on-chip optical sensing unit 102 is connected to the control and scheduling unit 101 and is used to regulate the reconfigurable metachip of the first target structure through the first target voltage signal to perform in-situ modulation and compression encoding of the high-dimensional light field to obtain the compressed feature value image of the light field. The on-chip signal preprocessing unit 103 is connected to the on-chip optical sensing unit 102 and is used to acquire the light field compression feature value image and preprocess the light field compression feature value image to obtain the target digital feature image. The on-chip intelligent computing unit 104 is connected to the on-chip signal preprocessing unit 103 and the control and scheduling unit 101. It is used to acquire the target digital feature image, process the target digital feature image through the first target neural network model, and output the task result.

[0022] In one embodiment of this disclosure, the target task may include at least one of digit recognition, angle reconstruction, and spectral band selection.

[0023] In one embodiment of this disclosure, the on-chip optical sensing unit 102 can be a reconfigurable metachip with a compact optical structure as a front-end information acquisition unit, responsible for completing the in-situ modulation and compression encoding of the high-dimensional light field, and outputting a compressed feature value image of the light field containing rich information.

[0024] In one embodiment of this disclosure, the reconfigurable metachip includes a metasurface image sensor to acquire an input light image. The metasurface image sensor is a liquid crystal-infused metasurface (LCIMS) image sensor, which overcomes the inherent limitations of traditional image sensor structures in terms of dimensional scalability, task adaptability, and feature response capability, and constructs an imaging system architecture with high intelligence and task adaptability.

[0025] In one embodiment of this disclosure, the above-mentioned reconfigurable metachip uses upper and lower double-layer glass to encapsulate the liquid crystal cavity to form a liquid crystal cavity. Combining electrically tunable liquid crystal and static metasurface structure, it realizes the collaborative perception of light field control and multi-dimensional information extraction at the micro-nano scale. In this case, one side of the liquid crystal cavity has a nanostructure, and the other side is a flat glass surface.

[0026] Furthermore, in one embodiment of this disclosure, the metasurface units inside the reconfigurable metachip are composed of a subwavelength-scale array of nanopillars, each of which can be freely designed in terms of its contour and topology to achieve local encoding of the target light field in four dimensions: space, angle, spectrum, and polarization.

[0027] Furthermore, in one embodiment of this disclosure, an initial set of nanopillar structure parameters specific to the target task can be designed based on prior information of the target task. This initial set serves as a template during chip manufacturing, enabling rapid task switching and adaptive operation through electro-hydraulic fine-tuning. For example, assuming the target task is a digit recognition task, dynamic weighting of different spectral channels can achieve a high robust recognition rate of the target digit under changing backgrounds; assuming the target task is angle reconstruction, a phase encoding structure that enhances angular resolution can be automatically selected, and spectral redundancy can be compressed, thereby achieving high-precision three-dimensional contour recognition. This hardware-level "task-aware" mechanism is difficult to achieve with traditional image sensors. Based on this, the control and scheduling unit can determine the first target structure of the reconfigurable metachip from the set of reconfigurable metachip structures through a second mapping relationship, according to the target task.

[0028] Furthermore, in one embodiment of this disclosure, the control and scheduling unit can determine the first target voltage signal corresponding to the target task from the voltage set through a first mapping relationship according to the target task, and send the first target voltage signal to the on-chip optical sensing unit to regulate the optical response characteristics of the reconfigurable metachip and realize task-related encoding.

[0029] Furthermore, in one embodiment of this disclosure, the on-chip signal preprocessing unit may include an image acquisition chip and an edge acceleration module. The method for acquiring an optical field compression feature value image and preprocessing it to obtain a target digital feature image may include: the image acquisition chip performing photoelectric conversion on the optical field compression feature value image to obtain an initial digital feature image; and the edge acceleration module preprocessing the initial digital feature image to obtain the target digital feature image.

[0030] In one embodiment of this disclosure, the image acquisition chip can be a built-in low-power image acquisition chip (such as a custom CMOS).

[0031] Furthermore, in one embodiment of this disclosure, the method by which the edge acceleration module preprocesses the initial digital feature image to obtain the target digital feature image may include: the edge acceleration module performing image reading, normalization, filtering, and enhancement on the initial digital feature image to obtain the target digital feature image.

[0032] Furthermore, in one embodiment of this disclosure, the control and scheduling unit 101 can determine a first target neural network model from the neural network model set through a third mapping relationship based on the target task. This allows the on-chip intelligent computing unit to load task-specific lightweight model weights, achieving an end-to-end data processing closed loop. The entire process can be driven by a task descriptor, managing the coordinated operation of each task through a unified interface, thereby improving the overall flexibility and resource utilization of the system. The neural network model set may include CNN and Transformer variants.

[0033] Furthermore, in one embodiment of this disclosure, the system further includes an adaptive adjustment unit 105; the adaptive adjustment unit 105 can be connected to the on-chip optical sensing unit 102 and the on-chip intelligent computing unit 104 respectively, wherein the adaptive adjustment unit is used to acquire task results and determine the corresponding second target voltage signal and the second target structure of the reconfigurable meta-chip, as well as the second target neural network model based on the task results.

[0034] In one embodiment of this disclosure, the method by which the adaptive adjustment unit 105 determines the corresponding second target voltage signal, the second target structure of the reconfigurable metachip, and the second target neural network model based on the task results may include: determining the corresponding second target voltage signal from the voltage set through a first mapping relationship based on the task results; determining the second target structure of the reconfigurable metachip from the structure set of the reconfigurable metachip through a second mapping relationship based on the task results; and determining the second target neural network model from the neural network model set through a third mapping relationship based on the task results.

[0035] Furthermore, in one embodiment of this disclosure, the aforementioned reconfigurable intelligent imaging chip system is suitable for rapid recognition tasks in fixed scenarios and can also adapt to perceptual changes in dynamic scenarios. The adaptive adjustment unit can monitor the distribution changes of the input image and the acquired task results in real time, dynamically adjusting the voltage signal, the target structure of the reconfigurable meta-chip, and the neural network model to form a dual closed-loop mechanism of "adaptive + self-feedback." This allows the reconfigurable intelligent imaging chip system to exhibit some characteristics of brain-like intelligence: adapting to new inputs without retraining when local scene changes, thus improving its robustness and versatility in practical deployments.

[0036] The reconfigurable intelligent imaging chip system disclosed herein includes a control and scheduling unit, an on-chip optical sensing unit, an on-chip signal preprocessing unit, and an on-chip intelligent computing unit. The control and scheduling unit is connected to both the on-chip optical sensing unit and the on-chip intelligent computing unit, and is used to acquire a target task, and based on the target task, determine a corresponding first target voltage signal, a first target structure of the reconfigurable meta-chip, and a first target neural network model. The on-chip optical sensing unit is connected to the control and scheduling unit, and is used to modulate the reconfigurable meta-chip of the first target structure using the first target voltage signal to perform in-situ modulation and compression encoding of a high-dimensional light field, obtaining a compressed light field feature image. The on-chip signal preprocessing unit is connected to the on-chip optical sensing unit, and is used to acquire the compressed light field feature image and preprocess it to obtain a target digital feature image. The on-chip intelligent computing unit is connected to both the signal preprocessing unit and the control and scheduling unit, and is used to acquire the target digital feature image and process it using the first target neural network model to output the task result. This disclosure constructs a complete end-to-end process from optical high-dimensional encoding to intelligent task execution through a control and scheduling unit, an on-chip optical sensing unit, an on-chip signal preprocessing unit, and an on-chip intelligent computing unit. This proposes a system that integrates optical sensing and intelligent computing, realizing a complete process from on-chip light field acquisition to intelligent information processing, and meeting the sensing needs of adapting to multiple tasks, multiple scenarios, and multiple modalities.

[0037] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in this disclosure all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0038] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0039] This disclosure is intended to provide implementation schemes for users to selectively prevent the use or access to their personal information data. Specifically, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information is de-identified to protect user privacy.

[0040] The acquisition, transmission, storage, use, and processing of data in this disclosed technical solution all comply with the relevant provisions of national laws and regulations.

[0041] It should be noted that in the embodiments disclosed herein, certain software, components, models, and other existing solutions in the industry may be mentioned. These should be considered as exemplary and are intended only to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used such solutions.

[0042] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0044] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0045] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0046] It should be understood that various parts of this disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0047] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium. When executed, the program includes one or a combination of the steps of the method embodiments.

[0048] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0049] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A reconfigurable intelligent imaging chip system, characterized in that, The system includes a control and scheduling unit, an on-chip optical sensing unit, an on-chip signal preprocessing unit, and an on-chip intelligent computing unit, wherein... The control and scheduling unit is connected to the on-chip optical sensing unit and the on-chip intelligent computing unit respectively, and is used to acquire the target task, and determine the corresponding first target voltage signal, the first target structure of the reconfigurable meta-chip, and the first target neural network model based on the target task; The on-chip optical sensing unit is connected to the control and scheduling unit and is used to regulate the reconfigurable metachip of the first target structure through the first target voltage signal to perform in-situ modulation and compression encoding of the high-dimensional light field to obtain a compressed feature value image of the light field. The on-chip signal preprocessing unit is connected to the on-chip optical sensing unit and is used to acquire the light field compression feature value image and preprocess the light field compression feature value image to obtain the target digital feature image. The on-chip intelligent computing unit is connected to the on-chip signal preprocessing unit and the control and scheduling unit, and is used to acquire the target digital feature image, process the target digital feature image through the first target neural network model, and output the task result.

2. The system according to claim 1, characterized in that, The reconfigurable metachip includes a metasurface image sensor to acquire an input light image, wherein the metasurface image sensor is a liquid crystal immersion composite metasurface image sensor.

3. The system according to claim 2, characterized in that, The reconfigurable meta-chip uses double-layer glass to encapsulate the liquid crystal cavity to form a liquid crystal cavity. Combining electrically tunable liquid crystal and static metasurface structure, it achieves collaborative perception of light field control and multi-dimensional information extraction at the micro-nano scale. One side of the liquid crystal cavity has a nanostructure, and the other side is a flat glass surface.

4. The system according to claim 3, characterized in that, The metasurface units inside the reconfigurable metachip are composed of subwavelength-scale nanopillar arrays. Each nanopillar can be freely designed in terms of its contour and topology to achieve local encoding of the target light field in four dimensions: space, angle, spectrum, and polarization.

5. The system according to claim 1, characterized in that, The on-chip signal preprocessing unit includes an image acquisition chip and an edge acceleration module; the step of acquiring the light field compression feature value image and preprocessing the light field compression feature value image to obtain the target digital feature image includes: The image acquisition chip performs photoelectric conversion on the light field compression feature value image to obtain an initial digital feature image; The edge acceleration module preprocesses the initial digital feature image to obtain the target digital feature image.

6. The system according to claim 5, characterized in that, The edge acceleration module preprocesses the initial digital feature image to obtain the target digital feature image, including: The edge acceleration module performs image reading, normalization, filtering, and enhancement on the initial digital feature image to obtain the target digital feature image.

7. The system according to claim 1, characterized in that, The determination of the corresponding first target voltage signal and the first target structure of the reconfigurable metachip based on the target task, as well as the first target neural network model, includes: Based on the target task, a first target voltage signal corresponding to the target task is determined from the voltage set through a first mapping relationship; Based on the target task, the first target structure of the reconfigurable metachip is determined from the set of reconfigurable metachip structures through a second mapping relationship; Based on the target task, the first target neural network model is determined from the set of neural network models through a third mapping relationship.

8. The system according to claim 1, characterized in that, The system further includes an adaptive adjustment unit; the adaptive adjustment unit is connected to both the on-chip optical sensing unit and the on-chip intelligent computing unit, wherein... The adaptive adjustment unit is used to acquire the task result and determine the corresponding second target voltage signal, the second target structure of the reconfigurable metachip, and the second target neural network model based on the task result.

9. The system according to claim 8, characterized in that, The step of determining the corresponding second target voltage signal and the second target structure of the reconfigurable metachip, as well as the second target neural network model based on the task results, includes: Based on the task results, the corresponding second target voltage signal is determined from the voltage set through a first mapping relationship; Based on the task results, the second target structure of the reconfigurable metachip is determined from the set of reconfigurable metachip structures through a second mapping relationship; Based on the task results, a second target neural network model is determined from the set of neural network models through a third mapping relationship.

10. The system according to any one of claims 1-9, characterized in that, The target task includes at least one of digital recognition, angle reconstruction, and spectral band selection.

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