Semiconductor device, and method for forming a semiconductor device

Abstract

In some embodiments, a semiconductor device is provided. The semiconductor device includes an interconnect structure disposed over a substrate, where the interconnect structure includes a conductive feature disposed in a dielectric layer; a first passivation layer disposed over the interconnect structure; a second passivation layer disposed over the etch stop layer; a plurality of holes and a plurality of trenches extending into the second passivation layer from an upper surface of the second passivation layer, in which the trenches overlap the etch stop layer in a plan view; a first capacitor structure including a first conductive layer, a first insulating layer, and a second conductive layer disposed over the second passivation layer and extending into the hole; and a second capacitor structure including a third conductive layer, a second insulating layer, and a fourth conductive layer disposed over the second passivation layer and extending into the trench. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] This application relates to semiconductor devices and methods for forming semiconductor devices. Background Technology

[0002] Electronic devices involving semiconductor devices are crucial for many modern applications. Technological advancements in materials and design have resulted in generations of semiconductor devices, each with smaller and more complex circuitry than the previous one. In the course of progress and innovation, functional density (i.e., the number of interconnect devices per chip region) typically increases, while geometry (i.e., the smallest component that can be produced using manufacturing processes) decreases. These advancements increase the complexity of handling and manufacturing semiconductor devices.

[0003] Capacitors are typically embedded in integrated passive devices to replace ceramic capacitors, thereby reducing the size and cost of mobile devices, improving their functionality, or any combination thereof. To provide improved characteristics and performance, metal-insulator-metal (MIM) capacitor designs, involving multiple metal and dielectric layers in an interlaced pattern, have recently been introduced. When the layers of a MIM capacitor are formed within recesses with a high aspect ratio, the manufacturing process becomes complex and difficult to control. Therefore, an improved MIM capacitor structure and its manufacturing method are needed. Summary of the Invention

[0004] One embodiment of this application provides a semiconductor device, comprising: an interconnect structure disposed above a substrate, wherein the interconnect structure includes conductive components disposed in a dielectric layer; a first passivation layer disposed above the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; an etch stop layer disposed above the first passivation layer; a second passivation layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from the upper surface of the second passivation layer into the second passivation layer, wherein at least one of the holes includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and wherein at least one of the trenches includes a third width along the first direction that is smaller than the first width. The trench includes a width and a fourth width along the second direction that is greater than the second width, wherein the trench overlaps with the etch stop layer in a plan view; a first capacitor structure including a first conductive layer, a first insulating layer, and a second conductive layer, the first conductive layer, the first insulating layer, and the second conductive layer being disposed above the second passivation layer and extending into the hole, wherein the second conductive layer is located above the first conductive layer and the first insulating layer, and the second conductive layer has a curved top surface at least a portion above the upper surface of the second passivation layer; and a second capacitor structure including a third conductive layer, a second insulating layer, and a fourth conductive layer, the third conductive layer, the second insulating layer, and the fourth conductive layer being disposed above the second passivation layer and extending into the trench.

[0005] Another embodiment of this application provides a semiconductor device, comprising: a device disposed above a substrate, wherein the device includes source / drain components, and each of the source / drain components includes multiple layers, the multiple layers comprising different amounts of the same semiconductor material; a first dielectric layer disposed above the device; an etch stop layer disposed above the first dielectric layer; a second dielectric layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from the upper surface of the second dielectric layer into the second dielectric layer, wherein the holes are disposed in a first region, the trenches are disposed in a second region, and at least one of the holes... The trench includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and at least one of the trenches includes a third width along the first direction and a fourth width along the second direction, wherein the difference between the first width and the second width is less than the difference between the third width and the fourth width; and a capacitor structure including a first conductive layer, an insulating layer, and a second conductive layer, the first conductive layer, the insulating layer, and the second conductive layer being disposed above the upper surface of the second dielectric layer and extending into the hole and the trench, wherein a first occupied area of ​​the first region is greater than a second occupied area of ​​the second region.

[0006] Another aspect of this application relates to a method for forming a semiconductor device, the method comprising: forming an interconnect structure over a substrate, wherein the interconnect structure includes conductive components disposed in a dielectric layer; forming a first passivation layer over the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; forming an etch stop layer over the first passivation layer; forming a second passivation layer over the etch stop layer; and performing an etching process to form a plurality of holes and a plurality of trenches in the second passivation layer, wherein at least one of the holes includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and at least one of the trenches includes a third width along the first direction that is smaller than the first width and a third width along the second direction. The second direction has a fourth width greater than the second width; and a first capacitor structure and a second capacitor structure are formed above the second passivation layer, wherein the first capacitor structure includes a first conductive layer, a first insulating layer and a second conductive layer, the first conductive layer, the first insulating layer and the second conductive layer extending into the hole, wherein the second conductive layer is disposed above the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer above the second passivation layer has a curved top surface, wherein the second capacitor structure includes a third conductive layer, a second insulating layer and a fourth conductive layer, the third conductive layer, the second insulating layer and the fourth conductive layer extending into the trench, wherein the trench overlaps with the etch stop layer in a plan view. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a perspective view of a semiconductor device including device layers and interconnect structures according to some embodiments;

[0009] Figure 2 This is a cross-sectional view of the interconnect structure of a semiconductor device according to some embodiments;

[0010] Figure 3 A cross-sectional view of a semiconductor device including interconnect structures in a passivation structure according to some embodiments is shown;

[0011] Figure 4 This is a schematic diagram, according to some embodiments, of a region in a unit area of ​​a semiconductor device in a plan view for arranging capacitor structures.

[0012] Figure 5A , Figure 5B ,and Figure 5C Various embodiments are shown respectively. Figure 4 Enlarged view of the aperture capacitor, trench capacitor, and hybrid capacitor in the area shown;

[0013] Figures 6 to 12 A cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments is shown;

[0014] Figure 13 A cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments is shown;

[0015] Figure 14 A cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments is shown;

[0016] Figure 15 A cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments is shown;

[0017] Figure 16 A cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments is shown;

[0018] Figure 17 A cross-sectional view of a semiconductor device including a capacitor structure in a passivation structure according to some embodiments is shown;

[0019] Figure 18 A cross-sectional view of a semiconductor package according to some embodiments is shown;

[0020] Figure 19 A cross-sectional view of a semiconductor device including a capacitor structure and a back-side interconnect structure according to some embodiments is shown. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," "above," "top," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0023] According to some embodiments, a semiconductor device including a capacitor structure is provided. The semiconductor device may include a via capacitor and a trench capacitor formed in a passivation structure above an interconnect structure. The via capacitor includes a layer extending into the via, while the trench capacitor includes a layer extending into the trench. The via capacitor can generate less stress in the semiconductor device, while the trench capacitor can be disposed in a region with a smaller size. The passivation structure may include an etch stop layer at least at the location where a trench is to be formed. The etch stop layer may partially or completely resist the etch process used to form the trench. Therefore, although the etch process may have a higher etch rate when forming a trench than when forming a via, the trench may be located away from the underlying interconnect structure without damaging the underlying interconnect structure when the via reaches its desired depth. Therefore, the semiconductor device can simultaneously include both via capacitors and trench capacitors, resulting in improved manufacturing yield.

[0024] Figure 1 This is a perspective cross-sectional view of a semiconductor device 100 including device layer 200 and interconnect structure 250. Device layer 200 includes substrate 102 and one or more devices formed in or on substrate 102. Substrate 102 may be a semiconductor substrate. In some embodiments, substrate 102 includes at least a crystalline semiconductor layer on the surface of substrate 102. Substrate 102 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). For example, substrate 102 is made of Si. In some embodiments, substrate 102 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxygen-containing material, such as an oxide.

[0025] The substrate 102 may include various regions, including active regions and isolation regions. The active regions may be appropriately doped with impurities (e.g., p-type or n-type impurities) to form, for example, well regions.

[0026] As described above, device layer 200 may include any suitable device, such as a transistor, diode, imaging sensor, resistor, capacitor, inductor, memory cell, or a combination thereof. In some embodiments, device layer 200 includes transistors, such as planar field-effect transistors (FETs), FinFETs, nanostructured transistors, or other suitable transistors. Nanostructured transistors may include nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge-channel (MBC) transistors, or any transistor having a gate electrode surrounding a channel. An example of a device formed on substrate 102 is a FinFET, such as... Figure 1 As shown in the diagram. Device layer 200 includes source / drain (S / D) regions 124 and gate stack 140. Figure 1 (Only one is shown in the image). Each gate stack 140 may be disposed between one or more S / D regions 124 used as source regions and one or more S / D regions 124 used as drain regions. For example, each gate stack 140 may extend along the Y-axis between one or more S / D regions 124 used as source regions and one or more S / D regions 124 used as drain regions. Although not shown, a channel region is formed between the S / D regions 124, and at least three surfaces are surrounded by the gate stack 140.

[0027] The S / D region 124 may include a semiconductor material, such as Si or Ge, a III-V compound semiconductor, a II-VI compound semiconductor, or other suitable semiconductor materials. Exemplary S / D regions 124 may include, but are not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, etc. The S / D region 124 may include: p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. The S / D region 124 may be formed using epitaxial growth methods such as CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The channel region may include one or more semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, or InP. The channel region may include the same semiconductor material as the substrate 102. In some embodiments, the device layer 200 may include a FinFET, and the channel region is a plurality of fins disposed below the gate stack 140. In some embodiments, the device layer 200 may include a nanostructured transistor, and the channel region is surrounded by the gate stack 140.

[0028] The gate stack 140 includes a gate electrode layer 138 disposed above (or around) the channel region for a nanostructure transistor. The gate electrode layer 138 may be a metallic material, such as tungsten, cobalt, aluminum, ruthenium, copper, or multiples thereof, and may be deposited using ALD, plasma-enhanced chemical vapor deposition (PECVD), MBD, physical vapor deposition (PVD), or any suitable deposition technique. The gate stack 140 may also include a gate dielectric layer 136 disposed above the channel region. The gate electrode layer 138 may be disposed above the gate dielectric layer 136. In some embodiments, an interface layer (not shown) may be disposed between the channel region 108 and the gate dielectric layer 136, and one or more work function layers (not shown) may be formed between the gate dielectric layer 136 and the gate electrode layer 138. The interface dielectric layer may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, or multiples thereof, and may be formed using any suitable deposition method such as CVD, PECVD, or ALD. The gate dielectric layer 136 may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, a high-k dielectric material having a k-value greater than that of silicon dioxide, or multiple layers thereof. The gate dielectric layer 136 may be formed by any suitable method, such as CVD, PECVD, or ALD. In some embodiments, the gate dielectric layer 136 may be a conformal layer. The term "conformal" may be used herein to conveniently describe layers having substantially the same thickness over different regions. One or more work-function layers may include titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, etc.

[0029] Gate spacer 122 is formed along the sidewalls of gate stack 140 (e.g., the sidewalls of gate dielectric layer 136). Gate spacer 122 may comprise silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., multilayers thereof, or combinations thereof, and may be deposited by CVD, ALD, or other suitable deposition techniques. In some embodiments, fin sidewall spacers 123 may be disposed on opposite sides of each S / D region 124, and fin sidewall spacers 123 may comprise the same material as gate spacer 122. Portions of gate stack 140, gate spacer 122, and fin sidewall spacers 123 may be disposed on isolation region 114. Isolation region 114 is disposed on substrate 102. Isolation region 114 may comprise an insulating material, such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. In some embodiments, isolation region 114 is shallow trench isolation (STI). Insulating materials can be formed using high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. In one aspect, the isolation region 114 comprises silicon oxide formed by the FCVD process.

[0030] A contact etch stop layer (CESL) 126 is formed on the S / D region 124 and the isolation region 114, and an interlayer dielectric (ILD) layer 128 is formed on the CESL 126. When an opening is formed in the ILD layer 128, the CESL 126 can provide a mechanism to stop the etching process. The CESL 126 can be conformally deposited on the surfaces of the S / D region 124 and the isolation region 114. The CESL 126 can include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, etc., or combinations thereof, and can be deposited by CVD, PECVD, ALD, or any suitable deposition technique. The ILD layer 128 may comprise an oxide formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), organosilicon glass (OSG), SiOC, and / or any suitable low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon dioxide), and may be deposited by spin coating, CVD, FCVD, PECVD, PVD, or any suitable deposition technique.

[0031] An S / D contact 142 may be disposed within the ILD layer 128 and above the S / D region 124. The S / D contact 142 may be conductive and comprises one or more materials selected from Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The conductive contact may be formed by any suitable method, such as electrochemical plating (ECP), CVD, or PVD. A silicide layer 144 may be disposed between the S / D contact 142 and the S / D region 124. The silicide layer 144 may be made of a metal or metal alloy silicide, and the metal may include noble metals, refractory metals, rare earth metals, their alloys, or combinations thereof.

[0032] In integrated circuits, interconnect structures (or interconnections) are used to provide signal routing and power to semiconductor devices. Integrated circuit chips typically include device layers fabricated during front-end line (FEOL) and middle-end line (MEOL) processes, and back-end line (BEOL) layers. Device layers can be formed in and / or on a substrate, and BEOL layers are formed on the front and / or back sides of the device layers. Device layers can include various semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., and can be formed in and / or on a substrate. In some embodiments, the device layer may also include MEOL structures, such as one or more dielectric layers having conductive structures connected to gate and source / drain components in the device layer. Interconnect structures typically include wires and vias formed in both the device layers and the BEOL layers.

[0033] Figure 2 This is a cross-sectional view of the interconnect structure at an intermediate stage of the fabrication of a semiconductor device 100 according to some embodiments, showing a detailed structure illustrating its interconnect structure. Interconnect structure 250 is formed above device layer 200. Interconnect structure 250 includes various conductive components 204 formed in dielectric layer 202, such as wires 205 and conductive vias 206. Dielectric layer 202 may be an inter-metal dielectric (IMD) layer or an inter-layer dielectric (ILD) layer. Dielectric layer 202 may include multiple dielectric layers embedded with multiple layers of wires 205 and vias 206. Dielectric layer 202 includes a dielectric material, such as SiO2. x Si O x C y H z or SiO x C y Where x, y, and z are integers or non-integers. In some embodiments, dielectric layer 202 includes a low-k dielectric material having a k-value less than that of silicon oxide. The wires 205 and conductive vias 206 can be formed from one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. The conductive vias 206 and wires 205 are arranged hierarchically to provide access to the gate electrode layer 138 in the device layer. Figure 1 ) and S / D contact 142 ( Figure 1 The electrical path of ).

[0034] Figure 3 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor device 100 according to some embodiments, showing a detailed structure illustrating its passivation structure. Figure 3 In this embodiment, a passivation structure 300 is formed above the interconnect structure 250. The passivation structure 300 may include a first passivation structure 310 disposed above the interconnect structure 250, and a second passivation structure 350 disposed above the first passivation structure 310. A capacitor structure 320 and / or other passivation devices may be formed in the first passivation structure 310. A bonding structure 360 ​​may be formed in the second passivation structure 350. In some embodiments, a conductive through-hole 370 extends through the first passivation structure 310 to electrically connect the bonding structure 360 ​​and the conductive components 204 of the interconnect structure 250.

[0035] In some embodiments, the first passivation structure 310 includes a first etch stop layer 312 above the dielectric layer 202 of the interconnect structure 250, a first passivation layer 314 above the first etch stop layer 312, a second etch stop layer 316 above the first passivation layer 314, and a second passivation layer 318 above the second etch stop layer 316. The first etch stop layer 312 may include a material different from the dielectric layer 202 to have different etch selectivity compared to the dielectric layer 202. In some embodiments, the first etch stop layer 312 is made of an insulating material such as carbide, nitride, metal oxide, metal nitride, or combinations thereof. Suitable materials for the first etch stop layer 312 may include, but are not limited to, silicon carbide, silicon carbonitride, silicon oxycarbonitride, aluminum nitride, aluminum oxide, titanium oxide, or combinations thereof. The first etch stop layer 312 may be formed by any suitable process, such as CVD, ALD, PVD, PECVD, or combinations thereof. According to some embodiments, the first etch stop layer 312 has a thickness of about 100 nm to about 200 nm. The first etch stop layer 312 can partially or completely resist the etching process used to form through-holes containing conductive through-holes 370. In this way, an additional etching process with a lower etch rate can be implemented to etch through the first etch stop layer so that the through-holes extend through the first etch stop layer 312, thereby reducing or avoiding over-etching that could damage the conductive components 204 of the interconnect structure 250.

[0036] According to some embodiments, the first passivation layer 314 comprises a material different from that of the dielectric layer 202 and the first etch stop layer 312. For example, the first passivation layer 314 is a passivation layer that provides, for example, moisture-proof sealing properties or mechanical robustness to protect the underlying interconnect structure 250 and device layer 200. The first passivation layer 314 may include a dielectric constant greater than that of the dielectric layer 202 in the interconnect structure 250. In some embodiments, the first passivation layer 314 comprises silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the dielectric layer 202 is silicon oxide, and the first passivation layer 314 is silicon nitride. The first passivation layer 314 may have a thickness T1 of about 150 nm to about 500 nm.

[0037] The second etch stop layer 316 may comprise a different material than the first passivation layer 314 to have different etch selectivity compared to the first passivation layer 314. For example, the second etch stop layer 316 may be or comprise a high-resistivity material, such as silicon carbonitride, silicon carbide, silicon oxycarbonitride, undoped silicon, undoped germanium, undoped silicon germanium, silicon nitride, hafnium oxide, zirconium oxide, or a stacked structure comprising oxide-nitride-oxide layers (e.g., SiO-SiN-SiO). The second etch stop layer 316 has a thickness greater than that of the first etch stop layer 312 but less than that of the first passivation layer 314. For example, the second etch stop layer 316 may have a thickness of about 30 nm to about 80 nm.

[0038] According to some embodiments, the second passivation layer 318 comprises a material different from that of the dielectric layer 202 and the second etch stop layer 316. For example, the second passivation layer 318 is a passivation layer that provides, for example, moisture-proof sealing properties or mechanical robustness to protect the underlying interconnect structure 250 and device layer 200. The second passivation layer 318 may be or comprise a material similar to that of the first passivation layer 314. For example, the second passivation layer 318 comprises silicon nitride, silicon oxynitride, or a combination thereof. The second passivation layer 318 may have a thickness of about 150 μm to about 500 μm. In some embodiments, the second passivation layer 318 has a substantially the same thickness as the first passivation layer 314, although different thicknesses may be achieved for the first passivation layer 314 and the second passivation layer 318.

[0039] A capacitor structure 320 is formed over the second passivation layer 318. According to some embodiments, the capacitor structure 320 extends into the first passivation layer 314, the second etch stop layer 316, and the second passivation layer 318 to increase the surface area. The capacitor structure 320 may be a metal-insulator-metal (MIM) structure. For example, the capacitor structure 320 may each include a first conductive layer 322, an insulating layer 324 over the first conductive layer 322, and a second conductive layer 326 over the insulating layer 324. Although... Figure 3 The diagram shows three layers, but capacitor structure 320 may include more layers.

[0040] In some embodiments, the first conductive layer 322 comprises one or more layers of Cu, Al, W, Co, Ti, Ta, TiN, TaN, or alloys thereof. In some embodiments, the thickness of the first conductive layer 322 is in the range of about 10 nm to about 100 nm, depending on design and / or process requirements. An insulating layer 324 is formed over the first conductive layer 322 and the first passivation layer 314. In some embodiments, the insulating layer 324 comprises one or more high-k dielectric layers having a dielectric constant greater than that of silicon oxide. In some embodiments, the first insulating layer 120 comprises one or more layers of Hf, Al, Zr, combinations thereof, or multiple layers thereof, of metal oxides or silicates. In some embodiments, hafnium oxide is used. Other suitable materials include La, Mg, Ba, Ti, Pb, and Zr, in the form of metal oxides, metal alloy oxides, or combinations thereof. Exemplary materials include MgO, BaTiO, BaSrTiO, PbTiO, PbZrTiyO, AlO, LaO, TaO, YO, HfO, ZrO, HfSiON, YGeO, YSiO, and LaAlO, and combinations thereof. In some embodiments, depending on design and / or process requirements, the insulating layer 324 has a thickness ranging from about 1 nm to about 10 nm, and in other embodiments from about 2 nm to about 5 nm. The second conductive layer 326 may include or be made of the same material as the first conductive layer 322. In some embodiments, seams or air gaps may be formed in the capacitor structure 320, sealed by the second conductive layer 326 or the insulating layer 324. In some embodiments, at least a portion of the first conductive layer 322 above the upper surface of the second passivation layer 318 has a curved top surface. At least a portion of the insulating layer 324 above the upper surface of the second passivation layer 318 may have a curved top surface. At least a portion of the second conductive layer 326 above the upper surface of the second passivation layer 318 may have a curved top surface.

[0041] According to some embodiments, a plurality of holes 328A and trenches 328B are formed in the second passivation layer 318. The holes 328A and trenches 328B can extend from the upper surface of the second passivation layer 318 and enter the second passivation layer 318. For example, refer to… Figure 4 and Figures 5A-5C Holes 328A can be arranged in a matrix within hole area 329A. In a plan view, each hole 328A can have a circular or near-circular shape. For example, at least one hole has a shape along a first direction (e.g., Figure 4 The first width W1 in the X direction, and the second width along the direction perpendicular to the first direction (e.g., Figure 4The second width W2 (in the Y direction). The groove 328B may have a longitudinal axis along the first direction and be repeated along the second direction, and / or have a longitudinal axis along the second direction and be repeated along the first direction. For example, as Figure 4 As shown, at least one of the trenches 328B has a third width W3 along the first direction and along the second direction (e.g., Figure 4 The fourth width W4 (in the Y direction) is greater than the third width W3. In some embodiments, the difference between the first width W1 and the second width W2 is less than the difference between the third width W3 and the fourth width W4, and the second spacing S2 between adjacent trenches 328B of the trench capacitor 320B is less than the first spacing S1 of the aperture capacitor 320A.

[0042] Return to reference Figure 3 The capacitor structure 320 may include portions extending into the aperture 328A and the trench 328B. For example, the capacitor structure 320 may include one or more aperture capacitors 320A, one or more trench capacitors 320B, one or more hybrid capacitors 320C, and one or more pseudo-MIM structures 320D. The aperture capacitor 320A may include a first conductive layer 322, an insulating layer 324, and a second conductive layer 326 disposed above the upper surface of the insulating layer 324 and extending into the aperture 328A. The trench capacitor 320B may include a first conductive layer 322, an insulating layer 324, and a second conductive layer 326 disposed above the upper surface of the insulating layer 324 and extending into the trench 328B. The hybrid capacitor 320C may include a first conductive layer 322, an insulating layer 324, and a second conductive layer 326 disposed above the upper surface of the insulating layer 324 and extending into the aperture 328A and the trench 328B. The pseudo-MIM structure 320D can be disposed above the second passivation layer 318. The pseudo-MIM structure 320D can be electrically isolated from other capacitors in the capacitor structure 320.

[0043] As described below, a hole 328A for accommodating a via capacitor 320A and a trench 328B for accommodating a trench capacitor 320B can be formed in the same process, wherein the etching rate for forming the trench 328B will be greater than the etching rate for forming the hole 328A due to pattern differences. After the etching process, the trench 328B can be etched to a greater depth than the hole 328A. For example, the hole 328A can have a depth D1 ranging from about 200 nm to about 400 nm, such as from about 100 nm to about 300 nm, although deeper or shallower holes can be used. The trench 328B can have a depth D2 ranging from about 500 μm to about 850 nm, such as from about 600 nm to about 700 nm, although deeper or shallower trenches can be used. The trench 328B and the hole 328A can have a vertical gap G1 of about 100 nm to about 300 nm, which is about 0.5 to about 1.5 times the depth D1 of the hole 328A.

[0044] In some embodiments, trench 328B has a bottom located below the second etch stop layer 316, while via 328A has a bottom located above the second etch stop layer 316. Therefore, trench capacitor 320B has a deeper depth than via capacitor 320A. In some embodiments, after the etching process, trench capacitor 320B extends through the second etch stop layer 316, while via capacitor 320A is located above the second etch stop layer 316. Figure 3 As shown, the first conductive layer 322 in the aperture capacitor 320A can be at a certain distance from the second etch stop layer 316, and the first conductive layer 322 in the trench capacitor 320B can be in contact with the second etch stop layer 316.

[0045] According to some embodiments, the first passivation structure 310 further includes a filler layer 332 located above the capacitor structure 320. The filler layer 332 may extend into and fill the remaining space of the hole 328A and / or trench 328B. The filler layer 332 also serves as an insulating layer to electrically isolate the capacitor structures 320 from each other. The filler layer 332 may have a material similar to the first passivation layer 314 or the second passivation layer 318. In embodiments, the filler layer 332 has a flat upper surface.

[0046] According to some embodiments, conductive through-holes 370 are formed in a first passivation layer 314, a second etch stop layer 316, and a second passivation layer 318. The conductive through-holes 370 may extend through the first etch stop layer 312 to electrically connect to the underlying conductive component 204 of the interconnect structure 250. The conductive through-holes 370 may include a low-resistivity main conductive material 372, such as Cu, W, Ru, Al, Au, Ag, or combinations thereof. The conductive through-holes 370 may also include a barrier layer 374 and / or a seed layer 376 located between the main conductive material 372 and the layer adjacent to the conductive through-holes 370. The barrier layer 374 may include metals such as Ti, Ta, Ru, or metal nitrides such as TiN, TaN, or combinations thereof. The barrier layer 374 may have a thickness ranging from about 1 nm to about 10 nm. If the thickness of the barrier layer 374 is less than about 1 nm, the barrier layer 374 may be insufficient to prevent the diffusion of the main conductive material 372. The seed layer 376 may include Cu, Ti, or a composite structure containing Cu and Ti layers.

[0047] A conductive through-hole 370 may also pass through one of the capacitor structures 320, such as the second conductive layer 326, the insulating layer 324, and the first conductive layer 322. Depending on design requirements, the conductive through-hole 370 may pass through a via capacitor 320A, a trench capacitor 320B, or a hybrid capacitor 320C to electrically connect to the via capacitor 320, the trench capacitor 320B, or the hybrid capacitor 320C. Alternatively, when the conductive through-hole 370 is designed not to be electrically connected to an active capacitor structure 320 (e.g., 320A, 320B, or 320C), the conductive through-hole 370 may pass through a pseudo-MIM structure 320D.

[0048] Figure 4 This is a schematic diagram according to some embodiments of a region in a unit area of ​​a semiconductor device 100 in a plan view for arranging capacitor structures. Figure 5A , Figure 5B ,and Figure 5C Various embodiments are shown respectively. Figure 4 Enlarged view of the aperture capacitor 320A, trench capacitor 320B, and hybrid capacitor 320C in the area shown. Figure 3 It is according to some embodiments along Figure 4The corresponding cross-sectional view of section A-A' shown. Semiconductor device 100 may include a via region 329A, in which a via 328A is formed and for arranging a via capacitor 320A. Semiconductor device 100 may also include a trench region 329B, in which a trench 328B is formed and for arranging a trench capacitor 320B. Semiconductor device 100 may also include a via region 329C for arranging a conductive through-hole 370 therein, and an isolation region 330 that may be filled with a filling layer 332.

[0049] It has been found that the aperture capacitor 320A can generate less stress compared to the trench capacitor 3200B. Therefore, in a semiconductor device, the aperture region 329A can occupy a major portion of the unit area of ​​the semiconductor device 100, and the trench region 329B can be located at or adjacent to the edge of the aperture region 329A. For example, in... Figure 4 In the semiconductor device 100 shown, the via region 329A can have a larger occupied area than the trench region 329B to reduce the stress in the semiconductor device 100, thereby reducing or preventing thin film cracking or delamination. On the other hand, compared to the width and spacing of the vias 328A in the via capacitor 320A, the trenches 328B in the trench capacitor 320B have a smaller width and spacing. Therefore, the trench region 329B for the trench capacitor 320B can be arranged at the edge of the via region 329A, for example, in the region near the via region 329C, or at the edge of a unit area of ​​the semiconductor device 100. In some embodiments, such as Figure 4 As shown, a trench region 329B is disposed between the through-hole region 329C and the hole region 329A. In some embodiments, the through-hole region 329C is surrounded by the trench region 329B, and / or further surrounded by the hole region 329A. In some embodiments, the through-hole region 329C is jointly surrounded by the trench region 329B and the isolation region 330.

[0050] The presence of the trench capacitor 320B (or hybrid capacitor 320C) increases the pattern density of the capacitor structure 320. Therefore, the capacitor density and wiring design flexibility of the capacitor structure 320 can be improved. Furthermore, the trench capacitor 320B can generate only limited or negligible stress, which may not lead to film cracking or delamination problems when its occupancy in a given area is limited.

[0051] Return to reference Figure 3According to some embodiments, a second passivation structure 350 is formed over the first passivation structure 310. The second passivation structure 350 may include a third passivation layer 352 formed over the filler layer 332, a fourth passivation layer 354 formed over the third passivation layer 352, and a dielectric layer 356 formed over the fourth passivation layer 354. In embodiments, the third passivation layer 352 may include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or combinations thereof. The fourth passivation layer 354 may include a material different from the third passivation layer 352, such as silicon oxide or glass, including silicate glass, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), or combinations thereof. The dielectric layer 356 may include silicon oxide, silicate glass, molding compounds, or organic materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), other suitable organic polymers, or combinations thereof. The third passivation layer 352 and the fourth passivation layer 354 may be conformal layers. The dielectric layer 356 has a thickness greater than that of the third passivation layer 352 and the fourth passivation layer 354, and has a flat upper surface. In some embodiments, one of the third passivation layer 352 and the fourth passivation layer 354 may be omitted to save costs.

[0052] In some embodiments, the conductive through-hole 370 protrudes above the first passivation structure 310 and extends into the second passivation structure 350, although the conductive through-hole 370 may have a top surface flush with the top surface of the second passivation layer 318. In embodiments where the conductive through-hole 370 extends into the second passivation structure 350, a third passivation layer 352 and a fourth passivation layer 354 are conformally located on the conductive through-hole 370. In some embodiments, the protrusion of the conductive through-hole 370 is a conductor, thus the conductive through-hole 370 can be used as a redistribution layer.

[0053] In some embodiments, a bonding structure 360 ​​is formed in dielectric layer 356. The bonding structure 360 ​​may also extend through a fourth passivation layer 354 and a third passivation layer 352 to physically and / or electrically connect to a conductive through-hole 370. The bonding structure 360 ​​may include Cu or other materials suitable for bonding (e.g., Ni, Au, Ag, Pd, Al, Sn). In some embodiments, the bonding structure 360 ​​may also include a barrier layer and / or seed layer similar to the conductive through-hole 370. Depending on the bonding requirements, the bonding structure 360 ​​may be a bump protruding above dielectric layer 356, or have a top surface flush with the top surface of dielectric layer 356. In embodiments, another dielectric layer (e.g., silicon oxide) may be additionally formed above dielectric layer 356 to provide bonding functionality, and the bonding structure 360 ​​may protrude above bonding layer 358 or have a top surface flush with bonding layer 358.

[0054] Figures 6 to 12 A cross-sectional view is shown of an intermediate stage in the manufacture of a semiconductor device 100 according to some embodiments. Figure 6 In this process, after forming the device layer 200 and interconnect structure 250 above the substrate 102, a first etch stop layer 312, a first passivation layer 314, a second etch stop layer 316, and a second passivation layer 318 are sequentially formed above the dielectric layer 202 and the conductive component 204. The first etch stop layer 312, the first passivation layer 314, the second etch stop layer 316, and the second passivation layer 318 can each be formed using a suitable deposition process, such as CVD, ALD, PVD, PECVD, or combinations thereof. In some embodiments, the first etch stop layer 312, the first passivation layer 314, the second etch stop layer 316, and the second passivation layer 318 can be formed in the same deposition machine or in the same chamber of the deposition machine to improve production throughput, as this saves transfer time between different chambers or deposition machines.

[0055] exist Figure 7 In some embodiments, an anisotropic etching process can be used to form holes 328A for accommodating via capacitor 320A and trenches 328B for accommodating trench capacitor 320B in the second passivation layer 318 and the layer below it. In one embodiment, a patterned mask is formed over the second passivation layer 318. The patterned mask can be a photoresist material, a hard mask (e.g., silicon oxide, TiN, TiO, etc.), or a combination thereof. An etching process can then be performed to transfer the pattern of the patterned mask to the underlying layer. The etching process can be an anisotropic etching process, such as reactive ion etching (RIE) or neutral beam etching (NBE). For example, the etching process can include chemical and physical ion bombardment comprising HBr, NF3, O2, SF6, or combinations thereof.

[0056] Although via 328A and trench 328B are formed in the same etching process, it has been found that the etching rate for forming trench 328B is faster than that for forming via 328A. In this embodiment, the etching rate for forming trench 328B is approximately three times faster than that for forming via 328A. Therefore, when via 328A is etched to the desired depth, trench 328B may penetrate the second passivation layer 318, the second etch stop layer 316, and the first passivation layer 314, thereby creating an undesirable short circuit between trench capacitor 320B and the conductive component 204 of interconnect structure 250. The presence of the second etch stop layer 316 can effectively reduce the etching rate for forming trench 328B, thereby preventing or reducing the frequency at which trench 328B penetrates the first passivation layer 314 and the first etch stop layer 312.

[0057] like Figure 7As shown, according to some embodiments, trench 328B extends through the second etch stop layer 316 and partially enters the first passivation layer 314. In other embodiments, trench 328B rests on the second etch stop layer 316 and does not extend through it. The presence of the second etch stop layer 316 can also reduce the gap G1 between the bottom of the hole 328A and the trench 328B. Therefore, for a given thickness of the second passivation layer 318 and the first passivation layer 314, the capacitance density of the capacitor structure 320 can be increased because, due to the reduced gap G1, the hole-type capacitor 320A, which occupies a relatively large area, can be designed to have a deeper depth. In some embodiments, during the etching process, the hole 328A may still be some distance from the second etch stop layer 316 when the trench 328B passes through it. After forming the hole 328A and the trench 328B, the patterned mask can be removed by, for example, an ashing process or an etching process.

[0058] exist Figure 8 In some embodiments, a first conductive layer 322, an insulating layer 324, and a second conductive layer 326 are formed in the top surface of the trench 328B, the hole 328A, and the second passivation layer 318. Specifically, the first conductive layer 322 is conformally formed in the hole 328A and the trench 328B above the upper surface of the second passivation layer 318. The first conductive layer 322 can be formed by PVD, CVD, or ALD. An insulating layer 324 is conformally formed above the first conductive layer 322. In some embodiments, the insulating layer 324 is formed by CVD or ALD. Next, the second conductive layer 326 is conformally formed above the insulating layer 324. The second conductive layer 326 can be formed by PVD, CVD, or ALD. In some embodiments, since the trench 328B can have a small width, the trench 328B can be sealed by the second conductive layer 326 or the insulating layer 324, while the hole 328A is not sealed. Therefore, the seam or air gap is formed in the groove 328B, but not in the hole 328A. In some embodiments, the hole 328A may also be sealed, for example, through the second conductive layer 326, or when more layers are used in the capacitor structure 320.

[0059] After the formation of the first conductive layer 322, the insulating layer 324, and the second conductive layer 326, an anisotropic etching process can be performed to etch the first conductive layer 322, the insulating layer 324, and the second conductive layer 326 to define the boundary of each of the capacitor structures 320. Although, as shown above, a single etching process can be used to define the boundary of the capacitor structure 320, the pattern of each layer 322, 324, 326 of the capacitor structure 320 can be defined individually, for example, shortly after its deposition and before the formation of the next layer, by one or more etching processes to individually pattern each layer 322, 324, 326.

[0060] exist Figure 9 In some embodiments, after forming the capacitor structure 320, a filler layer 332 is formed to cover the capacitor structure 320. In embodiments where the trench 328B and / or the via 328A are not sealed, the filler layer 332 may extend into the trench 328B and / or the via 328A to fill the remaining space in the trench 328B and / or the via 328A. The filler layer 332 can be formed by a suitable deposition process, such as CVD, PECVD, LPCVD, etc., and the upper surface of the filler layer 332 can be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0061] exist Figure 10 In some embodiments, conductive through-holes 370 are formed in the first etch stop layer 312, the first passivation layer 314, the second etch stop layer 316, the second passivation layer 318, the capacitor structure 320, and the fill layer 332. The conductive through-holes 370 can be electrically connected to the conductive components 204 of the interconnect structure. The conductive through-holes 370 can be formed by one or more etching processes and the deposition of layers in the openings. The etching processes can include anisotropic processes, such as RIE or NBE. In some embodiments, a mask, such as a hard mask layer, can be disposed above the fill layer 332 before performing the etching process. The hard mask can include silicon oxide, titanium nitride, aluminum oxide, titanium dioxide, or combinations thereof.

[0062] After forming the opening for the conductive through-hole 370, a barrier layer 374, a seed layer 376, and a main conductive material 372 are subsequently formed within the opening. The barrier layer 374 and seed layer 376 are conformally deposited within the opening and above the upper surface of the filling layer 332, for example by ALD, CVD, or PVD. Next, a photoresist layer is formed over the barrier layer 374 or seed layer 376 and patterned to expose portions of the seed layer 376 and its adjacent portions within the opening. In some embodiments, plating (e.g., electroplating or electroless plating) or other suitable deposition processes are performed to form the main conductive material 372 over the exposed portion of the seed layer 376. The deposited conductive through-hole 370 may include protrusions above the upper surface of the filling layer 332. After forming the conductive through-hole 370, the photoresist layer is removed by a suitable process, such as wet stripping or ashing, and portions of the seed layer 376 and barrier layer 374 are also removed by a suitable wet etching process. Figure 3 As shown, the protrusion of the conductive through-hole 370 can be retained and covered by the second passivation structure 350. Alternatively, depending on the design requirements of the bonding structure 360, the protrusion of the conductive through-hole 370 can be removed by a planarization process such as CMP.

[0063] exist Figure 11 In some embodiments, a second passivation structure 350 is formed over the first passivation structure 310 and the conductive through-hole 370. The formation of the second passivation structure 350 may include forming a third passivation layer 352 over the upper surface of the filler layer 332 and the conductive through-hole 370, and optionally forming a fourth passivation layer 354 over the third passivation layer 352. The third passivation layer 352 and the fourth passivation layer 354 may be conformally deposited, for example, by CVD, PVD, ALD, or a combination thereof. Next, a dielectric layer 356 is formed over the third passivation layer 352 or the fourth passivation layer 354 (if present). The dielectric layer 356 may be formed by suitable deposition processes, such as CVD, PECVD, LPCVD, MOCVD, spin coating, or combinations thereof. After depositing the dielectric layer 356, a planarization process such as CMP or mechanical polishing may be performed. In some embodiments where a bonding layer 358 is required, the bonding layer 358 is deposited above the upper surface of the dielectric layer 356, for example by CVD, PECVD, LPCVD, ALD, PVD, etc.

[0064] exist Figure 12In some embodiments, a bonding structure 360 ​​is formed in dielectric layer 356 (and bonding layer 358, if present). Forming the bonding structure 360 ​​may include forming an opening through dielectric layer 356, fourth passivation layer 354, and third passivation layer 352 to expose a conductive through-hole 370 by one or more etching processes, and then placing or depositing a suitable conductive material in the opening. In some embodiments, a planarization process is performed to planarize the bonding structure 360 ​​so that the upper surface of the bonding structure 360 ​​has an upper surface flush with the upper surface of dielectric layer 356 or bonding layer 358, which may facilitate a direct bonding process.

[0065] Figure 13 A cross-sectional view of a semiconductor device 400 according to some embodiments is shown. Semiconductor device 400 is similar to semiconductor device 100, wherein the same reference numerals denote the same elements. In semiconductor device 400, a second etch stop layer 416 can be used as an etch stop for both via 328A and trench 328B. Figure 13 In this process, the second passivation layer 418 may have a thickness T3, which is substantially equal to the desired depth D1 of the via capacitor 320A, although the via capacitor 320A may be larger or shallower than the thickness T3 during fabrication. The first passivation layer 414 may have a thickness T4, which is greater than the thickness T3 of the second passivation layer 418, to achieve the goal that the thickness T3 is substantially equal to the desired depth D1 of the via capacitor 320A. In some embodiments, the thickness T4 of the first passivation layer 414 is at least twice as large as the thickness T3 of the second passivation layer 418. Since the second etch stop layer 416 can effectively reduce the etch rate of forming the trench 328B and provides a sufficiently thick first passivation layer 414, the trench 328B may not penetrate the first passivation layer 404. In some embodiments, the first passivation layer 414, the second etch stop layer 416, and the second passivation layer 418 have the same material as the first passivation layer 314, the second etch stop layer 316, and the second passivation layer 318, respectively, and can be formed by a similar method.

[0066] Figure 14A cross-sectional view of a semiconductor device 500 according to some embodiments is shown. Semiconductor device 500 is similar to semiconductor device 400, wherein the same reference numerals denote the same elements. In semiconductor device 500, a second etch stop layer 416 can be used as an etch stop to reduce the etch rate of forming vias 328A and trenches 328B. In some embodiments, a third etch stop layer 566 is disposed within a first passivation layer 314 to provide additional protection against trenches 328B penetrating the first passivation layer 314. The third etch stop layer 566 can successfully stop the etching of trenches 328B and allows trenches 328B to fall onto the third etch stop layer 566. Alternatively, trenches 328B (or trench capacitors 320B) can still penetrate the third etch stop layer 566, but at a distance from the first etch stop layer 312. The third etch stop layer 566 can be or comprise the same material and thickness as the second etch stop layer 416 and can be formed by a similar method.

[0067] Figure 15 A cross-sectional view of a semiconductor device 600 according to some embodiments is shown. Semiconductor device 600 is similar to semiconductor devices 100, 400, or 500, wherein the same reference numerals denote the same elements. In semiconductor device 600, a second etch stop layer 616 may have an opening 616A to allow a conductive through-hole 370 to pass through. The opening 616A of the second etch stop layer is filled with a second passivation layer 318. Thus, the second etch stop layer 616 can be separated from the conductive through-hole 370 by the second passivation layer 318. The second etch stop layer 616 may include a different material than the first passivation layer 314 to have a different etch selectivity compared to the first passivation layer 314. For example, the second etch stop layer 616 may include either a high-resistivity material, such as silicon carbonitride, silicon carbide, silicon oxycarbonitride, undoped silicon, undoped germanium, undoped silicon germanium, silicon nitride, hafnium oxide, zirconium oxide, or a structure comprising a stack of oxide-nitride-oxide layers (e.g., SiO-SiN-SiO). The second etch stop layer 616 can be formed by a method similar to that used for the second etch stop layer 316.

[0068] Figure 16A cross-sectional view of a semiconductor device 700 according to some embodiments is shown. Semiconductor device 700 is similar to semiconductor devices 100, 400, 500, or 600, wherein the same reference numerals denote the same elements. In semiconductor device 700, a second etch stop layer 716 is or comprises a low-resistance material, such as a metallic material or a metal nitride material. In some embodiments, the low-resistance material includes TiN, TaN, W, Ta, Ti, or combinations thereof. The second etch stop layer 716 may have an opening 716A to allow a conductive through-hole 370 to pass through. A second passivation layer 318 may fill the opening 716A. Thus, the second etch stop layer 716 can be separated from the conductive through-hole 370 by the second passivation layer 318. Additionally, besides the opening 716A, the second etch stop layer 716 includes the same pattern as the first conductive layer 322 used to define the boundary of capacitor structure 320. Since the second etch stop layer 716 is in contact with the first conductive layer 322 of the capacitor structure 320, having a pattern corresponding to the first conductive layer 322 can prevent unwanted short circuits between the capacitor structures 320. For example, as Figure 14 As shown, the second etch stop layer 716 includes not only an opening 716A electrically isolated from the conductive through-hole 370, but also an opening 716A for electrically isolating the capacitor structures 320 from each other (e.g., by...). Figure 14 The aperture 716B of the hole capacitor 320A and the trench capacitor 320B shown is electrically isolated, wherein the second passivation layer 318 fills the aperture 716A and the aperture 716B.

[0069] Figure 17A cross-sectional view of a semiconductor device 800 according to some embodiments is shown. Semiconductor device 800 is similar to semiconductor devices 100, 400, 500, 600, or 700, wherein the same reference numerals denote the same elements. In semiconductor device 800, a second etch stop layer 816 is located only below trench capacitor 320B. That is, the second etch stop layer 816 can be used solely as an etch stop layer for forming trench 328B. Thus, in some embodiments, the aperture 328A is etched to a deeper depth D3 (e.g., about 400 nm to about 600 nm) below the second etch stop layer 816, and the etch rate for forming aperture 328A will be affected by the second etch stop layer 816, thereby reducing the gap G2 between aperture capacitor 320A and trench capacitor 320B. The gap G2 can be in the range of about 50 nm to about 150 nm, which is smaller than the depth D3 of aperture 828A. In some embodiments, the second etch stop layer 816 comprises a high-resistivity material, such as silicon carbonitride, silicon carbide, silicon oxycarbonitride, undoped silicon, undoped germanium, undoped silicon germanium, silicon nitride, hafnium oxide, zirconium oxide, or a stacked structure comprising oxide-nitride-oxide layers (e.g., SiO-SiN-SiO). Alternatively, the second etch stop layer 816 may be or comprise a low-resistivity material, such as a metallic material or a metal nitride material. Low-resistivity materials may include TiN, TaN, W, Ta, Ti, or combinations thereof.

[0070] Figure 18 A cross-sectional view of a semiconductor package 900 according to some embodiments is shown. In the semiconductor package 900, a semiconductor device 100 is bonded to another semiconductor device 100 via direct bonding. Figure 18 In the semiconductor device 100, the semiconductor device 100 may include a bonding structure 360 ​​having a top surface flush with the bonding layer 358, and the semiconductor device 100 may also include a metal bonding structure having a top surface flush with the bonding layer 358. The bonding structure 360 ​​in the semiconductor device 100 can be bonded by direct contact with a metal-to-metal bond. The bonding layer 358 of the semiconductor device 100 can be bonded by a covalent bond, such as an oxide-to-oxide bond. Although two semiconductor devices 100 are used as an example to illustrate a semiconductor package 910, either of the semiconductor devices 100 can be replaced by semiconductor devices 400, 500, 600, 700, 800, or other suitable semiconductor devices, and the capacitor structure 320 may or may not be formed in the passivation structure 300. Although Figure 1 The device layer 200 is not specifically shown, but a through-substrate via 984 through the substrate 102 to electrically connect the device layer 200 to an external component can be implemented in the semiconductor device 100 or other suitable semiconductor device.

[0071] Figure 19 A cross-sectional view of a semiconductor device 1000 according to some embodiments is shown. In the semiconductor device 1000, a first passivation structure 1350 and a capacitor structure 1320 may be disposed on the back side of the device layer 200 (or the back side of the substrate 102). The capacitor structure 1320 may be similar to the capacitor structure 320 and may be formed by a similar method. The first passivation structure 1350 may be similar to the first passivation structure 310 and may be formed by a similar method. For example, the first passivation structure 1350 and the capacitor structure 1320 may be vertically reversed compared to the first passivation structure 310 and the capacitor structure 320.

[0072] According to some embodiments, a back-side interconnect structure 1250 may be disposed below the first passivation structure 1350 and the capacitor structure 1320 to provide power and / or additional signal connections to the device layer 200. A conductive through-hole 1270 may pass through the back-side interconnect structure 1250, the capacitor structure 1320, and the first passivation structure 1350 to electrically connect to components in the device layer 200. The back-side interconnect structure 1250 may include conductive components disposed in a dielectric layer, similar to interconnect structure 250. The conductive through-hole 1270 passes through the first passivation structure 1350 and is physically and / or electrically connected to the source / drain regions 124 in the device layer 200. Additionally, the back-side interconnect structure 1250 may be formed on the back side of the device layer 200 to provide power and / or additional signal connections to the device layer 200. The back-side interconnect structure 1250 may include a power rail 1260, which is a wire electrically connecting the source / drain regions 124 in the device layer 200 to a reference voltage, power supply voltage, etc. Advantages can be achieved by placing the power rails on the back side of the semiconductor device 100, rather than on the front side. For example, the gate density in device layer 200 and / or the interconnect density in interconnect structure 250 can be increased. Additionally, the back side of the semiconductor device 100 can accommodate wider power rails, thereby reducing resistance and improving the efficiency of power delivery to the semiconductor device 100. For example, the width of power rail 1260 can be at least twice the width of the first layer of conductor 206 in interconnect structure 250. Placing the capacitor structure 1320 on the back side of device layer 200 also provides advantages. The capacitor structure 1320 may be electrically connected to the power rail 1260 and / or the back through-hole 1270, which are physically and / or electrically connected to the source / drain region 124, to regulate the large current supplied from the conductive through-hole 1270 and / or the power rail 1260 before the large current is delivered to the source / drain region 124, thereby protecting the devices (e.g., the source / drain region 124) in the device layer 200 from damage by large pulses.

[0073] According to some embodiments, a semiconductor device including a capacitor structure is provided. The semiconductor device may include a via capacitor and a trench capacitor formed in a passivation structure above an interconnect structure. The via capacitor includes a layer extending into the via, and the trench capacitor includes a layer extending into the trench. The via capacitor can generate less stress in the semiconductor device, and the trench capacitor can be disposed in a region with a smaller size. The passivation structure may include an etch stop layer at least located at the location where a trench is to be formed. The etch stop layer may partially or completely resist the etch process used to form the trench. Therefore, although the etch process may have a higher etch rate when forming a trench than when forming a via, the trench may be located away from the underlying interconnect structure without damaging the underlying interconnect structure when the via reaches its desired depth. Therefore, the semiconductor device can simultaneously include and form both a via capacitor and a trench capacitor, resulting in improved manufacturing yield. Additionally, a semiconductor package and a semiconductor device having a back-side interconnect structure including a capacitor structure are also provided.

[0074] In an embodiment, a semiconductor device is provided. The semiconductor device includes: an interconnect structure disposed above a substrate, wherein the interconnect structure includes conductive components disposed in a dielectric layer; a first passivation layer disposed above the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; an etch stop layer disposed above the first passivation layer; a second passivation layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from the upper surface of the second passivation layer into the second passivation layer, wherein at least one of the holes includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and wherein at least one of the trenches includes a third width along the first direction that is less than the first width and a third width along the second direction that is greater than the first width. A second width and a fourth width, wherein the trench overlaps with the etch stop layer in a plan view; a first capacitor structure, the first capacitor structure including a first conductive layer, a first insulating layer, and a second conductive layer, the first conductive layer, the first insulating layer and the second conductive layer being disposed above a second passivation layer and extending into a via, wherein the second conductive layer is located above the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer above the upper surface of the second passivation layer has a curved top surface; and a second capacitor structure, the second capacitor structure including a third conductive layer, a second insulating layer and a fourth conductive layer, the third conductive layer, the second insulating layer and the fourth conductive layer being disposed above the second passivation layer and extending into a trench. In an embodiment, the bottom of the first conductive layer is located above the etch stop layer, and the bottom of the third conductive layer is located below the etch stop layer. In an embodiment, the third conductive layer is in contact with the etch stop layer, and the first conductive layer is separated from the etch stop layer by the second passivation layer. In an embodiment, the semiconductor device further includes a conductive through-hole passing through the second passivation layer, the first passivation layer, and one of the first capacitor structure or the second capacitor structure, for electrically connecting to conductive components of an interconnect structure. In one embodiment, a conductive through-hole is laterally surrounded by an etch stop layer, and a lateral gap exists between the conductive through-hole and the etch stop layer, wherein the lateral gap is filled by a second passivation layer. In another embodiment, the etch stop layer comprises a metallic material or a conductive metal nitride material. In yet another embodiment, the hole does not overlap with the etch stop layer in a planar view.

[0075] In an embodiment, a semiconductor device is provided. The semiconductor device includes: a device disposed above a substrate, wherein the device includes source / drain components, and each of the source / drain components includes multiple layers containing the same semiconductor material in different amounts; a first dielectric layer disposed above the device; an etch stop layer disposed above the first dielectric layer; a second dielectric layer disposed above the etch stop layer; a plurality of holes and a plurality of trenches extending from the upper surface of the second dielectric layer and into the second dielectric layer, wherein the holes are disposed in a first region, and the trenches are disposed in a second region, wherein at least one of the holes includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and at least one of the trenches includes a third width along the first direction and a fourth width along the second direction, wherein the difference between the first width and the second width is less than the difference between the third width and the fourth width; and a capacitor structure including a first conductive layer, an insulating layer, and a second conductive layer, the first conductive layer, the insulating layer, and the second conductive layer being disposed above the upper surface of the second dielectric layer and extending into the holes and trenches, wherein a first occupied area of ​​the first region is greater than a second occupied area of ​​the second region. In one embodiment, the bottom of the trench is lower than the bottom of the via. In another embodiment, the semiconductor device further includes a conductive through-hole through the capacitor structure, with a second region between the conductive through-hole and the first region. In another embodiment, the conductive through-hole is laterally surrounded by the first and second regions. In another embodiment, the trench has a bottom lower than the bottom of the etch stop layer, and the via has a bottom higher than the bottom of the etch stop layer. In another embodiment, the second dielectric layer has a thickness less than the thickness of the first dielectric layer. In another embodiment, the semiconductor device further includes: an insulating fill layer disposed over the capacitor structure and the second dielectric layer; a passivation structure disposed over the insulating fill layer, wherein the conductive through-hole passes through the insulating layer and includes a protrusion extending in the passivation structure; and a conductive bonding structure disposed in the passivation structure, wherein the conductive bonding structure is exposed from the passivation structure and electrically connected to the conductive through-hole.

[0076] In an embodiment, a method for forming a semiconductor device is provided, the method comprising: forming an interconnect structure over a substrate, wherein the interconnect structure includes conductive components disposed in a dielectric layer; forming a first passivation layer over the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; forming an etch stop layer over the first passivation layer; forming a second passivation layer over the etch stop layer; and performing an etching process to form a plurality of holes and a plurality of trenches in the second passivation layer, wherein at least one of the holes includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and at least one of the trenches includes a second width along the first direction less than the first width. The second capacitor structure comprises a third conductive layer, a first insulating layer, and a second conductive layer, extending into a hole along a second direction and greater than the second width; and a first capacitor structure and a second capacitor structure are formed over a second passivation layer, wherein the first capacitor structure includes a first conductive layer, a first insulating layer, and a second conductive layer, the first conductive layer, the first insulating layer, and the second conductive layer extending into the hole, wherein the second conductive layer is disposed over the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer over the second passivation layer has a curved top surface, wherein the second capacitor structure includes a third conductive layer, a second insulating layer, and a fourth conductive layer, the third conductive layer, the second insulating layer, and the fourth conductive layer extending into a trench, wherein the trench overlaps with an etch stop layer in a planar view. In an embodiment, the etching process has a first etch rate when forming the hole and a second etch rate when forming the trench, wherein the second etch rate is greater than the first etch rate. In an embodiment, during the etching process, the hole is spaced apart from the etch stop layer by a distance when the trench passes through the etch stop layer. In an embodiment, forming the etch stop layer includes: depositing a layer over the first passivation layer; and patterning the layer. In one embodiment, patterning the layer includes removing a first portion of the layer that overlaps with the holes in the planar view. In another embodiment, the etch stop layer comprises a metallic material or a conductive metal nitride material.

[0077] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: An interconnect structure is disposed above a substrate, wherein the interconnect structure includes conductive components disposed in a dielectric layer; A first passivation layer is disposed above the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; An etch stop layer is disposed above the first passivation layer; A second passivation layer is disposed above the etch stop layer; Multiple holes and multiple trenches extend from the upper surface of the second passivation layer into the second passivation layer, wherein at least one of the holes includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and wherein at least one of the trenches includes a third width along the first direction that is less than the first width and a fourth width along the second direction that is greater than the second width, wherein the trenches overlap with the etch stop layer in a planar view; A first capacitor structure includes a first conductive layer, a first insulating layer, and a second conductive layer. The first conductive layer, the first insulating layer, and the second conductive layer are disposed above a second passivation layer and extend into the hole. The second conductive layer is located above the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer above the upper surface of the second passivation layer has a curved top surface. The second capacitor structure includes a third conductive layer, a second insulating layer, and a fourth conductive layer, which are disposed above the second passivation layer and extend into the trench.

2. The semiconductor device according to claim 1, wherein, The bottom of the first conductive layer is located above the etch stop layer, and the bottom of the third conductive layer is located below the etch stop layer.

3. The semiconductor device according to claim 1, wherein, The third conductive layer is in contact with the etch stop layer, and the first conductive layer is separated from the etch stop layer by the second passivation layer.

4. The semiconductor device of claim 1 further includes a conductive through-hole, the conductive through-hole passing through the second passivation layer, the first passivation layer, and through one of the first capacitor structure or the second capacitor structure, to be electrically connected to the conductive component of the interconnect structure.

5. The semiconductor device according to claim 1, wherein, The conductive through-hole is laterally surrounded by the etch stop layer, and there is a lateral gap between the conductive through-hole and the etch stop layer, wherein the lateral gap is filled by the second passivation layer.

6. The semiconductor device according to claim 5, wherein, The etch stop layer comprises a metallic material or a conductive metal nitride material.

7. The semiconductor device according to claim 1, wherein, The hole does not overlap with the etch stop layer in the plan view.

8. A semiconductor device, comprising: A device disposed above a substrate, wherein the device includes source / drain components, and each of the source / drain components includes multiple layers containing different amounts of the same semiconductor material; A first dielectric layer is disposed above the device; An etch stop layer is disposed above the first dielectric layer; A second dielectric layer is disposed above the etch stop layer; A plurality of holes and a plurality of trenches extend from the upper surface of the second dielectric layer into the second dielectric layer, wherein the holes are disposed in a first region, and the trenches are disposed in a second region, wherein at least one of the holes includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and at least one of the trenches includes a third width along the first direction and a fourth width along the second direction, wherein the difference between the first width and the second width is less than the difference between the third width and the fourth width; and A capacitor structure includes a first conductive layer, an insulating layer, and a second conductive layer. The first conductive layer, the insulating layer, and the second conductive layer are disposed above the upper surface of the second dielectric layer and extend into the hole and the trench, wherein a first occupied area of ​​the first region is greater than a second occupied area of ​​the second region.

9. The semiconductor device according to claim 8, wherein, The groove has a bottom that is lower than the bottom of the hole.

10. A method for forming a semiconductor device, the method comprising: An interconnect structure is formed above a substrate, wherein the interconnect structure includes conductive components disposed in a dielectric layer; A first passivation layer is formed above the interconnect structure, wherein the dielectric constant of the first passivation layer is greater than the dielectric constant of the dielectric layer; An etch stop layer is formed above the first passivation layer; A second passivation layer is formed above the etch stop layer; An etching process is performed to form a plurality of holes and a plurality of trenches in the second passivation layer, wherein at least one of the holes includes a first width along a first direction and a second width along a second direction perpendicular to the first direction, and at least one of the trenches includes a third width along the first direction that is smaller than the first width and a fourth width along the second direction that is larger than the second width; and A first capacitor structure and a second capacitor structure are formed above the second passivation layer. The first capacitor structure includes a first conductive layer, a first insulating layer, and a second conductive layer. The first conductive layer, the first insulating layer, and the second conductive layer extend into the hole. The second conductive layer is disposed above the first conductive layer and the first insulating layer, and at least a portion of the second conductive layer above the second passivation layer has a curved top surface. The second capacitor structure includes a third conductive layer, a second insulating layer, and a fourth conductive layer. The third conductive layer, the second insulating layer, and the fourth conductive layer extend into the trench. The trench overlaps with the etch stop layer in a plan view.

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