Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention provides a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device includes a plurality of source contact layers, a plurality of gate contact layers, a connection portion, and a gate contact hole. The source contact layers are arranged at intervals in the first direction, the gate contact layers are arranged at intervals in the first direction, and each gate contact layer is located between the adjacent source contact layers; the plurality of gate contact layers extend along a second direction to form extension parts; the connecting part is arranged on one side, deviating from the plurality of source contact layers, of the extension part and is connected with the plurality of extension parts; the grid contact hole is formed in the connecting part, and the aperture of the grid contact hole is greater than a preset value; the first direction intersects the second direction. The manufacturing process of the semiconductor device can be simplified, and the production cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] In the fabrication process of silicon carbide (SiC) power semiconductor devices, especially in the fabrication process of junction field-effect transistors (JFETs), metal interconnect and contact hole filling technologies are key factors that determine the performance, reliability, and manufacturing cost of semiconductor devices.

[0003] Given the small size of the gate contact hole, tungsten chemical vapor deposition (W-plug) is commonly used in related technologies to fabricate it, thereby improving the performance of the gate contact plug. However, the W-plug process is relatively complex, increasing the manufacturing cost of the gate contact plug. Summary of the Invention

[0004] In view of the above problems, this application provides a semiconductor device and its preparation method, as well as an electronic device, which can simplify the preparation process of semiconductor devices and reduce production costs.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a semiconductor device, comprising:

[0007] Multiple source contact layers, wherein the multiple source contact layers are spaced apart along a first direction;

[0008] A plurality of gate contact layers are arranged at intervals along a first direction, and each gate contact layer is located between adjacent source contact layers; each of the plurality of gate contact layers extends along a second direction to form an extension portion;

[0009] A connecting portion is disposed on the side of the extension portion opposite to the plurality of source contact layers and is connected to the plurality of extension portions;

[0010] A gate contact hole is disposed on the connection portion, and the diameter of the gate contact hole is greater than a preset value; wherein the first direction intersects the second direction.

[0011] In one possible implementation, the extension includes a connection terminal connected to the corresponding gate contact layer;

[0012] In the first direction, the width of the connection end is greater than the width of the gate contact layer, and there is a gap between the connection end and the adjacent source contact layer.

[0013] In one possible implementation, in the first direction, at least one surface of the extension is connected to the connecting portion via an arcuate transition.

[0014] In one possible implementation, the cross-section is parallel to the source contact layer, and the cross-sectional shape of the connection portion is square.

[0015] In one possible implementation, a gate contact plug is disposed within the gate contact hole, and the gate contact plug is made of aluminum.

[0016] In one possible implementation, the semiconductor device includes a substrate, and the plurality of source contact layers, the plurality of gate contact layers, and the connection portion are all disposed on the substrate;

[0017] Along a direction perpendicular to the substrate and away from the source contact layer, the aperture of the gate contact hole tends to increase.

[0018] In one possible implementation, the substrate further comprises a plurality of gate regions and a plurality of source regions, the plurality of gate regions and the plurality of source regions being spaced apart and alternately arranged along a first direction;

[0019] The plurality of gate regions correspond to the plurality of gate contact layers, and the plurality of source regions correspond to the plurality of source contact layers.

[0020] Secondly, an embodiment of this application provides a method for fabricating a semiconductor device, comprising: providing a substrate;

[0021] A dielectric layer is formed on the substrate, and the dielectric layer is patterned to form a filling region within the dielectric layer. The filling region includes a plurality of first filling regions, a plurality of second filling regions, and a third filling region. The plurality of first filling regions and the plurality of second filling regions are spaced apart and alternately arranged along a first direction. Each of the plurality of second filling regions protrudes along a second direction to form an extension region. The third filling region is located on one side of the plurality of first filling regions in the second direction and communicates with the plurality of extension regions.

[0022] A source contact layer and a gate contact layer are formed, wherein the gate contact layer is located within the extension region to form an extension portion, and the gate contact layer is located within the third filling region to form a connection portion;

[0023] A gate contact hole is formed within the connection portion.

[0024] In one possible implementation, a gate contact plug is formed within the gate contact hole using an aluminum filling process.

[0025] Thirdly, embodiments of this application provide an electronic device including the semiconductor device described in the first aspect.

[0026] In the semiconductor devices and fabrication methods and electronic devices provided in this application, by extending the gate contact layer to form a larger connection portion, the size of the gate contact hole can be increased. For example, the diameter of the gate contact hole can be larger than a preset value. This can overcome the diameter limitations of gate contact holes in related technologies, thereby enabling a process migration from the high-cost, high-complexity W-plug process to the low-cost, low-complexity Al-plug process, thus simplifying the fabrication process, reducing fabrication costs, and improving the performance of semiconductor devices.

[0027] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor devices and their preparation methods and electronic devices provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this application Figure 1 ;

[0030] Figure 2 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this application Figure 2 ;

[0031] Figure 3 A process flow diagram of the method for fabricating a semiconductor device provided in the embodiments of this application;

[0032] Figure 4 A schematic diagram of a substrate provided in the method for fabricating a semiconductor device according to an embodiment of this application;

[0033] Figure 5 This is a schematic diagram illustrating the formation of a dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0034] Figure 6This is a schematic diagram of the patterned dielectric layer in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0035] Figure 7 A top view of the patterned dielectric layer in the method for fabricating a semiconductor device provided in the embodiments of this application;

[0036] Figure 8 This is a schematic diagram illustrating the formation of a precursor layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0037] Figure 9 This is a schematic diagram illustrating the formation of the source contact layer and the gate contact layer in the fabrication method of the semiconductor device provided in the embodiments of this application;

[0038] Figure 10 This is a schematic diagram of removing the remaining precursor layer in the method for fabricating a semiconductor device provided in the embodiments of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100: Source contact layer; 200: Gate contact layer; 210: Extension; 300: Connection; 400: Gate contact hole; 500: Gate contact plug; 600: Substrate; 700: Dielectric layer; 710: First filling region; 720: Second filling region; 730: Extension region; 740: Third filling region; 800: Precursor layer. Detailed Implementation

[0041] As described in the background art, related technologies require patterning the gate contact layer to form gate contact holes, facilitating the formation of gate contact plugs within these holes. Due to the small distance between adjacent source contact layers, the size of the formed gate contact hole is limited by this distance; for example, the gate contact hole size is approximately 0.4 μm. If an aluminum reverse-patterning plugging process (Al-plug) is used to form the gate contact plug within the gate contact hole, gaps or holes may form within the plug, affecting the performance of the semiconductor device. Therefore, related technologies employ tungsten chemical vapor deposition and chemical mechanical polishing plugging (W-plug) to fabricate the gate contact plug. This increases the number of fabrication steps, significantly prolonging the semiconductor device's process cycle time, reducing production efficiency, and increasing manufacturing costs.

[0042] To address the aforementioned technical problems, embodiments of this application provide a semiconductor device and its fabrication method, as well as an electronic device. By extending the gate contact layer to form a larger connection portion, the size of the gate contact hole can be increased; for example, the diameter of the gate contact hole can be larger than a preset value. This overcomes the diameter limitations of gate contact holes in related technologies, thereby enabling a process migration from the high-cost, high-complexity W-plug process to the low-cost, low-complexity Al-plug process, thus simplifying the fabrication process, reducing fabrication costs, and improving the performance of the semiconductor device.

[0043] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] Please refer to Figure 1 and Figure 2 This application provides a semiconductor device, which can be a silicon carbide junction field-effect transistor (JFET).

[0045] Semiconductor devices include:

[0046] Multiple source contact layers 100 are arranged at intervals along a first direction. The source contact layers 100 are used to connect the source region and the source contact plug of a semiconductor device to reduce the contact resistance between the source region and the source contact plug. For example, the source contact layers 100 are typically made of nickel silicide (NiSi).

[0047] It should be noted that the source region is typically made of heavily doped N-type silicon carbide or heavily doped P-type silicon carbide. The source contact plug, on the other hand, is typically made of metal, such as tungsten or aluminum. Due to the difference in their work functions, a potential barrier is formed, which in turn affects the electrical performance of the semiconductor device. Therefore, this embodiment uses a source contact layer 100 between the source region and the source contact plug to reduce the contact resistance between the two, thereby forming a low-resistance, stable, and reliable electrical connection channel, and thus reducing the conduction loss of the semiconductor device.

[0048] The semiconductor device also includes a plurality of gate contact layers 200, which are spaced apart along a first direction, and each gate contact layer 200 is located between adjacent source contact layers 100. Alternatively, the plurality of gate contact layers 200 and the plurality of source contact layers 100 are spaced apart and alternately arranged along the first direction. It should be noted that the purpose of the gate contact layers 200 is the same as that of the source contact layers 100, and will not be elaborated further in this embodiment.

[0049] Each of the plurality of gate contact layers 200 extends along a second direction to form an extension 210. That is, each gate contact layer 200 extends along the second direction such that the extension 210 protrudes beyond the source contact layer 100 in the second direction. The second direction intersects the first direction. Figure 1 Taking the directions shown as an example, the first direction is Figure 1 The middle X direction, the second direction is Figure 1 In the Y direction. The semiconductor device also includes a connection portion 300, which is disposed on the side of the extension portion 210 opposite to the plurality of source contact layers 100 and is connected to the plurality of extension portions 210.

[0050] The semiconductor device also includes a gate contact hole 400, which is disposed on the connection portion 300, and the aperture of the gate contact hole 400 is larger than a preset value. The preset value can be 1 μm. Given that the connection portion 300 is relatively large in this embodiment, the gate contact hole 400 can be disposed on the connection portion, and its size can be increased, for example, by making its aperture larger than the preset value. This overcomes the aperture limitation of the gate contact hole 400 in related technologies, eliminating reliance on the distance between adjacent source contact layers 100. This allows for a process migration from the high-cost, high-complexity W-plug process to the low-cost, low-complexity aluminum plug process (Al-plug process), thereby simplifying the fabrication process, reducing fabrication costs, and improving the performance of the semiconductor device.

[0051] In one possible implementation, the extension 210 includes a connection terminal connected to the corresponding gate contact layer 200. Alternatively, the connection terminal is the connection portion between the extension 210 and the gate contact layer 200.

[0052] In the first direction, the width of the connection end is greater than the width of the gate contact layer 200, and there is a gap between the connection end and the adjacent source contact layer 100, so as to avoid the gate contact layer 200 from contacting the source contact layer 100, thereby preventing the gate contact layer 200 and the source contact layer 100 from short-circuiting and improving the yield of the semiconductor device.

[0053] At the same time, the width of the connection end is greater than the width of the gate contact layer 200, which can better regulate the electric field near the gate by using the wider extension 210, so that the electric field is more uniformly distributed in the gate region, avoids the electric field being too concentrated, and ensures the stability of the semiconductor device.

[0054] It should be noted that the connection between the extension 210 and the connecting part 300 can be a right-angle connection or an arc-shaped connection.

[0055] In one possible implementation, in the first direction, at least one surface of the extension 210 is connected to the connecting portion 300 via an arcuate transition. It should be understood that, in addition to the arcuate transition between one surface of the extension 210 and the connecting portion 300 in the first direction, it is also possible that two surfaces of the extension 210 are connected to the connecting portion 300 via arcuate transitions in the first direction.

[0056] In this way, the stress between the extension 210 and the connection 300 can be reduced by the arc transition connection. This significantly reduces the risk of cracks, lattice defects or even breakage of the gate contact layer 200 due to stress accumulation at the connection during device manufacturing processes (such as thermal annealing) and thermal cycling conditions, thereby improving the yield of semiconductor devices.

[0057] It should be noted that, regarding the setting of the curvature of the arc, the curvature can be appropriately increased while ensuring a safe insulation distance between the arc segment and the adjacent source contact layer 100, so as to reduce the stress between the extension 210 and the connection 300 as much as possible.

[0058] Please continue to refer to this. Figure 1 and Figure 2 The cross-sectional shape of the connection portion 300 is square, with a cross-section parallel to the source contact layer 100 as the cross-section. For example, the cross-sectional shape of the connection portion 300 can be square or rectangular. This increases the area of ​​the connection portion 300, thereby reducing the error rate in the patterning process and effectively increasing the size of the gate contact hole 400 formed on the connection portion 300. This allows for the fabrication of the gate contact plug using a low-complexity Al-plug process, eliminating the need for a WEB process compared to the high-complexity W-plug process, reducing equipment dependence, and lowering the fabrication cost of semiconductor devices. It should be noted that the WEB process refers to further filling the sidewalls and bottom of the contact hole through plasma-enhanced chemical vapor deposition to eliminate voids.

[0059] In one possible implementation, a gate contact plug 500 is disposed within the gate contact hole 400, and the gate contact plug 500 is made of aluminum. This can reduce the manufacturing cost of semiconductor devices.

[0060] It should be noted that the aperture of the gate contact hole 400 can be the same or different everywhere. In some embodiments, the semiconductor device further includes a substrate 600, a plurality of source contact layers 100, a plurality of gate contact layers 200, and a connection portion 300 disposed on the substrate 600.

[0061] Along a direction perpendicular to the substrate 600 and away from the source contact layer 100, the aperture of the gate contact hole 400 tends to increase. This direction, perpendicular to the substrate 600 and away from the connection portion 300, can be understood as from top to bottom.

[0062] It should be noted that the increasing trend can be understood as the bottom diameter of the gate contact hole 400 being smaller than the top diameter of the gate contact hole 400, and does not strictly follow a gradually increasing trend. The increasing trend can also be understood as the diameter of the gate contact hole 400 potentially increasing gradually.

[0063] In this way, the wettability and adhesion of the filler material (such as Al) can be improved during the formation of the gate contact plug 500, reducing the probability of void formation. In addition, the trapezoidal structure optimizes the flow path of the filler material, reduces the capillary pressure during the filling process, thereby improving the filling uniformity and enhancing the conductivity and structural stability of the gate contact plug.

[0064] In this embodiment, the substrate 600 also has multiple gate regions (not shown) and multiple source regions (not shown), which are alternately arranged along a first direction. The gate regions and source regions have different conductivity types, forming a PN junction between them. Multiple source contact layers 100 correspond to multiple source regions, and multiple gate contact layers 200 correspond to multiple gate regions. When a voltage is applied to the gate contact plug 500, the voltage can be transmitted to the gate region through the gate contact layer 200, causing the PN junction formed by the gate and source regions to be in a zero-bias or slightly reverse-biased state, thus opening the conductive channel. At this time, if a positive voltage is applied between the drain and source, electrons can start from the source, smoothly pass through this open N-type channel, and reach the drain, ensuring that the semiconductor device is in the on state.

[0065] It should be noted that an intermediate layer is provided between the gate contact plug 500 and the inner wall of the gate contact hole 400. Using the intermediate layer as a transition can improve the interfacial bonding force between the gate contact plug 500 and the gate contact layer 200.

[0066] For example, an intermediate layer can be formed on the inner wall of the gate contact hole 400 using atomic layer deposition or chemical vapor deposition. The intermediate layer can be made of titanium nitride (TiN) or tantalum nitride (TaN). This intermediate layer (TiN / TaN) acts as a diffusion barrier layer, preventing interdiffusion of elements between the filler material (such as Al or Cu) and the gate contact layer 200, thereby maintaining interface stability. Furthermore, the high conductivity of the intermediate layer can further reduce contact resistance and improve the high-frequency response capability of the semiconductor device.

[0067] Please refer to Figure 3 This application also provides a method for fabricating a semiconductor device, comprising:

[0068] Step S100: Provide a substrate. Please refer to [reference needed]. Figure 4 The substrate 600 can be made of silicon carbide (SiC).

[0069] Step S200: A dielectric layer is formed on the substrate and the dielectric layer is patterned to form a filling region within the dielectric layer. The filling region includes a plurality of first filling regions, a plurality of second filling regions, and a third filling region. The plurality of first filling regions and the plurality of second filling regions are spaced apart and alternately arranged along a first direction. The plurality of second filling regions protrude along a second direction to form an extension region. The third filling region is located on one side of the plurality of first filling regions in the second direction and is connected to the plurality of extension regions.

[0070] Please refer to Figure 5 A dielectric layer 700 is formed on a substrate 600 by a deposition process, wherein the dielectric layer 700 is made of silicon oxide.

[0071] Next, please refer to Figure 6 and Figure 7 Pattern the dielectric layer 700 to form a fill area within the dielectric layer 700. Please refer to [reference needed]. Figure 7 The filling region includes multiple first filling regions 710, multiple second filling regions 720, and a third filling region 740. The multiple first filling regions 710 and multiple second filling regions 720 are spaced apart and alternately arranged along a first direction. The multiple first filling regions 710 and multiple second filling regions 720 extend along a second direction, and the first filling regions 710 and multiple second filling regions 720 have a strip-shaped structure. It should be noted that the orthographic projection of the first filling region 710 on the substrate 600 coincides with the source region in the substrate 600, and the orthographic projection of the second filling region 720 on the substrate 600 coincides with the gate region in the substrate 600.

[0072] All of the plurality of second filling regions 720 protrude along the second direction to form an extension region 730; the third filling region 740 is located on one side of the plurality of first filling regions 710 in the second direction and communicates with the plurality of extension regions 730.

[0073] For example, a mask layer (not shown) can be formed on the surface of the dielectric layer 700 facing away from the substrate 600. The mask pattern is then transferred onto the mask layer, and the dielectric layer 700 is etched using an etching process to form a filling region within the dielectric layer 700, using the mask layer as a mask. It should be noted that the mask layer can be a photoresist layer or a hard mask layer. When the mask layer is a hard mask layer, it can be a stacked structure, thus improving the accuracy during pattern transfer. The etching process can be dry etching or wet etching.

[0074] Step S300: Form a source contact layer and a gate contact layer. The gate contact layer is located in the extension region to form an extension portion, and the gate contact layer is located in the third filling region to form a connection portion.

[0075] Please refer to Figure 8 For example, a precursor layer 800 is formed in the filled area by a deposition process. The precursor layer 800 covers the inner wall of the filled area and extends to the outside of the filled area, covering the top surface of the substrate 600. The precursor layer 800 is made of nickel (Ni) and has a thickness of 500 Å.

[0076] Please refer to Figure 9 Subsequently, the device is subjected to a heat treatment process, in which the precursor layer 800 reacts with the substrate 600 to form the source contact layer 100 and the gate contact layer 200. The heat treatment temperature is 650°C, and the heat treatment time is 300 seconds. Alternatively, the precursor layer 800 in the first filling region forms the source contact layer 100, the precursor layer 800 in the second filling region forms the gate contact layer 200, the precursor layer 800 in the extension region forms the extension 210 of the gate contact layer 200, and the precursor layer 800 in the third filling region forms the connection portion 300.

[0077] Please refer to Figure 10 Finally, the precursor layer 800 on the top surface of the substrate 600 can be removed by a cleaning process, for example, by an acid pickling process.

[0078] Step S400: Form a gate contact hole in the connection portion.

[0079] For example, the connection portion 300 is patterned to form a gate contact hole 400 within the connection portion 300. Given the relatively large size of the connection portion 300 in this embodiment, the size of the gate contact hole 400 can be increased; for example, the aperture of the gate contact hole 400 can be larger than a preset value. This overcomes the aperture limitation of the gate contact hole 400 in related technologies, thereby enabling a process migration from the high-cost, high-complexity W-plug process to the low-cost, low-complexity Al-plug process, thus simplifying the fabrication process, reducing fabrication costs, and improving the performance of semiconductor devices.

[0080] In one possible implementation, the gate contact plug 500 is formed within the gate contact hole 400 using an aluminum filling process. This eliminates the need for a web process compared to the highly complex W-plug, reducing reliance on equipment and lowering the manufacturing cost of the semiconductor device.

[0081] It should be noted that the introduction of laser-assisted heating during the Al-plug filling process can improve the wettability and diffusion ability of the filler material through local heating, thereby enhancing the fluidity of the filler material and reducing the formation of voids.

[0082] This application also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a power converter, a motor drive and controller, a renewable energy power generation system, etc.

[0083] Given that the electronic device provided in this application includes the semiconductor device described in any of the above embodiments, it possesses all the structure and all the beneficial effects of a semiconductor device, and will not be described in detail here.

[0084] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0085] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Multiple source contact layers, wherein the multiple source contact layers are spaced apart along a first direction; A plurality of gate contact layers are arranged at intervals along a first direction, and each gate contact layer is located between adjacent source contact layers; the plurality of gate contact layers extend along a second direction to form an extension. A connecting portion is disposed on the side of the extension portion opposite to the plurality of source contact layers and is connected to the plurality of extension portions; A gate contact hole is disposed on the connection portion, and the diameter of the gate contact hole is greater than a preset value; wherein the first direction intersects the second direction.

2. The semiconductor device according to claim 1, characterized in that, The extension includes a connection end connected to the corresponding gate contact layer; In the first direction, the width of the connection end is greater than the width of the gate contact layer, and there is a gap between the connection end and the adjacent source contact layer.

3. The semiconductor device according to claim 2, characterized in that, In the first direction, at least one surface of the extension is connected to the connecting portion by an arc-shaped transition.

4. The semiconductor device according to claim 3, characterized in that, With the cross section parallel to the source contact layer as the cross section, the cross section shape of the connection part is square.

5. The semiconductor device according to any one of claims 1-4, characterized in that, A gate contact plug is provided inside the gate contact hole, and the gate contact plug is made of aluminum.

6. The semiconductor device according to any one of claims 1-4, characterized in that, The semiconductor device includes a substrate, and the plurality of source contact layers, the plurality of gate contact layers and the connection portion are all disposed on the substrate; Along a direction perpendicular to the substrate and away from the source contact layer, the aperture of the gate contact hole tends to increase.

7. The semiconductor device according to claim 6, characterized in that, The substrate is further provided with a plurality of gate regions and a plurality of source regions, which are spaced apart and alternately arranged along a first direction; The plurality of gate regions correspond to the plurality of gate contact layers, and the plurality of source regions correspond to the plurality of source contact layers.

8. A method for fabricating a semiconductor device, characterized in that, include: Provide a base; A dielectric layer is formed on the substrate, and the dielectric layer is patterned to form a filling region within the dielectric layer. The filling region includes a plurality of first filling regions, a plurality of second filling regions, and a third filling region. The plurality of first filling regions and the plurality of second filling regions are spaced apart and alternately arranged along a first direction. Each of the plurality of second filling regions protrudes along a second direction to form an extension region. The third filling region is located on one side of the plurality of first filling regions in the second direction and communicates with the plurality of extension regions. A source contact layer and a gate contact layer are formed, wherein the gate contact layer is located within the extension region to form an extension portion, and the gate contact layer is located within the third filling region to form a connection portion; A gate contact hole is formed within the connection portion.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, A gate contact plug is formed inside the gate contact hole using an aluminum filling process.

10. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1-8.

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