SPI (Serial Peripheral Interface) communication system, SPI communication method and printing equipment

Abstract

The invention provides an SPI (Serial Peripheral Interface) communication system, an SPI communication method and printing equipment, and the SPI communication system comprises master control equipment and slave equipment, wherein the master control equipment is connected with the slave equipment through an SPI (Serial Peripheral Interface) bus, and a communication link independent of the SPI bus is also arranged between the master control equipment and the slave equipment; the master control equipment is used for sending a data emptying instruction aiming at an SPI buffer area to the slave equipment through the communication link when detecting that communication between the master control equipment and the slave equipment is abnormal; and / or the master control equipment is used for acquiring the equipment state of the slave equipment through the communication link, and sending an instruction to the slave equipment through the SPI bus when the slave equipment is determined to be in an idle state through the equipment state.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and more specifically, to an SPI communication system, an SPI communication method, and a printing device. Background Technology

[0002] In electronic devices, the master and slave devices typically exchange data via the standard SPI protocol. In this process, the master device sends data, and the slave device responds. However, due to the single communication method between the master and slave, there is a certain lag in data transmission. For example, when electrical interference, signal jitter, or delayed handshakes occur between the master and slave, leading to data corruption during SPI communication, the existing anomaly recovery methods are time-consuming, which can easily cause delays in data transmission between the master and slave. Summary of the Invention

[0003] This disclosure provides at least one SPI communication system, SPI communication method, and printing device.

[0004] In a first aspect, embodiments of this disclosure provide an SPI communication system, including: a master device and a slave device; wherein the master device and the slave device are connected via an SPI bus, and a communication link independent of the SPI bus is further provided between the master device and the slave device; The master control device is used to send a data clearing command for the SPI buffer to the slave device through the communication link when an abnormality in communication with the slave device is detected. and / or The master control device is used to obtain the device status of the slave device through the communication link, and when it is determined through the device status that the slave device is in an idle state, it sends a command to the slave device through the SPI bus.

[0005] In one optional implementation, the signal transmitted by the communication link includes a first status control bit; The master control device is used to send the data clearing command to the slave device by changing the level state of the first state control bit; The slave device is configured to clear the data in the SPI buffer when it detects a change in the level of the first state control bit.

[0006] In one optional implementation, the signal transmitted by the communication link includes a second status control bit; The slave device is used to identify its own device state by changing the level of the second state control bit; The master control device is used to determine the device status of the slave device by reading the level status of the second status control bit.

[0007] In one optional implementation, the master device is configured to set the interface receiving the second state control bit to a falling edge interrupt trigger mode when the device state of the slave device is determined to be in a working state based on the level state of the second state control bit.

[0008] In one alternative implementation, The slave device is configured to change the level of the second state control bit when its own device state changes from working state to idle state; The master control device is configured to trigger the execution of an interrupt task in response to a change in the level state of the second state control bit under the falling edge interrupt trigger mode; wherein the interrupt task is to send a command to the slave device via the SPI bus.

[0009] In a second aspect, embodiments of this disclosure provide an SPI communication method, applied to the SPI communication system described in any one of the first aspects, the method comprising: The master control device sends a data clearing command to the slave device through the communication link established between the master control device and the slave device, and / or sends the device status of the slave device to the master control device through the communication link; The communication link is independent of the SPI bus. The data clearing command is sent by the master device to the slave device when the communication between the master device and the slave device is abnormal. The data clearing command is used to trigger the slave device to clear the SPI buffer. When the device is in an idle state, the master device sends data to the slave device through the SPI bus.

[0010] In one optional implementation, the signal transmitted by the communication link includes a first status control bit; The step of sending a data clearing command to the slave device via the communication link established between the master control device and the slave device includes: Obtain the communication status between the master control device and the slave device; When the communication status is determined to be abnormal, the master control device changes the level of the first status control bit to send the data clearing command to the slave device.

[0011] In one optional implementation, the signal transmitted by the communication link includes a second status control bit; sending the device status of the slave device to the master device through the communication link includes: Before the master device sends a command to the slave device via the SPI bus, the device status of the slave device is obtained by reading the level status of the second status control bit.

[0012] Thirdly, embodiments of this disclosure provide a printing device including the SPI communication system described in any of the first aspects above.

[0013] In one optional implementation, the master device in the printing device is a printer master controller, and the slave device in the printing device is a trusted chip.

[0014] This disclosure provides an SPI communication system, an SPI communication method, and a printing device. In this embodiment, the SPI communication system includes a master device and a slave device; wherein the master device and the slave device are connected via an SPI bus, and a communication link independent of the SPI bus is also provided between the master device and the slave device; the master device is used to send a data clearing command for the SPI buffer to the slave device via the communication link when a communication anomaly is detected with the slave device; and / or, the master device is used to obtain the device status of the slave device via the communication link, and when the device status determines that the slave device is in an idle state, send a command to the slave device via the SPI bus.

[0015] In the above embodiments, a communication link independent of the SPI bus is added to the existing SPI bus between the master device and the slave device. This communication link allows the master device to send a data clearing command for the SPI buffer and / or transmit the slave device's device status. When communication between the master and slave devices fails, this communication link allows the master device to directly send a data clearing command to the slave device, thereby clearing the SPI buffer. Compared to the existing method of clearing residual data by reading from the SPI buffer, this solution quickly clears residual data, shortens the time required for clearing residual data, and significantly reduces system downtime due to communication failures, making it particularly suitable for applications with high real-time requirements. Furthermore, in this solution, the master device can query the slave device's device status through this communication link before sending a command. When the device status is idle, the master device sends a command to the slave device. This approach avoids data conflicts or loss caused by initiating communication when the slave device is "busy."

[0016] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of an SPI communication system provided in an embodiment of this disclosure is shown; Figure 2 A schematic diagram of another SPI communication system provided by an embodiment of this disclosure is shown; Figure 3 A flowchart of an SPI communication method provided by an embodiment of this disclosure is shown; Figure 4 This illustration shows an interaction flowchart between a printer main controller and a trusted chip provided in an embodiment of this disclosure; Figure 5 This illustration shows another flowchart of the interaction between a printer master controller and a trusted chip provided in an embodiment of this disclosure; Figure 6 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0022] In electronic devices, the master and slave devices typically exchange data via the standard SPI protocol. In this process, the master device sends data, and the slave device responds. However, due to the single communication method between the master and slave, there is a certain lag in data transmission. For example, when electrical interference, signal jitter, or delayed handshakes occur between the master and slave, causing data corruption during SPI communication, the existing anomaly recovery methods are time-consuming, easily leading to data transmission delays between the master and slave. Furthermore, if the slave processes commands serially, when the slave is processing a command, if the master sends a command, that command may be discarded or queued. For the master, since it cannot know whether the slave is idle or can process commands promptly, it often needs to wait in a blocking manner, which also easily leads to data transmission delays between the master and slave.

[0023] Based on the above research, this disclosure provides an SPI communication system, an SPI communication method, and a printing device. In the embodiments of this application, the SPI communication system includes a master device and a slave device; wherein the master device and the slave device are connected via an SPI bus, and a communication link independent of the SPI bus is also provided between the master device and the slave device; the master device is used to send a data clearing command for the SPI buffer to the slave device via the communication link when a communication anomaly is detected with the slave device; and / or, the master device is used to obtain the device status of the slave device via the communication link, and when the device status determines that the slave device is in an idle state, send a command to the slave device via the SPI bus.

[0024] In the above embodiments, a communication link independent of the SPI bus is added to the existing SPI bus between the master device and the slave device. This communication link allows the master device to send a data clearing command for the SPI buffer and / or transmit the slave device's device status. When communication between the master and slave devices fails, this communication link allows the master device to directly send a data clearing command to the slave device, thereby clearing the SPI buffer. Compared to the existing method of clearing residual data by reading from the SPI buffer, this solution quickly clears residual data, shortens the time required for clearing residual data, and significantly reduces system downtime due to communication failures, making it particularly suitable for applications with high real-time requirements. Furthermore, in this solution, the master device can query the slave device's device status through this communication link before sending a command. When the device status is idle, the master device sends a command to the slave device. This approach avoids data conflicts or loss caused by initiating communication when the slave device is "busy."

[0025] To facilitate understanding of this embodiment, a detailed description of an SPI communication system disclosed in this disclosure embodiment will be provided first.

[0026] See Figure 1 The diagram shown is a structural schematic of an SPI communication system provided in an embodiment of this disclosure. Figure 1 As shown, the SPI communication system includes a master device 100 and a slave device 200; wherein the master device 100 and the slave device 200 are connected via an SPI bus, and a communication link independent of the SPI bus is also provided between the master device 100 and the slave device 200.

[0027] The master control device 100 is used to send a data clearing command for the SPI buffer to the slave device through the communication link when an abnormality in communication with the slave device is detected. and / or The master control device 100 is used to obtain the device status of the slave device through the communication link, and when it is determined through the device status that the slave device is in an idle state, it sends a command to the slave device through the SPI bus.

[0028] In this embodiment of the application, a communication link can be established between the master device and the slave device based on any one of the I / O interface, I2C interface and USB interface.

[0029] When the master device detects a communication anomaly with the slave device, it can send a data clearing command for the SPI buffer to the slave device through this communication link. After receiving the data clearing command through this communication link, the slave device performs a data clearing operation on the SPI buffer.

[0030] Before the master device sends commands to the slave device via the SPI bus, it can request the device status from the slave device through this communication link. Upon receiving the request, the slave device returns its device status to the master device via the same communication link. If the master device determines the slave device is idle based on this device status, it sends a command to the slave device via the SPI bus. If the master device determines the slave device is active based on this device status, it sets the falling-edge interrupt trigger mode for the interface corresponding to the communication link. When it determines to trigger an interrupt task based on this falling-edge interrupt trigger mode, it sends a command to the slave device.

[0031] In the embodiments of this application, the master control device can be the main controller of any electronic device, and the slave device can be a device in the electronic device that exchanges data with the master control device via an SPI bus. For example, the master control device can be a system-on-a-chip (SoC) in the electronic device, and the slave device can be a trusted chip in the electronic device. Here, the specific device types of the master control device and the slave device are not specifically limited. Any device that can use the SPI communication system proposed in this application for communication fault recovery and / or device status monitoring is within the protection scope of this application.

[0032] In the embodiments of this application, such as Figure 2 As shown, the signals transmitted by the communication link include the first state control bit IO1.

[0033] Here, the first status control bit is used to clear the data in the SPI buffer, ensuring that there is no data residue in the SPI buffer. When an anomaly occurs in the SPI communication between the master and slave devices, the master device can send a data clear command to the slave device through this first status control bit. After receiving the data clear command, the slave device clears the data in the SPI buffer, thereby ensuring that subsequent communication is not affected by residual data from the communication anomaly.

[0034] Based on this, the master control device is used to send a data clear command to the slave device by changing the level state of the first state control bit.

[0035] The slave device is used to clear the data in the SPI buffer when a change in the level of the first state control bit is detected.

[0036] To resolve the issue of abnormal SPI communication between the master and slave devices, when the master device detects an abnormal SPI communication with the slave device, it can change the level of the first state control bit.

[0037] For example, the first state control bit IO1 can be inverted. When the slave device detects a change in the IO1 level, it confirms that a data clear command has been received. The slave device then clears the SPI buffer. After clearing the SPI buffer, the slave device returns a clearing completion response to the master device. The master device can then resend commands to the slave device via the SPI bus. This process ensures that subsequent retransmissions are not affected by residual data from communication failures.

[0038] For example, the current state of the first state control bit IO1 is 1. If the master device detects an SPI communication anomaly with the slave device, it inverts the first state control bit IO1, changing its state to "0". After detecting the change in the first state control bit's state, the slave device recognizes the received data clear command. It then clears the data in the SPI buffer. After clearing the data, the slave device returns a clearing completion response to the master device. The master device can then resend commands to the slave device via the SPI bus.

[0039] In the embodiments of this application, such as Figure 2 As shown, the signals transmitted by the communication link include the second state control bit IO2.

[0040] The slave device is used to identify its own device state by changing the level of the second state control bit; The master control device is used to determine the device status of the slave device by reading the level status of the second status control bit.

[0041] If the slave device processes commands serially, then when the slave device is processing a command, if the master device sends another command to the slave device at the same time, that command may be dropped or need to be queued. For the master device, since it cannot know whether the slave device is idle or whether it can process the command in time, it often needs to wait in a blocking manner.

[0042] Based on this, the technical solution of this application sets a second state control bit to reflect the device state of the slave device. The device state includes working state and idle state. For example, when the second state control bit is "0", it means that the slave device is in idle state, and when the second state control bit is "1", it means that the slave device is in working state.

[0043] When a slave device changes from an idle state to an active state, it can change the level of the second state control bit from "0" to "1". When a slave device changes from an active state to an idle state, it can change the level of the second state control bit from "1" to "0".

[0044] Before sending commands to the slave device via the SPI bus, the master device can first obtain the level status of the second status control bit, and then determine the device status of the slave device based on the level status of the second status control bit. Specifically, if the level status of the second status control bit obtained by the master device is "0", it indicates that the device status of the slave device is idle. In this case, the master device directly sends commands to the slave device via the SPI bus.

[0045] In the above embodiments, before sending a command, the master control device can query the device status of the slave device through the communication link. When the device status is idle, the master control device sends a command to the slave device. This processing method avoids data conflicts or loss caused by initiating communication when the slave device is "busy".

[0046] In this embodiment of the application, the master control device is configured to set the interface receiving the second state control bit to a falling edge interrupt trigger mode when the device state of the slave device is determined to be in working state based on the level state of the second state control bit.

[0047] In this scenario, the slave device is configured to change the level of the second state control bit when its own device state changes from an active state to an idle state; the master device is configured to trigger the execution of an interrupt task in response to the change in the level of the second state control bit in a falling edge interrupt trigger mode; wherein, the interrupt task is to send a command to the slave device via the SPI bus.

[0048] Before sending commands to the slave device via the SPI bus, the master device can first obtain the level status of the second status control bit, and then determine the device status of the slave device based on the level status of the second status control bit. Specifically, if the level status of the second status control bit obtained by the master device is "1", it indicates that the slave device is in the working state. At this time, the master device can set the interface receiving the second status control bit to the falling edge interrupt trigger mode.

[0049] In other words, when the master device determines that the slave device is in a working state, the master device sets the interface to falling edge interrupt trigger mode. At this time, the master device can continue to process other services. When the level of the second state control bit changes to "0", the master device can be triggered to pause the currently processed service and trigger the execution of an interrupt task. This interrupt task is the task of sending commands to the slave device via the SPI bus.

[0050] In practice, when a slave device changes from an idle state to an active state, it can change the level of its second state control bit from "0" to "1". Before sending commands to the slave device via the SPI bus, the master device can first obtain the level of the second state control bit. If the master device obtains a level of "1" for the second state control bit, it indicates that the slave device is in an active state. At this time, the master device sets the interface for receiving the second state control bit to falling edge interrupt trigger mode. When the slave device changes its own state from active to idle, the level of its second state control bit changes to "0", that is, it outputs a falling edge signal to the master device. The master device then triggers an interrupt task and sends commands to the slave device via the SPI bus.

[0051] In the above embodiments, by setting the falling edge interrupt trigger mode, commands can be sent to the slave device in a timely manner when the slave device becomes idle, so that the slave device can process the commands sent by the master device in a timely manner.

[0052] See Figure 3 The diagram shows a flowchart of an SPI communication method provided in an embodiment of this disclosure. The method includes step S301, wherein: S301: Send a data clear command to the slave device through the communication link set between the master device and the slave device, and / or send the device status of the slave device to the master device through the communication link; The communication link is independent of the SPI bus settings. The data clear command is sent from the master device to the slave device when there is a communication failure between the master device and the slave device. The data clear command is used to trigger the slave device to clear the SPI buffer. When the device is in an idle state, the master device sends data to the slave device through the SPI bus.

[0053] In this embodiment of the application, a communication link can be established between the master device and the slave device based on any one of the I / O interface, I2C interface and USB interface.

[0054] When the master device detects a communication anomaly with the slave device, it can send a data clearing command for the SPI buffer to the slave device through this communication link. After receiving the data clearing command through this communication link, the slave device performs a data clearing operation on the SPI buffer.

[0055] Before the master device sends a command to the slave device via the SPI bus, it can request the device status from the slave device through this communication link. Upon receiving the request, the slave device returns its device status to the master device via the same communication link. If the master device determines the slave device is idle based on this device status, it sends a command to the slave device via the SPI bus. If the master device determines the slave device is active based on this device status, it sends a command to the slave device by setting the falling-edge interrupt trigger mode for the interface corresponding to the communication link.

[0056] In the embodiments of this application, the master control device can be the main controller of any electronic device, and the slave device can be a device in the electronic device that exchanges data with the master control device via an SPI bus. For example, the master control device can be a system-on-a-chip (SoC) in the electronic device, and the slave device can be a trusted chip in the electronic device. Here, the specific device types of the master control device and the slave device are not specifically limited. Any device that can use the SPI communication system proposed in this application for communication fault recovery and / or device status monitoring is within the protection scope of this application.

[0057] In the above embodiments, a communication link independent of the SPI bus is added to the existing SPI bus between the master device and the slave device. This communication link allows the master device to send a data clearing command for the SPI buffer and / or transmit the slave device's device status. When communication between the master and slave devices fails, this communication link allows the master device to directly send a data clearing command to the slave device, thereby clearing the SPI buffer. Compared to the existing method of clearing residual data by reading from the SPI buffer, this solution quickly clears residual data, shortens the time required for clearing residual data, and significantly reduces system downtime due to communication failures, making it particularly suitable for applications with high real-time requirements. Furthermore, in this solution, the master device can query the slave device's device status through this communication link before sending a command. When the device status is idle, the master device sends a command to the slave device. This approach avoids data conflicts or loss caused by initiating communication when the slave device is "busy."

[0058] In this embodiment of the application, the signal transmitted by the communication link includes a first status control bit. In this case, the above step S301 sends a data clearing command to the slave device through the communication link set between the master device and the slave device, including the following steps: Step S11: Obtain the communication status between the master control device and the slave device; Step S12: When the communication status is determined to be abnormal, the master control device changes the level of the first status control bit to send the data clearing command to the slave device.

[0059] To resolve the issue of abnormal SPI communication between the master and slave devices, when the master device detects an abnormal SPI communication with the slave device, it can change the level of the first state control bit.

[0060] For example, the first state control bit IO1 can be inverted. When the slave device detects a change in the IO1 level, it confirms that a data clear command has been received. The slave device then clears the SPI buffer. After clearing the SPI buffer, the slave device returns a clearing completion response to the master device. The master device can then resend commands to the slave device via the SPI bus. This process ensures that subsequent retransmissions are not affected by residual data from communication failures.

[0061] For example, the current state of the first state control bit IO1 is 1. If the master device detects an SPI communication anomaly with the slave device, it inverts the first state control bit IO1, changing its state to "0". After detecting the change in the first state control bit's state, the slave device recognizes the received data clear command. It then clears the data in the SPI buffer. After clearing the data, the slave device returns a clearing completion response to the master device. The master device can then resend commands to the slave device via the SPI bus.

[0062] In this embodiment of the application, the signal transmitted by the communication link includes a second status control bit. In this case, sending the device status of the slave device to the master device through the communication link includes: Step S21: Before the master device sends a command to the slave device through the SPI bus, the device status of the slave device is obtained by reading the level status of the second status control bit.

[0063] If the slave device processes commands serially, then when the slave device is processing a command, if the master device sends another command to the slave device at the same time, that command may be dropped or need to be queued. For the master device, since it cannot know whether the slave device is idle or whether it can process the command in time, it often needs to wait in a blocking manner.

[0064] Based on this, the technical solution of this application sets a second state control bit to reflect the device state of the slave device. The device state includes working state and idle state. For example, when the second state control bit is "0", it means that the slave device is in idle state, and when the second state control bit is "1", it means that the slave device is in working state.

[0065] When a slave device changes from an idle state to an active state, it can change the level of the second state control bit from "0" to "1". When a slave device changes from an active state to an idle state, it can change the level of the second state control bit from "1" to "0".

[0066] Before sending commands to the slave device via the SPI bus, the master device can first obtain the level status of the second status control bit, and then determine the device status of the slave device based on the level status of the second status control bit. Specifically, if the level status of the second status control bit obtained by the master device is "0", it indicates that the device status of the slave device is idle. In this case, the master device directly sends commands to the slave device via the SPI bus.

[0067] In the above embodiments, before sending a command, the master control device can query the device status of the slave device through the communication link. When the device status is idle, the master control device sends a command to the slave device. This processing method avoids data conflicts or loss caused by initiating communication when the slave device is "busy".

[0068] In this application embodiment, a printing device is also provided, including the SPI communication system described in the above embodiments. The master device in the printing device is a printer master controller, and the slave device is a trusted chip.

[0069] In practice, a communication link can be established between the printer main controller and the trusted chip based on any one of the IO interface, I2C interface, and USB interface.

[0070] Before the printer master controller sends commands to the trusted chip via the SPI bus, it can request the device status from the trusted chip through this communication link. Upon receiving the request, the trusted chip returns its device status to the printer master controller via the same communication link. If the printer master controller determines that the trusted chip is idle based on the device status, it sends commands to the trusted chip via the SPI bus. If the printer master controller determines that the trusted chip is active based on the device status, it sends commands to the trusted chip by setting the falling edge interrupt trigger mode for the interface corresponding to the communication link.

[0071] The technical solution of this application can quickly clear residual data, shorten the time spent clearing residual data, and greatly reduce the time the system is stuck due to communication failures, making it particularly suitable for applications with high real-time requirements. Furthermore, in this technical solution, the printer main controller can query the device status of the trusted chip through this communication link before sending a command. When the device status is idle, it sends a command to the trusted chip. This processing method avoids data conflicts or loss caused by initiating communication when the trusted chip is "busy".

[0072] The following is combined with Figure 4 and Figure 5 This section introduces the SPI communication methods used in SPI communication systems. For example... Figure 4 and Figure 5 As shown, the master control device is the printer's main controller, i.e., the printer's system-on-a-chip (SoC), and the slave devices are trusted chips. For example... Figure 4 As shown, the SPI communication method includes the following steps: S401: The printer main controller sends commands to the trusted chip via the SPI bus; S402: Printer main controller detects an SPI communication error between the printer main controller and the trusted chip; S403: The printer main controller inverts the level state of the first state control bit on the communication link; by inverting the level state, the level state of the first state control bit can be changed, thereby sending the data clear command to the slave device; S404: After the trusted chip determines that the level of the first state control bit has changed, it clears the data in the SPI buffer. S405: The trusted chip returns a clearing completion response to the printer main controller; S406: The printer's main controller sends commands to the trusted chip via the SPI bus.

[0073] To address the SPI communication anomaly, when an anomaly is detected between the trusted chip and the printer main controller, the printer main controller can invert the first state control bit IO1. At this time, the trusted chip detects the change in the level of IO1, which is a double-edge trigger, and can clear the SPI buffer to ensure that subsequent retransmissions are not affected by residual data from the communication anomaly.

[0074] like Figure 5 As shown, the SPI communication method includes the following steps: S501: The printer main controller requests the level status of the second state control bit from the trusted chip; S502: The trusted chip returns the level status of the second state control bit to the printer main controller; S503: When the printer main controller determines that the trusted chip is in working state based on the level state, it configures the second state control bit through the communication link to trigger an interrupt on the falling edge. S504: When the device state of the trusted chip changes from the working state to the idle state, an interrupt signal is generated; S505: In response to the interrupt signal, the printer master controller sends a command to the trusted chip via SPI.

[0075] Specifically, before sending commands to the trusted chip, the printer master controller can request the level of the second state control bit from the trusted chip via the I / O channel. The trusted chip then feeds back the level of the second state control bit to the printer master controller. When the trusted chip is busy, the printer master controller pauses sending commands to the trusted chip and handles other tasks. When the trusted chip completes its work and its state changes to idle, the trusted chip actively pulls the status line low, setting the level of the second state control bit to "0". Then, it quickly restores the level to high. This falling edge triggers an interrupt on the printer master controller, and the printer master controller's interrupt service routine begins execution. In this routine, the printer master controller sends data to the trusted chip via the SPI bus.

[0076] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0077] Corresponding to Figure 1 In addition to the SPI communication method, this disclosure also provides an electronic device 600, such as... Figure 6 The diagram shown is a structural schematic of an electronic device 600 provided in an embodiment of this disclosure, including: The system includes a processor 61, a memory 62, and a bus 63. The memory 62 stores execution instructions and includes main memory 621 and external memory 622. The main memory 621, also called internal memory, temporarily stores the computational data in the processor 61, as well as data exchanged with external memory such as a hard disk. The processor 61 exchanges data with the external memory 622 through the main memory 621. When the electronic device 600 is running, the processor 61 communicates with the memory 62 through the bus 63, causing the processor 61 to execute the following instructions: The master control device sends a data clearing command to the slave device through the communication link established between the master control device and the slave device, and / or sends the device status of the slave device to the master control device through the communication link; The communication link is independent of the SPI bus. The data clearing command is sent by the master device to the slave device when the communication between the master device and the slave device is abnormal. The data clearing command is used to trigger the slave device to clear the SPI buffer. When the device is in an idle state, the master device sends data to the slave device through the SPI bus.

[0078] This disclosure also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the SPI communication method described in the above-described method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0079] This disclosure also provides a computer program product carrying program code. The program code includes instructions that can be used to execute the steps of the SPI communication method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0080] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division; in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0082] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0083] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0084] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0085] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. An SPI communication system, characterized in that, include: A master control device and a slave device; wherein the master control device and the slave device are connected via an SPI bus, and a communication link independent of the SPI bus is also provided between the master control device and the slave device; The master control device is used to send a data clearing command for the SPI buffer to the slave device through the communication link when an abnormality in communication with the slave device is detected. and / or The master control device is used to obtain the device status of the slave device through the communication link, and when it is determined through the device status that the slave device is in an idle state, it sends a command to the slave device through the SPI bus.

2. The SPI communication system according to claim 1, characterized in that, The signals transmitted by the communication link include a first status control bit; The master control device is used to send the data clearing command to the slave device by changing the level state of the first state control bit; The slave device is configured to clear the data in the SPI buffer when it detects a change in the level of the first state control bit.

3. The SPI communication system according to claim 1, characterized in that, The signals transmitted by the communication link include a second status control bit; The slave device is used to identify its own device state by changing the level of the second state control bit; The master control device is used to determine the device status of the slave device by reading the level status of the second status control bit.

4. The SPI communication system according to claim 3, characterized in that, The master control device is configured to set the interface receiving the second state control bit to a falling edge interrupt trigger mode when it determines that the device state of the slave device is in a working state based on the level state of the second state control bit.

5. The SPI communication system according to claim 4, characterized in that, The slave device is configured to change the level of the second state control bit when its own device state changes from working state to idle state; The master control device is configured to trigger the execution of an interrupt task in response to a change in the level state of the second state control bit under the falling edge interrupt trigger mode; wherein the interrupt task is to send a command to the slave device via the SPI bus.

6. An SPI communication method, characterized in that, Applied to the SPI communication system as described in any one of claims 1-5, the method comprises: The master control device sends a data clearing command to the slave device through the communication link established between the master control device and the slave device, and / or sends the device status of the slave device to the master control device through the communication link; The communication link is independent of the SPI bus. The data clearing command is sent by the master device to the slave device when the communication between the master device and the slave device is abnormal. The data clearing command is used to trigger the slave device to clear the SPI buffer. When the device is in an idle state, the master device sends data to the slave device through the SPI bus.

7. The SPI communication method according to claim 6, characterized in that, The signals transmitted by the communication link include a first status control bit; The step of sending a data clearing command to the slave device via the communication link established between the master control device and the slave device includes: Obtain the communication status between the master control device and the slave device; When the communication status is determined to be abnormal, the master control device changes the level of the first status control bit to send the data clearing command to the slave device.

8. The SPI communication method according to claim 6, characterized in that, The signals transmitted via the communication link include a second status control bit; sending the device status of the slave device to the master device via the communication link includes: Before the master device sends a command to the slave device via the SPI bus, the device status of the slave device is obtained by reading the level status of the second status control bit.

9. A printing device, characterized in that, It includes at least one SPI communication system as described in any one of claims 1 to 5.

10. The printing apparatus according to claim 9, characterized in that, The main control device in the printing device is the printer main controller, and the slave device in the printing device is a trusted chip.

Images