Data processing card, data processing method and data processing system

Abstract

The invention relates to a data processing card, a data processing method and a data processing system, and belongs to the technical field of chips. The data processing card can assist an input / output device to perform data interaction with a tested device in a prototype verification device through an internal data transmission circuit, can obtain target data in the data interaction process from the data transmission circuit through an internal control chip, and transmits the target data to a host. Therefore, additional hardware equipment does not need to be connected in series between the data processing card and the input and output equipment, and the target data does not need to be grabbed through the additional hardware equipment, so that the hardware cost of chip prototype verification can be reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the chip technical field, and in particular to a data processing card, a data processing method and a data processing system. BACKGROUND

[0002] The device equipped with the prototype verification platform can be referred to as a prototype verification device. At present, a user can perform prototype verification on a certain function of a chip through the prototype verification platform in the prototype verification device. Taking verification of an input and output function of the chip as an example, the prototype verification manner can be that a to-be-tested device and a data processing card are arranged on the prototype verification platform, the user connects a protocol analyzer to the data processing card and an input and output device to establish a communication link between the to-be-tested device and the input and output device of the prototype verification platform, and the data processing card and the protocol analyzer are both on the communication link; the to-be-tested device runs function code of the input and output function of the chip to perform data interaction with the input and output device, and in the data interaction process, the to-be-tested device and the input and output device both transmit respective data packets to each other through the communication link, the protocol analyzer captures target data from the data packets transmitted on the communication link, and uploads the target data to a host computer, so that the host computer performs data analysis on the target data to perform prototype verification on the input and output function of the chip.

[0003] However, in the prototype verification manner described above, the host computer needs to capture the target data by means of the protocol analyzer, and the price of the protocol analyzer is relatively high, thereby increasing the hardware cost of chip prototype verification. Therefore, there is an urgent need for a data processing card that can be applied to a prototype verification platform and can reduce the hardware cost of chip prototype verification. SUMMARY

[0004] The present disclosure provides a data processing card, a data processing method and a data processing system to at least solve the problem of high hardware cost of chip prototype verification in the related art. The technical solutions of the present disclosure are as follows: According to a first aspect of an embodiment of the present disclosure, a data processing card is provided, which comprises a data transmission circuit and a control chip, wherein the data transmission circuit is connected with the control chip; The data transmission circuit is configured to connect a prototype verification device and an input and output device; The control chip is configured to connect a host computer; The data transmission circuit is further configured to receive a first data packet, transmit the first data packet to the input and output device, receive a second data packet, and transmit the second data packet to a to-be-tested device in the prototype verification device; wherein the first data packet is a data packet sent by the to-be-tested device, and the second data packet is a data packet sent by the input and output device; The control chip is further configured to receive a control command of the host, acquire target data from a target data message transmitted by the data transmission circuit based on the control command, and send the target data to the host; wherein the control command instructs the control chip to report the target data carried by the target data message, and the target data message includes the first data message and / or the second data message.

[0005] Optionally, the control chip is further configured to send a data acquisition request signal to the data transmission circuit based on the control command, and the data acquisition request signal instructs to acquire the target data. The data transmission circuit is further configured to parse the target data from the target data message based on the received data acquisition request signal, and send the parsed target data to the control chip. The control chip is further configured to receive the target data.

[0006] Optionally, the data transmission circuit includes a speed bridge connected with the control chip. The speed bridge is configured to connect the prototype verification device and the input / output device. The speed bridge is further configured to receive the first data message, transmit the first data message to the input / output device at a second data transmission speed, receive the second data message, and transmit the second data message to the device under test at a first data transmission speed, wherein the first data transmission speed and the second data transmission speed are different. The speed bridge is further configured to receive the data acquisition request signal, parse the target data from the target data message based on the data acquisition request signal, and send the parsed target data to the control chip.

[0007] Optionally, the control chip is further configured to: Load the firmware of the speed bridge from the host to the speed bridge.

[0008] Optionally, the data processing card further includes a first storage chip connected with the control chip, and the first storage chip stores the firmware of the speed bridge. The control chip is further configured to load the firmware of the speed bridge from the first storage chip to the speed bridge.

[0009] Optionally, the first storage chip stores a plurality of firmwares of the speed bridge, and different firmwares support different input / output protocols; and the first data message and the second data message are both messages of a target input / output protocol. The control chip is further configured to load a target firmware from the first storage chip to the speed bridge, the target firmware supporting the target input / output protocol.

[0010] Optionally, the data transmission circuit further comprises a reset control circuit, the reset control circuit being connected with the speed bridge and the control chip. The control chip is further configured to send a reset signal to the reset control circuit in response to the speed bridge satisfying a reset condition, the reset signal indicating resetting the speed bridge. The reset control circuit is configured to reset the speed bridge based on the received reset signal.

[0011] Optionally, the data processing card further comprises a second storage chip, the second storage chip being connected with the control chip. The control chip is further configured to cache the obtained target data into the second storage chip, and send the target data in the second storage chip to the host in response to a size of a free storage space of the second storage chip being less than or equal to a first threshold.

[0012] According to a second aspect of the embodiments of the present disclosure, a data processing method is provided, the method being applied to a data processing card, and the method comprising: receiving a first data packet, transmitting the first data packet to an input / output device, receiving a second data packet, and transmitting the second data packet to a device under test in a prototype verification device; wherein the first data packet is a data packet sent by a device under test in a prototype verification device, and the second data packet is a data packet sent by an input / output device; receiving a control command of a host, obtaining target data from a transmitted target data packet based on the control command, and sending the target data to the host; wherein the control command instructs the control chip to report the target data carried by the target data packet, and the target data packet comprises the first data packet and / or the second data packet.

[0013] Optionally, the first data packet and the second data packet are received and sent by a data transmission circuit in the data processing card; and the obtaining of the target data from the transmitted target data packet based on the control command comprises: the control chip in the data processing card sends a data obtaining request signal to the data transmission circuit based on the control command, the data obtaining request signal instructing the obtaining of the target data; the data transmission circuit parses the target data from the target data packet based on the received data obtaining request signal, and sends the parsed target data to the control chip. The control chip receives the target data.

[0014] Optionally, the data transmission circuit includes a speed bridge; and the receiving the first data message, transmitting the first data message to the input / output device, receiving the second data message, and transmitting the second data message to the device under test in the prototype verification device include: The speed bridge receives the first data message, transmits the first data message to the input / output device at a second data transmission speed, receives the second data message, and transmits the second data message to the device under test at a first data transmission speed, the first data transmission speed being different from the second data transmission speed; The data transmission circuit analyzes the target data from the target data message based on the received data acquisition request signal, and sends the analyzed target data to the control chip, including: The speed bridge receives the data acquisition request signal, analyzes the target data from the target data message based on the data acquisition request signal, and sends the analyzed target data to the control chip.

[0015] Optionally, the method further includes: The control chip loads the firmware of the speed bridge from the host computer to the speed bridge.

[0016] Optionally, the data processing card further includes a first storage chip, and the method further includes: The control chip loads the firmware of the speed bridge from the first storage chip to the speed bridge.

[0017] Optionally, the first storage chip stores a plurality of firmwares of the speed bridge, different firmwares support different input / output protocols; and the first data message and the second data message are both messages of a target input / output protocol. The control chip loads the firmware of the speed bridge from the first storage chip to the speed bridge includes: The control chip loads a target firmware from the first storage chip to the speed bridge, the target firmware supporting the target input / output protocol.

[0018] Optionally, the data transmission circuit further includes a reset control circuit; and the method further includes: The control chip sends a reset signal to the reset control circuit in response to the speed bridge satisfying a reset condition, the reset signal indicating resetting the speed bridge; The reset control circuit resets the speed bridge based on the received reset signal.

[0019] Optionally, the data processing card further comprises a second storage chip, and the sending of the target data to the host comprises: the control chip caches the obtained target data into the second storage chip, and sends the target data in the second storage chip to the host in response to the size of the free storage space of the second storage chip being less than or equal to a first threshold.

[0020] According to a third aspect of the embodiments of the present disclosure, a data processing system is provided, comprising a data processing card, a prototype verification device, an input / output device, and a host, wherein the data processing card is connected with the prototype verification device, the input / output device, and the host; the DUT in the prototype verification device is configured to send a first data packet to a data transmission circuit in the data processing card; the input / output device is configured to send a second data packet to the data transmission circuit; the data transmission circuit is configured to receive the first data packet, transmit the first data packet to the input / output device, receive the second data packet, and transmit the second data packet to the DUT; the host is configured to send a control command to a control chip in the data processing card, wherein the control command instructs the control chip to report target data carried by a target data packet, and the target data packet comprises the first data packet and / or the second data packet; the control chip is configured to receive the control command of the host, obtain target data from a target data packet transmitted by the data transmission circuit based on the control command, and send the target data to the host; the host is further configured to receive the target data and perform data analysis on the target data.

[0021] Optionally, the control chip is further configured to send a data acquisition request signal to the data transmission circuit based on the control command, wherein the data acquisition request signal instructs to acquire the target data. the data transmission circuit is further configured to parse the target data from the target data packet based on the received data acquisition request signal, and send the parsed target data to the control chip; the control chip is further configured to receive the target data.

[0022] Optionally, the data transmission circuit comprises a speed bridge, and the speed bridge is connected with the control chip. the speed bridge is configured to connect the prototype verification device and the input / output device. The speed bridge is further configured to receive the first data message, transmit the first data message to the input / output device at a second data transmission speed, receive the second data message, and transmit the second data message to the device under test at a first data transmission speed, wherein the first data transmission speed is different from the second data transmission speed. The speed bridge is further configured to receive the data acquisition request signal, parse the target data from the target data message based on the data acquisition request signal, and send the parsed target data to the control chip.

[0023] Optionally, the control chip is further configured to: load the firmware of the speed bridge from the host computer to the speed bridge.

[0024] Optionally, the data processing card further comprises a first storage chip, the first storage chip being connected to the control chip, and the firmware of the speed bridge being stored in the first storage chip. The control chip is further configured to load the firmware of the speed bridge from the first storage chip to the speed bridge.

[0025] Optionally, the first storage chip stores a plurality of firmwares of the speed bridge, different firmwares supporting different input / output protocols, and the first data message and the second data message being messages of a target input / output protocol. The control chip is further configured to load a target firmware from the first storage chip to the speed bridge, the target firmware supporting the target input / output protocol.

[0026] Optionally, the data transmission circuit further comprises a reset control circuit, the reset control circuit being connected to the speed bridge and the control chip. The control chip is further configured to send a reset signal to the reset control circuit in response to the speed bridge satisfying a reset condition, the reset signal indicating resetting the speed bridge. The reset control circuit is configured to reset the speed bridge based on the received reset signal.

[0027] Optionally, the data processing card further comprises a second storage chip, the second storage chip being connected to the control chip. The control chip is further configured to cache the target data obtained in the second storage chip, and send the target data in the second storage chip to the host computer in response to the size of the free storage space of the second storage chip being less than or equal to a first threshold value.

[0028] According to a fourth aspect of the embodiments of the present disclosure, a computer readable storage medium is provided. When at least one instruction in the computer readable storage medium is executed by one or more processors of a host, the host is enabled to implement the functions of the host provided in any possible implementation of the fourth aspect.

[0029] According to a fifth aspect of the embodiments of the present disclosure, a computer program product is provided. The computer program product includes one or more instructions executable by one or more processors of a host, so that the host is enabled to implement the functions of the host provided in any possible implementation of the fourth aspect.

[0030] The data processing card provided by the present disclosure can assist the input and output device to interact with the DUT in the prototype verification device through the internal data transmission circuit, and the target data in the data interaction process can be obtained from the data transmission circuit through the internal control chip, and the target data is transmitted to the host, so that additional hardware devices (such as protocol analyzers) do not need to be connected in series between the data processing card and the input and output device, and the target data does not need to be captured through additional hardware devices, so that the hardware cost of chip prototype verification can be reduced.

[0031] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings incorporated in the specification and forming a part of it illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure, and do not constitute an undue limitation on the present disclosure.

[0033] Figure 1 is a schematic diagram of a data processing system according to an exemplary embodiment; Figure 2 is a structural schematic diagram of a data processing card according to an exemplary embodiment; Figure 3 is a schematic diagram of the internal and external connection relationship of a data processing card according to an exemplary embodiment; Figure 4 is a functional schematic diagram of a control chip according to an exemplary embodiment; Figure 5 is an interaction flowchart between a host computer and a data processing card according to an exemplary embodiment. DETAILED DESCRIPTION

[0034] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims. In the present disclosure, "in response to" is used to indicate a condition or state on which an operation is performed, and when the dependent condition or state is met, the performed one or more operations can be in real time or have a set delay; in the absence of a specific description, there is no limitation on the execution sequence of the performed multiple operations.

[0036] The information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the present disclosure are authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the target data involved in the present disclosure is obtained under sufficient authorization.

[0037] In some embodiments, the meaning of A and / or B includes: A and B, A, B, and three cases.

[0038] The present disclosure provides a data processing card capable of being applied to a prototype verification device, the prototype verification device being equipped with a prototype verification platform, the data processing card being capable of assisting a device under test (DUT) in the prototype verification platform to interact with a communication device outside the prototype verification device, and also being capable of collecting data required by a host for data analysis in the process of the data interaction. The data processing card can be a board card or other types of cards other than the board card.

[0039] In the following, the implementation environment of such a data processing card, the internal structure of such a data processing card, and the internal and external connection relationship of such a processing card will be introduced in conjunction with Figure 1 , Figure 2 and Figure 3 .

[0040] Figure 1 is a schematic diagram of a data processing system according to an exemplary embodiment. As Figure 1As shown, the data processing system includes a prototype verification device 10, a data processing card 20, an input output (IO) device 30, and a host 40, the data processing card 20 is connected with the prototype verification device 10, the IO device 30, and the host 40.

[0041] The prototype verification device 10 is provided with a prototype verification platform, the prototype verification platform is a hardware system used for building, testing, and verifying a prototype in chip development, the prototype verification platform can perform prototype verification on a chip, the prototype verification platform can be a hardware system built based on a field programmable gate array (FPGA), therefore, the prototype verification platform can also be referred to as an FPGA prototype verification platform, of course, the prototype verification platform can also be built by using other types of hardware except for the FPGA, and the hardware form of the prototype verification platform is not limited in the embodiments of the present disclosure.

[0042] The prototype verification platform is provided with a DUT 11, when a certain function of a chip is verified, the function code of the function can be loaded to the DUT 11, the DUT 11 runs the function code, so that the DUT 11 can implement the function.

[0043] The data processing card 20 provided by the embodiments of the present disclosure can be plugged into the prototype verification device 10 (such as being plugged into the prototype verification platform), therefore, the data processing card 20 can also be referred to as a daughter card of the prototype verification device 10 (or the prototype verification platform). The data processing card 20 is plugged into the prototype verification device 10, and can be connected with the DUT 11 in the prototype verification platform.

[0044] The data processing card 20 is connected with the IO device 30 through a wireless or wired network, or can be connected with the IO device 30 by using other connection manners. The data processing card 20 is connected with the host 40 through a wireless or wired network, or can be connected with the host 40 by using other connection manners.

[0045] When a certain function of a chip is verified, the data processing card 20 can assist the DUT 11 to interact with the IO device 30, the interaction data used for prototype verification in the interaction process is referred to as target data, in the interaction process, the data processing card 20 can also obtain the target data from the interaction data between the DUT 11 and the IO device 30, and transmit the obtained target data to the host 40, so that the host 40 can perform data analysis on the target data, to verify the certain function of the chip.

[0046] The IO device 30 is an external device of the prototype verification device 10. When different functions of the chip are to be prototyped, the type of the IO device 30 required can be different, and can also be different. The IO device 30 includes but is not limited to a multimedia IO device, a Peripheral Component Interconnect Express (PCIe) interface type IO device, a Universal Serial Bus (USB) interface IO device, a Serial Advanced Technology Attachment (SATA) interface type IO device, or a network type IO device, etc.

[0047] The host 40 is a host in any electronic device, which can be a server or a terminal device, including but not limited to a mobile phone, a personal computer (PC), a desktop computer, a laptop computer, a wearable device, etc.

[0048] The host 40 runs host software, which is used to control the data processing card 20 to obtain target data, and perform data analysis on the target data, so as to prototype a certain function of the chip.

[0049] Figure 1 The host 40 is connected to one data processing card 20 as an example. In some embodiments, the host 40 can also be connected to multiple data processing cards 20, each of which is connected to a DUT 11 and an IO device 30. The host 40 can obtain data required for different prototyping from different data processing cards 20, so as to prototype different chips.

[0050] Figure 2 is a structural schematic diagram of a data processing card according to an exemplary embodiment. As shown in Figure 2 The data processing card 20 includes a data transmission circuit 21 and a control chip 22, and the data transmission circuit 21 is connected to the control chip 22.

[0051] The data transmission circuit 21 can be implemented in at least one of a Digital Signal Processing (DSP), an FPGA, a Programmable Logic Array (PLA), and an Application Specific Integrated Circuit (ASIC). The implementation form of the data transmission circuit 21 is not limited in the embodiments of the present disclosure.

[0052] The data transmission circuit 21 is configured to connect the prototype verification device 10 and the IO device 30. For example, the data processing card 20 is plugged into the prototype verification device 10 or a prototype verification platform in the prototype verification device 10, so that the data transmission circuit 21 is connected to the DUT 11 in the prototype verification platform, and the data transmission circuit 21 can communicate with the DUT 11 in the prototype verification platform. The connection between the IO device 30 and the data processing card 20 is established, so that the IO device 30 can be connected to the data transmission circuit 21, and the IO device 30 can communicate with the data transmission circuit 21.

[0053] When the data processing card 20 is connected between the prototype verification platform and the IO device 30, the data transmission circuit 21 serves as a node between the DUT 11 and the IO device 30, and the data transmission circuit 21 can assist the DUT 11 and the IO device 30 to interact with each other. For example, in order to perform prototype verification on a certain function of a chip, the function code of the function is loaded into the DUT 11, and the DUT 11 runs the function code to trigger the DUT 11 and the IO device 30 to interact with each other. During the data interaction between the DUT 11 and the IO device 30, the DUT 11 sends data packets to the data transmission circuit 21, and the IO device 30 also sends data packets to the data transmission circuit 21. The data transmission circuit 21 forwards the data packets sent by the DUT 11 to the IO device 30, and forwards the data packets sent by the IO device 30 to the DUT 11, so that the DUT 11 and the IO device 30 can exchange the data packets sent by each other, so as to realize the data interaction between the DUT 11 and the IO device 30.

[0054] For the convenience of description, the data packets sent by the DUT 11 are referred to as first data packets, and the data packets sent by the IO device 30 are referred to as second data packets. Correspondingly, the data transmission circuit 21 is further configured to receive the first data packets, transmit the first data packets to the IO device 30, receive the second data packets, and transmit the second data packets to the DUT 11 in the prototype verification device 10.

[0055] The first data packet is a data packet generated by the DUT 11 when running a certain function (referred to as a target function) of the chip. Taking the IO function of the chip as an example, it is assumed that the prototype verification of the IO function is to verify whether the support of the IO function for the target IO protocol meets the standard protocol. For example, it is verified whether the IO function can meet the data interaction quality of the target IO protocol specified by the standard protocol when the IO function interacts with the IO device 30 based on the target IO protocol. At this time, the IO device 30 also interacts with the DUT 11 based on the target IO protocol, and the first data packet and the second data packet are both encapsulated based on the target IO protocol. The first data packet and the second data packet are both target IO protocol packets. The target IO protocol is an IO protocol involved in the prototype verification, and the IO function of the chip supports at least one IO protocol. The target IO protocol is any one of the IO protocols supported by the IO function. In this embodiment of the present disclosure, the IO protocols supported by the IO function and the number of IO protocols are not limited.

[0056] In the data interaction process between the DUT 11 and the IO device 30, the DUT 11 sends a plurality of first data packets to the data transmission circuit 21, and the data transmission circuit 21 sends the received first data packet to the IO device 30 every time it receives a first data packet. When the message format of the data packet supported by the IO device 30 is different from the message format of the first data packet, the data transmission circuit 21 converts the message format of the first data packet into the message format supported by the IO device 30, and sends the first data packet after format conversion to the IO device 30. The first data packet can be a request packet or not. When the first data packet is a request packet, the data transmission circuit 21 also returns a third data packet to the DUT 11, wherein the third data packet is a response packet of the first data packet, and the third data packet indicates that the data transmission circuit 21 receives the first data packet.

[0057] In the data interaction process between the DUT 11 and the IO device 30, the IO device 30 sends a plurality of second data packets to the data transmission circuit 21, and the data transmission circuit 21 sends the received second data packet to the DUT 11 every time it receives a second data packet. When the message format of the data packet supported by the DUT 11 is different from the message format of the second data packet, the data transmission circuit 21 converts the message format of the second data packet into the message format supported by the DUT 11, and sends the second data packet after format conversion to the DUT 11. The second data packet can be a request packet or not. When the second data packet is a request packet, the data transmission circuit 21 also returns a fourth data packet to the IO device 30, wherein the fourth data packet is a response packet of the second data packet, and the fourth data packet indicates that the data transmission circuit 21 receives the second data packet.

[0058] Optionally, the data packet transmission speed supported by DUT11 differs from that supported by IO device 30. The data packet transmission speed supported by DUT11 is referred to as the first data transmission speed, and the data packet transmission speed supported by IO device 30 is referred to as the second data transmission speed. The first data transmission speed and the second data transmission speed are different; for example, the first data transmission speed is lower than the second transmission speed. Therefore, the transmission speeds supported by DUT11 and IO device 30 are mismatched. Based on this, data transmission circuit 21 can adjust the transmission speeds of the first and second data packets, so that the first data packet can be transmitted to IO device 30 at the second data transmission speed, and the second data packet can be transmitted to DUT11 at the first data transmission speed. This allows both IO device 30 and DUT11 to receive data packets sent by each other at their respective supported transmission speeds, enabling data interaction between IO device 30 and DUT11 and resolving the data transmission speed mismatch problem between IO device 30 and DUT11.

[0059] For example, such as Figure 3 As shown, the data transmission circuit 21 includes a speed bridge 211 and a physical layer (PHY) 212. The speed bridge 211 is connected to the control chip 22 and the PHY 212. For example, the speed bridge 211 is connected to the PHY 212 via a Physical Interface for PCI Express (PIPE). Alternatively, it can be connected to the PHY 212 using other methods besides PIPE. The speed bridge 211 is used to connect the prototype verification device 10 and the I / O device 30. For example, the speed bridge 211 is used to connect to the DUT 11 in the prototype verification device 10, and the speed bridge 211 is connected to the I / O device 30 via the PHY 212. The PHY 212 is used to connect to the I / O device 30. For example, the PHY 212 is connected to the I / O device 30 via a cable. Alternatively, it can be connected to the I / O device 30 using other methods besides cables.

[0060] Speed ​​bridge 211 is also used to receive a first data packet, transmit the first data packet to I / O device 30 at a second data transmission speed, and receive a second data packet. This ensures that the first data packet can be transmitted to I / O device 30 at the second data transmission speed, maintaining normal interaction with I / O device 30.

[0061] For example, the DUT 11 transmits a first data packet to the speed bridge 211 at a first transmission speed. After receiving the first data packet, the speed bridge 211 transmits the first data packet to the PHY 212 at a second data transmission speed. The PHY 212 receives the first data packet and transmits the first data packet to the IO device 30 at the second data transmission speed. The IO device 30 receives the first data packet. When the data packet format supported by the IO device 30 is different from the data packet format of the first data packet, the speed bridge 211 converts the data packet format of the first data packet into the data packet format supported by the IO device 30, and transmits the converted first data packet to the PHY 212 at the second data transmission speed. The PHY 212 transmits the converted first data packet to the IO device 30 at the second data transmission speed. When the first data packet is a request packet, the speed bridge 211 transmits a third data packet to the DUT 11 at the first data transmission speed. The DUT 11 receives the third data packet returned by the speed bridge 211 for the first data packet.

[0062] The speed bridge 211 is further configured to transmit a second data packet to the DUT 11 at the first data transmission speed. In this way, the second data packet can be transmitted to the DUT 11 at the first data transmission speed, and normal interaction between the DUT 11 and the speed bridge 211 can be maintained.

[0063] For example, the IO device 30 transmits a first data packet to the PHY 212 at a second data transmission speed. After receiving the second data packet, the PHY 212 transmits the second data packet to the speed bridge 211 at the second data transmission speed. The speed bridge 211 receives the second data packet and transmits the second data packet to the DUT 11 at the first data transmission speed. The DUT 11 receives the second data packet. When the data packet format supported by the DUT 11 is different from the data packet format of the second data packet, the speed bridge 211 converts the data packet format of the second data packet into the data packet format supported by the DUT 11, and outputs the converted second data packet to the DUT 11 at the first data transmission speed. When the second data packet is a request packet, the speed bridge 211 transmits a fourth data packet to the PHY 212 at the second data transmission speed. The PHY 212 transmits the received fourth data packet to the IO device 30 at the second data transmission speed. The IO device 30 receives the fourth data packet returned by the speed bridge 211 for the second data packet.

[0064] In the case that the first data transmission speed is less than the second data transmission speed, the DUT 11 transmits the first data packet to the speed bridge 211 at a low speed relative to the IO device 30, the IO device 30 transmits the first data packet to the speed bridge 211 at a high speed relative to the DUT 11, the speed bridge 211 speeds up the transmission speed of the first data packet, transmits the first data packet sent by the DUT 11 to the IO device 30 at a high speed, and slows down the second data packet, transmits the first data packet to the DUT 11 at a low speed, so as to solve the problem of mismatching of data transmission speed between the high-speed IO device 30 and the low-speed DUT 11. In some embodiments, the speed bridge 211 can also be referred to as a speed adaptor (SA) or a speed-down bridge. The data transmission circuit 21 can also be referred to as a speed-down bridge system (i.e., a SA system).

[0065] The control chip 22 can be implemented in at least one of a hardware form of a DSP, an FPGA, a PLA, and an ASIC. The implementation form of the control chip 22 is not limited in the embodiments of the present disclosure. The control chip 22 can be a microprocessor unit (MPU) or a processor or chip of other types than the MPU, and the chip type of the control chip 22 is not limited in the embodiments of the present disclosure.

[0066] The control chip 22 is used to connect the host 40. As shown in Figure 3 The data processing card 20 further includes a communication interface 23, the control chip 22 is connected with the communication interface 23, and the communication interface 23 is used to connect the host 40, so that the control chip 22 can connect the host 40 and communicate with the host 40 through the communication interface 23. In some embodiments, as shown in Figure 3 The data processing card 20 includes a probe on board (PoB) system, the PoB system is a master control system of the data processing card 20, and the PoB system includes the control chip 22 and the communication interface 23.

[0067] The control chip 22 is a general control of the data processing card 20, as shown in Figure 4As shown, the control chip 22 has a communication management function, which is used to manage the communication between the data processing card 20 and the host 40 (i.e. the communication between the control chip 22 and the host 40). For example, the host 40 scans the available PoB system, when the PoB system in the data processing card 20 is scanned and available, the host 40 establishes a communication channel between the PoB system and the host 40 (i.e. a communication channel between the control chip 22 in the PoB system and the host 40), the control chip 22 broadcasts the information of the data processing card 20 to the communication channel, i.e. the control chip 22 sends broadcast data to the communication channel, and the host 40 receives the broadcast data and parses the information of the data processing card 20 from the broadcast data.

[0068] The broadcast data includes the information of the data processing card 20, and the information of the data processing card 20 includes the identification of the data processing card 20 or the identification of the PoB system in the data processing card 20, and the information of the data processing card 20 further includes the state identification of the data processing card 20, which indicates the current state of the data processing card 20, such as the state identification being a preparation completion identification, indicating that the data processing card 20 is in a preparation completion state, and the data processing card 20 can transmit data between the IO device 30 and the DUT 11, or obtain data from the transmitted data packet. Optionally, the data processing card 20 further includes the capability information of the data processing card 20, which indicates the data processing capability of the data processing card 20, such as the type of IO protocol supported by the data transmission circuit 21 (or the speed bridge 211) in the data processing card 20.

[0069] In some embodiments, the data processing card 20 connects the host 40 through a gateway, such as the communication interface 23 in the data processing card 20 connecting the gateway, and the gateway connecting the host 40, and the control chip 22 can send the information of the data processing card 20 to the gateway, and the gateway sends the information of the data processing card 20 to the host 40.

[0070] After the host 40 obtains the information of the data processing card 20, the host 40 obtains the capability information of the data processing card 20 from the information of the data processing card 20, and when the capability indicated by the capability information is consistent with the capability required by the prototype verification, the host 40 sends a control command to the data processing card 20, such as sending a control command to the communication interface 23 of the data processing card 20.

[0071] The control command indicates the target data carried by a target data packet reported by the control chip 22. The target data packet includes the first data packet and / or the second data packet. Optionally, the target data packet further includes the third data packet and / or the fourth data packet. The target data is interaction data in a target data interaction process required for prototype verification of a target function of the chip. The target data interaction process is an interaction process between the DUT 11 and the IO device 30 triggered by the DUT 11 running the functional code of the target function. The first data packet and the second data packet are both data packets in the target data interaction process. The target data packet is a data packet in which the target data is located.

[0072] Optionally, the control command includes a trigger condition and a position of the target data in the target data packet. The trigger condition refers to a condition for triggering the target data. The trigger condition includes description information of the target data packet. The description information is used to describe the target data packet. The description information can include a packet type of the target data packet. In this way, the host 40 can specify the packet type of the data packet in which the target data is located through the description information, so that the data processing card 20 can parse the target data from the data packet (i.e., the target data packet) of the packet type. When the target data in the target data packet of different packet types is required, the host 40 can specify the packet type to trigger the data processing card 20 to obtain the target data in the target data packet of different packet types.

[0073] When the target data packet is a packet of a target IO protocol, an IO protocol model of the target IO protocol includes multiple layers, such as a physical layer, a data link layer, a network layer, a transport layer, a session layer, a presentation layer, and an application layer. The packet of the target IO protocol includes a packet corresponding to each layer. Optionally, the description information includes an identifier of a layer corresponding to the target data packet. In this way, the host 40 can specify the layer corresponding to the data packet in which the target data is located through the description information, so that the data processing card 20 can parse the target data from the data packet (i.e., the target data packet) of the specified layer. When the target data in the target data packet of different layers is required, the host 40 can specify the layer of the target data packet to trigger the data processing card 20 to obtain the target data in the target data packet of different layers.

[0074] Optionally, the control command comprises an identification of a transmission mode of the target data, the transmission mode refers to a mode in which the control chip 22 transmits the target data to the host 40, the transmission mode can be a real-time transmission mode or an offline transmission mode, wherein the real-time transmission mode refers to that the control chip 22 transmits the target data to the host 40 as soon as the target data is acquired. The offline transmission mode refers to that the control chip 22 caches the target data as soon as the target data is acquired, and then transmits the cached target data to the host 40. In some embodiments, the transmission mode of the target data is agreed upon by the control chip 22 and the host 40 in advance, and the control command does not comprise the identification of the transmission mode of the target data.

[0075] As shown in Figure 4 The control chip 22 has a data acquisition function, the data acquisition function comprises acquiring the target data from the data transmission circuit 21 and reporting the acquired target data to the host 40, so that the host 40 performs prototype verification on the target function of the chip based on the target data. For example, the host 40 performs data analysis on the target data to perform prototype verification on the target function of the chip.

[0076] For example, the control chip 22 is also configured to receive a control command of the host 40, acquire the target data from a target data packet transmitted by the data transmission circuit 21 based on the control command, and send the target data to the host 40. For example, the host 40 sends a control command to the communication interface 23 of the data processing card 20, and the control chip 22 receives the control command through the communication interface 23. During the data interaction process of the DUT 11 and the IO device 30, the control chip 22 determines a target data packet from the data packets transmitted by the data transmission circuit 21 in the data interaction process based on the trigger condition in the control command, analyzes the target data from the target data packet, and transmits the analyzed target data to the host 40 according to the agreed transmission mode or the transmission mode specified by the control command.

[0077] Since all data packets in the data interaction process pass through the data transmission circuit 21, in some embodiments, the control chip 22 can also control the data transmission circuit 21 to acquire the target data, so as to improve the acquisition efficiency of the target data.

[0078] For example, the control chip 22 is also configured to send a data acquisition request signal to the data transmission circuit 21 based on the control command. The data acquisition request signal indicates to acquire the target data, the data acquisition request signal is a signal carrying a data acquisition request, the data acquisition request indicates to acquire the target data, and the data acquisition request comprises the trigger condition carried by the control command. For example, the control chip 22 analyzes the trigger condition from the control command and sends the data acquisition request signal to the data transmission circuit 21 based on the trigger condition.

[0079] ​The data transmission circuit 21 is further configured to parse target data from the target data message based on the received data acquisition request signal, and transmit the parsed target data to the control chip 22.

[0080] For example, the data transmission circuit 21 receives the data acquisition request signal of the control chip 22, parses the trigger condition from the data acquisition request signal, and takes the data message meeting the trigger condition in the received data message (including the first data message, the second data message, the third data message, and the fourth data message) as the target data message. Taking the description information included in the trigger condition message as an example, it is assumed that the description information includes the message type of the target data message, and the data message with the message type is transmitted as the target message. It is further assumed that the description information includes the identification of a certain level in the IO protocol model of the target IO protocol, and the data message corresponding to the level is transmitted as the target message. The data transmission circuit 21 parses the target data from the target data message and transmits the parsed target data to the control chip 22. For example, based on the parsed target data, a data acquisition response signal is returned to the control chip 22, the data acquisition response signal is a signal carrying a data acquisition response, and the data acquisition response includes the target data. Alternatively, the data acquisition response further includes the execution status of the data acquisition request, for example, if the target data is acquired, the execution status is an execution completion status, indicating that the data acquisition request is executed successfully, and if the target data is not acquired, the execution status is an execution incomplete status, indicating that the data acquisition request fails.

[0081] In the case where the data transmission circuit 21 includes the speed bridge 211, the speed bridge 211 is further configured to parse target data from the target data message based on the received data acquisition request signal, and transmit the parsed target data to the control chip 22. Figure 3 For example, the control chip 22 transmits a data acquisition request signal to the speed bridge 211, the speed bridge 211 parses the trigger condition from the received data acquisition request signal, takes the data message meeting the trigger condition in the received data message as the target data, parses the target data from the target data message, and transmits the parsed target data to the control chip 22. There are multiple target data messages, and the speed bridge 211 can transmit the parsed target data to the control chip 22 after parsing the target data from each target data message, or can first cache the parsed target data, and then transmit the cached target data to the control chip 22 after the cached target data reaches a certain amount.

[0082] The control chip 22 is further configured to receive the target data returned by the data transmission circuit 21 based on the data acquisition request signal.

[0083] After receiving the target data, the control chip transmits the target data to the host according to the agreed transmission mode or the transmission mode specified by the control command, so as to realize reporting the target data to the host. Figure 3 For example, the communication interface 23 is connected with the host 40, and the control chip 22 sends the target data to the host 40 through the communication interface 23, and the host 40 receives the target data. If the communication interface 23 is connected with the host 40 through a gateway, the control chip 22 sends the target data to the gateway through the communication interface 23, the gateway forwards the target data to the host 40, and the host 40 receives the target data forwarded by the gateway.

[0084] The control chip 22 obtains a plurality of target data from the data transmission circuit 21, and transmits the plurality of target data to the host 40. The host 40 receives the plurality of target data, and performs prototype verification on the target function of the chip based on the plurality of target data. For example, data analysis is performed on the plurality of target data, and prototype verification is performed on the target function of the chip according to the analysis result.

[0085] The data processing card in the related art includes a speed bridge and a PHY, but the speed bridge in the related art only supports the auxiliary DUT and the IO device to interact with data, and does not support analyzing data messages. Compared with the data processing card in the related art, in the data processing card 20 provided in the embodiment of the present disclosure, the function of the speed bridge is strengthened, so that the speed bridge can analyze the target data from the data message, and additionally, the communication interface 23 is additionally added, so that the host 40 can be connected with and communicate with the data processing card 20, and additionally, the control chip 22 is additionally added, so that the control chip 22 can obtain the target data from the speed bridge, so that the data processing card 20 can obtain the target data through its own internal circuit, thereby not needing to analyze the target data from the data message transmitted by the data processing card 20 through an additional hardware device (such as a protocol analyzer), and further being capable of reducing the hardware cost of chip prototype verification.

[0086] The data processing card 20 provided in the embodiment of the present disclosure can assist the IO device 30 and the measured device in the prototype verification device 10 to interact with data through the internal data transmission circuit 21, and the control chip 22 can obtain the target data in the data interaction process from the data transmission circuit 21 and transmit the target data to the host 40, so that an additional hardware device (such as a protocol analyzer) does not need to be connected in series between the data processing card 20 and the IO device 30, and the target data does not need to be captured through the additional hardware device, thereby being capable of reducing the hardware cost of chip prototype verification.

[0087] In some embodiments, as Figure 4As shown, the control chip 22 also has a firmware management function, which is used to manage firmware of the speed bridge 211 and firmware of the data processing card 20. The firmware management function of the speed bridge 211 includes loading firmware of the speed bridge 211 to the speed bridge 211 and updating the firmware of the speed bridge 211. The firmware management function of the data processing card 20 includes loading firmware of the data processing card 20 and updating the firmware of the data processing card 20. The firmware of the speed bridge 211 is the bottom software of the speed bridge 211, which is responsible for the basic functions of the speed bridge 211. The firmware of the data processing card 20 refers to the system firmware of the data processing card 20, which is the bottom software of the entire system of the data processing card 20 and is responsible for the basic functions of the data processing card 20.

[0088] For example, the control chip 22 is also used to load the firmware of the speed bridge 211 from the host 40 to the speed bridge 211. For example, the control chip 22 obtains the firmware of the speed bridge 211 from the host 40, loads the obtained firmware of the speed bridge 211 to the speed bridge 211, and the speed bridge 211 runs the loaded firmware to realize the functions of the speed bridge 211. The firmware of the speed bridge 211 supports updating, and the host 40 can extend the functions of the speed bridge 211 by updating the firmware of the speed bridge 211. When updating the firmware of the speed bridge 211, the host 40 can load the updated firmware of the speed bridge 211 from the host 40 in this way, and the speed bridge 211 runs the updated firmware to extend the functions of the speed bridge 211. In a similar manner, the control chip 22 can also load the firmware of the data processing card 20 or the updated firmware of the data card from the host 40.

[0089] For another example, referring to Figure 3 The data processing card 20 further includes a first storage chip 24 connected with the control chip 22, and the first control chip 22 is located in the PoB system. The first storage chip 24 is a storage chip supporting firmware storage, for example, the first storage chip 24 includes but is not limited to a flash memory.

[0090] The firmware of the speed bridge 211 is stored in the first storage chip 24, and the control chip 22 is also used to load the firmware of the speed bridge 211 from the first storage chip 24 to the speed bridge 211. The speed bridge 211 runs the loaded firmware to realize the functions of the speed bridge 211. In each time of loading the firmware of the speed bridge 211, the loading of the firmware of the speed bridge 211 can be completed inside the data processing card 20 in this way, without the need to load the firmware of the speed bridge 211 from the host 40 each time, which can improve the loading efficiency of the firmware of the speed bridge 211.

[0091] In some embodiments, the speed bridge 211 has multiple firmware, different firmware of the speed bridge 211 supports different input / output protocols (i.e. IO protocols), the speed bridge 211 runs the firmware supporting any IO protocol, so that the speed bridge 211 can support transmission and parsing of packets encapsulated based on the IO protocol (i.e. packets of the IO protocol). The first control chip 22 stores multiple firmware of the speed bridge 211. When the IO functions of the chip are prototyped for different IO protocols, the firmware of the speed bridge 211 supporting the corresponding IO protocol can be loaded from the first storage chip 24 to the speed bridge 211 as needed, so that the speed bridge 211 can transmit and parse the packets of the corresponding IO protocol to meet the needs of different prototyping.

[0092] For example, the IO protocol used to encapsulate the first data packet and the second data packet is referred to as the target IO protocol, i.e. the first data packet and the second data packet are both packets of the target IO protocol, and the firmware of the multiple firmware of the speed bridge 211 supporting the target IO protocol is referred to as the target firmware.

[0093] The control chip 22 is also configured to load the target firmware of the multiple firmware of the speed bridge 211 from the first storage chip 24 to the speed bridge 211. The target firmware supports the target IO protocol, i.e. the target firmware is the firmware of the speed bridge 211 supporting the target IO protocol. Before receiving the first data packet and the second data packet, the control chip 22 first loads the target firmware from the first storage chip 24 to the speed bridge 211, and runs the target firmware by the speed bridge 211, so that the speed bridge 211 can identify, parse and transmit the data packets of the target IO protocol.

[0094] The first storage chip 24 also stores the firmware of the data processing card 20, and the control chip 22 can load the firmware of the data processing card 20 from the first storage chip 24 and run the firmware of the data processing card 20. Alternatively, the control chip 22 does not load the firmware of the data processing card 20, but directly runs the firmware of the data processing card 20 in the first storage chip 24.

[0095] The first storage chip 24 is an optional component in the data processing card 20, and in some embodiments, the data processing card 20 does not include the first storage chip 24 (such as when the data processing card 20 is a hardware accelerator card). Figure 2In some embodiments, as shown in FIG. 2, the control chip 22 further has a speed bridge 211 reset control function, which is used to control the speed bridge 211, such as controlling the speed bridge 211 to reset or controlling the speed bridge 211 to extract target data. Taking the control of the speed bridge 211 to reset as an example, the data transmission circuit 21 further includes a reset control circuit, which is connected with the speed bridge 211 and the control chip 22. The control chip 22 is further configured to send a reset signal to the reset control circuit in response to the speed bridge 211 satisfying a reset condition, the reset signal indicating to reset the speed bridge 211. Correspondingly, the reset control circuit is configured to reset the speed bridge 211 based on the received reset signal.

[0096] In some embodiments, as shown in FIG. 2, the control chip 22 further has a speed bridge 211 reset control function, which is used to control the speed bridge 211, such as controlling the speed bridge 211 to reset or controlling the speed bridge 211 to extract target data. Taking the control of the speed bridge 211 to reset as an example, the data transmission circuit 21 further includes a reset control circuit, which is connected with the speed bridge 211 and the control chip 22. The control chip 22 is further configured to send a reset signal to the reset control circuit in response to the speed bridge 211 satisfying a reset condition, the reset signal indicating to reset the speed bridge 211. Correspondingly, the reset control circuit is configured to reset the speed bridge 211 based on the received reset signal. Figure 4

[0097] In some embodiments, as shown in FIG. 2, the control chip 22 further has a speed bridge 211 reset control function, which is used to control the speed bridge 211, such as controlling the speed bridge 211 to reset or controlling the speed bridge 211 to extract target data. Taking the control of the speed bridge 211 to reset as an example, the data transmission circuit 21 further includes a reset control circuit, which is connected with the speed bridge 211 and the control chip 22. The control chip 22 is further configured to send a reset signal to the reset control circuit in response to the speed bridge 211 satisfying a reset condition, the reset signal indicating to reset the speed bridge 211. Correspondingly, the reset control circuit is configured to reset the speed bridge 211 based on the received reset signal.

[0098] In some embodiments, as shown in FIG. 2, the control chip 22 further has a speed bridge 211 reset control function, which is used to control the speed bridge 211, such as controlling the speed bridge 211 to reset or controlling the speed bridge 211 to extract target data. Taking the control of the speed bridge 211 to reset as an example, the data transmission circuit 21 further includes a reset control circuit, which is connected with the speed bridge 211 and the control chip 22. The control chip 22 is further configured to send a reset signal to the reset control circuit in response to the speed bridge 211 satisfying a reset condition, the reset signal indicating to reset the speed bridge 211. Correspondingly, the reset control circuit is configured to reset the speed bridge 211 based on the received reset signal. Figure 4 In some embodiments, as shown in FIG. 2, the control chip 22 further has a speed bridge 211 reset control function, which is used to control the speed bridge 211, such as controlling the speed bridge 211 to reset or controlling the speed bridge 211 to extract target data. Taking the control of the speed bridge 211 to reset as an example, the data transmission circuit 21 further includes a reset control circuit, which is connected with the speed bridge 211 and the control chip 22. The control chip 22 is further configured to send a reset signal to the reset control circuit in response to the speed bridge 211 satisfying a reset condition, the reset signal indicating to reset the speed bridge 211. Correspondingly, the reset control circuit is configured to reset the speed bridge 211 based on the received reset signal.

[0099] Figure 3 ​​For example, the data processing card 20 further comprises a second storage chip 25, the second storage chip 25 is connected with the control chip 22, and the second control chip 22 is located in the PoB system. The second storage chip 25 is the memory of the data processing card 20, and is used to provide a cache space for the control chip 22. The second storage chip 25 can be a non-transient storage. The non-transient storage can be a volatile storage or a non-volatile storage, or the non-transient storage can include a volatile storage and a non-volatile storage. The volatile storage is, for example, a random access memory (RAM), a double data rate (DDR) memory, a static random access memory (SRAM) or the like. The non-volatile storage is, for example, a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid state drive (SSD) or the like.

[0100] The control chip 22 is further configured to cache the obtained target data into the second storage chip 25, and in response to the size of the free storage space of the second storage chip 25 being less than or equal to a first threshold, send the target data in the second storage chip 25 to the host 40. The free storage space is the storage space that is free in the second storage chip 25 (i.e., the storage space that does not store data), and the first threshold can be reasonably set according to a specific application scenario. In this embodiment of the present disclosure, the first threshold is not limited.

[0101] For example, the control chip 22 obtains a plurality of target data from the stored data, and caches the obtained target data into the second storage chip 25 every time a target data is obtained. As the number of obtained target data increases, the free storage space of the second storage chip 25 is gradually occupied, and the size of the free storage space becomes smaller and smaller, until the size of the free storage space is less than or equal to the first threshold. The control chip 22 then sends all the target data cached in the second storage chip 25 to the host 40, releases the storage space occupied by the target data in the second storage chip 25, increases the size of the free storage space of the second storage chip 25, and enables the control chip 22 to continue to cache target data using the second storage chip 25. In this way, the target data is sent to the host 40 offline, and the control chip 22 does not need to immediately send the obtained target data to the host 40 every time a target data is obtained, thereby reducing the working pressure of the control chip 22 and improving the working efficiency of the control chip 22.

[0102] The host 40 runs host software (referred to as a host computer) which interacts with the data processing card 20 to obtain target data from the data processing card 20, and the host 40 performs prototype verification on the target function of the chip based on the target data through the host computer. Next, taking Figure 3 , as an example, the interaction process between the host computer and the data processing card 20 is introduced as follows. After the prototype verification platform is powered on and runs, the interaction process shown in Figure 5 is started, and the interaction process includes the following steps. Figure 5

[0103] 51. The data processing card 20 is reset after being powered on, and the data processing card 20 enters the following step 52 after completing the reset.

[0104] 52. The PoB system in the data processing card 20 is reset, and after the reset is completed, the PoB system is initialized. After the PoB system completes the initialization, it enters the following step 53.

[0105] 53. The PoB system loads and runs the firmware of the data processing card 20, and in the process of running the firmware of the data processing card 20, the SA system in the data processing card 20 is initialized.

[0106] 54. The PoB system waits for the SA system to complete the initialization and to have normal work.

[0107] The SA system can assist the DUT 11 and the IO device 30 to interact data when the SA system works normally. In the waiting process, the PoB system reads the working state of the SA system, judges whether the currently read working state of the SA system is a ready state, if it is the ready state, continues to read the working state of the SA system, until the read working state is the ready state, indicating that the SA system completes the initialization and has normal work, then enters the following step 55.

[0108] 55. When the SA system works normally, the PoB system starts to broadcast the state of the data processing card 20 (such as sending broadcast data, the broadcast data including a ready completion identifier of the data processing card 20).

[0109] 56. The PoB system waits for the host computer to connect, and after the host computer and the PoB system establish a connection, the PoB system starts to wait for the host computer to send a control command.

[0110] For example, after the host computer receives the broadcast data of the PoB system, it determines that the PoB system is ready to extract target data according to the ready completion identifier in the broadcast data, establishes a connection with the PoB system, and sends a control command to the PoB system through the established connection. ​

[0111] 57. After the host computer issues a control command, the control information carried by the control command (such as trigger conditions and data transmission methods) is obtained.

[0112] 58. The PoB system synchronizes the control information to the SA system.

[0113] 59. The SA system extracts target data from the target data message according to the control information, and uploads the extracted target data to the PoB system.

[0114] 510. The PoB system receives the target data uploaded by the SA system, and uploads the target data to the host computer.

[0115] 511. The host computer processes the target data uploaded by the PoB system.

[0116] For example, the data format of the target data is adjusted so that the target data after format modification is convenient for data analysis. Or, the target data is screened to screen out effective target data for data analysis.

[0117] 512. The host computer performs data analysis on the target data, and saves the data analysis result. The data analysis result is used for prototype verification of the target function of the chip, or the data analysis result is a verification structure for prototype verification of the target function of the chip.

[0118] In the process of steps 51 to 512, the steps performed by the PoB system are completed by the control chip 22 in the PoB system, and the steps performed by the SA system are completed by the SA in the SA system.

[0119] In some embodiments, the host computer includes a PoB control system and a data analysis system, wherein the PoB control system is used to control the PoB system. The PoB control system is used to scan the available PoB systems, and establish a communication channel with the PoB systems; analyze the broadcast data of the online PoB systems, so as to confirm the SA system type and the corresponding IO type supported by the PoB system; issue control information to the PoB system; update the firmware of the data processing card 20 and the firmware of the SA; process the state information (such as the execution state in the data acquisition response) of the SA system forwarded by the PoB system; obtain the target data uploaded by the PoB system, and upload the target data to the data analysis system.

[0120] The data analysis system is used to perform prototype verification of the target function of the chip based on the uploaded target data. For example, the uploaded target data is analyzed, and the data analysis result is maintained.

[0121] The embodiments of the present disclosure also provide a data processing method applied to a data processing card, which includes the following steps S1 and S2.

[0122] S1, the data processing card receives a first data message, transmits the first data message to an IO device, receives a second data message, and transmits the second data message to a device under test in the prototype verification device; wherein the first data message is a data message sent by a device under test in the prototype verification device, and the second data message is a data message sent by the IO device.

[0123] The data processing card is the data processing card 20 described above. Step S1 can be performed by an input / output circuit in the data processing card. That is, the first data message and the second data message are received and sent by a data transmission circuit in the data processing card.

[0124] Optionally, the data transmission circuit includes a speed bridge; and the receiving the first data message, transmitting the first data message to the IO device, receiving the second data message, and transmitting the second data message to the device under test in the prototype verification device include: The speed bridge receives the first data message, transmits the first data message to the IO device at a second data transmission speed, receives the second data message, and transmits the second data message to the device under test at a first data transmission speed, the first data transmission speed and the second data transmission speed being different.

[0125] S2, the data processing card receives a control command of a host, obtains target data from a target data message transmitted based on the control command, and sends the target data to the host; wherein the control command instructs the control chip to report the target data carried by the target data message, and the target data message includes the first data message and / or the second data message.

[0126] Optionally, the first data message and the second data message are received and sent by a data transmission circuit in the data processing card, and the obtaining target data from a target data message transmitted based on the control command includes: The control chip in the data processing card sends a data acquisition request signal to the data transmission circuit based on the control command, the data acquisition request signal instructing to acquire the target data; The data transmission circuit parses the target data from the target data message based on the received data acquisition request signal, and sends the parsed target data to the control chip; The control chip receives the target data.

[0127] Optionally, the data transmission circuit includes a speed bridge, and the data transmission circuit is configured to parse the target data from the target data packet based on the received data acquisition request signal, and send the parsed target data to the control chip. The speed bridge is configured to receive the data acquisition request signal, parse the target data from the target data packet based on the data acquisition request signal, and send the parsed target data to the control chip.

[0128] Optionally, the method further includes: The control chip loads the firmware of the speed bridge from the host to the speed bridge.

[0129] Optionally, the data processing card further includes a first storage chip, and the method further includes: The control chip loads the firmware of the speed bridge from the first storage chip to the speed bridge.

[0130] Optionally, the first storage chip stores a plurality of firmwares of the speed bridge, and different firmwares support different input / output protocols; the first data packet and the second data packet are both packets of a target input / output protocol. The control chip loads the firmware of the speed bridge from the first storage chip to the speed bridge includes: The control chip loads a target firmware from the first storage chip to the speed bridge, and the target firmware supports the target input / output protocol.

[0131] Optionally, the data transmission circuit further includes a reset control circuit; and the method further includes: The control chip sends a reset signal to the reset control circuit in response to the speed bridge satisfying a reset condition, and the reset signal indicates resetting the speed bridge. The reset control circuit resets the speed bridge based on the received reset signal.

[0132] Optionally, the data processing card further includes a second storage chip, and the sending the target data to the host includes: The control chip caches the acquired target data into the second storage chip, and sends the target data in the second storage chip to the host in response to a size of a free storage space of the second storage chip being less than or equal to a first threshold.

[0133] The data processing method provided by the present disclosure can assist the IO device and the DUT in the prototype verification device in data interaction through the data transmission circuit inside the data processing card, and the control chip inside the data processing card can obtain the target data in the data interaction process from the data transmission circuit and transmit the target data to the host, so that the additional hardware device (such as a protocol analyzer) does not need to be connected in series between the data processing card and the IO device, and the target data does not need to be captured through the additional hardware device, thereby reducing the hardware cost of chip prototype verification.

[0134] It should be understood that the data processing method provided by the present disclosure belongs to the same inventive concept as the data processing card 20 described above, and the features of the data processing card 20 described above also apply to the data processing method.

[0135] All the optional technical solutions described above can be combined to form optional embodiments of the present disclosure, which will not be described one by one here.

[0136] In an example embodiment, a host is also provided, which includes a processor and a memory, and the memory stores at least one instruction, and the processor executes the at least one instruction to enable the host to implement the steps performed by the host 40 provided in each of the above embodiments.

[0137] In an example embodiment, a computer readable storage medium including at least one instruction is also provided, for example, a memory including at least one instruction, and the at least one instruction can be executed by a processor in a host to complete the steps performed by the host 40 in each of the above embodiments. Alternatively, the computer readable storage medium can be a non-transitory computer readable storage medium, for example, the non-transitory computer readable storage medium can include ROM, RAM, compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0138] In an example embodiment, a computer program product is also provided, which includes one or more instructions that can be executed by a processor of a host to complete the steps performed by the host 40 provided in each of the above embodiments.

[0139] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the aspects of the present disclosure disclosed herein. It is intended that the present disclosure cover any and all variations of the present disclosure that come within the scope of the claims and their equivalents. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0140] It should be understood that the present disclosure is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A data processing card, characterized in that, The data processing card includes a data transmission circuit and a control chip, and the data transmission circuit is connected to the control chip. The data transmission circuit is used to connect the prototype verification device and the input / output device; The control chip is used to connect to the host computer; The data transmission circuit is further configured to receive a first data packet, transmit the first data packet to the input / output device, receive a second data packet, and transmit the second data packet to the device under test in the prototype verification device; wherein, the first data packet is a data packet sent by the device under test, and the second data packet is a data packet sent by the input / output device; The control chip is further configured to receive control commands from the host, obtain target data from the target data packet transmitted by the data transmission circuit based on the control commands, and send the target data to the host; wherein, the control commands instruct the control chip to report the target data carried in the target data packet, and the target data packet includes the first data packet and / or the second data packet.

2. The data processing card according to claim 1, characterized in that, The control chip is also used to send a data acquisition request signal to the data transmission circuit based on the control command, wherein the data acquisition request signal indicates that the target data is acquired. The data transmission circuit is further configured to parse the target data from the target data message based on the received data acquisition request signal, and send the parsed target data to the control chip; The control chip is also used to receive the target data.

3. The data processing card according to claim 2, characterized in that, The data transmission circuit includes a speed bridge, which is connected to the control chip. The speed bridge is used to connect the prototype verification device and the input / output device; The speed bridge is also used to receive the first data packet, transmit the first data packet to the input / output device using the second data transmission speed, receive the second data packet, and transmit the second data packet to the device under test using the first data transmission speed, wherein the first data transmission speed and the second data transmission speed are different; The speed bridge is also used to receive the data acquisition request signal, parse the target data from the target data message based on the data acquisition request signal, and send the parsed target data to the control chip.

4. The data processing card according to claim 3, characterized in that, The control chip is also used for: The firmware of the speed bridge is loaded from the host to the speed bridge.

5. The data processing card according to claim 3, characterized in that, The data processing card further includes a first storage chip, which is connected to the control chip, and stores the firmware of the speed bridge in the first storage chip; The control chip is also used to load the firmware of the speed bridge from the first storage chip into the speed bridge.

6. The data processing card according to claim 5, characterized in that, The first memory chip stores multiple firmware files for the speed bridge, and different firmware files support different input / output protocols; both the first data packet and the second data packet are packets of the target input / output protocol; The control chip is also used to load the target firmware from the first storage chip into the speed bridge from the plurality of firmware, wherein the target firmware supports the target input / output protocol.

7. The data processing card according to any one of claims 3-6, characterized in that, The data transmission circuit further includes a reset control circuit, which is connected to the speed bridge and the control chip. The control chip is also configured to send a reset signal to the reset control circuit in response to the speed bridge meeting the reset condition, the reset signal indicating that the speed bridge should be reset; The reset control circuit is used to reset the speed bridge based on the received reset signal.

8. The data processing card according to any one of claims 1-6, characterized in that, The data processing card also includes a second storage chip, which is connected to the control chip. The control chip is further configured to cache the acquired target data in the second storage chip, and send the target data in the second storage chip to the host in response to the size of the free storage space of the second storage chip being less than or equal to a first threshold.

9. A data processing method, characterized in that, Applied to a data processing card, the method includes: The device receives a first data packet, transmits the first data packet to an input / output device, receives a second data packet, and transmits the second data packet to the device under test in the prototype verification device; wherein, the first data packet is a data packet sent by the device under test in the prototype verification device, and the second data packet is a data packet sent by the input / output device; The system receives a control command from the host, obtains target data from the transmitted target data packet based on the control command, and sends the target data to the host; wherein the control command instructs the control chip to report the target data carried in the target data packet, and the target data packet includes the first data packet and / or the second data packet.

10. A data processing system, characterized in that, The data processing system includes a data processing card, a prototype verification device, input / output devices, and a host computer. The data processing card is connected to the prototype verification device, the input / output devices, and the host computer. The device under test in the prototype verification device is used to send a first data message to the data transmission circuit in the data processing card. The input / output device is used to send a second data message to the data transmission circuit; The data transmission circuit is configured to receive the first data packet, transmit the first data packet to the input / output device, receive the second data packet, and transmit the second data packet to the device under test. The host is used to send a control command to the control chip in the data processing card. The control command instructs the control chip to report the target data carried in the target data packet. The target data packet includes the first data packet and / or the second data packet. The control chip is used to receive control commands from the host, obtain target data from the target data packet transmitted by the data transmission circuit based on the control commands, and send the target data to the host. The host is also used to receive the target data and perform data analysis on the target data.

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