Display driving chip, driving method thereof and display device

Abstract

The invention discloses a display driving chip, a driving method thereof and a display device, and relates to the field of display. Detecting an external time sequence parameter of the input signal, and comparing the external time sequence parameter with a preset target safety time sequence parameter; real-time adjustment is carried out according to whether the number of effective pixel rows and / or columns of the external time sequence parameters is completely consistent with the number of pixel rows and / or columns of an effective display area of a display panel or not and whether a blanking period of the external time sequence parameters covers a virtual pixel area of the display panel or not, so that it is ensured that the virtual pixel area is not mistakenly activated; outputting a time sequence signal according to the adjusted external time sequence parameter; and judging whether the output time sequence corresponds to the period of the virtual pixel region or not, and if the output time sequence corresponds to the period of the virtual pixel region, prohibiting the output of an effective signal so as to ensure that the virtual pixel region is kept in an inactive state. According to the invention, the dual guarantee of avoiding false activation of the virtual pixel region is realized by adjusting the external time sequence parameters and a physical disconnection mode.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a display driver chip, its driving method, and a display device. Background Technology

[0002] Current display panels include an effective display area and a virtual display area, also known as a dummy area, surrounding the effective display area. The virtual pixel area is a virtual display area manufactured using the same materials and similar material structure as the effective display area. It has the function of mitigating screen burn-in by shifting pixels. The principle is: by periodically shifting the display image by a small amount, the same image content will not stay on the same physical pixel for a long time, thus sharing the pressure of pixel aging, extending the screen life, and meeting the process requirements at the same time.

[0003] However, when the aforementioned display panel is connected to an external projection device such as a computer, mobile phone, or TV box, unexpected bright lines or bright blocks appear in the virtual display area, i.e., there is a problem of abnormal lighting in the virtual pixel area. Therefore, based on the above reasons, this invention designs a display driver chip and its driving method, as well as a display device. Summary of the Invention

[0004] The purpose of this invention is to solve the problem that in the prior art, the driver chip is prone to transmitting data incorrectly to the virtual pixel area, causing it to malfunction. The invention proposes a display driver chip, its driving method, and a display device.

[0005] On one hand, the present invention provides a driving method for a display driver chip, comprising: Receive external input signals; The input signal is subjected to detection of external timing parameters, and compared with preset target security timing parameters; The system makes real-time adjustments based on whether the effective number of pixel rows and / or columns of the external timing parameters is completely consistent with the effective number of pixel rows and / or columns of the display panel and whether the blanking period of the external timing parameters covers the virtual pixel area of ​​the display panel, so as to ensure that the virtual pixel area is not mistakenly activated. The timing signal is output according to the adjusted external timing parameters; it is determined whether the output timing corresponds to the period of the virtual pixel area. If it corresponds to the period of the virtual pixel area, the output of the valid signal is prohibited to ensure that the virtual pixel area remains inactive.

[0006] In the above method, whether the blanking period of the external timing parameter covers the virtual pixel area of ​​the display panel includes: Whether the vertical blanking period of the external timing parameter covers the upper and lower virtual pixel rows of the virtual pixel area of ​​the display panel, and whether the horizontal blanking period of the external timing parameter covers the left and right virtual pixel columns of the virtual pixel area.

[0007] In the above method, real-time adjustment is performed based on whether the effective number of pixel rows and / or columns of the external timing parameters is completely consistent with the effective number of pixel rows and / or columns of the display panel, including: When the number of valid pixel rows and / or columns of the external timing parameters exceeds the number of pixel rows and / or columns of the effective display area, the excess valid pixel rows and / or columns of the external timing parameters are automatically cropped. Furthermore, the vertical blanking period of the external timing parameters is adjusted in real time to ensure that it covers the upper and lower virtual pixel rows of the virtual pixel area of ​​the display panel, and the horizontal blanking period of the external timing parameters covers the left and right virtual pixel columns of the virtual pixel area, including: When the vertical blanking period of the external timing parameter is less than the upper and lower virtual pixel rows of the virtual pixel area, and / or the horizontal blanking period of the external timing parameter is less than the left and right virtual pixel columns, blank rows and / or column pixels or safety level signals are inserted into the data path.

[0008] In the above method, determining whether the output timing corresponds to the period of the virtual pixel area, and if it does, then prohibiting the output of a valid signal to ensure that the virtual pixel area remains inactive, includes: Determine whether the output timing corresponds to the period of the upper and lower virtual pixel rows of the virtual pixel area. If so, forcibly prohibit the output of a valid start scan signal. Determine whether the output timing corresponds to the period of the left and right virtual pixel columns of the virtual pixel area. If so, force the output voltage to a preset safe level.

[0009] In the above method, determining whether the output timing corresponds to the period of the virtual pixel region includes: If, within the period corresponding to the effective display area, the scan lines and data lines of the virtual pixel area are disconnected by controlling the switch matrix, or the scan lines and data lines of the virtual pixel area are made to be in a high-impedance state.

[0010] On the other hand, the present invention also provides a display driver chip, comprising: The input module is used to receive external input signals; The timing analysis and remapping module is used to detect external timing parameters of the input signal, compare them with preset target safe timing parameters, and make real-time adjustments based on whether the effective number of pixel rows and / or columns of the external timing parameters are completely consistent with the effective number of pixel rows and / or columns of the display panel and whether the blanking period of the external timing parameters covers the virtual pixel area of ​​the display panel, so as to ensure that the virtual pixel area is not mistakenly activated. The control module is used to receive the output timing signal of the adjusted external timing parameters and determine whether the output timing corresponds to the period of the virtual pixel area. If it corresponds to the period of the virtual pixel area, the output of the valid signal is prohibited to ensure that the virtual pixel area remains inactive.

[0011] In the aforementioned display driver chip, the timing analysis and remapping module includes: The timing detection unit is used to detect the external timing parameters of the input signal in real time. The external timing parameters include the total number of horizontal rows, the number of effective horizontal rows, the horizontal leading edge, the total number of vertical columns, the number of effective vertical columns, the vertical leading edge, and the vertical trailing edge. A parameter comparison unit is used to compare the external timing parameters with preset target safety timing parameters. The dynamic adjustment unit is used to adjust the external timing parameters in real time based on the comparison results to ensure that the virtual pixel area is not mistakenly activated.

[0012] In the aforementioned display driver chip, the control module includes: A row driving circuit is used to receive the output timing signal of the adjusted external timing parameters and to drive the scan line; A column driver circuit is used to receive the output timing signal and to drive the data lines; The scanning control unit is used to control the row driving circuit to forcibly disable the output of the scanning signal at the on level during the period of the upper and lower virtual pixel rows corresponding to the virtual pixel area of ​​the output timing parameters; The data control unit is used to control the column driving circuit to force the data line voltage to a preset safe level during the period of the left and right virtual pixel columns corresponding to the virtual pixel area of ​​the output timing parameters.

[0013] The aforementioned display driver chip also includes a switch matrix for signal transmission with the virtual pixel area; the switch matrix includes a row-side switch matrix and a column-side switch matrix. The input terminal of the row-side switch matrix is ​​electrically connected to the row drive circuit, and its output terminal is electrically connected to the scan line column of the effective display area and the virtual pixel area; The input terminal of the column-side switch matrix is ​​electrically connected to the column drive circuit, and its output terminal is electrically connected to the data lines of the effective display area and the virtual pixel area.

[0014] In addition, the present invention also provides a display screen device, comprising: The display panel and the aforementioned display driver chip, wherein the display panel includes an effective display area and a virtual pixel area surrounding the display area.

[0015] The beneficial effects of this invention are as follows: 1. This invention avoids the false activation of virtual pixel areas by comparing and dynamically adjusting the timing parameters of the input signal with the safety timing parameters.

[0016] 2. By detecting whether the display panel covers the blanking period and effective area size of the input signal, and by dynamically trimming the excess data or filling the blanking data, the output timing is forced to match the physical structure of the display panel, thereby ensuring that the output timing parameters meet the safety timing parameter requirements.

[0017] 3. Within the timing window corresponding to the virtual pixel area, the virtual pixel area is prevented from being accidentally activated by a forced physical disconnection method. Attached Figure Description

[0018] Figure 1 A flowchart of a driving method for a display driver chip provided by the present invention; Figure 2 A schematic diagram of the structure of a display driver chip provided by the present invention; Figure 3 This is a schematic diagram of the structure of a display device provided by the present invention. Detailed Implementation

[0019] To facilitate understanding of this application and to make the aforementioned objectives, features, and advantages of this application more apparent, a detailed description of specific embodiments of this application is provided below in conjunction with the accompanying drawings. Numerous specific details are set forth in the following description to provide a thorough understanding of this application, and preferred embodiments are shown in the accompanying drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application. This application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise explicitly specified. It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementations. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is only for describing particular implementations and is not intended to limit the scope of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0020] First, some technical features will be explained, including: Effective display area: refers to the pixel area on the display panel that is actually used to display image content. For example, the effective display area of ​​a panel with a resolution of 1920x1080 is a rectangular area composed of 1920 column pixels and 1080 row pixels.

[0021] Virtual pixel area: Usually located around the effective display area, it is a pixel unit that is not designed for normal image display. It is used for process compensation during panel manufacturing or as a physical buffer. In the field of silicon-based OLED, the virtual pixel area can periodically shift the display image to prevent the same image content from staying on the same physical pixel for a long time, thus sharing the pressure of pixel aging.

[0022] External timing parameters: These refer to the timing information contained in the signals transmitted to the display driver chip from an external host (such as a computer, mobile phone, or TV box). These parameters may include the total number of horizontal rows, the number of effective horizontal rows, the leading edge of the horizontal row, the trailing edge of the horizontal row, the total number of vertical columns, the number of effective vertical columns, the leading edge of the vertical row, and the trailing edge of the vertical row.

[0023] This invention primarily addresses the problem in existing technologies where, when a display panel is connected to an external projection device such as a computer, mobile phone, or TV box, unexpected bright lines or patches appear in the virtual display area, indicating abnormal lighting of the virtual pixel area. Research has revealed that this phenomenon is caused by timing mismatches in the driver chips used in existing technologies. Specifically, there are significant differences in the timing of the video signals output by different devices, and some video signal timings even fail to meet the preset specifications of the display panel. This causes the display driver chip to incorrectly apply data or invalid levels that should be processed during the blanking period to the scan lines and data lines of the virtual pixel area, resulting in abnormal lighting. Therefore, based on the above research, this invention provides a driving method for a display driver chip, referring to... Figure 1 As shown It receives external input signals, including data, horizontal synchronization HSYNC, vertical synchronization VSYNC, clock, etc. The input signal is subjected to detection of external timing parameters, and compared with preset target security timing parameters; The system makes real-time adjustments based on whether the effective number of pixel rows and / or columns of the external timing parameters is completely consistent with the effective number of pixel rows and / or columns of the display panel and whether the blanking period of the external timing parameters covers the virtual pixel area of ​​the display panel, so as to ensure that the virtual pixel area is not mistakenly activated. The timing signal is output according to the adjusted external timing parameters; it is determined whether the output timing corresponds to the period of the virtual pixel area. If it corresponds to the period of the virtual pixel area, the output of the valid signal is prohibited to ensure that the virtual pixel area remains inactive.

[0024] The target security timing parameters are a set of preset target security timing parameters stored internally in the chip. These parameters are pre-configured based on the physical characteristics of the specific display panel currently connected, and include at least: The exact number of pixel rows and columns in the effective display area and virtual display area of ​​the display panel; The timing cycle range corresponding to the display panel.

[0025] The purpose of the comparison is to identify whether the timing specifications of the external input signal match the actual timing of the panel. If they do not match, there is a risk of activating virtual pixel areas. The reason for this risk is: On the one hand, there is a mismatch between the output signal parameters of external devices and the actual parameters of the display driver chip, which can easily lead to an excessively large effective area. For example, the number of rows and columns of the effective display area in the output signal parameters of the external device may not match the number of pixel rows and columns of the effective display area of ​​the display panel. When this happens, the virtual pixel area may be mistakenly activated. Therefore, this invention ensures that the virtual pixel area is not mistakenly activated by adjusting the external timing parameters to be completely consistent with the preset target safety timing parameters. At this time, the output timing is automatically adjusted to take the preset safety timing parameters as the standard, ignores the definition of the erroneous valid display area in the external signal, and ensures that the valid area in the timing of the final driving panel is strictly aligned with the physical valid area.

[0026] On the other hand, the blanking period of the external device output signal has the problem that it cannot completely cover the virtual pixel area of ​​the display panel. Therefore, the virtual pixel area can be ensured not to be accidentally activated by checking whether the blanking period in the external timing parameters can completely cover the virtual pixel area of ​​the display panel and adjusting it.

[0027] Specifically, if the blanking period of the external signal is too short to cover the entire virtual pixel area, the driver chip will extend the blanking period. Specifically, it will adjust the total horizontal period and / or the total vertical period to ensure that the adjusted blanking period can completely cover the virtual pixel area on the time axis. Depending on the design, it can be extended based on the external timing or replaced based on the internal safety timing. This step ensures that the virtual pixel area is always in the data invalid phase in time.

[0028] In one feasible embodiment, the problem that the blanking period in the timing parameters of the external device output signal cannot completely cover the virtual pixel area of ​​the display panel mainly includes the following situations: The vertical blanking period of the external timing parameters cannot cover the upper and lower virtual pixel rows of the virtual pixel area of ​​the display panel; Furthermore, the horizontal blanking period of the external timing parameters cannot cover the left and right virtual pixel columns of the virtual pixel area; When the vertical blanking period of the external timing parameters cannot cover the upper and lower virtual pixel rows of the display panel's virtual pixel area, it may be due to an inconsistency in the definition of their effective areas. The number of vertically effective rows in the external timing parameters input from the external device may be less than the number of physically effective display rows on the display panel. For example, the external signal may be defined as having 1080 effective rows, while the panel actually has 1080 effective rows plus one virtual row each at the top and bottom, totaling 1082 vertical pixels. If the total number of vertical rows for the external signal is also only 1080, then its vertical blanking period cannot cover the upper and lower virtual rows of the panel.

[0029] At the same time, even if the number of valid rows in the external signal is consistent with the effective display area of ​​the display panel, if its total vertical period is set too small, the calculated vertical blanking period will be insufficient to accommodate the virtual pixel area of ​​the display panel, resulting in some virtual pixel areas not being covered by the blanking period. When the above problem occurs, if the virtual pixel area is not completely covered by the blanking period, the driver chip will mistakenly identify these virtual rows as new valid image rows when the next valid signal is input. As a result, it will write random or residual data from the current input data bus into these virtual pixels, causing the virtual pixel areas on the top and bottom sides to be in an active state.

[0030] Similarly, when the horizontal blanking period of the external timing parameters is too short to cover the left and right virtual pixel columns of the virtual pixel area of ​​the display panel, the display driver chip may mistakenly write the data at the beginning of the next valid row into the virtual column that should be in the blanking state, causing the virtual pixel area on the side to be in the active state.

[0031] In one feasible embodiment, real-time adjustment is performed based on whether the effective number of pixel rows and / or columns of external timing parameters is completely consistent with the effective display area of ​​the display panel, including: When the number of valid pixel rows and / or columns of external timing parameters exceeds the number of pixel rows and / or columns of the effective display area, the excess valid pixel rows and / or columns of external timing parameters are automatically cropped. In addition, the vertical blanking period of the external timing parameters covers the upper and lower virtual pixel rows of the virtual pixel area of ​​the display panel, and the horizontal blanking period of the external timing parameters covers the left and right virtual pixel columns of the virtual pixel area, are adjusted in real time, including: When the vertical blanking period of the external timing parameter is less than the upper and lower virtual pixel rows of the virtual pixel area, and / or the horizontal blanking period of the external timing parameter is less than the left and right virtual pixel columns, blank rows and / or column pixels or safety level signals are inserted into the data path.

[0032] Regarding the issue of a mismatch between the number of effective pixel rows and columns in the output signal parameters of external devices and the number of pixel rows and columns in the effective display area of ​​the display panel, taking a problem with the horizontal leading edge as an example: The horizontal leading edge and horizontal trailing edge are signals output from external devices to the upper and lower sides of the virtual pixel area in the display panel, respectively. The horizontal effective row count is the signal input to the effective display area in the display panel. When the input horizontal leading edge is short and the horizontal effective row count and horizontal trailing edge are normal, some horizontal effective row counts will be input to the virtual pixel area located on the upper side, causing the virtual display area located on the upper side to be lit. At this time, a blank row or a safety level signal can be automatically inserted at the horizontal leading edge to ensure that its length is consistent with the horizontal leading edge length in the preset safety timing parameters. When the horizontal leading edge is long and the horizontal effective row count and horizontal trailing edge are normal, some horizontal effective row counts will be input to the virtual pixel area below, causing the virtual pixel area to be falsely activated. At this time, the excess part can be trimmed to make its length consistent with the horizontal leading edge length in the preset safety timing parameters. Similarly, the same processing method can be referred to for other external timing parameters. For the part exceeding the preset length, trim it; for the part less than the preset length, insert padding.

[0033] The problem proposed in this embodiment that the blanking period of the external device output signal cannot completely cover the virtual pixel area of ​​the display panel includes two states: the vertical blanking period of the external timing parameter cannot cover the upper and lower virtual pixel rows of the virtual pixel area of ​​the display panel, and the horizontal blanking period of the external timing parameter cannot cover the left and right virtual pixel columns of the virtual pixel area. Inserting blank rows, blank columns, or safety level signals into the data path to extend the blanking period ensures that data is inactive when input to the virtual pixel area.

[0034] As a feasible implementation, by determining whether the output timing corresponds to the period of the virtual pixel area, if it does, then the valid output signal is prohibited from being input into the virtual pixel area during the period of the virtual pixel area, ensuring that the virtual pixel area remains inactive. The above determination is mainly based on two modes. Mode 1: Determine whether the output timing corresponds to the period of the upper and lower virtual pixel rows of the virtual pixel area. If so, forcibly prohibit the output of a valid start scan signal. Mode 2: Determine whether the output timing corresponds to the period of the left and right virtual pixel columns of the virtual pixel area. If so, force the output voltage to a preset safe level. Therefore, even if scanning is prohibited, the voltage output to the virtual pixel area is still kept at a preset safe level, which can prevent the virtual pixel area from being accidentally activated through double protection.

[0035] In one feasible embodiment, determining whether the output timing corresponds to the period of the virtual pixel region includes: If, within the period corresponding to the effective display area, the scan lines and data lines of the virtual pixel area are disconnected by controlling the switch matrix, or the scan lines and data lines of the virtual pixel area are made to be in a high-resistance state, the scan and data connection can be physically disconnected by the switch matrix to prevent the virtual pixel area from being accidentally activated.

[0036] The present invention also discloses a display driver chip using the above-described display driving method.

[0037] Includes the following parts: The input module is used to receive external input signals, mainly including signals from devices such as computers, mobile phones, and TV boxes. Input signals typically include image data packets, horizontal synchronization signals, vertical synchronization signals, data validity signals, and pixel clocks.

[0038] The timing analysis and remapping module is used to detect external timing parameters of the input signal, compare them with preset target safe timing parameters, and make real-time adjustments based on whether the effective number of pixel rows and / or columns of the external timing parameters are completely consistent with the effective number of pixel rows and / or columns of the display panel and whether the blanking period of the external timing parameters covers the virtual pixel area of ​​the display panel, so as to ensure that the virtual pixel area is not mistakenly activated. The control module receives the output timing signal of the adjusted external timing parameters and determines whether the output timing corresponds to the period of the virtual pixel area. If it corresponds to the period of the virtual pixel area, the output of the valid signal is prohibited to ensure that the virtual pixel area remains inactive. That is, by leveraging the characteristic that the virtual pixel area is inactive during its period, the data bus output to the driver is clamped to a safe level by forcibly pulling the valid data signal low, thereby prohibiting the output of the valid signal. This action is at the hardware level and has an extremely fast response speed, ensuring that the input port of the display panel always receives an inactive signal throughout the entire period of the virtual pixel area, thus ensuring that the virtual pixel area remains inactive.

[0039] The preset target security timing parameters mainly include: The exact number of pixel rows and columns in the effective display area and virtual display area of ​​the display panel; The timing cycle range corresponding to the display panel.

[0040] The exact number of rows and columns of the effective display area of ​​the panel and the timing range of the virtual pixel area were clarified.

[0041] This part first determines whether the number of valid pixel rows / columns in the external timing parameters is completely consistent with the target parameters. If they are inconsistent, the decision logic will ignore the definition of the valid display area of ​​the external signal and instead use the internally preset safe timing parameters.

[0042] Blanking period coverage judgment: This section also determines whether the blanking period of the external timing parameters can completely cover the virtual pixel area of ​​the panel, including: Determine if the vertical blanking period is long enough to cover the virtual pixel rows at the top and bottom edges of the panel.

[0043] Determine if the horizontal blanking period is long enough to cover the virtual pixel columns at the left and right edges of the panel.

[0044] If any of the above judgment results are negative, indicating a mismatch, this part will initiate real-time adjustments and resynthesize an output timing scheme based on the safety timing parameters. For example, when the external vertical blanking period is too short, the module will force the total number of vertical rows of the output signal to be extended to a safe value to ensure that the blanking period can completely cover the upper and lower virtual rows. This operation ensures that the subsequent driving timing is fundamentally safe.

[0045] In one feasible embodiment, the timing analysis and remapping module includes: The timing detection unit is used to detect the external timing parameters of the input signal in real time. The external timing parameters include the total number of horizontal rows, the number of effective horizontal rows, the horizontal leading edge, the horizontal trailing edge, the total number of vertical columns, the number of effective vertical columns, the vertical leading edge, and the vertical trailing edge. The external timing parameters mainly cover the physical definition of the effective display area and virtual pixel area in the display panel by the external device. The parameter comparison unit is used to compare the external timing parameters with the preset target safety timing parameters. The main comparison is whether the external device's definition of the effective display area and virtual pixel area of ​​the display panel is the same as the actual effective display area and virtual pixel area of ​​the display panel. The dynamic adjustment unit is used to adjust the external timing parameters in real time according to the comparison results to ensure that the virtual pixel area is not accidentally activated. The key point is to adjust the timing parameters according to the actual size of the display panel so that they are the same as the preset target safety timing parameters and match the actual size of the display panel.

[0046] In specific implementation, the timing detection unit can use a counter to perform the above functions. The counter can be set as a row counter and a column counter to count the field synchronization signal and the row synchronization signal, respectively. By monitoring the rising and falling edges of the valid data signal and combining the counter value, key external timing parameters such as the total number of horizontal rows, the number of valid horizontal rows, the horizontal leading edge, the horizontal trailing edge, the total number of vertical columns, the number of valid vertical columns, the vertical leading edge, and the vertical trailing edge can be accurately calculated. These quantified parameters are output to the parameter comparison unit in real time.

[0047] The parameter comparison unit is responsible for security judgment. This function can be achieved by configuring a comparator and a register group storing preset security timing parameters. During comparison, the following is included: Number of valid external pixel rows / columns and number of valid target pixel rows / columns; External vertical blanking period and minimum safe blanking period required to cover the upper and lower virtual pixel rows; The external horizontal blanking period and the minimum safe blanking period required to cover the left and right virtual pixel columns.

[0048] The comparison result will then be output as a control signal to the dynamic adjustment unit.

[0049] The dynamic adjustment unit generates the final safety timing based on the comparison results. The adjustment strategy includes: when the parameter comparison unit determines that the size of the external effective area is inconsistent with the target, the dynamic adjustment unit will ignore the definition of the effective display area of ​​the external signal and directly use the internally stored target safety effective area parameters to generate a new timing.

[0050] When it is determined that the external blanking period is insufficient to cover the virtual pixel area, the blanking period can be actively extended to ensure that it can completely cover the virtual pixel area.

[0051] After the above adjustments, the unit outputs a safe timing signal that perfectly matches the physical characteristics of the display panel to the control module.

[0052] In one feasible embodiment, the control module includes a row drive circuit, a column drive circuit, a scan control unit, and a data control unit.

[0053] A row driving circuit is used to receive the output timing signal of the adjusted external timing parameters and to drive the scan line; A column driver circuit is used to receive the output timing signal and to drive the data lines; The scanning control unit is used to control the row driving circuit to forcibly disable the output of the scanning signal at the on level during the period of the upper and lower virtual pixel rows corresponding to the output timing parameters of the virtual pixel area, thereby preventing the activation of the virtual pixel area by disabling the scanning signal. The data control unit is used to control the column driving circuit to force the data line voltage to a preset safe level during the period of the left and right virtual pixel columns corresponding to the virtual pixel area of ​​the output timing parameters.

[0054] The row drive circuit receives the adjusted external timing parameters and outputs a timing signal to drive the scan lines. Specifically, the row drive circuit can employ logic circuitry where one input of an AND gate receives the corrected row scan timing signal from the dynamic adjustment unit, and the other input receives a region enable signal. This region enable signal is pulled low to an inactive level during the period corresponding to the upper and lower virtual pixel rows of the virtual pixel area. In this way, even if a scan pulse is generated internally within the row drive circuit, the scan signal output to the panel will be forced to remain at an inactive level under the action of the AND gate, thus ensuring that no row of virtual pixels is selected.

[0055] The scan control unit can employ logic circuitry, with one input receiving a row scan timing signal from the dynamic adjustment unit and the other receiving a region enable signal. This region enable signal is pulled low to an inactive level during the period corresponding to the upper and lower virtual pixel rows of the virtual pixel area. In this way, even if a scan pulse is generated internally in the row drive circuit, the scan signal output to the panel will be forced to remain at an inactive level due to the AND gate, thus ensuring that no row of virtual pixels is selected.

[0056] The column driver circuit converts digital pixel data into analog voltage and outputs it to the data lines. Specifically, the column driver circuit can select a multiplexer. The two data input terminals of the multiplexer are connected to the original image data bus and a fixed voltage source, respectively. Its selection terminal is controlled by a data selection signal. When the output timing is in the effective display area, the selection signal controls the multiplexer to output the original image data. When the timing enters the cycle of the left and right virtual pixel columns in the virtual pixel area, the selection signal immediately switches, controlling the multiplexer to continuously output a safe level. In this way, even if the virtual pixel row is accidentally activated, the voltage on its data line is fixed and safe, and abnormal colors will not be displayed.

[0057] In one feasible embodiment, the display driver chip may further include a switch matrix for signal transmission with the virtual pixel area, the switch matrix being further divided into a row-side switch matrix and a column-side switch matrix.

[0058] The input of the horizontal switch matrix is ​​connected to the output of the horizontal drive circuit, and its output is connected to each scan line of the effective display area and the virtual pixel area respectively. The input of the column-side switch matrix is ​​connected to the output of the column drive circuit, and its output is connected to each data line of the effective display area and the virtual pixel area respectively.

[0059] During operation, the scanning control unit and the data control unit can not only control the output of the drive circuit, but also operate the two switch matrices by sending control signals. Within the period corresponding to the virtual pixel area, the control unit can issue instructions to physically disconnect the channel connecting the virtual pixel area in the switch matrix, thus preventing signal crosstalk or leakage from causing the virtual pixel to be mistakenly activated.

[0060] The present invention also provides a display device, which includes a display panel and a display driver chip.

[0061] The display panel is physically divided into two areas: the effective display area in the center and the virtual pixel area surrounding it. The virtual pixel area is generally not designed for normal image display; its purpose is mainly for testing and process requirements.

[0062] The display driver chip is connected to the signal lines of the effective display area and virtual pixel area of ​​the display panel through its output pins. The chip is internally configured with safety timing parameters that are consistent with the physical parameters of the display panel.

[0063] During operation, by detecting and adjusting external timing parameters and determining whether the output timing corresponds to the period of the virtual pixel area, the problem of false activation of the virtual pixel area is avoided, thus ensuring the display quality of the display panel.

[0064] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or its equivalents are included in this invention.

Claims

1. A driving method for a display driver chip, characterized in that, include: Receive external input signals; The input signal is subjected to detection of external timing parameters, and compared with preset target security timing parameters; The system makes real-time adjustments based on whether the effective number of pixel rows and / or columns of the external timing parameters is completely consistent with the effective number of pixel rows and / or columns of the display panel and whether the blanking period of the external timing parameters covers the virtual pixel area of ​​the display panel, so as to ensure that the virtual pixel area is not mistakenly activated. The timing signal is output according to the adjusted external timing parameters; it is determined whether the output timing corresponds to the period of the virtual pixel area. If it corresponds to the period of the virtual pixel area, the output of the valid signal is prohibited to ensure that the virtual pixel area remains inactive.

2. The driving method according to claim 1, characterized in that, Whether the blanking period of the external timing parameters covers the virtual pixel area of ​​the display panel includes: Whether the vertical blanking period of the external timing parameter covers the upper and lower virtual pixel rows of the virtual pixel area of ​​the display panel, and whether the horizontal blanking period of the external timing parameter covers the left and right virtual pixel columns of the virtual pixel area.

3. The driving method according to claim 2, characterized in that, Real-time adjustments are made based on whether the effective number of pixel rows and / or columns of the external timing parameters are completely consistent with the effective number of pixel rows and / or columns of the display panel, including: When the number of valid pixel rows and / or columns of the external timing parameters exceeds the number of pixel rows and / or columns of the effective display area, the excess valid pixel rows and / or columns of the external timing parameters are automatically cropped. Furthermore, the vertical blanking period of the external timing parameters is adjusted in real time to ensure that it covers the upper and lower virtual pixel rows of the virtual pixel area of ​​the display panel, and the horizontal blanking period of the external timing parameters covers the left and right virtual pixel columns of the virtual pixel area, including: When the vertical blanking period of the external timing parameter is less than the upper and lower virtual pixel rows of the virtual pixel area, and / or the horizontal blanking period of the external timing parameter is less than the left and right virtual pixel columns, blank rows and / or column pixels or safety level signals are inserted into the data path.

4. The driving method according to claim 2, characterized in that, Determining whether the output timing corresponds to the period of the virtual pixel area; if it does, then disabling the output of valid signals to ensure that the virtual pixel area remains inactive, including: Determine whether the output timing corresponds to the period of the upper and lower virtual pixel rows of the virtual pixel area. If so, forcibly disable the output of the effective start scan signal. Determine whether the output timing corresponds to the period of the left and right virtual pixel columns of the virtual pixel area. If so, force the output voltage to a preset safe level.

5. The driving method according to claim 4, characterized in that, Determining whether the output timing corresponds to the period of the virtual pixel region includes: If, within the period corresponding to the effective display area, the scan lines and data lines of the virtual pixel area are disconnected by controlling the switch matrix, or the scan lines and data lines of the virtual pixel area are made to be in a high-impedance state.

6. A display driver chip, characterized in that, include: The input module is used to receive external input signals; The timing analysis and remapping module is used to detect external timing parameters of the input signal, compare them with preset target safe timing parameters, and make real-time adjustments based on whether the effective number of pixel rows and / or columns of the external timing parameters are completely consistent with the effective number of pixel rows and / or columns of the display panel and whether the blanking period of the external timing parameters covers the virtual pixel area of ​​the display panel, so as to ensure that the virtual pixel area is not mistakenly activated. The control module is used to receive the output timing signal of the adjusted external timing parameters and determine whether the output timing corresponds to the period of the virtual pixel area. If it corresponds to the period of the virtual pixel area, the output of the valid signal is prohibited to ensure that the virtual pixel area remains inactive.

7. The display driver chip according to claim 6, characterized in that, The timing analysis and remapping module includes: The timing detection unit is used to detect the external timing parameters of the input signal in real time. The external timing parameters include the total number of horizontal rows, the number of effective horizontal rows, the horizontal leading edge, the horizontal trailing edge, the total number of vertical columns, the number of effective vertical columns, the vertical leading edge, and the vertical trailing edge. A parameter comparison unit is used to compare the external timing parameters with preset target safety timing parameters. The dynamic adjustment unit is used to adjust the external timing parameters in real time based on the comparison results to ensure that the virtual pixel area is not mistakenly activated.

8. The display driver chip according to claim 6, characterized in that, The control module includes: A row driving circuit is used to receive the output timing signal of the adjusted external timing parameters and to drive the scan line; A column driver circuit is used to receive the output timing signal and to drive the data lines; The scanning control unit is used to control the row driving circuit to forcibly disable the output of the scanning signal at the on level during the period of the upper and lower virtual pixel rows corresponding to the virtual pixel area of ​​the output timing parameters; The data control unit is used to control the column driving circuit to force the data line voltage to a preset safe level during the period of the left and right virtual pixel columns corresponding to the virtual pixel area of ​​the output timing parameters.

9. The display driver chip according to claim 8, characterized in that, It also includes a switch matrix for signal transmission with the virtual pixel area; the switch matrix includes a row-side switch matrix and a column-side switch matrix; The input terminal of the row-side switch matrix is ​​electrically connected to the row drive circuit, and its output terminal is electrically connected to the scan line column of the effective display area and the virtual pixel area; The input terminal of the column-side switch matrix is ​​electrically connected to the column drive circuit, and its output terminal is electrically connected to the data lines of the effective display area and the virtual pixel area.

10. A display device, characterized in that, The invention includes a display panel and a display driver chip according to any one of claims 1-5, wherein the display panel includes an effective display area and a virtual pixel area disposed around the display area.

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