Pixel circuit and display panel

Abstract

The embodiment of the invention provides a pixel circuit and a display panel. According to the pixel circuit, a first capacitor and a second capacitor are arranged, one pole plate of the first capacitor, a grid electrode of a driving transistor and the output end of a compensation unit are connected to a first node, the other pole plate of the first capacitor, a data line and one pole plate of the second capacitor are connected to a fourth node, and a reset signal is written into a third node through a reset unit. A high-potential power supply signal can be discharged through the compensation unit and the driving transistor, so that the threshold voltage of the driving transistor is stored in the first capacitor, the threshold voltage does not need to be stored in a first node in a coupling mode, and the compensation effect is improved; and the second capacitor stores the data signal, so that the brightness of the light-emitting device in the light-emitting stage is relatively stable.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit and a display panel. BACKGROUND

[0002] In order to improve the performance of thin film transistors, the existing display device adopts the LTPO (Low Temperature Polysilicon Oxide) technology; specifically, low-temperature polysilicon thin film transistors and metal oxide thin film transistors are prepared on the same backplane at the same time, so as to take advantage of the low-temperature polysilicon thin film transistors and the metal oxide thin film transistors, and improve the performance of the display device. In order to avoid the problem that the threshold voltage offset of the driving transistor leads to display abnormalities, the threshold voltage of the driving transistor is compensated.

[0003] The existing threshold voltage compensation method is to store the threshold voltage information in the source electrode of the driving transistor first, and then store the threshold voltage information in the gate electrode of the driving transistor through the capacitor, so as to compensate the threshold voltage of the driving transistor. However, due to the existence of the parasitic capacitance of the gate electrode of the driving transistor, when the threshold voltage information is coupled from the source electrode of the driving transistor to the gate electrode of the driving transistor, there will be a certain loss, which leads to the fact that the pixel circuit cannot completely compensate the threshold voltage of the driving transistor, and the residual image problem occurs during display.

[0004] Therefore, the existing display device has the technical problem that the threshold voltage of the driving transistor cannot be completely compensated, leading to display abnormalities. SUMMARY

[0005] The embodiments of the present application provide a pixel circuit and a display panel, which solve the technical problem that the threshold voltage of the driving transistor cannot be completely compensated in the existing display device, leading to display abnormalities.

[0006] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a pixel circuit is provided, which comprises a driving transistor, a compensation unit, a reset unit, a first capacitor, a second capacitor and a light emitting device; The gate electrode of the driving transistor is connected to a first node with one plate of the first capacitor and the output end of the compensation unit, the first electrode of the driving transistor is connected to a second node with the input end of the compensation unit and a high potential power supply line, and the output end of the reset unit is connected to a third node with the light emitting device and the second electrode of the driving transistor; One plate of the second capacitor is connected to a fourth node with the other plate of the first capacitor and a data line; When the pixel circuit is configured to compensate the threshold voltage of the driving transistor, the reset unit is configured to write the reset signal to the third node, and the high potential power signal written by the high potential power line is discharged through the compensation unit and the driving transistor until the driving transistor is turned off, and the threshold voltage of the driving transistor is stored to the first capacitor; and the second capacitor is configured to store the data signal output by the data line.

[0007] According to a second aspect of the present application, a display panel is provided, which comprises the pixel circuit according to any one of the above embodiments.

[0008] The pixel circuit and the display panel provided by the embodiments of the present application have the following advantages. The first capacitor and the second capacitor are provided, one pole plate of the first capacitor is connected to the first node with the gate of the driving transistor and the output terminal of the compensation unit, the other pole plate of the first capacitor and one pole plate of the second capacitor are connected to the fourth node with the data line, the reset signal is written to the third node by the reset unit, the high potential power signal can be discharged through the compensation unit and the driving transistor, and thus the threshold voltage of the driving transistor is stored to the first capacitor, without storing the threshold voltage to the first node in a coupling manner, and the compensation effect is improved; and the second capacitor stores the data signal, and the brightness of the light emitting device in the light emitting stage is relatively stable.

[0009] Other features and advantages of the present application will be illustrated in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0010] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0011] Figure 1 The circuit diagram of the comparative pixel circuit provided by the embodiments of the present application is shown.

[0012] Figure 2 The timing diagram of the comparative pixel circuit provided by the embodiments of the present application is shown.

[0013] Figure 3 The first circuit diagram of the pixel circuit provided by the embodiments of the present application is shown.

[0014] Figure 4A second circuit diagram of the pixel circuit provided by the embodiment of the present application.

[0015] Figure 5 A third circuit diagram of the pixel circuit provided by the embodiment of the present application.

[0016] Figure 6 A first timing diagram of the pixel circuit provided by the embodiment of the present application.

[0017] Figure 7 A fourth circuit diagram of the pixel circuit provided by the embodiment of the present application.

[0018] Figure 8 A second timing diagram of the pixel circuit provided by the embodiment of the present application.

[0019] Figure 9 A contrast line diagram of the output current of the pixel circuit provided by the embodiment of the present application and the rate of change of the output current of the pixel circuit in the embodiment of the present application with the threshold voltage offset of the driving transistor. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0021] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms “mounting”, “connection”, “linking”, “electric connection”, “electrically connected” should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electric connection or can communicate with each other; can be directly connected, can also be indirectly connected through intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0022] In order to explain the principle of the technical problem in the embodiments of the present application, the present application provides some comparative pixel circuits, which can be understood as not being considered as prior art in the embodiments of the present application. For example, Figure 1As shown, the comparison pixel circuit includes a first transistor T01, a second transistor T02, a third transistor T03, a fourth transistor T04, a fifth transistor T05, a sixth transistor T06, a seventh transistor T07, a first storage capacitor Cst0, and a second storage capacitor C0. The gate of the first transistor T01 is connected to the second electrode of the second transistor T02, the second electrode of the third transistor T03, and one plate of the first storage capacitor Cst0 at the first node Q1. The first electrode of the first transistor T01 is connected to the second electrode of the fifth transistor T05 at the second node A1. The second electrode of the first transistor T01 is connected to the first electrode of the sixth transistor T06, the other plate of the first storage capacitor Cst0, and one plate of the second storage capacitor C0 at the third node B1.

[0023] The first electrode of the second transistor T02 is connected to the data signal line Data0, and the gate of the second transistor T02 is connected to the second scan signal line Scan02. The first electrode of the third transistor T03 is connected to the reference line Vref0, and the gate of the third transistor T03 is connected to the first scan signal line Scan01. The gate of the fourth transistor T04 is connected to the third scan signal line Scan03, and the first electrode of the fourth transistor T04 is connected to the initialization line VI-A. The second electrode of the fourth transistor T04 is connected to one end of the light-emitting unit LED0 at the fourth node C3. The gate of the fifth transistor T05... The first electrode of the fifth transistor T05 is connected to the first power supply line VDD0, the gate of the sixth transistor T06 is connected to the second light-emitting line EM02, the second electrode of the sixth transistor T06 is connected to one end of the light-emitting unit LED0 at the fourth node C3, the gate of the seventh transistor T07 is connected to the third scan signal line Scan03, the first electrode of the seventh transistor T07 is connected to the first power supply line VDD0, the second electrode of the seventh transistor T07 is connected to the other plate of the second storage capacitor C0, and the other end of the light-emitting unit LED0 is connected to the second power supply line VSS0.

[0024] like Figure 2 As shown, referring to the timing of each signal line, the working process of the pixel circuit is as follows: In the first working stage t01, the first light-emitting line EM01, the second light-emitting line EM02, the first scan signal line Scan01, the second scan signal line Scan02, and the third scan signal line Scan03 are at high potential, low potential, high potential, low potential, and high potential respectively, which turns on the third transistor T03, the fourth transistor T04, the sixth transistor T06, and the seventh transistor T07, and resets the third node B1 and the first node Q1 respectively.

[0025] In the second working stage t02, the first light emitting line EM01, the second light emitting line EM02, the first scan signal line Scan01, the second scan signal line Scan02 and the third scan signal line Scan03 are at low potential, high potential, high potential, low potential and high potential respectively, so that the first transistor T01, the third transistor T03, the fourth transistor T04, the fifth transistor T05 and the seventh transistor T07 are turned on, the third node B1 is charged, and the threshold voltage information of the driving transistor is written.

[0026] In the third working stage t03, the first light emitting line EM01, the second light emitting line EM02, the first scan signal line Scan01, the second scan signal line Scan02 and the third scan signal line Scan03 are at high potential, high potential, low potential, high potential and high potential respectively, so that the second transistor T02, the fourth transistor T04 and the seventh transistor T07 are turned on, the third transistor T03, the fifth transistor T05 and the sixth transistor T06 are turned off, and the data signal is written into the first node Q1.

[0027] In the fourth working stage, the first light emitting line EM01, the second light emitting line EM02, the first scan signal line Scan01, the second scan signal line Scan02 and the third scan signal line Scan03 are at high potential, low potential, low potential, low potential and high potential respectively, so that the fourth transistor T04, the sixth transistor T06 and the seventh transistor T07 are turned on, and the third node B1 is reset.

[0028] In the fifth working stage, the first light emitting line EM01, the second light emitting line EM02, the first scan signal line Scan01, the second scan signal line Scan02 and the third scan signal line Scan03 are at low potential, low potential, low potential, low potential and low potential respectively, so that the first transistor T01, the fifth transistor T05 and the sixth transistor T06 are turned on, a path is formed between the first power supply line VDD0 and the second power supply line VSS0, and the light emitting unit LED0 emits light.

[0029] As can be seen from the working process of the comparison pixel circuit, the threshold voltage compensation information of the first transistor T01 is first stored in the third node B1, and then coupled and stored in the first node Q1 through the first storage capacitor Cst0. However, the first node Q1 has a parasitic capacitor, for example, a parasitic capacitor between the second transistor T02, so that when the threshold voltage compensation information is coupled from the third node B1 to the first node Q1, there will be a certain loss, which leads to the fact that the circuit cannot completely compensate for the threshold voltage shift of the first transistor T01, and residual image problems will occur when the screen works for a long time. Therefore, the existing display device has the technical problem that the threshold voltage of the driving transistor cannot be completely compensated, resulting in display abnormalities.

[0030] Embodiments of the present application are directed to the above technical problems, and provide a pixel circuit and a display panel to solve the above technical problems.

[0031] Figure 3 A first circuit diagram of the pixel circuit provided by the embodiments of the present application. Figure 4 A second circuit diagram of the pixel circuit provided by the embodiments of the present application. Figure 5 A third circuit diagram of the pixel circuit provided by the embodiments of the present application. Figure 6 A first timing diagram of the pixel circuit provided by the embodiments of the present application. Figure 7 A fourth circuit diagram of the pixel circuit provided by the embodiments of the present application. Figure 8 A second timing diagram of the pixel circuit provided by the embodiments of the present application. Figure 9 A contrast pixel circuit and a broken line contrast diagram of the rate of change of the output current of the pixel circuit in the embodiments of the present application with respect to the threshold voltage offset of the driving transistor.

[0032] As shown in Figures 3 to 8 The embodiments of the present application provide a pixel circuit, which comprises a driving transistor T1, a switch unit 11, a compensation unit 12, a light-emitting control unit 13, a reset unit 14, an initialization unit 15, a first capacitor C1, a second capacitor C2 and a light-emitting device OLED; a gate of the driving transistor T1 is connected to a first node Q with one plate of the first capacitor C1 and an output end of the compensation unit 12; a first electrode of the driving transistor T1 is connected to a second node A with an input end of the compensation unit 12 and an output end of the light-emitting control unit 13; an output end of the reset unit 14 and the light-emitting device OLED are connected to a third node C; an input end of the switch unit 11 is connected with a data line Data; an output end of the switch unit 11 is connected to a fourth node P with the initialization unit 15, the other plate of the first capacitor C1 and one plate of the second capacitor C2; an input end of the light-emitting control unit 13 is connected with a high potential power line VDD.

[0033] As shown in Figures 3 to 8As shown, the embodiment of the present application provides a pixel circuit, the pixel circuit 1 comprises a driving transistor T1, a compensation unit 12, a reset unit 14, a first capacitor C1, a second capacitor C2 and a light emitting device OLED; a gate of the driving transistor T1 is connected with one plate of the first capacitor C1 and an output end of the compensation unit 12 to a first node Q, a first electrode of the driving transistor T1 is connected with an input end of the compensation unit 12 and a high potential power supply line VDD to a second node A, an output end of the reset unit 14 and the light emitting device OLED and a second electrode of the driving transistor T1 are electrically connected to a third node C; one plate of the second capacitor C2 is electrically connected with the other plate of the first capacitor C1 and a data line Data to a fourth node P. Wherein, when the pixel circuit 1 is configured to compensate the threshold voltage of the driving transistor T1, the reset unit 14 is configured to write the reset signal to the third node C, the high potential power signal written by the high potential power supply line VDD is discharged through the compensation unit 12 and the driving transistor T1 until the driving transistor is closed, and the threshold voltage of the driving transistor T1 is stored to the first capacitor C1; the second capacitor C2 is configured to store the data signal output by the data line Data.

[0034] The embodiment of the present application provides a pixel circuit; the pixel circuit 1 is configured by the first capacitor C1 and the second capacitor C2, one plate of the first capacitor C1 is connected with the gate of the driving transistor T1 and the output end of the compensation unit 12 to the first node Q, the other plate of the first capacitor C1 is connected with the data line Data and one plate of the second capacitor C2 to the fourth node P, and the reset unit 14 is configured to write the reset signal to the third node C, so that the high potential power signal can be discharged through the compensation unit 12 and the driving transistor T1, thereby storing the threshold voltage of the driving transistor T1 to the first capacitor C1, without storing the threshold voltage to the first node Q through the coupling mode, improving the compensation effect; and the second capacitor C2 stores the data signal, so that the brightness of the light emitting device OLED in the light emitting stage is relatively stable.

[0035] Specifically, compared with some comparative pixel circuits, one capacitor is connected to the first node Q and the fourth node P, and another capacitor is connected to the first node Q and the fifth node B, so that the capacitance of the first node Q is controlled by two capacitors. When the voltage of the fifth node B changes, the voltage of the first node Q is controlled by the voltage change of the fifth node B, and the Vgs of the driving transistor is the voltage difference between the first node Q and the fifth node B, so that the Vgs of the driving transistor changes, resulting in the problem of brightness deviation during display. The second capacitor C2 in the embodiment of the application is connected to the fourth node P instead of being connected to the first node Q, so that the voltage of the first node Q is related to the first capacitor C1, and the voltage of the first node Q is prevented from being affected by the second capacitor C2, thereby improving the brightness stability and improving the display effect.

[0036] Specifically, in the embodiment of the application, the input end of each unit can be one of the first electrode and the second electrode of the transistor, and the output end of each unit can be the other of the first electrode and the second electrode of the transistor. For example, the switching unit 11 includes a switching transistor T2, the input end of the switching unit 11 can be the first electrode of the switching transistor T2, and the output end of the switching unit 11 can be the second electrode of the switching transistor T2. Similarly, the specific structure to which the input end and the output end of each unit refer can be determined.

[0037] Specifically, in the embodiment of the application, each unit can include one, two or more transistors, and each transistor can be connected in series or in parallel. For example, the switching unit 11 can include one switching transistor T2, or two or more switching transistors T2 connected in series. Similarly, the specific structure of each unit can be determined.

[0038] In some embodiments, as shown in Figures 3 to 8 The compensation unit 12 includes a compensation transistor T3, the first electrode of the compensation transistor T3 is connected to the second node A with the first electrode of the driving transistor T1, and the second electrode of the compensation transistor T3 is connected to the first node Q with the gate of the driving transistor T1. When the pixel circuit 1 is configured to compensate the threshold voltage of the driving transistor T1, the compensation transistor T3 is turned on, the high potential power signal of the first node Q is discharged through the compensation transistor T3 and the driving transistor T1, until the driving transistor T1 is turned off, and the threshold voltage of the driving transistor T1 is stored in the first capacitor C1. Therefore, when the threshold voltage of the driving transistor T1 is compensated, the compensation transistor T3 can turn on the gate of the driving transistor T1 and the first electrode of the driving transistor T1, so as to reset the gate of the driving transistor T1 and compensate the threshold voltage of the driving transistor T1.

[0039] In some embodiments, as shown in Figures 3 to 8As shown, the pixel circuit 1 further comprises a switch transistor T2, a first electrode of the switch transistor T2 is connected with the data line Data, and a second electrode of the switch transistor T2 is connected with the other plate of the first capacitor C1 at the fourth node P; so that the switch transistor T2 can control the writing of the data signal output by the data line Data, and control the current of the pixel circuit.

[0040] In some embodiments, as shown in Figures 3 to 8 As shown, the pixel circuit 1 further comprises a first light-emitting control transistor T5, a first electrode of the first light-emitting control transistor T5 is connected with the high-potential power supply line VDD, and a second electrode of the first light-emitting control transistor T5 is connected with the first electrode of the drive transistor T1 at the second node A; wherein, before the pixel circuit 1 is configured to compensate the threshold voltage of the drive transistor T1, the first light-emitting control transistor T5 is turned on, the compensation transistor T3 is turned on, and the high-potential power supply line VDD writes the high-potential power supply signal to the first node Q and the second node A; so that the first light-emitting control transistor T5 can control the writing of the high-potential power supply signal output by the high-potential power supply line, reset the first node Q, or control the conduction of the pixel circuit to make the light-emitting device OLED emit light.

[0041] In some embodiments, as shown in Figures 3 to 8 As shown, the pixel circuit 1 further comprises an initialization transistor T4, one electrode of the initialization transistor T4 is connected with one plate of the first capacitor C1 and one plate of the second capacitor C2 at the fourth node P. By connecting one electrode of the initialization transistor T4 with one plate of the first capacitor C1 and one plate of the second capacitor C2 at the fourth node P, the initialization transistor can control the input of the initialization signal when compensating the threshold voltage of the drive transistor T1, so that the voltage of one plate of the first capacitor C1 can be stabilized, so that the threshold voltage written by the other plate of the first capacitor C1 is more accurate, the compensation effect of the threshold voltage of the drive transistor is improved, and the fourth node can be reset before the light-emitting device OLED emits light, thereby improving the display effect.

[0042] In some embodiments, as shown in Figures 3 to 8 As shown, the reset unit 14 comprises a reset transistor T7, one electrode of the reset transistor T7 is connected with the light-emitting device OLED at the third node C. By connecting one electrode of the reset transistor T7 with the light-emitting device OLED at the third node C, the reset transistor T7 can control the input of the initialization signal, reset the anode of the light-emitting device OLED, and the reset transistor T7 can control the writing of the initialization signal to the first node, and compensate the threshold voltage of the drive transistor.

[0043] In some embodiments, as shown in Figure 3 , Figure 7 the other electrode of the initialization transistor T4 and the other electrode of the reset transistor T7 are connected with an initialization signal line Vref. By connecting the other electrode of the initialization transistor T4 and the other electrode of the reset transistor T7 with the initialization signal line Vref, the initialization signal (reset signal) can be input through an initialization signal line Vref when setting the pixel circuit, the number of signal lines is reduced, the complexity of the pixel circuit is reduced, and the space occupied by the pixel circuit is reduced.

[0044] Specifically, as shown in Figure 3 , Figure 7 the first electrode of the initialization transistor T4 is connected with the initialization signal line Vref, and the second electrode of the initialization transistor T4 is connected with one plate of the first capacitor C1 and one plate of the second capacitor C2 at the fourth node P.

[0045] Specifically, as shown in Figure 3 , Figure 7 the first electrode of the reset transistor T7 is connected with the initialization signal line Vref, and the second electrode of the reset transistor T7 is connected with the light emitting device OLED at the third node C.

[0046] In some embodiments, as shown in Figure 4 , Figure 5 the other electrode of the initialization transistor T4 is connected with a first initialization signal line Vref1, the other electrode of the reset transistor T7 is connected with a second initialization signal line Vref2, and the output signal of the first initialization signal line Vref1 is different from the output signal of the second initialization signal line Vref2. By connecting the other electrode of the initialization transistor T4 with the first initialization signal line Vref1 and connecting the other electrode of the reset transistor T7 with the second initialization signal line Vref2, the initialization signal (reset signal) output by the first initialization signal line Vref1 and the second initialization signal line Vref2 is more in line with the requirements, and the performance of the pixel circuit is improved.

[0047] Specifically, as shown in Figure 4 , Figure 5 the first electrode of the initialization transistor T4 is connected with the first initialization signal line Vref1, and the second electrode of the initialization transistor T4 is connected with one plate of the first capacitor C1 and one plate of the second capacitor C2 at the fourth node P.

[0048] Specifically, as shown in Figure 4 , Figure 5As shown, the first electrode of the reset transistor T7 is connected to the second initialization signal line Vref2, and the second electrode of the reset transistor T7 is connected to the third node C with the light emitting device OLED.

[0049] Specifically, when controlling the current in the pixel circuit, the signals of the first initialization signal line Vref1 and the data line Data need to be adjusted, when controlling the compensation effect of the threshold voltage, the electrical signal of the second initialization signal line Vref2 needs to be adjusted, and when controlling the starting speed of the light emitting device OLED, the electrical signal of the second initialization signal line Vref2 needs to be adjusted; when the other electrode of the initialization transistor T4 and the other electrode of the reset transistor T7 are connected to the same initialization signal line, the output signal of the initialization signal line is controlled by the signals of the data line Data, the compensation effect of the threshold voltage, and the starting speed of the light emitting device OLED, and the output signal of the initialization signal line is difficult to meet various requirements, for example, when the voltage of the data line Data needs to be increased to maintain the same current, the voltage of the output signal of the initialization signal line needs to be increased, while the compensation effect of the threshold voltage requires the voltage of the output signal of the initialization signal line to be smaller, resulting in difficulty in balancing the two. The embodiments of the present application make the other electrode of the initialization transistor T4 and the other electrode of the reset transistor T7 connected to the first initialization signal line Vref1 and the second initialization signal line Vref2 respectively, so that the first initialization signal line Vref1 can adjust the voltage of the output signal to optimize the voltage range of the data line, and the second initialization signal line Vref2 can adjust the compensation effect of the threshold voltage and the starting speed of the light emitting device, thereby improving the performance of the pixel circuit.

[0050] In some embodiments, as shown in FIG. 1, the pixel circuit 1 further includes a second initialization signal line Vref2, the other electrode of the initialization transistor T4 is connected to the second initialization signal line Vref2, and the other electrode of the reset transistor T7 is connected to the second initialization signal line Vref2. Figures 3 to 8 As shown, the pixel circuit 1 further includes a second light emitting control transistor T6, the first electrode of the second light emitting control transistor T6 is connected to the fifth node B with the second electrode of the driving transistor T1, and the second electrode of the second light emitting control transistor T6 is connected to the third node C with the light emitting device OLED; wherein when the pixel circuit 1 is configured to compensate the threshold voltage of the driving transistor T1, the second light emitting control transistor T6 is turned on to write the reset signal to the fifth node B. By setting the second light emitting control transistor T6, the second electrode of the second light emitting control transistor T6 is connected to the third node C with the light emitting device OLED, so that the second light emitting control transistor T6 can control the light emitting of the light emitting device OLED.

[0051] In some embodiments, as shown in FIG. 1, the pixel circuit 1 further includes a second light emitting control transistor T6, the first electrode of the second light emitting control transistor T6 is connected to the fifth node B with the second electrode of the driving transistor T1, and the second electrode of the second light emitting control transistor T6 is connected to the third node C with the light emitting device OLED; wherein when the pixel circuit 1 is configured to compensate the threshold voltage of the driving transistor T1, the second light emitting control transistor T6 is turned on to write the reset signal to the fifth node B. By setting the second light emitting control transistor T6, the second electrode of the second light emitting control transistor T6 is connected to the third node C with the light emitting device OLED, so that the second light emitting control transistor T6 can control the light emitting of the light emitting device OLED. Figure 3 , Figure 4 , Figure 7As shown, the other plate of the second capacitor C2 is connected to the second electrode of the second light-emitting control transistor T6 and the second electrode of the reset transistor T7 at the third node C. This allows data signals to be written to one plate of the second capacitor C2, and the other plate of the second capacitor C2 is stabilized by the signal at the third node C, thereby storing the data signals in the second capacitor C2. This ensures that the gate voltage of the driving transistor can be stabilized during display, thus improving the display effect.

[0052] In some embodiments, such as Figure 5 As shown, the other plate of the second capacitor C2 is connected to the second electrode of the driving transistor T1 and the first electrode of the second light-emitting control transistor T6 at the fifth node B; this allows data signals to be written to one plate of the second capacitor C2, and the other plate of the second capacitor C2 is stabilized by the signal at the fifth node B, thereby storing the data signals in the second capacitor C2, stabilizing the gate voltage of the driving transistor during display, and improving the display effect.

[0053] In some embodiments, such as Figures 3 to 5 As shown, the gates of the compensation transistor T3 and the initialization transistor T4 are both connected to the first scan line Scan1, and the gate of the switching transistor T2 is connected to the second scan line Scan2. By connecting the gates of the compensation transistor T3 and the initialization transistor T4 to the first scan line Scan1, the compensation transistor T3 and the initialization transistor T4 can be controlled through the same scan line, reducing the complexity of the pixel circuit, decreasing the number of traces in the pixel circuit, and thus reducing the space occupied by the pixel circuit.

[0054] In some embodiments, such as Figure 7 As shown, the gate of the initialization transistor T4 is connected to the first scan line Scan1, the gate of the switching transistor T2 is connected to the second scan line Scan2, and the gate of the compensation transistor T3 is connected to the third scan line Scan3, so that each transistor can be controlled by different scan lines.

[0055] In some embodiments, such as Figures 3 to 5 , Figure 7As shown, the gates of the first light-emitting control transistor T5 and the reset transistor T7 are connected to the first light-emitting control line EM1, and the gate of the second light-emitting control transistor T6 is connected to the second light-emitting control line EM2. One of the first light-emitting control transistor T5 and the reset transistor T7 is an N-type transistor, and the other is a P-type transistor. By connecting the gates of the first light-emitting control transistor T5 and the reset transistor T7 to the first light-emitting control line EM1, both transistors can be controlled via the same control line, reducing the complexity of the pixel circuit, decreasing the number of traces in the pixel circuit, and thus reducing the space occupied by the pixel circuit. Furthermore, the fact that one of the first light-emitting control transistors T5 and the reset transistor T7 is an N-type transistor and the other is a P-type transistor allows the first light-emitting control transistor T5 and the reset transistor T7 to be turned on in a time-division multiplexing manner, enabling the pixel circuit to operate normally. Additionally, the connection of the gate of the second light-emitting control transistor T6 to the second light-emitting control line EM2 allows the second light-emitting control transistor T6 to be controlled independently, thereby enabling the pixel circuit to operate normally.

[0056] In some embodiments, the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistor T4, and the reset transistor T7 are N-type transistors, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are P-type transistors.

[0057] In some embodiments, the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistor T4, and the reset transistor T7 are oxide semiconductor transistors, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are silicon semiconductor transistors; this allows the pixel circuit to combine the advantages of silicon semiconductor transistors and oxide semiconductor transistors, thereby improving the performance of the pixel circuit.

[0058] Specifically, the driving transistor T1, the switching transistor T2, the compensation transistor T3, the initialization transistor T4, and the reset transistor T7 are metal-oxide-slim transistors, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are low-temperature polycrystalline silicon thin-film transistors.

[0059] Specifically, the first electrode of each transistor can be the source and the second electrode can be the drain; or the first electrode of each transistor can be the drain and the second electrode can be the source.

[0060] In some embodiments, such as Figures 2 to 8 As shown, when the pixel circuit 1 is configured in the first stage t1, the light-emitting device OLED stops emitting light; When the pixel circuit 1 is configured as the second stage t2, the compensation transistor T3 and the first light emitting control transistor T5 are turned on, and the high potential power supply line VDD writes the high potential power supply signal into the first node Q and the second node A. When the pixel circuit 1 is configured as the third stage t3, the first light emitting control transistor T5 is turned off, and the reset unit 14 resets the third node C. When the pixel circuit 1 is configured as the fourth stage t4, the driving transistor T1 is turned on according to the high potential power supply signal written into the first node Q, so that the charge of the first node Q is discharged through the compensation transistor T3 and the driving transistor T1 until the driving transistor T1 is turned off, thereby realizing compensation of the threshold voltage of the driving transistor T1, and the reset unit 14 writes the reset signal into the first node Q. When the pixel circuit 1 is configured as the fifth stage t5, the switch transistor T2 is turned on, and the data signal is written into the fourth node P. When the pixel circuit 1 is configured as the sixth stage t6, the first light emitting control transistor EM1 is turned on, and the driving transistor T1 is turned on according to the potential of the first node Q, so that the light emitting device OLED emits light.

[0061] Specifically, one end of the light emitting device OLED is connected to the low potential power supply line VSS.

[0062] Specifically, as shown in Figure 3 , Figure 6 the pixel circuit shown in Figure 3 , the timing shown in Figure 6 illustrates the working process of the pixel circuit, and for the pixel circuit shown in Figure 4 , Figure 5 the timing shown in Figure 6 can be used, and the working process can be referred to the following description.

[0063] As shown in Figure 3 , Figure 6 , when the pixel circuit is configured as the first stage t1, the first light emitting control line EM1, the second light emitting control line EM2, the first scan line Scan1, the second scan line Scan2 are at low potential, high potential, low potential, low potential respectively, the second light emitting control transistor T6 is turned off, and the light emitting device OLED stops emitting light; at this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P and the fifth node B are respectively no potential, the high potential power supply signal V1 output by the high potential power supply line VDD, no potential, no potential, V1-Vth (Vth is the threshold voltage of the driving transistor).

[0064] AsFigure 3 、 Figure 6 As shown in FIG. 2, when the pixel circuit is configured as the second stage t2, the first light emitting control line EM1, the second light emitting control line EM2, the first scan line Scan1, and the second scan line Scan2 are at low potential, high potential, high potential, and low potential, respectively, the compensation transistor T3, the initialization transistor T4, and the first light emitting control transistor T5 are turned on, the switch transistor T2, the second light emitting control transistor T6, and the reset transistor T7 are turned off, the high potential power supply line VDD writes the high potential power supply signal into the first node Q and the second node A, and the initialization signal line Vref writes the initialization signal into the fourth node P; at this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are V1, V1, no potential, the initialization signal V2 output by the initialization signal line Vref, and V1-Vth, respectively.

[0065] As shown in FIG. 2, Figure 3 、 Figure 6 As shown in FIG. 2, when the pixel circuit is configured as the second stage t2, the first light emitting control line EM1, the second light emitting control line EM2, the first scan line Scan1, and the second scan line Scan2 are at low potential, high potential, high potential, and low potential, respectively, the compensation transistor T3, the initialization transistor T4, and the first light emitting control transistor T5 are turned on, the switch transistor T2, the second light emitting control transistor T6, and the reset transistor T7 are turned off, the high potential power supply line VDD writes the high potential power supply signal into the first node Q and the second node A, and the initialization signal line Vref writes the initialization signal into the fourth node P; at this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are V1, V1, no potential, the initialization signal V2 output by the initialization signal line Vref, and V1-Vth, respectively.

[0066] As shown in FIG. 2, Figure 3 、 Figure 6 As shown in FIG. 2, when the pixel circuit is configured as the second stage t2, the first light emitting control line EM1, the second light emitting control line EM2, the first scan line Scan1, and the second scan line Scan2 are at low potential, high potential, high potential, and low potential, respectively, the compensation transistor T3, the initialization transistor T4, and the first light emitting control transistor T5 are turned on, the switch transistor T2, the second light emitting control transistor T6, and the reset transistor T7 are turned off, the high potential power supply line VDD writes the high potential power supply signal into the first node Q and the second node A, and the initialization signal line Vref writes the initialization signal into the fourth node P; at this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are V1, V1, no potential, the initialization signal V2 output by the initialization signal line Vref, and V1-Vth, respectively.

[0067] As shown in FIG. 2, Figure 3 ,Figure 6 As shown, when the pixel circuit is configured in the fifth stage t5, the first light emission control line EM1, the second light emission control line EM2, the first scan line Scan1, and the second scan line Scan2 are at high potential, low potential, low potential, and high potential, respectively. The compensation transistor T3 and the initialization transistor T4 are turned off, while the switching transistor T2, the second light emission control transistor T6, and the reset transistor T7 are turned on. The data line Data writes the data signal Vdata to the fourth node P and stores it in the second capacitor C2. At this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are Vdata+Vth, no potential, V2, Vdata, and V2, respectively.

[0068] like Figure 3 , Figure 6 As shown, when the pixel circuit is configured in the sixth stage t6, the first light-emitting control line EM1, the second light-emitting control line EM2, the first scan line Scan1, and the second scan line Scan2 are at low potentials, low potentials, low potentials, and low potentials, respectively. The driving transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are turned on, forming a path between the high-potential power line VDD and the low-potential power line VSS. The OLED emits light, and the current is proportional to (Vdata - V2). 2 At this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P and the fifth node B are Vdata+Vth+Vc (i.e. the potential of the third node C)-V2, V1, Vc, Vdata+Vc-V2, Vc, respectively.

[0069] As can be seen from the working process of the pixel circuit, the threshold voltage of the driving transistor is directly written to the first node Q, without needing to be coupled from the third node C or the fifth node B to the first node Q. This avoids the loss of threshold voltage information and improves the problem of image retention when the display device is working.

[0070] Specifically, in the pixel circuit for Figure 7 The pixel circuit shown has the following timing sequence: Figure 8 The timing shown differs from the above in that the initialization transistor T4 is controlled by the first scan line Scan1 and the compensation transistor T3 is controlled by the third scan line Scan3. The on and off states of each transistor in each stage and the potential of each node can be found in the following description.

[0071] like Figure 7 , Figure 8As shown, when the pixel circuit is configured in the first stage t1, the first light-emitting control line EM1, the second light-emitting control line EM2, the first scan line Scan1, the second scan line Scan2, and the third scan line Scan3 are at low potential, high potential, low potential, low potential, and low potential, respectively. The second light-emitting control transistor T6 is turned off, and the light-emitting device OLED stops emitting light. At this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are respectively no potential, high potential power signal V1 output by the power line VDD, no potential, no potential, and V1-Vth (Vth is the threshold voltage of the driving transistor).

[0072] like Figure 7 , Figure 8 As shown, when the pixel circuit is configured in the second stage t2, the first light emission control line EM1, the second light emission control line EM2, the first scan line Scan1, the second scan line Scan2, and the third scan line Scan3 are at low potential, high potential, high potential, low potential, and high potential, respectively. The compensation transistor T3, the initialization transistor T4, and the first light emission control transistor T5 are turned on, while the switching transistor T2, the second light emission control transistor T6, and the reset transistor T7 are turned off. The high potential power supply line VDD writes the high potential power supply signal to the first node Q and the second node A, and the initialization signal line Vref writes the initialization signal to the fourth node P. At this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are V1, V1, no potential, and the initialization signal V2 and V1-Vth output by the initialization signal line Vref, respectively.

[0073] like Figure 7 , Figure 8 As shown, when the pixel circuit is configured in the third stage t3, the first light emission control line EM1, the second light emission control line EM2, the first scan line Scan1, the second scan line Scan2, and the third scan line Scan3 are at high potential, high potential, high potential, low potential, and high potential, respectively. The compensation transistor T3, the initialization transistor T4, and the reset transistor T7 are turned on, the first light emission control transistor T5 is turned off, and the initialization signal line Vref writes the initialization signal to the third node C to reset the third node C. At this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are V1, V1, V2, V2, and V1-Vth, respectively.

[0074] like Figure 7 , Figure 8As shown, when the pixel circuit is configured in the fourth stage t4, the first light emission control line EM1, the second light emission control line EM2, the first scan line Scan1, the second scan line Scan2, and the third scan line Scan3 are at high potential, low potential, high potential, low potential, and high potential, respectively. The compensation transistor T3, the initialization transistor T4, the second light emission control transistor T6, and the reset transistor T7 are turned on, the first light emission control transistor T5 is turned off, and the driving transistor T1 is turned on according to the high potential power supply signal written to the first node Q, so that the charge of the first node Q is discharged through the compensation transistor T3 and the driving transistor T1 until the driving transistor T1 is turned off, thereby compensating for the threshold voltage of the driving transistor T1. The initialization signal line Vref writes the initialization signal (reset signal) to the third node C. At this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are V2+Vth, V2+Vth, V2, V2, and V2, respectively.

[0075] like Figure 7 , Figure 8 As shown, when the pixel circuit is configured in the fifth stage t5, the first light emission control line EM1, the second light emission control line EM2, the first scan line Scan1, the second scan line Scan2, and the third scan line Scan3 are at high potential, low potential, low potential, high potential, and low potential, respectively. The compensation transistor T3 and the initialization transistor T4 are turned off, while the switching transistor T2, the second light emission control transistor T6, and the reset transistor T7 are turned on. The data line Data writes the data signal Vdata to the fourth node P and stores it in the second capacitor C2. At this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P, and the fifth node B are Vdata+Vth, no potential, V2, Vdata, and V2, respectively.

[0076] like Figure 7 , Figure 8 As shown, when the pixel circuit is configured in the sixth stage t6, the first light-emitting control line EM1, the second light-emitting control line EM2, the first scan line Scan1, the second scan line Scan2, and the third scan line Scan3 are at low potentials, low potential, low potential, low potential, and low potential, respectively. This turns on the driving transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6, forming a path between the high-potential power line VDD and the low-potential power line VSS. The OLED emits light, and the current is proportional to (Vdata - V2). 2 At this time, the potentials of the first node Q, the second node A, the third node C, the fourth node P and the fifth node B are Vdata+Vth+Vc (i.e. the potential of the third node C)-V2, V1, Vc, Vdata+Vc-V2, Vc, respectively.

[0077] like Figure 9 As shown, using Figure 1 The pixel circuits in the comparison diagram and the pixel circuits in the embodiments of this application are compared through electrical simulation. Figure 9 The horizontal axis represents the threshold voltage drift amplitude of the driving transistor, in volts, and the vertical axis represents the rate of change of output current caused by the threshold voltage drift of the driving transistor. Simulations were performed at a low 48 grayscale level, yielding line 1 and line 2. Line 1 is a line showing the rate of change of output current of the comparative pixel circuit as a function of the threshold voltage drift of the driving transistor, while line 2 is a line showing the rate of change of output current of the pixel circuit in this embodiment as a function of the threshold voltage drift of the driving transistor. Figure 9 As can be seen, the pixel circuit in this embodiment can improve the brightness decay caused by the aging of the driving transistor (forward bias of the threshold voltage) and improve the display effect.

[0078] Specifically, the above embodiments have been described in detail from the aspects of circuit design and timing in the pixel circuit. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the gate of the compensation transistor and the gate of the initialization transistor are both connected to the first scan line, the gate of the switching transistor is connected to the second scan line, and one plate of the second capacitor is connected to the second electrode of the driving transistor and the first electrode of the second light-emitting control transistor at the fifth node.

[0079] Meanwhile, this application provides a display panel that includes pixel circuits as described in any of the above embodiments.

[0080] Specifically, the display panel can be an organic light-emitting diode (OLED) display panel.

[0081] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0084] The above are only the preferred embodiments of the present application, and do not limit the present application in any form, but any simple modification, equivalent change and modification made to the above embodiments without departing from the technical solution of the present application and according to the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A pixel circuit, characterized in that, It includes a driving transistor, a compensation unit, a reset unit, a first capacitor, a second capacitor, and a light-emitting device; The gate of the driving transistor is connected to one plate of the first capacitor and the output terminal of the compensation unit at a first node. The first electrode of the driving transistor is electrically connected to the input terminal of the compensation unit and the high-potential power line at a second node. The output terminal of the reset unit is electrically connected to the light-emitting device and the second electrode of the driving transistor at a third node. One plate of the second capacitor is electrically connected to the other plate of the first capacitor and the data line at the fourth node; Specifically, when the pixel circuit is configured to compensate the threshold voltage of the driving transistor, the reset unit is configured to write the reset signal to the third node, and the high-potential power signal written by the high-potential power line is discharged through the compensation unit and the driving transistor until the driving transistor is turned off, and the threshold voltage of the driving transistor is stored in the first capacitor; the second capacitor is configured to store the data signal output by the data line.

2. The pixel circuit according to claim 1, characterized in that, The compensation unit includes a compensation transistor, the first electrode of which is connected to the first electrode of the driving transistor at the second node, and the second electrode of which is connected to the gate of the driving transistor at the first node. When the pixel circuit is configured to compensate the threshold voltage of the driving transistor, the compensation transistor is turned on, and the high-potential power signal of the first node is discharged through the compensation transistor and the driving transistor until the driving transistor is turned off, and the threshold voltage of the driving transistor is stored in the first capacitor.

3. The pixel circuit according to claim 2, characterized in that, The pixel circuit also includes a switching transistor, the first electrode of which is connected to the data line, and the second electrode of which is connected to the other plate of the first capacitor at the fourth node.

4. The pixel circuit according to claim 3, characterized in that, The pixel circuit further includes a first light-emitting control transistor, the first electrode of which is connected to the high-potential power line, and the second electrode of which is connected to the first electrode of the driving transistor at the second node. Specifically, before the pixel circuit is configured to compensate the threshold voltage of the driving transistor, the first light-emitting control transistor is turned on, and the compensation transistor is turned on, and the high-potential power line writes a high-potential power signal into the first node and the second node.

5. The pixel circuit according to claim 4, characterized in that, The pixel circuit also includes an initialization transistor, one electrode of which is connected to a plate of the first capacitor and a plate of the second capacitor at the fourth node.

6. The pixel circuit according to claim 5, characterized in that, The reset unit includes a reset transistor, and one electrode of the reset transistor is connected to the light-emitting device at the third node.

7. The pixel circuit according to claim 6, characterized in that, The other electrode of the initialization transistor and the other electrode of the reset transistor are both connected to the initialization signal line.

8. The pixel circuit according to claim 6, characterized in that, The other electrode of the initialization transistor is connected to the first initialization signal line, and the other electrode of the reset transistor is connected to the second initialization signal line. The output signal of the first initialization signal line is different from the output signal of the second initialization signal line.

9. The pixel circuit according to claim 6, characterized in that, The pixel circuit further includes a second light-emitting control transistor, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor at the fifth node, and the second electrode of the second light-emitting control transistor is connected to the light-emitting device at the third node; Specifically, when the pixel circuit is configured to compensate for the threshold voltage of the driving transistor, the second light-emitting control transistor is turned on to write the reset signal to the fifth node.

10. The pixel circuit according to claim 9, characterized in that, The other plate of the second capacitor is connected to the second electrode of the second light-emitting control transistor and the second electrode of the reset transistor at the third node.

11. The pixel circuit according to claim 9, characterized in that, The other plate of the second capacitor is connected to the second electrode of the driving transistor and the first electrode of the second light-emitting control transistor at the fifth node.

12. The pixel circuit according to claim 9, characterized in that, The gates of the compensation transistor and the initialization transistor are both connected to the first scan line, and the gate of the switching transistor is connected to the second scan line.

13. The pixel circuit according to claim 9, characterized in that, The gate of the initialization transistor is connected to the first scan line, the gate of the switching transistor is connected to the second scan line, and the gate of the compensation transistor is connected to the third scan line.

14. The pixel circuit according to claim 9, characterized in that, The gate of the first light-emitting control transistor and the gate of the reset transistor are connected to the first light-emitting control line, and the gate of the second light-emitting control transistor is connected to the second light-emitting control line. One of the first light-emitting control transistor and the reset transistor is an N-type transistor, and the other is a P-type transistor.

15. The pixel circuit according to claim 9, characterized in that, The driving transistor, the switching transistor, the compensation transistor, the initialization transistor, and the reset transistor are N-type transistors, and the first light-emitting control transistor and the second light-emitting control transistor are P-type transistors.

16. The pixel circuit according to any one of claims 4 to 15, characterized in that, When the pixel circuit is configured in the first stage, the light-emitting device stops emitting light; When the pixel circuit is configured in the second stage, the compensation transistor and the first light-emitting control transistor are turned on, and the high-potential power line writes a high-potential power signal into the first node and the second node. When the pixel circuit is configured in the third stage, the first light-emitting control transistor is turned off, and the reset unit resets the third node; When the pixel circuit is configured in the fourth stage, the driving transistor is turned on according to the high potential power supply signal written by the first node, so that the charge of the first node is discharged through the compensation transistor and the driving transistor until the driving transistor is turned off, thereby compensating for the threshold voltage of the driving transistor. The reset unit writes a reset signal to the third node. When the pixel circuit is configured in the fifth stage, the switching transistor is turned on, and the data signal is written to the fourth node; When the pixel circuit is configured in the sixth stage, the first light-emitting control transistor is turned on, and the driving transistor is turned on according to the potential of the first node, so as to make the light-emitting device emit light.

17. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 16.

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