Signal connector circuit

Abstract

The application discloses a signal connector circuit, relates to the technical field of circuit design, and comprises a signal connector, a low-frequency filter capacitor, a first filter capacitor group and a printed circuit board, wherein the signal connector is used for connecting a central processing unit and a slave device, the low-frequency filter capacitor is used for filtering a low-frequency power supply ripple, and the first filter capacitor group is used for filtering a high-frequency power supply ripple; the low-frequency filter capacitor is located on a first voltage supply path of the signal connector, and the distance between the positive electrode of the low-frequency filter capacitor and the first power supply pin of the signal connector is less than a first distance; the first filter capacitor group is located on the upper side of a second power supply pin of the signal connector, and the distance between the first filter capacitor group and the second power supply pin is less than a second distance. The application can improve the transmission quality of signals between the central processing unit and the slave device.

Description

Technical Field

[0001] This application relates to the field of circuit design technology, and in particular to a signal connector circuit. Background Technology

[0002] In server motherboard design, signal connectors are key components for achieving high-speed and stable data transmission between the central server and slave devices. Signal connectors are soldered to the printed circuit board (PCB) via gold-plated pins. The circuit design on the PCB, including traces, vias, and filter capacitors, directly affects the signal transmission quality.

[0003] In related technologies, the distance between the filter capacitor and the power pin of the signal connector is relatively far, resulting in a long current transmission path in the signal connector, and the power supply ripple is not effectively suppressed, leading to poor signal quality in the signal connector. Summary of the Invention

[0004] This application provides a signal connector circuit to at least solve the problem of poor signal quality in signal connectors in the related art.

[0005] This application provides a signal connector circuit, including: a signal connector, a low-frequency filter capacitor, a first filter capacitor group, and a printed circuit board, wherein,

[0006] The signal connector is used to connect the central processing unit and the slave device; the low-frequency filter capacitor is used to filter low-frequency power supply ripple; and the first filter capacitor group is used to filter high-frequency power supply ripple.

[0007] The low-frequency filter capacitor is located on the first voltage power supply path of the signal connector, and the distance between the positive terminal of the low-frequency filter capacitor and the first power-on pin of the signal connector is less than the first distance.

[0008] The first filter capacitor bank is located on the upper side of the second power-contacting pin of the signal connector, and the distance between the first filter capacitor bank and the second power-contacting pin is less than the second distance.

[0009] Optionally, a first via is provided on the left side of the low-frequency filter capacitor, and the first via is used to provide a first voltage power supply.

[0010] Multiple second vias are provided on the left side of the first current-carrying pin. The second vias are used to reduce the current density of the first current-carrying pin.

[0011] The first voltage supply path flows from the first via to the second via.

[0012] Optionally, the signal connector circuit also includes a second filter capacitor bank, wherein,

[0013] The low-frequency filter capacitor and the second filter capacitor group are located on the front of the printed circuit board, and the first filter capacitor group is located on the back of the printed circuit board.

[0014] The second filter capacitor group is located on the upper side of the third via on the printed circuit board, and the third via is located on the upper side of the third power pin of the signal connector.

[0015] The third via is used to provide a second voltage supply;

[0016] The distance between the third power pin and the third via is less than the third distance;

[0017] The distance between the third via and the pin of the low-frequency filter capacitor is less than the distance of the fourth via.

[0018] Optionally, the signal connector circuit also includes a grounding network, wherein,

[0019] The grounding network is set between the first and third live pins;

[0020] The grounding network is used to provide a return path for current and signals;

[0021] The grounding network includes the pins of the low-frequency filter capacitor, the pins of the second filter capacitor group, the second power-on pin, and the fourth power-on pin of the signal connector.

[0022] Optionally, the third power-consuming pin has a copper-filled design. The copper-filled design does not cover the gap between the pins and is used to prevent solder bridging between the pins during soldering.

[0023] Optionally, the first filter capacitor bank includes a first sub-filter capacitor and a second sub-filter capacitor, wherein,

[0024] The capacitance of the first sub-filter capacitor is greater than the capacitance of the second sub-filter capacitor;

[0025] The first sub-filter capacitor is used to filter low-frequency power supply ripple.

[0026] The second sub-filter capacitor is used to filter high-frequency power supply ripple.

[0027] Optionally, the second filter capacitor bank includes a third sub-filter capacitor and a fourth sub-filter capacitor, wherein,

[0028] The capacitance of the third sub-filter capacitor is greater than that of the fourth sub-filter capacitor;

[0029] The third sub-filter capacitor is used to filter low-frequency power supply ripple.

[0030] The fourth sub-filter capacitor is used to filter high-frequency power supply ripple.

[0031] Optionally, the signal connector includes a clock signal line, a high-speed signal line, and a low-speed signal line. The clock signal line is used to transmit clock signals, the high-speed signal line is used to transmit high-speed signals, and the low-speed signal line is used to transmit low-speed signals.

[0032] The signal connector includes at least one ground pin, at least one return via, at least one low-speed via, and at least one high-speed via pair. The ground pin is used to provide a signal return path, the return via is used to improve the speed at which high-speed signals return to the ground network, the low-speed via is used to enable the interconnection and transmission of low-speed signals at different layers of the printed circuit board, and the high-speed via pair is used to enable the interconnection and transmission of high-speed signals at different layers of the printed circuit board.

[0033] A return current via is provided on each side of the grounding pin, and at least one of the return current vias on both sides is tangent to the edge of the grounding pin.

[0034] Optionally, the clock signal line exits from the inside of the signal connector and branches outwards;

[0035] Clock signal lines should not come into contact with return vias, low-speed vias, or high-speed vias.

[0036] Optionally, the distance between the clock signal line and the low-speed signal line is greater than the fifth distance;

[0037] The distance between the clock signal line and the return via is greater than the sixth distance.

[0038] Optionally, the upper part of the signal connector includes at least one set of coupling capacitors;

[0039] In the upper part of the signal connector, coupling capacitors, high-speed via pairs and return vias are arranged in groups, including at least two groups, each group containing a set of coupling capacitors, four return vias and a pair of high-speed vias.

[0040] The high-speed via is located to the right of the coupling capacitor;

[0041] Of the four return vias, two are located above the coupling capacitor and the high-speed via pair, and the other two are located below the coupling capacitor and the high-speed via pair.

[0042] Optionally, the grouping includes a first group and a second group, and the arrangement of coupling capacitors, high-speed via pairs and return vias in the first group and the second group is the same;

[0043] The distance between the high-speed via pairs in the first group and the coupling capacitors in the second group is the seventh distance, which includes 53.5 mil;

[0044] The distance between the high-speed via pairs in the first group and the high-speed via pairs in the second group is the eighth distance, which includes 97mm.

[0045] Optionally, for any group, the distance between the coupling capacitor and the high-speed via pair is the ninth distance, which includes 10.5mm;

[0046] For any given group, the angle between the two return vias and the horizontal line is the first angle, which includes 21.8 degrees.

[0047] For any given group, the distance between the return via and the coupling capacitor is the tenth distance, which includes 0.32mm.

[0048] Optionally, the group also includes high-speed signal lines, wherein,

[0049] High-speed signal lines are led out from the printed circuit board and connected in sequence to coupling capacitors and high-speed via pairs;

[0050] For any given group, the distance between the high-speed signal line and the return via is the eleventh distance, which includes 0.43mm.

[0051] The distance between the clock signal line and any high-speed via pair in a group is the twelfth distance, which includes 19.6 mm.

[0052] Optionally, the grouping may also include a third group, wherein,

[0053] The two return vias located above the coupling capacitor and high-speed via are horizontally positioned.

[0054] The two return vias located below the coupling capacitor and the high-speed via are horizontally positioned.

[0055] The four return through holes are symmetrical.

[0056] Optionally, in the lower half of the signal connector, high-speed via pairs and return via groups are arranged, including at least two groups, each group containing a high-speed via pair and at least two return vias.

[0057] Optionally, the grouping includes a fourth group;

[0058] The fourth group has a first high-speed via pair on the upper side and a second high-speed via pair on the lower side. Between the first high-speed via pair and the second high-speed via pair, there is a first return via. The first return via is used to shield the high-speed vias on the upper and lower sides from the transmission of high-speed signals.

[0059] Optionally, the grouping includes a fifth group and a sixth group, wherein,

[0060] The fifth and sixth groups each contain three reflux vias;

[0061] The distance between the high-speed via pairs in the fifth group and the high-speed via pairs in the sixth group is greater than the thirteenth distance.

[0062] Optionally, the grouping includes a seventh group, wherein,

[0063] The seventh group includes the third high-speed via pair, the second return via, and the third return via. The second and third return vias are tangent to the edge of the grounding pin.

[0064] When there are high-speed traces or power traces on the inner layer of the printed circuit board that pass through the third high-speed via pair, the seventh group also includes the fourth return via and the fifth return via, which are located below the third high-speed via pair.

[0065] Optionally, the grouping includes Group 8 and Group 9, wherein,

[0066] The distance between the high-speed via pair and the low-speed signal line in the eighth group is the fourteenth distance, which includes 0.95mm;

[0067] The ninth group includes two return vias and a high-speed via pair. The high-speed via pair is arranged vertically, and the two return vias are located on the upper and lower sides of the high-speed via pair, respectively. The distance between the high-speed via pair and the return via is the fifteenth distance, which includes 0.43mm.

[0068] The signal connector circuit provided in this application embodiment enables the low-frequency filter capacitor to directly intercept low-frequency fluctuations in the 12V power supply by placing the low-frequency filter capacitor on the first voltage power supply path of the signal connector. By setting the distance between the positive terminal of the low-frequency filter capacitor and the first power-consuming pin of the signal connector to be less than a first distance, the current transmission distance between the low-frequency filter capacitor and the first power-consuming pin can be minimized, reducing parasitic resistance and inductance. By placing the first filter capacitor group on the upper side of the second power-consuming pin of the signal connector and limiting the distance between the first filter capacitor group and the second power-consuming pin to be less than a second distance, the current path length between the first filter capacitor group and the second power-consuming pin can be minimized, reducing current transmission loss and improving signal transmission quality. Attached Figure Description

[0069] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0070] Figure 1 This is a connection diagram of a high-speed signal connector provided in an embodiment of this application;

[0071] Figure 2 Schematic diagram of the signal connector circuit provided in the embodiments of this application Figure 1 ;

[0072] Figure 3 Schematic diagram of the signal connector circuit provided in the embodiments of this application Figure 2 ;

[0073] Figure 4 Schematic diagram of the signal connector circuit provided in the embodiments of this application Figure 3 ;

[0074] Figure 5 for Figure 4 Enlarged view of the central area Figure 1 ;

[0075] Figure 6 for Figure 4 Enlarged view of the central area Figure 2 ;

[0076] Figure 7 for Figure 4 Enlarged view of the central area Figure 3 . Detailed Implementation

[0077] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0078] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0079] First, let's introduce the terms used in this application:

[0080] PCB traces: PCB traces refer to copper conductors with a certain width and thickness distributed on various layers. They are divided into strip lines and microstrip lines. Strip lines are strip traces that run on the inner layers of the PCB and are buried inside the PCB. They are embedded between two layers of conductors, so they are not easily affected by external radiation interference. Microstrip lines are strip traces that are attached to the surface layer of the PCB. One side of them is exposed to the air, and the other side is distributed in the insulating medium of the PCB, so they are easily affected by surrounding radiation interference.

[0081] Vias: Also known as metallized vias, vias are common holes drilled at the intersections of printed conductors that need to be connected between layers in double-sided and multilayer boards. The main parameters of a via include the drill hole size, the copper thickness of the hole wall, and the outer diameter of the hole.

[0082] Return vias: When routing signals on a printed circuit board, especially in multilayer boards, many signals must be connected by changing layers. This requires a large number of vias. Vias have two effects on return current: one is that vias form trenches that block return current, and the other is that vias cause return current to jump between layers. In this scenario, in order to ensure the speed of high-speed signal return, return vias with ground (GND) properties are added next to the high-speed layer-changing vias, so that the current can quickly return to the GND terminal.

[0083] Differential traces: A pair of traces responsible for carrying differential signals is called a differential trace. Differential signals require equal signal magnitude and opposite direction, so the coupling between two differential traces is very good, and the impedance transformation is more matched. External noise signals will basically be coupled to both lines at the same time, and the receiving end only focuses on the difference between the two signals. Therefore, external common-mode noise can be completely eliminated, improving the signal transmission quality.

[0084] With the development of cloud computing applications, information technology is gradually covering all areas of society. People are increasingly communicating through the internet in their daily work and life, and the amount of network data is constantly increasing, placing higher demands on server performance. Currently, the signals used in servers' Central Processing Units (CPUs) are mainly Peripheral Component Interconnect Express (PCIe) signals, connecting network cards, hard drives, graphics processing units (GPUs), and other devices. The PCIe signal speed has also evolved rapidly from 1.0 (2.5 GT / s), 2.0 (5 GT / s), 3.0 (8 GT / s), 4.0 (16 GT / s), to 5.0 (32 GT / s). Higher speeds are more susceptible to interference, causing data transmission errors.

[0085] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0086] refer to Figure 1 , Figure 1 This is a connection diagram of a high-speed signal connector provided in an embodiment of the present application, including a PCB board, a slave device, a signal connector, and a CPU.

[0087] High-speed signal connectors are key components for stable and high-speed data transmission between the CPU and slave devices. The slave device makes contact with the gold-plated pins on the connector, and the gold-plated pins are soldered to the PCB board. At the same time, the CPU is also soldered to the PCB board. The PCB board is designed with traces and vias to interconnect the CPU and the connector.

[0088] Devices such as PCIe network cards, cable boards, and GPU cards. Vias are common holes drilled at the intersections of conductors that need to connect different layers. PCB traces include outer layer traces and inner layer traces. Outer layer traces are strip-shaped traces attached to the PCB surface, with one side exposed to air and the other side distributed within the PCB's insulating medium. Inner layer traces are strip-shaped traces embedded within the PCB, nestled between two conductor layers.

[0089] The power supply of the device is obtained from the PCB board through the signal connector. The quality of the signal is directly related to the ripple of the power supply. A common technique is to add a filter capacitor at the power pin of the chip and ensure that the path from the filter capacitor to the power pin is the shortest possible.

[0090] In power transmission paths, related technologies often fail to place filter capacitors directly on the current path, resulting in ineffective suppression of power supply ripple. For example, large-value capacitors (such as 270μF) are not placed close to the power supply pins, and small-value capacitors are not placed adjacent to the chip's power supply pins, causing power supply noise to propagate along long paths and affecting signal quality. Insufficient spacing between high-speed differential signals (PCIe 5.0_RX / TX) and low-speed signals or clock signals leads to crosstalk problems. For example, when the clock signal shares a path with the PCIe 5.0 signal, high-frequency noise can couple into the high-speed signal, causing an increase in the bit error rate (BER).

[0091] Regarding signal routing and via layout, insufficient spacing between related vias can easily exacerbate signal crosstalk. Furthermore, the lack of sufficient GND return vias results in impedance discontinuities in the high-speed signal return path, further deteriorating signal integrity.

[0092] Based on this, embodiments of this application provide a signal connector circuit. By placing a low-frequency filter capacitor on the first voltage power supply path of the signal connector, the low-frequency filter capacitor can directly intercept low-frequency fluctuations in the power supply. By setting the distance between the positive terminal of the low-frequency filter capacitor and the first power-consuming pin of the signal connector to be less than a first distance, the current transmission distance between the low-frequency filter capacitor and the first power-consuming pin can be minimized, reducing parasitic resistance and inductance. By placing the first filter capacitor group on the upper side of the second power-consuming pin of the signal connector and limiting the distance between the first filter capacitor group and the second power-consuming pin to be less than a second distance, the current path length between the first filter capacitor group and the second power-consuming pin can be minimized, reducing current transmission loss and improving signal transmission quality.

[0093] Figure 2 Schematic diagram of the signal connector circuit provided in the embodiments of this application Figure 1 ,like Figure 2 As shown, it includes: a signal connector, a low-frequency filter capacitor, a first filter capacitor bank, and a printed circuit board, wherein... Figure 2 (a) is a schematic diagram of the signal connector circuit, which is a front view of the printed circuit board. Figure 2 (b) is a schematic diagram of the signal connector circuit, which is a view of the back of the printed circuit board.

[0094] Signal connector 1, low-frequency filter capacitor 2, and first filter capacitor group 3 are inserted onto printed circuit board 4. The signal connector is used to connect the central processing unit and the slave device, low-frequency filter capacitor 2 is used to filter low-frequency power supply ripple, and first filter capacitor group 3 is used to filter high-frequency power supply ripple.

[0095] The signal connector 1 includes two power supply voltages: 12V and 3.3V. The 12V supply is the first voltage, and the 3.3V supply is the second voltage. The first voltage supply path refers to the flow from the power supply via through the low-frequency filter capacitor 2 to the first power-contacting pin 5 of the signal connector.

[0096] The distance between the positive power terminal 21 of the low-frequency filter capacitor 2 and the first current-carrying pin 5 is less than a first distance, where the first distance is, for example, 8mm. In this embodiment, the distance between the positive power terminal 21 of the low-frequency filter capacitor 2 and the first current-carrying pin 5 is designed to be 7.2mm. Figure 2 As shown in d1 of (a), the capacitance of the low-frequency filter capacitor 2 is, for example, 270μF.

[0097] For example, the first filter capacitor group 3 can be located on the back of the printed circuit board 4. The first filter capacitor group 3 is located above the second power-contact pin 6 of the signal connector. The distance between the first filter capacitor group 3 and the second power-contact pin 6 is less than a second distance, such as 3mm. In this embodiment, the distance between the first filter capacitor group 3 and the second power-contact pin 6 is designed to be 3mm. Figure 2 As shown in d2 of (b).

[0098] For example, the first filter capacitor group 3 may include a first sub-filter capacitor 31 and a second sub-filter capacitor 32, wherein the capacitance value of the first sub-filter capacitor 31 is greater than the capacitance value of the second sub-filter capacitor 32; the first sub-filter capacitor 31 is used to filter low-frequency power supply ripple; and the second sub-filter capacitor 32 is used to filter high-frequency power supply ripple.

[0099] The capacitance of the first sub-filter capacitor 31 is, for example, 22μF, which can be used to filter low-frequency power supply ripple. The capacitance of the second sub-filter capacitor 32 is, for example, 0.1μF, which can be used to filter high-frequency power supply ripple.

[0100] In the aforementioned signal connector circuit, by placing the low-frequency filter capacitor on the first voltage power supply path of the signal connector, the low-frequency filter capacitor can directly intercept low-frequency fluctuations in the 12V power supply. By setting the distance between the positive terminal of the low-frequency filter capacitor and the first power-consuming pin of the signal connector to be less than a first distance, the current transmission distance between the low-frequency filter capacitor and the first power-consuming pin can be minimized, reducing parasitic resistance and inductance. By placing the first filter capacitor group on the upper side of the second power-consuming pin of the signal connector and limiting the distance between the first filter capacitor group and the second power-consuming pin to be less than a second distance, the current path length between the first filter capacitor group and the second power-consuming pin can be minimized, reducing current transmission loss and improving signal transmission quality.

[0101] Figure 3 Schematic diagram of the signal connector circuit provided in the embodiments of this application Figure 2 .like Figure 3 As shown, a first via 7 is provided on the left side of the low-frequency filter capacitor 2, which is used to provide a first voltage power supply; multiple second vias 8 are provided on the left side of the first current-carrying pin 5, which are used to reduce the current density of the first current-carrying pin 5; the first voltage power supply path flows from the first via 7 to the second via 8.

[0102] The first voltage supply is a 12V voltage supply. The printed circuit board 4 provides a 12V voltage supply to the signal connector 1 through the first via 7.

[0103] The first voltage power supply path flows sequentially from the first via 7 through the low-frequency filter capacitor 2, the second via 8, and the first power-consuming pin 5 of the signal connector.

[0104] The second via 8 is used to reduce the current density of the first current-carrying pin 5. High current density causes the resistive effect of conductors such as solder and pins on the PCB to dissipate electrical energy as heat, leading to an increased voltage drop. Simultaneously, excessively high temperatures can cause electron migration between the interconnects of the PCB layers, resulting in a short circuit and board burnout. Optionally, the second via 8 includes multiple vias, such as 17. In this embodiment, by providing 17 12V vias on the left side of the first current-carrying pin 5, the current density of the first current-carrying pin 5 can be reduced by approximately 70%, avoiding increased voltage drop and heat loss due to current concentration, and preventing electron migration between PCB layers or short circuits that could burn out the board.

[0105] Optional, see Figure 3 The signal connector circuit also includes a second filter capacitor group 9, wherein the low-frequency filter capacitor 2 and the second filter capacitor group 9 are located on the front side of the printed circuit board 4, and the first filter capacitor group 3 is located on the back side of the printed circuit board 4; the second filter capacitor group 9 is located above the third via 10 of the printed circuit board 4, and the third via 10 is located above the third power-on pin 11 of the signal connector; the third via 10 is used to provide a second voltage power supply; the distance between the third power-on pin 11 and the third via 10 is less than a third distance; the distance between the third via 10 and the pin 22 of the low-frequency filter capacitor 2 is less than a fourth distance.

[0106] The second voltage supply is a 3.3V voltage supply. The printed circuit board 4 provides a 3.3V voltage supply to the signal connector 1 through the third via 10. The third via 10 may include multiple vias, such as six vias.

[0107] The third distance, such as 1mm, means that the distance between the third power-conducting pin 11 and the third via 10 is less than 1mm. In this embodiment, the distance between the third power-conducting pin 11 and the third via 10 is designed to be 0.5mm. Figure 3 As shown in d3.

[0108] The fourth distance is 3mm, meaning the distance between the third via 10 and the pin 22 of the low-frequency filter capacitor 2 is less than 3mm. In this embodiment, the distance between the third via 10 and the pin 22 of the low-frequency filter capacitor 2 is set to 2.4mm, and the fourth distance is as follows: Figure 3 As shown in d4.

[0109] In the aforementioned signal connector circuit, the third 3.3V power supply to the third power-consuming pin is provided through the third via, and the third via includes multiple vias, which can reduce the current density at the location of the third power-consuming pin. By limiting the distance between the third via and the third power-consuming pin to a third distance and the distance between the third via and the pin of the low-frequency filter capacitor to a fourth distance, the current transmission path length can be minimized, thereby reducing parasitic resistance and inductance, and reducing voltage drop and power loss.

[0110] For example, the second filter capacitor group 9 includes a third sub-filter capacitor 91 and a fourth sub-filter capacitor 92, wherein the capacitance value of the third sub-filter capacitor 91 is greater than the capacitance value of the fourth sub-filter capacitor 92; the third sub-filter capacitor 91 is used to filter low-frequency power supply ripple; and the fourth sub-filter capacitor 92 is used to filter high-frequency power supply ripple.

[0111] The third sub-filter capacitor 91 has a capacitance value of, for example, 1μF, which can be used to filter low-frequency power supply ripple. The fourth sub-filter capacitor 92 has a capacitance value of, for example, 0.1μF, which can be used to filter high-frequency power supply ripple.

[0112] Optional, see Figure 3 The signal connector circuit also includes a grounding network 12, which is located between the first power-on pin 5 and the third power-on pin 11. The grounding network 12 is used to provide a return path for current and signal. The grounding network 12 includes the pin 22 of the low-frequency filter capacitor 2, the pin 93 of the second filter capacitor group 9, the second power-on pin 6, and the fourth power-on pin 13 of the signal connector.

[0113] The third power pin 11 consists of two parts, upper and lower. The grounding network 12, also known as the GND network, is used to provide a potential reference, establish a signal return path, shield interference, and ensure circuit safety.

[0114] In the GND network, the low-frequency filter capacitor is connected to the second filter capacitor group as one unit. The filtered ripple current can be quickly returned through GND, reducing the return path length and loss.

[0115] Furthermore, the GND network separates the 12V region from the 3.3V region, acting as a shield to prevent low-speed signals from being interfered with by the 12V. The 12V region includes the first via 7, the positive terminal 21 of the low-frequency filter capacitor 2, the second via 8, and the first current-carrying pin 5; the 3.3V region includes the third via 10 and the third current-carrying pin 11, where low-speed signals such as... Figure 3 The signal transmitted in area 14 is shown in the middle, where 14 is a low-speed signal line.

[0116] Optional, see Figure 3 The third power-consuming pin 11 has a copper-filled design. The copper-filled design does not cover the gap between the pins. The copper-filled design is used to prevent the pins from bridging during soldering.

[0117] In conventional copper pour designs, the copper fill covers the gaps between pins. In this embodiment, the copper fill between pins is removed, which prevents solder bridging during soldering and improves yield. Figure 3 As shown, the shaded area represents the copper pour design. There is no shade between adjacent pins in the third power-consuming pin 11, indicating that there is no copper pour between adjacent pins.

[0118] Figure 4 Schematic diagram of the signal connector circuit provided in the embodiments of this application Figure 3 .like Figure 4 The diagram shows the internal wiring of a signal connector. The signal connector includes clock signal lines, high-speed signal lines, and low-speed signal lines. The clock signal lines transmit clock signals, the high-speed signal lines transmit high-speed signals, and the low-speed signal lines transmit low-speed signals. The signal connector includes at least one ground pin, at least one return via, at least one low-speed via, and at least one pair of high-speed vias. The ground pin provides a signal return path, the return vias improve the speed at which high-speed signals return to the ground network, the low-speed vias enable the interconnection of low-speed signals across different layers of the printed circuit board, and the high-speed via pair enables the interconnection of high-speed signals across different layers of the printed circuit board. A return via is located on each side of the ground pin, and at least one of the return vias on each side is tangent to the edge of the ground pin.

[0119] Clock signal line such Figure 4 As shown in Figure 41, there are a total of 4 clock signal lines. The clock signal transmitted in the clock signal lines is called the clock signal.

[0120] High-speed signal lines such as Figure 4 As shown in Figure 42, a high-speed signal, such as a PCIe 5.0 signal, is transmitted through a high-speed signal line. PCIe 5.0 signals are differential traces, meaning each high-speed signal line includes two traces. Figure 4 All other unlabeled signal lines, including those with two separate traces, are high-speed signal lines.

[0121] Low-speed signal lines, such as Figure 4 The routing in area 43 is shown in the diagram. An area including a low-speed signal line is marked in the diagram; the low-speed signal line is a single signal line. Figure 4 The signal lines of the other unlabeled traces are all low-speed signal lines.

[0122] It should be understood that the signal connector in this embodiment includes at least one ground pin, at least one return via, at least one low-speed via, and at least one high-speed via pair. Figure 4 Only one or more components of the corresponding category are marked in the diagram, while the categories of unmarked components can be identified by their shape.

[0123] See Figure 4 44 is the grounding pin, i.e., the GND pin. At least one return via 45 is provided on the upper and lower sides of the grounding pin. At least one of the return vias 45 on the upper and lower sides is tangent to the edge of the grounding pin 44.

[0124] See Figure 446 represents a high-speed via pair. Since the high-speed signal line is designed with two traces, the corresponding high-speed via pair includes two high-speed vias, each corresponding to one of the two traces in the high-speed signal line.

[0125] For example, the clock signal line 41 exits from the inside of the signal connector and radiates outward; the clock signal line does not contact the return via, low-speed via, and high-speed via pairs.

[0126] In the above design, the clock signal is emitted outward from the inside of the signal connector, which can effectively avoid the PCIe 5.0 high-speed signal traces and high-speed via pairs. There will be no common path between the two signals, achieving the effect of no crosstalk between signals.

[0127] Optionally, the distance between the clock signal line and the low-speed signal line is greater than the fifth distance; the distance between the clock signal line and the return via is greater than the sixth distance.

[0128] Furthermore, Figure 4 The coupling capacitors, high-speed vias, and return vias are arranged in groups. Figure 4 R1 to R10 represent different groups of regions, which will be described in detail in the following embodiments.

[0129] For example, such as Figure 5 As shown, Figure 5 for Figure 4 Enlarged view of the central area Figure 1 Specifically, it refers to the first region R1. The fifth distance is as follows: Figure 5 As shown in d5, the upper side is the clock signal line and the lower side is the low-speed signal line. The distance between the low-speed signal line and the clock signal line is greater than the fifth distance d5, which is, for example, 12mil. Figure 4 The distance between all clock signal lines shown and any low-speed signal line is greater than the fifth distance d5.

[0130] The sixth distance is as follows Figure 5 As shown in d6, the upper right side is the clock signal line, and the lower side is the return via. The distance between the clock signal line and the return via is greater than the sixth distance d6, which is, for example, 8mil. Figure 4 The distance between all clock signal lines shown and any of the return vias is greater than the sixth distance d6.

[0131] In the aforementioned signal connector circuit, physical isolation is achieved by limiting the distance between the clock signal line and the low-speed signal line to a greater than the fifth distance, thus blocking crosstalk between the two signals. This prevents noise interference from the low-speed signal from interfering with the clock link and avoids high-frequency components of the clock signal interfering with the transmission of the low-speed signal. By limiting the distance between the clock signal line and the return via to a greater than the sixth distance, electrical insulation between the clock signal and GND is ensured, avoiding the risk of short circuits. At the same time, the small spacing does not compress the GND copper layer area, ensuring that the return current of the clock signal can be smoothly introduced into the GND network and reducing return path losses.

[0132] Furthermore, Figure 4 The upper half is the receiving end, and the lower half is the transmitting end. That is, the upper half is the PCIe 5.0_RX signal, and there is a coupling capacitor design between the signal connector and the CPU. The lower half is the PCIe 5.0_TX signal, and there is no coupling capacitor design between the connector and the CPU.

[0133] For example, the upper part of the signal connector includes at least one set of coupling capacitors; in the upper part of the signal connector, the coupling capacitors, high-speed via pairs and return vias are grouped and arranged, including at least two groups, each group including one set of coupling capacitors, four return vias and a pair of high-speed vias; the pair of high-speed vias is located to the right of the coupling capacitors; of the four return vias, two return vias are located above the coupling capacitors and the pair of high-speed vias, and the other two return vias are located below the coupling capacitors and the pair of high-speed vias.

[0134] For example, Figure 6 for Figure 4 Enlarged view of the central area Figure 2 Among them, (a) to (i) are included. It should be noted that the areas shown in (a), (d), (e), (f), and (g) are the same area and are used to demonstrate the annotations; the areas shown in (b) and (c) are the same area and are used to demonstrate the annotations.

[0135] See Figure 6 (a), Figure 6 (a) is Figure 4 Enlarged view of the second region R2 Figure 1 .

[0136] The area shown in R2 is a group, where 61 is a coupling capacitor, 62 to 65 are four return vias, and 66 is a pair of high-speed vias.

[0137] High-speed via pair 66 is located to the right of coupling capacitor 61, return via 62 and return via 63 are located above coupling capacitor 61 and high-speed via pair 66, and return via 64 and return via 65 are located below coupling capacitor 61 and high-speed via pair 66.

[0138] For example, the R3 region includes a first group and a second group, and the coupling capacitors, high-speed via pairs and return vias in the first group and the second group are arranged in the same way; the distance between the high-speed via pairs in the first group and the coupling capacitors in the second group is a seventh distance, which includes 53.5 mil; the distance between the high-speed via pairs in the first group and the high-speed via pairs in the second group is an eighth distance, which includes 97 mm.

[0139] See Figure 6 (b) Figure 6 (b) is Figure 4 Enlarged view of the third region R3 Figure 1 The first group is the left-side group, and the second group is the right-side group. The categories of components within the first and second groups can be found by referring to... Figure 6 (a), which will not be elaborated here. The distance between the rightmost high-speed via edge in the first group and the leftmost coupling capacitor edge in the second group is the seventh distance d7. In this embodiment, d7 is 53.5 mil. This distance can ensure that the spacing between the high-speed trace and the return via is greater than 26 mil.

[0140] See Figure 6 (c) Figure 6 (c) is Figure 4 Enlarged view of the third region R3 Figure 2 The distance between the right edge of the high-speed via pair in the first group and the left edge of the high-speed via pair in the second group is the eighth distance d8. In this embodiment, d8 is 97mm.

[0141] For example, for any group, the distance between the coupling capacitor and the high-speed via pair is the ninth distance, which includes 10.5 mm; for any group, the angle between the two return vias and the horizontal line is the first angle, which includes 21.8 degrees; for any group, the distance between the return via and the coupling capacitor is the tenth distance, which includes 0.32 mm.

[0142] See Figure 6 (d) Figure 6 (d) is Figure 4 Enlarged view of the second region R2 Figure 2 In this group, the distance between the right edge of the coupling capacitor and the left edge of the high-speed via pair is the ninth distance d9. In this embodiment, d9 is 10.5 mm.

[0143] See Figure 6 (e), Figure 6 (e) is Figure 4 Enlarged view of the second region R2 Figure 3 In this group, the angle between the two return vias located on the upper side of the coupling capacitor and the horizontal line is a first angle a1. In this embodiment, the first angle a1 is 21.8 degrees. Similarly, the angle between the two return vias located on the lower side of the coupling capacitor and the horizontal line is also a first angle a1.

[0144] See Figure 6 (f), Figure 6 (f) is Figure 4 Enlarged view of the second region R2 Figure 4 In this group, the distance between the lower edge of the return via closest to the coupling capacitor and the upper edge of the coupling capacitor is the tenth distance d10. In this embodiment, d10 is 0.32 mm.

[0145] For example, the group also includes a high-speed signal line, which is led out from the printed circuit board and connected in sequence to a coupling capacitor and a high-speed via pair; for any group, the distance between the high-speed signal line and the return via is an eleventh distance, which includes 0.43 mm; the distance between the clock signal line and the high-speed via pair in any group is a twelfth distance, which includes 19.6 mm.

[0146] See Figure 6 (g), Figure 6 (g) is Figure 4 Enlarged view of the second region R2 Figure 5 In this group, the distance between the return via closest to the high-speed via pair and the high-speed signal line is the eleventh distance d11. In this embodiment, the eleventh distance d11 is 0.43 mm.

[0147] See Figure 6 (h), Figure 6 (h) is Figure 4 An enlarged schematic diagram of the fourth region R4. The clock signal line emerges from the right side of the group in this region. The distance between the edge of the high-speed via and the outermost edge of the clock signal line is the twelfth distance d12. In this embodiment, the twelfth distance d12 is 19.6 mm.

[0148] Optionally, the grouping also includes a third group, wherein the two return vias located above the coupling capacitor and high-speed via pair are horizontally arranged; the two return vias located below the coupling capacitor and high-speed via pair are horizontally arranged; and the four return vias are symmetrical from left to right.

[0149] See Figure 6 (i), Figure 6 (i) is Figure 4The enlarged schematic diagram of the fifth region R5 is specifically an enlarged schematic diagram of the third group. Unlike the placement of the return vias in the first or second group, in this group, the two return vias above the coupling capacitor are located on the same horizontal line, the two return vias below the coupling capacitor are located on the same horizontal line, and the four return vias are symmetrically arranged from left to right.

[0150] Optionally, in the lower half of the signal connector, high-speed via pairs and return via groups are arranged, including at least two groups, each group containing a high-speed via pair and at least two return vias.

[0151] For example, the group includes a fourth group; the fourth group has a first high-speed via pair on the upper side and a second high-speed via pair on the lower side, and a first return via is provided between the first high-speed via pair and the second high-speed via pair. The first return via is used to shield the high-speed vias on the upper and lower sides from the influence of the high-speed signals transmitted.

[0152] See Figure 7 , Figure 7 for Figure 4 Enlarged view of the central area Figure 3 . Figure 7 (a) is Figure 4 The enlarged schematic diagram of region R6 in the middle section is shown, specifically the fourth group. Due to the absence of coupling capacitors in the fourth group, the design space is relatively large, and the traces and vias are staggered to increase spacing. The fourth group includes two pairs of high-speed vias and four return vias. The first high-speed via pair 71 is located at the top, and the second high-speed via pair 72 is located in the middle. Between the first high-speed via pair 71 and the second high-speed via pair 72, a first return via 73 is provided. The first return via 73 is located on the line connecting the first high-speed via pair 71 and the second high-speed via pair 72, or at a certain distance from that line, for example, 1mm to the left or 1mm to the right of that line. The first return via 73, positioned between the first high-speed via pair 71 and the second high-speed via pair 72, can shield the high-speed vias on the upper and lower sides from the transmission of high-speed signals. Optionally, the lower side of the second high-speed via pair may also include three return vias.

[0153] For example, the grouping includes a fifth group and a sixth group, wherein the fifth group and the sixth group each include three return vias; the distance between the high-speed via pairs in the fifth group and the high-speed via pairs in the sixth group is greater than the thirteenth distance.

[0154] See Figure 7 (b) Figure 7 (b) is Figure 4The enlarged schematic diagram of region R7 in the middle section specifically includes the fifth group and the sixth group, with the fifth group on the left and the sixth group on the right. The return vias and high-speed via pairs in the fifth and sixth groups are designed in the same positions, each including three return vias and one pair of high-speed vias.

[0155] The distance between the right edge of the high-speed via pair in the fifth group and the left edge of the high-speed via pair in the sixth group is greater than the thirteenth distance d13. In this embodiment, the thirteenth distance d13 is, for example, 85 mil.

[0156] For example, the group includes a seventh group, wherein the seventh group includes a third high-speed via pair, a second return via, and a third return via, the second return via and the third return via being tangent to the edge of the ground pin; when there are high-speed traces or power traces on the inner layer of the printed circuit board passing through the third high-speed via pair, the seventh group also includes a fourth return via and a fifth return via, the fourth return via and the fifth return via being located below the third high-speed via pair.

[0157] See Figure 7 (c) Figure 7 (c) is Figure 4 The enlarged schematic diagram of region R8 in the diagram is specifically an enlarged schematic diagram of group 7. In group 7, the third high-speed via pair is 74, the second return via is 75, and the third return via is 76. When high-speed or power traces on the inner layers of the PCB pass through the third high-speed via pair 74, group 7 also includes the fourth return via 77 and the fifth return via 78. That is, when high-speed or power traces on the inner layers of the PCB pass through the third return via 76, the fourth return via 77 and the fifth return via 78 must be retained; otherwise, they can be deleted.

[0158] For example, the group includes an eighth group and a ninth group, wherein the distance between the high-speed via pair and the low-speed signal line in the eighth group is the fourteenth distance, which includes 0.95mm; the ninth group includes two return vias and two high-speed via pairs, the two high-speed via pairs are arranged vertically, the two return vias are respectively located on the upper and lower sides of the two high-speed via pairs, and the distance between the high-speed via pairs and the return vias is the fifteenth distance, which includes 0.43mm.

[0159] See Figure 7 (d) Figure 7 (d) is Figure 4The enlarged schematic diagram of the ninth region R9 is specifically an enlarged schematic diagram of the eighth group. The eighth group includes two return vias and a pair of high-speed vias. The low-speed signal line passes through the right side of the eighth group, and the distance between the low-speed signal line and the right edge of the high-speed via pair is the fourteenth distance d14. In this embodiment, the fourteenth distance d14 is 0.95mm.

[0160] See Figure 7 (e), Figure 7 (e) is Figure 4 The enlarged schematic diagram of the tenth region R10 is specifically an enlarged schematic diagram of the ninth group. The ninth group includes two return vias and a pair of high-speed vias. Because the high-speed vias are far from other signals, only two return vias are designed, and these two return vias are located on the upper and lower sides of the high-speed via pair, respectively, and are in the same vertical direction as the high-speed via pair. The distance between the uppermost edge of the upper return via and the high-speed via pair is the fifteenth distance d15. In this embodiment, the fifteenth distance d15 is 0.43 mm. Similarly, the distance between the lower return via and the lowermost edge of the high-speed via pair is also d15.

[0161] The signal connector circuit provided in this application embodiment simultaneously hosts power, GND, PCIE5.0 signals, Clock signals, and low-speed signals. In this case, a large capacitor is placed in the current flow path, and the smaller the capacitance value, the closer it is to the power pin, effectively filtering out power ripple. The copper plating of the power pin of the signal connector is hollowed out, which can effectively avoid solder bridging during soldering. The PCIE5.0_TX, PCIE5.0_RX, and Clock signals are mutually exclusive in their emission directions through this design, and there will be no common path between any two, achieving the effect of no crosstalk between signals. The design of the relative positions of high-speed via pairs, return vias, coupling capacitors, and the angle of return vias for PCIE5.0_RX and TX signals fully considers the influence between signals, so that the PCIE5.0 signal can be transmitted stably.

[0162] The signal connector circuit provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A signal connector circuit, characterized in that, include: Signal connector, low-frequency filter capacitor, first filter capacitor bank, and printed circuit board, among which, The signal connector is used to connect the central processing unit and the slave device, the low-frequency filter capacitor is used to filter low-frequency power supply ripple, and the first filter capacitor group is used to filter high-frequency power supply ripple. The low-frequency filter capacitor is located on the first voltage power supply path of the signal connector, and the distance between the positive terminal of the low-frequency filter capacitor and the first power-contacting pin of the signal connector is less than the first distance. The first filter capacitor group is located on the upper side of the second power-contacting pin of the signal connector, and the distance between the first filter capacitor group and the second power-contacting pin is less than the second distance; The first distance is used to minimize the current transmission distance between the low-frequency filter capacitor and the first power-consuming pin, thereby reducing parasitic resistance and inductance. The second distance is used to minimize the current path length between the first filter capacitor bank and the second power-consuming pin, thereby reducing current transmission loss and improving signal transmission quality.

2. The signal connector circuit according to claim 1, characterized in that, A first via is provided on the left side of the low-frequency filter capacitor, and the first via is used to provide a first voltage power supply. Multiple second vias are provided on the left side of the first current-collecting pin. The second vias are used to reduce the current density of the first current-collecting pin. The first voltage supply path flows from the first via to the second via.

3. The signal connector circuit according to claim 1, characterized in that, It also includes a second filter capacitor bank, wherein, The low-frequency filter capacitor and the second filter capacitor group are located on the front side of the printed circuit board, and the first filter capacitor group is located on the back side of the printed circuit board. The second filter capacitor group is located above the third via on the printed circuit board, and the third via is located above the third power pin of the signal connector. The third via is used to provide a second voltage power supply; The distance between the third power-consuming pin and the third via is less than the third distance; The distance between the third via and the pin of the low-frequency filter capacitor is less than the fourth distance.

4. The signal connector circuit according to claim 3, characterized in that, It also includes the grounding network, in which, The grounding network is disposed between the first power-conducting pin and the third power-conducting pin; The grounding network is used to provide a return path for current and signals; The grounding network includes the pins of the low-frequency filter capacitor, the pins of the second filter capacitor group, the second power-consuming pin, and the fourth power-consuming pin of the signal connector.

5. The signal connector circuit according to claim 3, characterized in that, The third power-consuming pin has a copper-filled design that does not cover the gap between the pins. The copper-filled design is used to prevent solder bridging between the pins during soldering.

6. The signal connector circuit according to claim 1, characterized in that, The first filter capacitor group includes a first sub-filter capacitor and a second sub-filter capacitor, wherein, The capacitance of the first sub-filter capacitor is greater than the capacitance of the second sub-filter capacitor; The first sub-filter capacitor is used to filter low-frequency power supply ripple; The second sub-filter capacitor is used to filter high-frequency power supply ripple.

7. The signal connector circuit according to claim 3, characterized in that, The second filter capacitor group includes a third sub-filter capacitor and a fourth sub-filter capacitor, wherein, The capacitance value of the third sub-filter capacitor is greater than the capacitance value of the fourth sub-filter capacitor; The third sub-filter capacitor is used to filter low-frequency power supply ripple. The fourth sub-filter capacitor is used to filter high-frequency power supply ripple.

8. The signal connector circuit according to claim 1, characterized in that, The signal connector includes a clock signal line, a high-speed signal line, and a low-speed signal line. The clock signal line is used to transmit clock signals, the high-speed signal line is used to transmit high-speed signals, and the low-speed signal line is used to transmit low-speed signals. The signal connector includes at least one ground pin, at least one return via, at least one low-speed via, and at least one high-speed via pair. The ground pin is used to provide a signal return path, the return via is used to increase the speed at which high-speed signals return to the ground network, the low-speed via is used to enable the interconnection and transmission of low-speed signals at different layers of the printed circuit board, and the high-speed via pair is used to enable the interconnection and transmission of high-speed signals at different layers of the printed circuit board. Each of the grounding pins has a return current via on both sides, and at least one of the return current vias on both sides is tangent to the edge of the grounding pin.

9. The signal connector circuit according to claim 8, characterized in that, The clock signal line exits from the inside of the signal connector and extends outwards; The clock signal line does not come into contact with the return via, the low-speed via, and the high-speed via.

10. The signal connector circuit according to claim 8, characterized in that, The distance between the clock signal line and the low-speed signal line is greater than the fifth distance; The distance between the clock signal line and the return via is greater than the sixth distance.

11. The signal connector circuit according to claim 8, characterized in that, The upper part of the signal connector includes at least one set of coupling capacitors; In the upper part of the signal connector, the coupling capacitor, the high-speed via pair, and the return via are arranged in groups, including at least two groups, each group including a set of the coupling capacitor, four of the return vias, and the high-speed via pair; The high-speed via is located to the right of the coupling capacitor; Of the four return vias, two are located above the coupling capacitor and the high-speed via pair, and the other two are located below the coupling capacitor and the high-speed via pair.

12. The signal connector circuit according to claim 11, characterized in that, The grouping includes a first group and a second group, and the first group and the second group have the same arrangement of coupling capacitors, high-speed via pairs and return vias; The distance between the high-speed via pair in the first group and the coupling capacitor in the second group is the seventh distance, which includes 53.5 mil; The distance between the high-speed via pairs in the first group and the high-speed via pairs in the second group is the eighth distance, which includes 97 mm.

13. The signal connector circuit according to claim 12, characterized in that, For any given group, the distance between the coupling capacitor and the high-speed via pair is the ninth distance, which includes 10.5 mm; For any given group, the angle between the two return vias and the horizontal line is the first angle, which includes 21.8 degrees. For any given group, the distance between the return via and the coupling capacitor is the tenth distance, which includes 0.32 mm.

14. The signal connector circuit according to claim 13, characterized in that, The group also includes the high-speed signal line, wherein... The high-speed signal line is led out from the printed circuit board and connected in sequence to the coupling capacitor and the high-speed via pair; For any given group, the distance between the high-speed signal line and the return via is the eleventh distance, which includes 0.43 mm; The distance between the clock signal line and any high-speed via pair in the group is the twelfth distance, which includes 19.6 mm.

15. The signal connector circuit according to claim 12, characterized in that, The grouping also includes a third group, wherein, The two return vias located above the coupling capacitor and high-speed via are horizontally positioned. The two return vias located below the coupling capacitor and the high-speed via are horizontally positioned. The four reflux orifices are symmetrical from left to right.

16. The signal connector circuit according to claim 8, characterized in that, In the lower half of the signal connector, the high-speed via pairs and the return via groups are arranged, including at least two groups, each group including the high-speed via pairs and at least two of the return vias.

17. The signal connector circuit according to claim 16, characterized in that, The grouping includes a fourth group; The fourth group has a first high-speed via pair on the upper side and a second high-speed via pair on the lower side. A first return via is provided between the first high-speed via pair and the second high-speed via pair. The first return via is used to shield the high-speed vias on the upper and lower sides from the transmission of high-speed signals.

18. The signal connector circuit according to claim 16, characterized in that, The grouping includes a fifth group and a sixth group, wherein, The fifth group and the sixth group each include three reflux vias; The distance between the high-speed via pairs in the fifth group and the high-speed via pairs in the sixth group is greater than the thirteenth distance.

19. The signal connector circuit according to claim 16, characterized in that, The grouping includes a seventh group, wherein, The seventh group includes a third high-speed via pair, a second return via, and a third return via, wherein the second return via and the third return via are tangent to the edge of the grounding pin; When a high-speed trace or power trace exists in the inner layer of the printed circuit board and passes through the third high-speed via pair, the seventh group also includes a fourth return via and a fifth return via, which are located below the third high-speed via pair.

20. The signal connector circuit according to claim 16, characterized in that, The grouping includes group eight and group nine, wherein, The distance between the high-speed via pair and the low-speed signal line in the eighth group is the fourteenth distance, which includes 0.95mm; The ninth group includes two reflux vias and a high-speed via pair. The high-speed via pair is arranged vertically. The two reflux vias are respectively located on the upper and lower sides of the high-speed via pair. The distance between the high-speed via pair and the reflux via is the fifteenth distance, which includes 0.43mm.

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