High-reliability Hall decoding circuit for three-phase gate driver

Abstract

The invention discloses a high-reliability Hall decoding circuit for a three-phase gate driver. The device comprises an input filtering unit and a decoding unit. The input filtering unit is used for receiving Hall signals from the brushless direct current motor and filtering out non-ideal signals in the Hall signals so as to ensure the accuracy of Hall logic solution; and the decoding unit is used for resolving the Hall signals according to a specific logic sequence and converting the Hall signals into six paths of gate driving signals so as to control the motor to rotate. The circuit is high in reliability and simple in structure, and can be integrated into a three-phase gate driver, external input only needs to provide a single-path PWM signal and a DIR direction signal, generation and phase distribution of six paths of driving signals can be completed through internal logic, and the input complexity of control signals is effectively reduced.

Description

Technical Field

[0001] This invention relates to three-phase gate drive technology in integrated circuit driving systems, and more particularly to a high-reliability Hall decoding unit for a three-phase gate driver. Background Technology

[0002] Brushless DC motors are typical mechatronic products, characterized by high power, low noise, reliable operation, long service life, lightweight design, and low cost. They are widely used in consumer electronics, automotive electronics, and industrial equipment. A brushless DC motor generally consists of a stator with coil windings, a rotor made of permanent magnet materials, and Hall effect position sensors. Based on the principle of electromagnetic induction, the stator generates a magnetic field by controlling the winding current, which drives the rotor to rotate. Hall effect integrated circuits are evenly distributed on the motor stator. Each time the rotor rotates past a pair of magnetic poles, the sensor generates a set of transition signals. Typically, three Hall effect position sensors with a spatial position difference of 120° are used.

[0003] The three-phase full-bridge inverter circuit is an important component for controlling brushless DC motors. It converts DC input into three-phase AC. However, the logic input signal has limited voltage and current capabilities and cannot directly drive power semiconductor devices. Therefore, a gate drive circuit is used to amplify the logic signal to control the on and off of the power switching devices.

[0004] However, traditional three-phase gate drive circuits often require six independent logic input signals to obtain the six power drive signals needed to drive the power switching devices. This significantly increases the complexity of the control signal input. A common solution is to add a Hall decoder chip externally, but this also increases the overall drive system area, limiting application scenarios. During motor system operation, the working environment usually has strong electromagnetic interference, which can cause distortion of the Hall signal output by the motor, thus affecting the accuracy and reliability of Hall logic calculation and causing abnormal motor operation. In addition, due to the effect of motor inductance, a third phase conduction phenomenon may occur during non-commutation periods. When the motor starts and commutates, the current will be much larger than the normal operating current. The large conduction current will inevitably bring large torque ripples, and when the large current has nowhere to be released, there is a risk of burnout. Due to the above-mentioned problems, the high reliability and high stability application requirements of brushless DC motors cannot be met in related technologies. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing a highly reliable Hall decoding unit for a three-phase gate driver. This invention can filter out non-ideal signal components mixed in with the motor Hall signal, obtaining a stable and reliable drive signal. At the same time, it has a simple structure and can be integrated into a three-phase gate driver, effectively reducing the chip area.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A high-reliability Hall decoding unit for a three-phase gate driver includes an input filtering unit and a decoding unit. The input filtering unit receives Hall signals from a brushless DC motor and filters out non-ideal signals to ensure the accuracy of Hall logic calculation. The decoding unit decodes the Hall signals according to a specific logical sequence and converts them into six gate drive signals to control motor rotation.

[0007] Furthermore, the input filtering unit includes PMOS transistors PM0, PM1, PM2, PM3, and PM4; NMOS transistors NM0, NM1, and NM2; Schmitt trigger SCHT1; and inverters INV1 and INV2.

[0008] The PMOS transistors PM1 and PM2 are connected in series. The gates of PM1 and PM2 are connected to the external bias offset on one side and the gate of PM3 on the other side, forming a current mirror. The sources of PM2 and PM3 are connected to the power supply, and the drain of PM3 is connected to the source of PM0. PM0 and NM0 form an inverter. The source of NM0 is grounded, and its gate is connected to the input signal IN and the gate of NM1. Its drain is connected to the drain of NM2 and the input of SCHT1. The source of NM2 is connected to the drain of NM1. The source of NM1 is grounded. The gate of NM2 is connected to the output of SCHT1 and the input of INV1. The output of INV1 is connected to the input of INV2 and the final output terminal OUT. The output of INV2 is connected to the final output terminal OUT_.

[0009] Furthermore, the decoding unit includes XOR gates XOR1, XOR2, and XOR3; a Hall effect decoder circuit; three-input AND gates AND1, AND2, and AND3; and a two-input AND gate AND4.

[0010] The XOR gates XOR1, XOR2, and XOR3 are connected at one end to the direction signal DIR and at the other end to the Hall signal processed by the input filter unit, respectively. The outputs of XOR1, XOR2, and XOR3 are connected to the inputs of the Hall effect calculation circuit. Two inputs of the three-input AND gates AND1, AND2, and AND3 are connected to the outputs of the Hall effect calculation circuit, and the other input is connected to the output of the two-input AND gate AND4. The outputs of AND1, AND2, and AND3 serve as three high-side outputs H1, H2, and H3. The remaining outputs of the Hall effect calculation circuit serve as three low-side outputs L1, L2, and L3. The input of AND4 is connected to the PWM and the shutdown protection port SHUT.

[0011] This circuit can be integrated into a three-phase gate driver, effectively reducing the chip area.

[0012] The beneficial effects of this invention are as follows: 1. The present invention includes a filtering unit, which can filter out the non-ideal signal part mixed in the motor Hall signal and obtain a stable and reliable drive signal; 2. The present invention has a simple structure and can be directly integrated into a three-phase gate driver, which can effectively reduce the chip area compared with the existing discrete structure.

[0013] 3. The present invention has a built-in shutdown protection port SHUT. In order to improve motor efficiency and stabilize the starting state as soon as possible, the upper bridge arm of the SHUT is fully shut off, and the lower bridge arm is turned on for a certain period of time according to the input. This allows the current of the motor inductor to be discharged to zero as soon as possible through the lower bridge arm when the upper bridge arm is disconnected, thereby reducing the impact of torque pulsation and further improving reliability. Attached Figure Description

[0014] Figure 1 This is one embodiment of the present invention in practical application.

[0015] Figure 2 This is the circuit diagram of the input filter unit of the present invention.

[0016] Figure 3 This is a circuit diagram of the decoding unit of the present invention.

[0017] Figure 4 This is a waveform diagram of the present invention under normal operating conditions.

[0018] Figure 5 This is a waveform diagram of the present invention under the condition that the input signal is distorted.

[0019] Figure 6 This is a waveform diagram of the present invention with the shutdown protection function enabled. Detailed Implementation

[0020] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0021] Figure 1This is one embodiment of the invention in practical application. The input filtering unit receives three Hall signals from the motor, filtering out non-ideal signals. The decoding unit converts the Hall position signals of the brushless DC motor into control drive signals, achieving precise motor control. Specifically, the three Hall signals from the brushless motor Hall sensor, with a 120° phase difference, are filtered and decoded to generate six control signals H1, H2, H3 and L1, L2, L3 for driving the three-phase bridge arm power devices. The three-phase gate driver then converts the low-voltage control signals into high-voltage drive signals. The direction control signal (DIR) determines the motor's rotation direction, enabling forward and reverse rotation control. A single PWM signal input from the external microcontroller unit controls the motor speed by adjusting the duty cycle.

[0022] Figure 2 This is the circuit diagram of the input filtering unit. This circuit is powered by an internal power supply, effectively reducing chip area and power consumption. The bias offset port is connected to the current mirror; PM1 and PM2 are current mirror loads, providing a stable gate voltage to PM3. When PM3 is on, the loop current is limited. When the input signal IN is low, PM0 and PM3 are both on, limiting the gate capacitor charging current of the subsequent Schmitt trigger and extending the charging time. When the input signal IN is high but a narrow low-level pulse appears, this pulse can be directly filtered out to prevent non-ideal signals from affecting the accuracy and reliability of the subsequent decoding unit. When the input IN is high, NM0 is on, the Schmitt trigger outputs a high level, and the output feeds back to the gate of NM2, turning it on. Subsequently, NM1 is on, forming positive feedback and accelerating the level transition between OUT and OUT_.

[0023] Figure 3 This is the schematic diagram of the decoding unit circuit. A logic gate array is used to process the original Hall signal, generating and distributing six drive signals according to the correspondence in Table 1. Square wave modulation uses an H-PWM_L-ON control method, meaning the upper bridge arm uses PWM modulation, while the lower bridge arm remains constantly on during conduction. A combinational logic circuit is designed in the Hall logic section to output PWM on the high side and DC signal on the low side. This design reduces switching losses by half compared to simultaneous dual-arm PWM modulation (ON-PWM). The shutdown protection port SHUT controls the high-side output through AND gate AND4 to handle possible abnormal situations during motor operation. For example, when the motor experiences a short circuit or other fault, the system can quickly shut down the high-side power devices of the three-phase bridge arms through SHUT, effectively protecting the motor and drive circuit from damage.

[0024] Table 1 Figure 4The diagram shows the waveform of the present invention under normal operating conditions, which further illustrates the working principle of the present invention. The input filtering unit receives Hall signals HA, HB, and HC. The decoding unit decodes the signals in a "two-by-two" manner. Specifically, only one channel on the high side and one channel on the low side can be turned on at the same time. The output of the high side is a PWM square wave with the same frequency and phase, while the output of the low side is a constant high level during the conduction period.

[0025] Figure 5 The waveform diagram of the present invention under the condition of input signal distortion is shown. During the periods t1~t2 and t3~t4, the input signal has different degrees of distortion to simulate the interference signals that may exist in actual applications. Despite the presence of non-ideal input signals, the present invention can still correctly identify and decode them, ensuring that the six-channel drive signal output is normal and has high reliability.

[0026] Figure 6 The waveform diagram is shown when the shutdown protection function of the present invention is enabled. In the above state, the present invention will shut down all high-side outputs and the low-side will be turned on for a certain period of time according to the input. This allows the current of the motor inductor to be discharged to zero as soon as possible through the lower bridge arm when the upper bridge arm is disconnected, thereby reducing the influence of torque pulsation and dealing with abnormal situations that may occur during motor startup and commutation, thus effectively protecting the motor and drive circuit from damage.

[0027] The above description, in conjunction with specific / preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. Those skilled in the art can make various substitutions or modifications to these described embodiments without departing from the inventive concept, and all such substitutions or modifications should be considered within the scope of protection of the present invention.

[0028] The parts of this invention not described in detail are well-known to those skilled in the art.

Claims

1. A high-reliability Hall decoder circuit for a three-phase gate driver, characterized in that, It includes an input filtering unit and a decoding unit; the input filtering unit is used to receive Hall signals from the brushless DC motor and filter out non-ideal signals mixed in with the motor Hall signals; the decoding unit is used to decompose the Hall signals in a specific logical order and convert them into six gate drive signals to control the rotation of the motor.

2. The high-reliability Hall decoder circuit for a three-phase gate driver according to claim 1, characterized in that, The input filtering unit includes PMOS transistors PM0, PM1, PM2, PM3, and PM4; NMOS transistors NM0, NM1, and NM2; a Schmitt trigger SCHT1; and inverters INV1 and INV2. The PMOS transistors PM1 and PM2 are connected in series. The gates of PM1 and PM2 are connected to the external bias offset on one side and the gate of PM3 on the other side, forming a current mirror. The sources of PM2 and PM3 are connected to the power supply, and the drain of PM3 is connected to the source of PM0. PM0 and NM0 form an inverter. The source of NM0 is grounded, and its gate is connected to the input signal IN and the gate of NM1. Its drain is connected to the drain of NM2 and the input of SCHT1. The source of NM2 is connected to the drain of NM1. The source of NM1 is grounded. The gate of NM2 is connected to the output of SCHT1 and the input of INV1. The output of INV1 is connected to the input of INV2 and the final output terminal OUT. The output of INV2 is connected to the final output terminal OUT_.

3. A high-reliability Hall decoder circuit for a three-phase gate driver according to claim 2, characterized in that, The decoding unit includes XOR gates XOR1, XOR2, and XOR3; a Hall effect decoder circuit; three-input AND gates AND1, AND2, and AND3; and a two-input AND gate AND4. The XOR gates XOR1, XOR2, and XOR3 are connected at one end to the direction signal DIR and at the other end to the Hall signal processed by the input filter unit, respectively. The outputs of XOR1, XOR2, and XOR3 are connected to the inputs of the Hall effect calculation circuit. Two inputs of the three-input AND gates AND1, AND2, and AND3 are connected to the outputs of the Hall effect calculation circuit, and the other input is connected to the output of the two-input AND gate AND4. The outputs of AND1, AND2, and AND3 serve as three high-side outputs H1, H2, and H3. The remaining outputs of the Hall effect calculation circuit serve as three low-side outputs L1, L2, and L3. The input of AND4 is connected to the PWM and the shutdown protection port SHUT.

4. A high-reliability Hall decoder circuit for a three-phase gate driver according to claim 2, characterized in that, The circuit is implemented as follows: Three Hall signals with a 120° phase difference from the Hall sensor of the brushless motor are processed by the input filtering unit and the decoding unit to generate six control signals H1, H2, H3 and L1, L2, L3 for driving the three-phase bridge arm power devices. The three-phase gate driver completes the conversion of the low-voltage control signal to the high-voltage drive signal. The direction control signal received by the input filtering unit is used to determine the rotation direction of the motor and realize the control of forward and reverse rotation. The input filtering unit receives the PWM signal and adjusts the duty cycle to control the motor speed.

5. A high-reliability Hall decoder circuit for a three-phase gate driver according to claim 2, characterized in that, The input filtering unit works as follows: The input filtering unit is powered by an internal power supply circuit, effectively reducing the chip area and power consumption. The bias offset port is connected to the current mirror, and PM1 and PM2 are current mirror loads, providing a stable gate voltage to PM3. When PM3 is turned on, the loop current is limited. When the input signal IN is low, PM0 and PM3 are turned on simultaneously, limiting the charging current of the gate capacitor of the subsequent Schmitt trigger and extending the charging time. When the input signal IN is high but a narrow pulse with a low level appears, the pulse is directly filtered out to prevent non-ideal signals from affecting the accuracy and reliability of the subsequent decoding unit. When the input signal IN is high, NM0 is turned on, the Schmitt trigger outputs a high level, and the output is fed back to the gate of NM2 to turn on. Subsequently, NM1 is turned on, forming positive feedback and accelerating the level transition of OUT and OUT_.

6. A high-reliability Hall decoder circuit for a three-phase gate driver according to claim 5, characterized in that, The decoding unit performs the following tasks: The original Hall signal is processed using a logic gate array to generate and phase-allocate six drive signals according to a specified correspondence. The square wave modulation adopts the H-PWM_L-ON control method, that is, the upper bridge arm uses PWM modulation, and the lower bridge arm is always on during conduction. A combinational logic circuit is designed in the Hall calculation circuit so that the high side of the Hall logic section outputs PWM and the low side is a DC signal. Compared with the simultaneous PWM modulation of both arms, this design reduces the switching loss by half. The shutdown protection port SHUT controls the high side output through AND gate AND4 to deal with abnormal situations that occur during motor operation.

7. A high-reliability Hall decoder circuit for a three-phase gate driver according to claim 6, characterized in that, When all high-side outputs are turned off, the low-side is turned on for a certain period of time according to the input, so that the current of the motor inductor is discharged to zero as soon as possible through the lower bridge arm when the upper bridge arm is disconnected, reducing the influence of torque pulsation and dealing with abnormal situations that occur during motor startup and commutation, thereby effectively protecting the motor and drive circuit from damage.

8. A high-reliability Hall decoder circuit for a three-phase gate driver according to claim 6, characterized in that, This circuit can be integrated into a three-phase gate driver, effectively reducing the chip area.

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