Audio power amplifier and control method thereof

Abstract

The invention discloses an audio power amplifier and a control method thereof. The audio power amplifier comprises a filter circuit, a slope generation circuit and a modulation circuit, and the filter circuit receives a first input signal and a second input signal and filters the first input signal and the second input signal to generate a first filtered signal and a second filtered signal. The ramp generation circuit generates a ramp signal. The modulation circuit receives the first filtering signal, the second filtering signal and the ramp signal and generates a first modulation signal and a second modulation signal according to the first filtering signal, the second filtering signal and the ramp signal, and in the starting stage, the duty ratio of the first modulation signal is increased from a preset value. According to the audio power amplifier disclosed by the invention, the modulation signal is slowly increased from a low duty ratio in a starting stage, and the current is prevented from exceeding an overcurrent protection threshold due to overlarge current, so that the working reliability of the audio power amplifier is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of amplification circuit, in particular to an audio power amplifier and a control method thereof. BACKGROUND

[0002] The audio power amplifier is widely used in the vehicle-mounted audio system due to its high efficiency, small size and low heat loss. Unlike the traditional linear power amplifier, the class-D audio power amplifier modulates the audio signal through a high-frequency switching device to generate a pulse width modulation waveform, and then restores the analog audio signal through a low-pass filter circuit to drive the loudspeaker to produce sound.

[0003] In the vehicle-mounted environment, in order to meet the demand of large power output, the driving power supply voltage of the audio power amplifier is often designed as a higher voltage level such as 24V or 48V. However, during the system startup process, the higher driving power supply voltage will cause a larger current change rate across the inductor, so that the inductor current rises rapidly in a short time, and then easily triggers the overcurrent protection mechanism of the chip, causing the class-D power amplifier chip to fail to start normally, thereby affecting the normal operation of the audio system. SUMMARY

[0004] In view of the above defects of the prior art, the technical problem to be solved by the present application is how to avoid the current of the audio power amplifier being greater than the overcurrent protection threshold during the startup phase to improve the working reliability of the audio power amplifier.

[0005] In order to solve at least one of the above technical problems, the present application discloses an audio power amplifier and a control method thereof.

[0006] According to an aspect of the present application, an audio power amplifier is provided, comprising: a filter circuit receiving a first input signal and a second input signal, filtering the first input signal and the second input signal to generate a first filtered signal and a second filtered signal, wherein the first input signal and the second input signal are complementary, and the first filtered signal and the second filtered signal are complementary; a slope generation circuit generating a slope signal; and a modulation circuit receiving the first filtered signal, the second filtered signal and the slope signal, generating a first modulation signal and a second modulation signal according to the first filtered signal, the second filtered signal and the slope signal, wherein during the startup phase, the duty cycle of the first modulation signal starts to increase from a preset value.

[0007] According to an aspect of the present application, a control method of an audio power amplifier is provided, the method comprising: generating a first filtered signal and a second filtered signal according to a first input signal and a second input signal; generating a ramp signal; and generating a first modulation signal and a second modulation signal according to the first filtered signal, the second filtered signal and the ramp signal, wherein in a starting stage, a duty cycle of the first modulation signal and the second modulation signal is continuously increased from a preset value.

[0008] In the embodiments of the present application, the ramp generation circuit generates ramp signals with different common-mode values according to different control signals, or controls the common mode of the first filtered signal and the second filtered signal according to a common-mode control signal, so as to adjust the duty cycle of the modulation signal. The audio power amplifier in the present application adjusts the duty cycle of the first modulation signal and the second modulation signal by the above technical means, so that the current flowing through the inductor in the starting stage is less than the over-current protection threshold, which can avoid the influence of the over-current protection mechanism on the working performance of the audio power amplifier, thereby improving the working reliability of the audio power amplifier.

[0009] Other features and advantages of the present application will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0011] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0012] Figure 1 The circuit diagram of the audio power amplifier according to an embodiment of the present application is shown; Figure 2 The circuit structure schematic diagram of the ramp generation circuit 20 according to an embodiment of the present application is shown; Figure 3 The circuit structure schematic diagram of the ramp generation circuit according to an embodiment of the present application is shown; Figure 2 The circuit structure schematic diagram of the ramp generation circuit according to an embodiment of the present application is shown; Figure 4 The circuit structure schematic diagram of the ramp generation circuit according to an embodiment of the present application is shown; Figure 3 The schematic diagram of the duty cycle of the first modulation signal VOUT1 when the instruction value of the control signal CTRL is different in the example shown; Figure 5 The schematic diagram of the duty cycle of the first modulation signal VOUT1 when the instruction value of the control signal CTRL is different in the example shown; Figure 3 The waveform schematic diagram of each signal in the ramp generation circuit shown; Figure 6 A structural diagram of a filter circuit 10 according to an embodiment of the present application is shown; Figure 7 A structural diagram of a filter circuit 10 according to an embodiment of the present application is shown; Figure 8 A structural diagram of a filter circuit 10 according to an embodiment of the present application is shown; Figure 7 A waveform diagram of each signal in the filter circuit is shown; Figure 9 A structural diagram of a modulation circuit 30 according to an embodiment of the present application is shown; Figure 10 A control method 1000 of an audio power amplifier according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described in the specification of the present application combined with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0014] It should be noted that the terms "first", "second", and the like in the specification of the present application, the claims, and the above-described accompanying drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so as to implement those other than the order illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or server including a series of steps or circuits does not necessarily limit to those steps or circuits clearly listed, but can include other steps or circuits not clearly listed or inherent to these processes, methods, products, or devices.

[0015] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the drawings represent functionally the same or similar elements. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0016] The word "exemplary" is used herein in the sense of being an example, illustration, or demonstration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0017] The term "and / or", used in the present document, is used to describe the association relationship between associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" in the present document means any one of a plurality of combinations or any combination of at least two of a plurality of combinations, for example, including at least one of A, B and C can mean including any one or more elements selected from the set consisting of A, B and C.

[0018] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the specific embodiments below. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some examples, methods, means, elements and circuits that are well known to those skilled in the art are not described in detail, in order to highlight the main ideas of the present disclosure.

[0019] Figure 1 The circuit diagram of the audio power amplifier according to an embodiment of the present application is given. The audio power amplifier includes a filter circuit 10, a slope generation circuit 20 and a modulation circuit 30. The filter circuit 10 has a first input end receiving a first input signal VIN1, a second input end receiving a second input signal VIN2, a first output end providing a first filter signal VS1, and a second output end providing a second filter signal VS2. The filter circuit 10 generates the first filter signal VS1 and the second filter signal VS2 according to the first input signal VIN1 and the second input signal VIN2, wherein the first input signal VIN1 and the second input signal VIN2 are complementary, and the first filter signal VS1 and the second filter signal VS2 are complementary.

[0020] The slope generation circuit 20 has a control end receiving a control signal CTRL and an output end outputting a slope signal VR. The slope generation circuit 20 generates the slope signal VR according to the control signal CTRL, wherein the command value of the control signal CTRL controls the common mode value of the slope signal VR.

[0021] The modulation circuit 30 has a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal, wherein the first input terminal receives the first filtered signal VS1, the second input terminal receives the second filtered signal VS2, the third input terminal receives the ramp signal VR, the first output terminal outputs the first modulation signal VOUT1, and the second output terminal outputs the second modulation signal VOUT2. The modulation circuit 30 generates the first modulation signal VOUT1 and the second modulation signal VOUT2 according to the first filtered signal VS1, the second filtered signal VS2 and the ramp signal VR. In a start-up phase, the duty cycle of the first modulation signal VOUT1 starts to increase from a preset value DSET. In an embodiment, the preset value DSET is 5%. In another embodiment, the preset value DSET is 20%. In an embodiment, the audio power amplifier has an enable pin to receive an enable signal EN, and enters the start-up phase when the enable signal EN jumps from a first state to a second state. In another embodiment, the audio power amplifier has an enable pin to receive an enable signal EN, and enters the start-up phase when the enable signal EN jumps from a logic low to a logic high. In an embodiment, the start-up phase is a preset time length. In an embodiment, after the start-up phase, the duty cycle of the first modulation signal VOUT1 is 50%. In an embodiment, the duty cycle of the first modulation signal VOUT1 is adjusted by adjusting the common-mode value of the ramp signal VR. In another embodiment, the duty cycle of the first modulation signal VOUT1 is adjusted by adjusting the common-mode value of the first filtered signal VS1 and the second filtered signal VS2. In an embodiment, the common-mode value of the ramp signal VR is (VH+VL) / 2.

[0022] In the start-up phase, the current flowing through the inductor is large due to the large driving power supply voltage VBAT, which triggers the over-current protection mechanism in the chip and causes the start-up to fail. Therefore, in the present embodiment, the ramp signal VR has different common-mode values by different instruction values of the control signal CTRL. In the start-up phase, the common-mode value of the ramp signal VR is gradually reduced, or the common-mode value of the first filtered signal VS1 and the second filtered signal VS2 is gradually increased, so that the duty cycle of the output first modulation signal VOUT1 and the second modulation signal VOUT2 is gradually increased, so that the inductor current in the start-up phase of the audio power amplifier is less than the over-current protection threshold, and the over-current protection mechanism is not triggered; in the start-up completion phase, the BD mode (Bridged-Drive Pulse Width Modulation, bridge double pulse width modulation mode) ensures the normal working performance of the audio power amplifier.

[0023] Figure 2 The circuit structure schematic diagram of the ramp generation circuit 20 according to an embodiment of the present application is given. As shown in FIG. 2, the ramp generation circuit 20 has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal and a second output terminal, wherein the first input terminal receives a first clock signal CLK1, the second input terminal receives a second clock signal CLK2, the third input terminal receives a third clock signal CLK3, the fourth input terminal receives a fourth clock signal CLK4, the first output terminal outputs a first ramp signal VR1, and the second output terminal outputs a second ramp signal VR2. Figure 2As shown, the ramp generation circuit 20 includes a voltage divider circuit 201, a current mirror circuit 202, a reference signal conditioning circuit 203, a reference signal conditioning circuit 204, and a signal generation circuit 205. The voltage divider circuit 201 receives a first supply voltage PVDD and outputs a first current signal I1 based on the first supply voltage PVDD. The current mirror circuit 202 receives a second supply voltage AVDD and the first current signal I1, and outputs a second current signal I2 and a third current signal I3 based on the second supply voltage AVDD and the first current signal I1. The reference signal conditioning circuit 203 receives a control signal CTRL and generates a reference voltage signal VREF based on the control signal CTRL. The reference signal conditioning circuit 204 receives the reference voltage signal VREF and generates a first reference signal VH and a second reference signal VL based on the reference voltage signal VREF. The signal generation circuit 205 receives the first reference signal VH and the second reference signal VL, and generates a ramp signal VR based on the first reference signal VL and the second reference signal VL. The peak value of the ramp signal VR is the value of the first reference signal VH, and the valley value of the ramp signal VR is the value of the second reference signal VL.

[0024] Figure 3 Given Figure 2 The detailed circuit diagram of the ramp generation circuit 20 shown is as follows. Figure 3 As shown, the voltage divider circuit 201 includes a third operational amplifier AMP3, a third transistor M3, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The seventh resistor R7 and the eighth resistor R8 are connected in series between the first supply voltage PVDD and the reference ground. The third operational amplifier AMP3 has a first operational terminal, a second operational terminal, and a third operational output terminal. The first operational terminal is coupled between the seventh resistor R7 and the eighth resistor R8, and the second operational terminal is coupled to the drain of the third transistor M3. The gate terminal of the third transistor M3 is coupled to the third output terminal of the third operational amplifier AMP3, and the source terminal of the third transistor M3 provides the first current signal I1. The ninth resistor R9 is coupled to the reference ground GND and the drain of the third transistor M3. The working principle of the voltage divider circuit 201 is as follows: the seventh resistor R7 and the eighth resistor R8 divide the first supply voltage PVDD to generate a first voltage divider signal V1. The third operational amplifier AMP3 receives the first voltage divider signal V1 and determines the first current signal I1 based on the ninth resistor R9. The voltage value of the first voltage divider signal V1 can be calculated using the following formula: Where PVDD is the voltage value of the first supply voltage PVDD, R7 is the resistance value of the seventh resistor R7, and R8 is the resistance value of the eighth resistor R8. Therefore, the current value of the first current signal I1 is the ratio of the voltage value of the first voltage divider signal V1 to the resistance value of the ninth resistor R9. It should be noted that... Figure 3The voltage dividing circuit shown is only an example, any voltage dividing circuit that can generate the first current signal I1 according to the first supply voltage PVDD is included in the present application.

[0025] In some embodiments, the current mirror circuit 202 has a first input end receiving the second supply voltage AVDD, a second input end receiving the first current signal I1, a first output end providing the second current signal I2 for the reference signal adjusting circuit 203, and a second output end providing the third current signal I3 for the reference signal adjusting circuit 204. Figure 3 In some embodiments, the duty cycle of the first modulation signal VOUT1 and the second modulation signal VOUT2 is related to the common mode value of the ramp signal VR, and the duty cycle of the first modulation signal VOUT1 and the second modulation signal VOUT2 decreases as the common mode value of the ramp signal VR increases. In the start-up stage, the instruction value of the control signal CTRL controls the common mode value of the ramp signal VR to continuously decrease, and thus the duty cycle of the first modulation signal VOUT1 and the second modulation signal VOUT2 continuously increases.

[0026] As shown in Figure 3 The current mirror circuit 202 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The source end of the fourth transistor M4 receives the second supply voltage AVDD, the drain end of the fourth transistor M4 is coupled to the source end of the third transistor M3, and the gate end of the fourth transistor M4 receives the first current signal I1. The source end of the fifth transistor M5 receives the second supply voltage AVDD, the gate end of the fifth transistor M5 is coupled to the gate end of the fourth transistor M4, and the drain end of the fifth transistor M5 provides the second current signal I2. The source end of the sixth transistor M6 receives the second supply voltage AVDD, the gate end of the sixth transistor M6 is coupled to the gate end of the fourth transistor M4, and the drain end of the sixth transistor M6 provides the third current signal I3. The current values of the second current signal I2 and the third current signal I3 are calculated as follows: ; wherein R9 is the resistance value of the ninth resistor R9, K2 is the mirroring ratio of the current value of the second current signal I2 and the current value of the first current signal I1, and K3 is the mirroring ratio of the current value of the third current signal I3 and the current value of the first current signal I1. It should be noted that Figure 3 The current mirror circuit shown is only an example, any current mirror circuit that can generate the second current signal I2 and the third current signal I3 according to the second supply voltage AVDD and the first current signal I1 is included in the present application.

[0027] The reference signal adjusting circuit 203 receives the control signal CTRL and generates a reference voltage signal VREF according to the control signal CTRL. In Figure 3 ​The reference signal conditioning circuit 203 includes a variable resistor RS, a first operational amplifier AMP1, a first transistor M1, a first resistor R1, and a second resistor R2. The variable resistor RS has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal receives a second current signal I2, the third terminal provides a reference voltage signal VREF, and the control terminal receives a control signal CTRL. The first operational amplifier AMP1 has a first input terminal, a second input terminal, and a first output terminal. The second input terminal is coupled to the second terminal of the variable resistor RS. The source terminal of the first transistor M1 is coupled to reference ground GND, the gate terminal of the first transistor M1 is coupled to the first output terminal of the first operational amplifier AMP1, and the drain terminal of the first transistor M1 is coupled to the second terminal of the variable resistor RS. The first resistor R1 and the second resistor R2 are connected in series between the second power supply voltage AVDD and reference ground GND. The first resistor R1 and the second resistor R2 have a common terminal, which is coupled to the first input terminal of the first operational amplifier AMP1. Figure 3 In this embodiment, the control terminal of the variable resistor RS can receive the command value of the control signal CTRL to adjust the reference voltage signal VREF output by the reference signal conditioning circuit 203. The first resistor R1 and the second resistor R2 divide the second supply voltage AVDD to generate a second voltage divider signal V2. Wherein, the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2, then the voltage value of the second voltage divider signal V2 is 0.5*AVDD, where AVDD is the voltage value of the second supply voltage AVDD.

[0028] exist Figure 3 In this embodiment, the command value of the control signal CTRL can be output from a digital counter to the control terminal of the variable resistor RS. The voltage value of the reference voltage signal VREF can be calculated according to the following formula: ; Where D is the duty cycle, VR is the peak value of the ramp signal VR, and it is related to the first supply voltage PVDD, for example... .

[0029] In addition, combined Figure 3 It can be seen that VREF can also be calculated using the following formula: ; When the audio power amplifier is in 1SPW mode, the common-mode value of the ramp signal VR VCM = VREF Therefore, based on the above two formulas, it can be concluded that the common-mode value of the ramp signal VR can be adjusted by adjusting the resistance value of the variable resistor RS.

[0030] The reference signal conditioning circuit 204 is configured to receive a reference voltage signal VREF and output a first reference signal VH and a second reference signal VL based on the reference voltage signal VREF.

[0031] As shown in Figure 3 , the reference signal adjusting circuit 204 includes a second operational amplifier AMP2, a second transistor M2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6. The second operational amplifier AMP2 has a first input terminal, a second input terminal and an output terminal, and the first input terminal receives a reference voltage signal VREF. The source terminal of the second transistor M2 is coupled to a reference ground GND, and the gate terminal of the second transistor M2 is coupled to the second output terminal of the second operational amplifier AMP2. The first terminal of the third resistor R3 receives a third current signal I3, and the second terminal of the third resistor R3 provides a first reference signal VH. The first terminal of the fourth resistor R4 is coupled to the second terminal of the third resistor R3, and the second terminal of the fourth resistor R4 is coupled to the second input terminal of the second operational amplifier AMP2. The first terminal of the fifth resistor R5 is coupled to the second terminal of the fourth resistor R4, and the second terminal of the fifth resistor R5 provides a second reference signal VL. The first terminal of the sixth resistor R6 is coupled to the second terminal of the fifth resistor R5, and the second terminal of the sixth resistor R6 is coupled to the drain terminal of the second transistor M2. The first input terminal of the second operational amplifier AMP2 receives the reference voltage signal VREF, the second input terminal is coupled between the third resistor R3 and the fourth resistor R4, and the output terminal is coupled to the second gate terminal of the second transistor M2.

[0032] The voltage value of the first reference signal VH and the voltage value of the second reference signal VL can be calculated using the following formula: ; wherein, R4 is the resistance value of the fourth resistor R4, R5 is the resistance value of the fifth resistor R5, = .

[0033] The signal generating circuit 205 receives the first reference signal VH and the second reference signal VL, and generates a ramp signal VR according to the first reference signal VH and the second reference signal VL. In Figure 3 , the signal generating circuit 205 has a first input terminal to receive the first reference signal VH, a second input terminal to receive the second reference signal VL, and an output terminal to output the ramp signal VR to the modulation circuit 30. The ramp signal VR can be a triangular wave signal, the voltage value of the first reference signal VH corresponds to the maximum voltage value of the ramp signal VR, and the voltage value of the second reference signal VL corresponds to the minimum voltage value of the ramp signal VR.

[0034] Figure 4 The schematic diagrams of the duty cycle of the first modulation signal VOUT1 are given in the example shown in Figure 3 when the instruction value of the control signal CTRL is different. As shown in Figure 4As shown, at time t0, the startup phase begins, with the command value of the control signal CTRL being code0. The duty cycle D of the first modulation signal VOUT1 and the second modulation signal VOUT2 remains at 10%. At time t1, the command value of the control signal CTRL changes from code0 to code1, and the duty cycle D of the first modulation signal VOUT1 and the second modulation signal VOUT2 increases from 10% to 15%. The change in duty cycle D from 10% at time t0 to 15% at time t1 is defined as the duty cycle step VD. Figure 4 In this embodiment, the duty cycle step VD is 5%. It should be noted that in other embodiments, the duty cycle step VD can be 10% or other values. Figure 4 In this context, the time length from time t0 to time t1 is defined as the time step VT. Figure 4 During the period before time t3, i.e., as the duty cycle D increases from 10% to 50%, the audio power amplifier cannot send audio signals. When the duty cycle D is 50%, the audio power amplifier operates in BD mode. This avoids the problem of large inductor current during the startup phase while ensuring the operating performance of the audio power amplifier.

[0035] Figure 5 Given Figure 3 The diagram shows the waveforms of each signal in the ramp generation circuit. Figure 5 In the diagram, when the common-mode value of the ramp signal VR is high (VR@D=10% as shown by the dashed line), the duty cycle D of the first modulation signal VOUT1 is 10%, meaning that the time the first modulation signal VOUT1 is at a high level accounts for 10% of its period. When the common-mode value of the ramp signal VR is low (VR@D=50% as shown by the solid line), the duty cycle D of the first modulation signal VOUT1 is 50%, meaning that the time the first modulation signal VOUT1 is at a high level accounts for 50% of its period. Therefore, a lower duty cycle results in a smaller inductor current during the startup phase, avoiding triggering the overcurrent protection mechanism. Figure 5 As shown, during the startup phase, by gradually reducing the common-mode value of the ramp signal VR, the duty cycle of the first modulation signal VOUT1 is gradually increased, causing the audio power amplifier to enter BD modulation mode to ensure its working performance.

[0036] Figure 6 A schematic diagram of a filter circuit 10 according to an embodiment of this application is provided. Figure 6In the illustrated embodiment, the filter circuit 10 includes a first filter circuit 101 and a second filter circuit 102. The first filter circuit 101 has a first input terminal to receive the first input signal VIN1, a second input terminal to receive the second input signal VIN2, a first output terminal to provide the third filter signal VS3, and a second output terminal to provide the fourth filter signal VS4. The first filter circuit 101 generates the third filter signal VS3 and the fourth filter signal VS4 based on the first input signal VIN1 and the second input signal VIN2. The second filter circuit 102 has a first input terminal to receive the third filter signal VS3, a second input terminal to receive the fourth filter signal VS4, a first output terminal to provide the first filter signal VS1, and a second output terminal to provide the second filter signal VS2. The second filter circuit 102 generates the first filter signal VS1 and the second filter signal VS2 based on the third filter signal VS3 and the fourth filter signal VS4. It is noted that, Figure 6 The illustrated second order filter circuit 10 is merely an example. In another embodiment, the filter circuit 10 can be a first order filter circuit.

[0037] In Figure 6 In the illustrated embodiment, the first filter circuit 101 includes a fourth operational amplifier AMP4, a first filter resistor RIN1, a second filter resistor RIN2, a first capacitor C1, and a second capacitor C2. The fourth operational amplifier AMP4 has a first input terminal to receive the first input signal VIN1 through the first filter resistor RIN1, a second input terminal to receive the second input signal VIN2 through the second filter resistor RIN2, a first output terminal to provide the third filter signal VS3, and a second output terminal to provide the fourth filter signal VS4. Illustratively, the first input terminal of the fourth operational amplifier AMP4 can be a non-inverting input terminal, and the second input terminal can be an inverting input terminal. The first capacitor C1 has a first terminal coupled to the first input terminal of the fourth operational amplifier AMP4, and a second terminal coupled to the first output terminal of the fourth operational amplifier AMP4. The second capacitor C2 has a first terminal coupled to the second input terminal of the fourth operational amplifier AMP4, and a second terminal coupled to the second output terminal of the fourth operational amplifier AMP4.

[0038] In Figure 6In the embodiment shown, the second filter circuit 102 includes a tenth resistor R10, an eleventh resistor R11, a third capacitor C3, a fourth capacitor C4, a fifth operational amplifier AMP5, a fifth capacitor C5, and a sixth capacitor C6. The tenth resistor R10 has a first end receiving the third filter signal VS3 and a second end providing a fifth filter signal VS5. The third capacitor C3 has a first end coupled to the first end of the tenth resistor R10 and a second end coupled to the second end of the tenth resistor R10. The eleventh resistor R11 has a first end receiving a fourth filter signal VS4 and a second end providing a sixth filter signal VS6. The fourth capacitor C4 has a first end coupled to the first end of the eleventh resistor R11 and a second end coupled to the second end of the eleventh resistor R11. The fifth operational amplifier AMP5 has a first input receiving the fifth filter signal VS5, a second input receiving the sixth filter signal VS6, a first output providing the first filter signal VS1, and a second output providing the second filter signal VS2. Exemplarily, the first input of the fifth operational amplifier AMP5 can be an inverting input, and the second input can be a non-inverting input. The fifth capacitor C5 has a first end coupled to the second input of the fifth operational amplifier AMP5 and a second end coupled to the first output of the fifth operational amplifier AMP5. The sixth capacitor C6 has a first end coupled to the first input of the fifth operational amplifier AMP5 and a second end coupled to the second output of the fifth operational amplifier AMP5.

[0039] In Figure 6 the embodiment shown, the filter circuit 10 is a second-order loop filter for stabilizing the amplification circuit and eliminating noise by controlling the frequency response of the loop. The first filter circuit 101 is a first stage fully differential op-amp of the second-order loop filter, and the second filter circuit 102 is a second stage fully differential op-amp of the second-order loop filter. The filter loop of the first input resistor RIN1, the first capacitor C1, the tenth resistor R10, and the fifth capacitor C5 determines the circuit pole of the second-order loop filter (the same applies to the second filter resistor RIN2, the second capacitor C2, the eleventh resistor R11, and the sixth capacitor C6).

[0040] Figure 7 A structural schematic diagram of the filter circuit 10 according to an embodiment of the present application is shown. And Figure 6 The embodiment shown is different from the embodiment shown in Figure 7 , in that the filter circuit 10 further includes a common-mode feedback circuit 103. The common-mode feedback circuit 103 receives the first filter signal VS1, the second filter signal VS2, and a common-mode control signal VCT. In the start-up stage, the common-mode control signal VCT controls the common-mode values of the first filter signal VS1 and the second filter signal VS2 to continuously increase, so that the duty cycles of the first modulation signal VOUT1 and the second modulation signal VOUT2 continuously increase. It should be noted that Figure 7The second-order filter circuit shown is only an example, and in another embodiment, a first-order filter circuit with a common-mode feedback circuit 103 is also included in the present application.

[0041] Figure 8 The waveforms of the signals in the filter circuit are shown. In the Figure 7 The waveforms of the signals in the filter circuit are shown. In the Figure 8 In the embodiment, the common-mode value of the ramp signal VR is a fixed value, and in the starting stage, the duty cycle of the first modulation signal VOUT1 is changed by adjusting the common-mode value of the first filter signal VS1. In the Figure 8 In the embodiment, when the common-mode value of the first filter signal VS1 is low (VCM_VS1@D=10% shown by the dashed line in the figure), the duty cycle D of the first modulation signal VOUT1 is 10%, i.e., the time during which the first modulation signal VOUT1 is at a high level accounts for 10% of the period of the first modulation signal VOUT1. When the common-mode value of the first filter signal VS1 is high (VCM_VS1@D=50% shown by the solid line in the figure), the duty cycle D of the first modulation signal VOUT1 is 50%, i.e., the time during which the first modulation signal VOUT1 is at a high level accounts for 50% of the period of the first modulation signal VOUT1. That is, by adjusting the common-mode value of the first filter signal VS1, the common-mode value of the second filter signal VS2 can adjust the duty cycles of the first modulation signal VOUT1 and the second modulation signal VOUT2, thereby controlling the current flowing through the inductor in the starting stage.

[0042] Figure 9 A structural schematic diagram of a modulation circuit 30 provided according to an embodiment of the present application is shown. As shown in the Figure 9 The modulation circuit 30 includes a comparison circuit 301 and a drive circuit 302. The comparison circuit 301 has a first input end receiving a first filter signal VS1, a second input end receiving a second filter signal VS2, a first output end providing a first drive signal PWMP, and a second output end providing a second drive signal PWMN. The comparison circuit 301 generates the first drive signal PWMP and the second drive signal PWMN according to the first filter signal VS1 and the second filter signal VS2.

[0043] The drive circuit 302 has a first input end receiving the first drive signal PWMP, a second input end receiving the second drive signal PWMN, a first output end providing a first modulation signal VOUT1, and a second output end providing a second modulation signal VOUT2. The drive circuit 302 generates the first modulation signal VOUT1 and the second modulation signal VOUT2 according to the first drive signal PWMP and the second drive signal PWMN.

[0044] In the Figure 9In the illustrated embodiment, the comparison circuit 301 includes a first comparator COM1 and a second comparator COM2. The first comparator COM1 has a first input terminal receiving the first filtered signal VS1, a second input terminal receiving the ramp signal VR, and an output terminal providing a first drive signal PWMp. The first comparator COM1 generates the first drive signal PWMp according to the first filtered signal VS1 and the ramp signal VR. In an example, the first input terminal of the first comparator COM1 is a positive input terminal, and the second input terminal is a negative input terminal. The second comparator COM2 has a first input terminal receiving the second filtered signal VS2, a second input terminal receiving the ramp signal VR, and an output terminal providing a second drive signal PWMn. The second comparator COM2 generates the second drive signal PWMn according to the second filtered signal VS2 and the ramp signal VR. In an example, the first input terminal of the second comparator COM2 is a positive input terminal, and the second input terminal is a negative input terminal.

[0045] Continuing Figure 9 As described above, the drive circuit 302 includes a logic control circuit, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The seventh transistor M7 to the tenth transistor M10 are all N-type field effect transistors. The drain terminal of the seventh transistor M7 is coupled to a drive supply voltage VBAT, the source terminal of the seventh transistor M7 is coupled to the drain terminal of the eighth transistor M8, the source terminal of the eighth transistor M8 is coupled to a reference ground GND, and the gate terminals of the seventh transistor M7 and the eighth transistor M8 are both coupled to the logic control circuit. In an embodiment, the value of the drive supply voltage VBAT is 24V, and in another embodiment, the value of the drive supply voltage VBAT is 48V. The drain terminal of the ninth transistor M9 is coupled to the drive supply voltage VBAT, the source terminal of the ninth transistor M9 is coupled to the drain terminal of the tenth transistor M10, the source terminal of the tenth transistor M10 is coupled to the reference ground GND, and the gate terminals of the ninth transistor M9 and the tenth transistor M10 are both coupled to the logic control circuit. The seventh transistor M7 to the tenth transistor M10 form a full-bridge circuit. The logic control circuit generates the first modulation signal VOUT1 and the second modulation signal VOUT2 based on the first drive signal PWMp and the second drive signal PWMn, and outputs the first modulation signal VOUT1 and the second modulation signal VOUT2 to a load, which is usually a loudspeaker.

[0046] Figure 10 A control method 1000 of an audio power amplifier according to an embodiment of the present application is provided. The method 1000 includes: Step S101: generating a first filtered signal VS1 and a second filtered signal VS2 according to a first input signal VIN1 and a second input signal VIN2.

[0047] Step S102: generating a ramp signal VR.

[0048] Step S103: generating the first modulation signal VOUT1 and the second modulation signal VOUT2 according to the first filtered signal VS1, the second filtered signal VS2 and the ramp signal VR, wherein the duty cycle of the first modulation signal VOUT1 and the second modulation signal VOUT2 is continuously increased from a preset value in the starting stage. More specifically, in an embodiment, the common-mode value of the ramp signal VR is controlled according to the control signal CTRL to be continuously decreased in the starting stage, thereby controlling the duty cycle of the first modulation signal VOUT1 and the second modulation signal VOUT2 to be continuously increased from a preset value. In another embodiment, the common-mode value of the first filtered signal VS1 and the common-mode value of the second filtered signal VS2 are controlled to be continuously increased in the starting stage, thereby controlling the duty cycle of the first modulation signal VOUT1 and the second modulation signal VOUT2 to be continuously increased from a preset value. In another embodiment, the common-mode value of the first filtered signal VS1 and the common-mode value of the second filtered signal VS2 are controlled according to the common-mode control signal VCT to be continuously increased in the starting stage, thereby controlling the duty cycle of the first modulation signal VOUT1 and the second modulation signal VOUT2 to be continuously increased from a preset value.

[0049] In the description of the present application, the terms "first", "second" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0050] In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0051] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0052] The above is the preferred embodiment of the present application, and is not intended to limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application, without departing from the technical solution content of the present application, still falls within the scope of the technical solution of the present application. The selection of the terms used in this paper is intended to best explain the principles, practical application or market improvement of each embodiment, or to enable other ordinary skilled persons in the art to understand each embodiment disclosed in this paper.

Claims

1. An audio power amplifier, comprising: The filtering circuit receives a first input signal and a second input signal, and filters the first input signal and the second input signal to generate a first filtered signal and a second filtered signal, wherein the first input signal and the second input signal are complementary, and the first filtered signal and the second filtered signal are complementary. A ramp generation circuit generates a ramp signal. as well as The modulation circuit receives a first filtered signal, a second filtered signal, and a ramp signal, and generates a first modulation signal and a second modulation signal based on the first filtered signal, the second filtered signal, and the ramp signal. During the startup phase, the duty cycle of the first modulation signal increases from a preset value.

2. The audio power amplifier according to claim 1, wherein the duty cycle of the first modulation signal is set to 50% when the common mode value of the first filtered signal and the second filtered signal is equal to the common mode value of the ramp signal.

3. The audio power amplifier according to claim 1, wherein the preset value is less than 20%.

4. In the audio power amplifier according to claim 1, the ramp generation circuit receives a control signal and generates a ramp signal according to the control signal. During the startup phase, the common-mode value of the ramp signal continuously decreases.

5. The audio power amplifier of claim 4, wherein the ramp generation circuit comprises: The voltage divider circuit receives the first supply voltage and generates a first current signal based on the first supply voltage. The current mirror circuit receives a second supply voltage and a first current signal, and outputs a second current signal and a third current signal based on the second supply voltage and the first current signal. The reference signal conditioning circuit receives the control signal and generates a reference voltage signal based on the control signal. The reference signal conditioning circuit receives a reference voltage signal and generates a first reference signal and a second reference signal based on the reference voltage signal. as well as The signal generating circuit receives a first reference signal and a second reference signal, and generates a ramp signal based on the first reference signal and the second reference signal. The peak value of the ramp signal is the value of the first reference signal, and the valley value of the ramp signal is the value of the second reference signal.

6. The audio power amplifier according to claim 1, wherein the filtering circuit further includes a common-mode feedback circuit, wherein during the startup phase, the common-mode value of the first filtered signal and the second filtered signal continuously increases.

7. The audio power amplifier according to claim 6, wherein the common-mode feedback circuit receives a common-mode control signal and controls the common-mode values ​​of the first filtered signal and the second filtered signal according to the common-mode control signal.

8. A method for controlling an audio power amplifier, the method comprising: A first filtered signal and a second filtered signal are generated based on the first input signal and the second input signal; Generate a ramp signal; as well as Based on the first filtered signal, the second filtered signal, and the ramp signal, a first modulated signal and a second modulated signal are generated, wherein during the startup phase, the duty cycle of the first modulated signal and the second modulated signal continuously increases from a preset value.

9. The control method according to claim 8, wherein during the startup phase, the common-mode value of the ramp signal is continuously reduced according to the control signal.

10. The control method according to claim 8, wherein during the startup phase, the common-mode value of the first filter signal is controlled according to the common-mode control signal, and the common-mode value of the second filter signal is continuously increased.

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