Routing device on a CXL protocol exchange chip and transmission method thereof

Abstract

The application belongs to the field of exchange chips and relates to a routing device on a CXL protocol exchange chip and a transmission method thereof. The device comprises multiple routing nodes, each of which is connected with other routing nodes or device nodes and transmits messages through signaling handshake mechanism. The routing node topology is formed by interconnection of the multiple routing nodes. The routing passage is composed of a request channel, a response channel, a data channel and a monitoring channel. Each group of channels is a bidirectional channel and simultaneously supports CXL.mem protocol and CXL.cache protocol. Protocol messages are transmitted on the routing passage after being converted into a specified format at the device node, and each channel corresponds to a signaling transmission channel. The double-channel design ensures that the messages do not affect each other and improves efficiency. When the device node only supports a certain protocol or the traffic of a certain protocol is reduced, the single-channel design reduces power consumption and saves area.

Description

Technical Field

[0001] This invention relates to a routing device and transmission method on a CXL protocol switching chip, belonging to the field of switching chip technology. Background Technology

[0002] The Compute Express Link (CXL) interface is a widely used interface. There are three types of CXL interfaces: CXL.io, CXL.mem, and CXL.cache. The CXL.io interface is compatible with the PCIe interface. Two devices with the same CXL interface can be interconnected via the CXL interface.

[0003] The CXL interface switching chip can expand the number of devices that can be connected to the host. For example... Figure 1 As shown, a host can connect to multiple CXL devices through a single CXL switching port unit of a switching chip, thus expanding the CXL port count. Existing CXL switching chips only support the CXL 2.0 protocol, and their message processing and transmission still follow the PCIe tree structure, which has significant limitations. Furthermore, the interconnection of existing CXL switching chips is primarily based on switching matrices, which cannot cope with an increase in the number of ports.

[0004] When a switching network uses a Torus network (currently, there is no Torus network for CXL protocol transmission), the existing Torus network is only designed for a specific protocol and has a fixed number of channels. If multiple protocols share the same network, it will cause congestion and affect transmission efficiency. The switching network of the CXL switching chip needs to transmit both CXL.mem and CXL.cache protocol messages, which requires a new routing device and method to achieve efficient CXL protocol transmission.

[0005] Existing routing devices for switching chips mainly employ point-to-point routing in cross-connect matrices, where the source and destination nodes are unique. For example, the "DPU switch" disclosed in publication number CN223463083U uses point-to-point interconnection of switch nodes for routing. This routing method is highly efficient when supporting a small number of nodes, but it becomes physically difficult to implement as the number of nodes increases, making it unsuitable for large-scale switching chip designs.

[0006] In addition, in the design of Torus or Mesh networks, the routing device is mainly designed with a fixed number of ports and fixed routing channels, and it is not possible to flexibly configure the number of ports and routing channels according to actual needs. For example, in the "Reconfigurable On-Chip Network of a Data Stream Accelerator" disclosed in CN120670367A, the number of ports and routing channels are predefined, and the transmission is forwarded according to the pre-set traffic.

[0007] Based on this, the present invention is proposed. Summary of the Invention

[0008] This invention provides a routing device and transmission method for a CXL protocol switching chip, which enables the transmission of the CXL protocol on the switching chip through highly flexible configuration and a non-blocking routing method. The specific technical solution is as follows:

[0009] In a first aspect, a routing device on a CXL protocol switching chip includes:

[0010] Multiple routing nodes, each of which is connected to other routing nodes or device nodes and transmits messages through a signaling handshake mechanism;

[0011] The routing node topology is formed by interconnecting multiple routing nodes.

[0012] The routing path consists of a request channel, a response channel, a data channel, and a listening channel. Each channel is bidirectional and supports both the CXL.mem and CXL.cache protocols. Protocol messages are transmitted on the routing path after being converted into a unified specified format at the device node, and each channel has a corresponding signaling transmission channel.

[0013] The unified specified format mentioned here is a Flit structure that includes a protocol type identifier, source node ID, destination node ID, transaction type, data payload, and verification field. The protocol adaptation module in the device node parses the original CXL.cache or CXL.mem message and re-encapsulates it according to this unified format to generate Flit.

[0014] The signaling handshake mechanism adopts credit-based flow control. Each channel has an independent credit counter. The receiver provides signaling to the sender in advance. The sender consumes one signaling for each Flit sent. The receiver returns a credit token for each Flit successfully received. The sender can only send Flit when the credit counter is greater than zero.

[0015] The routing node includes multiple port input buffers and output selectors. Each input port is configured with 4 sets of input buffers, and the number of input buffers is configured according to the transmission traffic. The routing node uses the XY routing algorithm to ensure the order preservation of Flit transmission between the same source node and destination node, and uses the LRU algorithm to arbitrate the transmission of different source nodes on the shared path.

[0016] The output selector corresponds to the output ports of the routing node in different directions and the output ports of the device node connected to the routing node, and is used to arbitrate and select the output of the Flit to be sent in multiple input buffers.

[0017] A further improvement is that the routing node topology is a Mesh topology or a Torus ring topology.

[0018] In a further improvement, the request path, data path, and response path of the routing node are increased to two groups through customization, corresponding to the replication output selector and arbitration logic; all messages sent from the device node are sent to the device node after passing through the input pipeline, and are matched and searched according to the ID information of the destination node through a lookup table, and then distributed to the two groups of channels for transmission (the distribution strategy here includes, but is not limited to, the parity of the destination node coordinates, the load balancing factor, or the quality of service level, etc.). After reaching the destination node, the messages are sent to the device node through a two-to-one selector.

[0019] Further improvements include a destination ID lookup table, an output path selector, and a packet parsing module within the routing node.

[0020] The message parsing module is used to decode and parse CXL.cache messages and CXL.mem messages, extract valid fields for table lookup indexing, obtain the destination node ID (destination ID[n]) based on the address field and valid bits, and obtain the coordinates (X[n], Y[n]) of the destination ID[n].

[0021] The output path selector is used to select the transmission channel and output port based on the coordinates of the destination ID[n].

[0022] A further improvement is that the connection channel between the device node and the routing node selects the transmission channel according to one of the following strategies:

[0023] 1) Each channel has an independent interface, and the channel correspondence remains unchanged between routing nodes;

[0024] 2) Designate one channel as the default primary channel and another channel as a backup channel. The backup channel will be activated when the primary channel is congested.

[0025] 3) Based on the ID information of the destination node, determine and select the corresponding channel for transmission;

[0026] 4) The transmission channel to be used is determined by the LRG algorithm.

[0027] In a further improvement, the output selector performs arbitration at the output port of the routing node, and the arbitration rules are as follows:

[0028] When there are Flits to be distributed in the input buffer, the priority of the Flits to be distributed is higher than that of the Flits that have just arrived at the routing node, and the output selector will prioritize the distribution of the Flits to be distributed.

[0029] The destination ID lookup table in the input buffer determines the target output selector of the Flit. Each output selector determines the output order of multiple Flits in the input buffer through the LRG algorithm. The input buffer priority corresponding to the Flit that is allowed to be sent to the output selector's output is reduced to the lowest.

[0030] When the input buffer is empty, the output selector uses fixed-priority arbitration for simultaneously arriving Flits.

[0031] As a further improvement, the routing path channel configuration supports one of the following modes:

[0032] 1) Device nodes support independent CXL.cache and CXL.mem channels. The routing path is configured with two independent channels to transmit CXL.cache and CXL.mem packets respectively.

[0033] 2) Device nodes support independent CXL.cache and CXL.mem channels. A set of channels is set up for the routing path, and the routing node arbitrates the CXL.cache and CXL.mem messages and then shares the same set of channels.

[0034] 3) Device nodes support a set of converged channels, and routing paths are configured with a set of channels to transmit packets;

[0035] 4) The device node supports a set of converged channels. The routing path is set with two sets of channels, and the channel is selected for transmission according to the ID of the destination node.

[0036] Secondly, a transmission method for a routing device on a CXL protocol switching chip includes the following steps:

[0037] The switching port sends a request to the routing node, which stores it in the input buffer. It looks up the outgoing direction in the table based on the destination ID, determines the transmission channel according to the configuration algorithm, and sends it to the output selector. The output selector selects the output Flit according to its arbitration algorithm, and the forwarding transaction is completed.

[0038] The beneficial effects of this invention are:

[0039] 1. This invention proposes a routing device on a CXL protocol switching chip for routing CXL.mem and CXL.cache protocols. Its advantage is that the routing device can flexibly configure the number of channels according to the node design. When the device node supports both CXL.cache and CXL.mem protocols, the dual-channel design ensures that packets do not affect each other, thus improving efficiency. When the device node only supports one protocol or the traffic of a certain protocol is reduced, the single-channel design reduces power consumption and saves area.

[0040] 2. The routing device of the present invention can support routing of switching chips of more nodes. The routing device can perform non-blocking transmission of CXL.cache and CXL.mem protocols. Through the destination ID lookup table and output selector of CXL.cache and CXL.mem, the output port is selected for transmission. The number of channels can be flexibly configured according to the characteristics of the device nodes, thereby achieving a balance between performance and overhead. Attached Figure Description

[0041] Figure 1 It refers to the CXL switching chip structure in the background technology;

[0042] Figure 2 This is a schematic diagram of the routing device architecture on the CXL protocol switching chip;

[0043] Figure 3 This is a schematic diagram of the transmission channel between routing nodes;

[0044] Figure 4 This is a schematic diagram of the routing node microarchitecture;

[0045] Figure 5 This is a schematic diagram of a dual-path channel;

[0046] Figure 6 It is the target ID lookup table structure;

[0047] Figure 7 This is a schematic diagram of the routing path;

[0048] Figure 8 This is a flowchart of the routing device on the CXL protocol switching chip. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0050] Definitions of abbreviations and key terms

[0051] CXL: Compute Express Link, a cache-coherent interconnect protocol standard for processors, memory extensions, and accelerators;

[0052] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard;

[0053] .io: CXL input / output subprotocol;

[0054] .mem: CXL memory sub-protocol;

[0055] .cache: CXL caching subprotocol;

[0056] Host: The host computer;

[0057] ID: Identifier;

[0058] Request Channel: The channel through which requests are made.

[0059] Response Channel: The channel through which responses are received.

[0060] Snoop Channel: Listening channel;

[0061] Data Channel: Data channel;

[0062] D2H: Device to Host;

[0063] H2D: Host to Device;

[0064] M2S: Master to Slave;

[0065] S2M: Slave to Master;

[0066] M2S Req: No data requests (mainly read requests);

[0067] M2S RwD: With data requests (mainly write requests);

[0068] S2M NDR: No data response;

[0069] S2M DRS: With data response;

[0070] BIRsp: Back Invalidation Response;

[0071] BISnp: Back Invalidate Snoop, a write-back invalidation listener;

[0072] H2D Req: A request sent by the host to the slave device;

[0073] H2D Resp: The response from the device to H2D Req;

[0074] H2D Data: Data transmitted after H2D Resp;

[0075] D2H Req: A request sent from the device to the host;

[0076] D2H Resp: The host's response to D2H Req;

[0077] D2H Data: Data transmitted after D2H Resp;

[0078] Mesh: A type of "mesh" network structure;

[0079] Torus: A two-dimensional circular ring topology network;

[0080] Flit: Flow-controlled transmission unit;

[0081] Example 1

[0082] The technical problem to be solved by this invention is:

[0083] The CXL switching chip's routing can perform non-blocking, high-performance transmission based on the characteristics of the CXL.cache and CXL.mem protocols, thus avoiding the impact of routing channel congestion on the performance of other packets.

[0084] This invention provides a routing device on a CXL protocol switching chip, which completes the transmission and forwarding of CXL's .cache and .mem sub-protocol messages. Each routing node supports connections in all four directions (north, south, east, and west). Message transmission between routing nodes and between routing nodes and device nodes is conducted through a signaling handshake mechanism. The channels of both the CXL.cache and CXL.mem protocols can be represented as Request Channel, Response Channel, Data Channel, and Snoop Channel. Therefore, the following descriptions will follow these four channels without distinguishing between the H2D and D2H channels of the CXL.cache protocol, or the M2S and S2M channels of the CXL.mem protocol.

[0085] like Figure 2 As shown, a routing device on a CXL protocol switching chip includes:

[0086] 1. Routing Node Topology: Routing node topology plays a crucial role in the switching chip network architecture. The routing node topology involved in this invention possesses high flexibility and customization capabilities. It can be customized based on the specific specifications of the switching chip, including its processing power, number of ports, bandwidth capacity, and physical size, while fully considering practical factors such as space layout and heat dissipation requirements. In actual network construction, each routing node is interconnected, and this connection method can construct various common topologies. Among them, the Mesh topology has significant advantages, exhibiting decentralized and self-organizing characteristics. During data transmission, this topology supports multi-path redundancy, prioritizing the shortest or best-performing path for data transmission. When some nodes in the network fail or become congested, data can still complete communication through multiple hops on alternative paths, greatly improving network reliability and stability. The Torus ring topology, on the other hand, connects the first and last routing nodes of rows and columns on a similar mesh structure. This unique connection method effectively shortens the average network diameter, making the data transmission path in the network more optimized, thereby improving the network's transmission efficiency and response speed to a certain extent. It has important application value in application scenarios where data transmission latency requirements are relatively strict.

[0087] like Figure 2 As shown, this is a 2×4 mesh topology consisting of 8 routing nodes. Each routing node is marked with coordinates based on its location. Each routing node can connect to 1 or 2 device nodes (the diagram shows 1 as an example, where the device node is connected to a switch port). Multiple transmission channels interconnect the routing nodes, as shown in the diagram. Figure 3 As shown, there are request channels, response channels, data channels, and listening channels, and each transmission channel has a corresponding signaling transmission channel.

[0088] Among them, Figure 2 In the diagram, the eight routing nodes are routing node (0,1), routing node (1,1), routing node (2,1), routing node (3,1), routing node (0,0), routing node (1,0), routing node (2,0), and routing node (3,0); (0,1), (1,1), (2,1), (3,1), (0,0), (1,0), (2,0), and (3,0) are the coordinates marked by their locations.

[0089] exist Figure 3 In this context, a request Flit is a flow-controlled transmission unit for requesting a channel; a request signaling is a token for transmission in requesting a channel, and only those with valid signaling can issue the corresponding Flit. Figure 3In the middle, it means that a request signaling has been received, and then a request Flit can be issued; the same applies to others.

[0090] A Flit response is a flow-controlled transmission unit for the response channel; a Flit response is a token transmitted in the response channel, and only those with valid signaling can issue a Flit response.

[0091] A data Flit is a flow-controlled transmission unit for a data channel; data signaling is a token for data channel transmission, and a Flit can only be issued if a valid signaling is available.

[0092] A Flit is a flow-controlled transmission unit for a listening channel; a listening signal is a token for transmissions in the listening channel, and a Flit can only be issued if a valid signal is available.

[0093] 2. Routing Node: A schematic diagram of the internal micro-architecture of a routing node is shown below. Figure 4 As shown, it mainly consists of input buffers and output selectors for multiple ports.

[0094] 2.1 Ports are divided into two categories: device node ports and routing ports. Figure 4 In this configuration, each routing node has one device node and four routing ports, located on the east, south, west, and north sides respectively. Each input port has four sets of input buffers (…). Figure 4 The "East Side Input", "South Side Input", "West Side Input", and "North Side Input" options can be configured with different input buffer sizes to better accommodate varying transmission traffic.

[0095] exist Figure 4 In Flit, after passing through the routing algorithm within the routing node, it sends the data to the output selectors on the east, south, west, and north sides according to the destination node's ID. After arbitration, the data is sent to the output port. For example, if the data is sent to the output selector on the east side and then output from the east output selector, this output is called the "east output"; if it is sent to the output selector on the west side and then output from the west output selector, this output is called the "west output"; if it is sent to the output selector on the south side and then output from the south output selector, this output is called the "south output"; and if it is sent to the output selector on the north side and then output from the north output selector, this output is called the "north output". Figure 4 Port input in this context refers to input from the input buffer on the west side. Figure 4 The port output in the text refers to the output from the output selector on the east side.

[0096] 2.2 The routing node uses the XY routing algorithm internally, so for the same group of source and destination nodes, the transmission of Flits is ordered. However, if transmissions from different source nodes share a path, arbitration is required based on the internal LRU algorithm (Least Recently Used; a cache replacement strategy, often translated as "least recently used" or "unused algorithm"). This approach achieves a good balance between design implementation and performance requirements. However, if a large number of transmissions occur, the link may be occupied for a long time, leading to starvation. In this case, the request path, data path, and response path can be customized to improve transmission efficiency. The request path, data path, and response path can each be increased to two groups, and the output selector and arbitration logic will also be copied. Taking the data path and response path as an example, if... Figure 5 As shown, all packets sent from device nodes (device nodes are connected to the switch port) first pass through the input pipeline, and then a lookup table is searched based on the destination node's ID information. The packets are then assigned to two channels (e.g., "Data 1 / Response 1" and "Data 2 / Response 2") for transmission. According to the transmission direction, the packets are sent to the corresponding channels (e.g., North Data 1 refers to North Data 1, North Data 2 refers to North Data 2, North Response 1 refers to North Response 1, North Response 2 refers to North Response 2, South Data 1 refers to South Data 1, South Data 2 refers to South Data 2, South Response 1 refers to South Response 1, South Response 2 refers to South Response 2, East Data 1 refers to East Data 1, East Data 2 refers to East Data 2, East Response 1 refers to East Response 1, East Response 2 refers to East Response 2, West Data 1 refers to West Data 1, West Data 2 refers to West Data 2, West Response 1 refers to West Response 1, West Response 2 refers to West Response 2). Once it reaches the destination node, it will be sent to the device node through a static two-to-one selector.

[0097] Figure 5 In this context, "Data 1" refers to "Data Channel 1", "Response 1" refers to "Response Channel 1", "Data 2" refers to "Data Channel 2", and "Response 2" refers to "Response Channel 2".

[0098] Destination ID lookup table, output selector, etc. Figure 6As shown, CXL.cache packets and CXL.mem packets are first decoded and parsed in the packet parsing module, extracting valid fields for table look-up indexing, obtaining the ID of the destination node - destination ID[n] based on the address field and valid bit, where n is a positive integer. Then, based on the coordinates (X[n], Y[n]) of the destination ID[n], the output path is selected through the output selector. The selection method is as follows:

[0099] When the destination node ID Y[n] is odd, select data channel 1 for transmission;

[0100] When the destination node ID Y[n] is even, select data channel 2 for transmission.

[0101] Then, based on the comparison result between the destination node ID (X[n], Y[n]) and the current node ID (X0, Y0), the output port is selected. The output ports are divided into four directions: east, south, west, and north. The comparison method is as follows:

[0102] When X[n] > X0, output to the east;

[0103] When X[n] < X0, output to the west;

[0104] When X[n] = X0 and Y[n] > Y0, output to the north;

[0105] When X[n] = X0 and Y[n] < Y0, output to the south.

[0106] 2.3. Furthermore, the channels between the device node and the routing node can also be replicated. At this time, there are multiple choices for the connection between the device node and the routing node:

[0107] ①. Each channel has a separate interface and a unique corresponding channel during transmission. That is, the transmission of channel 0 will also be through channel 0 between routing nodes, and the transmission of channel 1 will also be through channel 1 between routing nodes;

[0108] ②. Channel 0 is always the default main channel. Flits are preferentially transmitted through channel 0, and only when channel 0 is congested will they be transmitted through channel 1;

[0109] ③. Determine through the ID of the destination node and select the corresponding channel for transmission;

[0110] ④. Determine which channel to use for packet transmission through the LRG algorithm.

[0111] 2.4. The output selector needs to perform arbitration judgment at the output port of the routing node.

[0112] When there are already Flits waiting to be dispatched in the input buffer, these Flits have a higher priority than Flits that have just arrived at the routing node. In this case, the output selector dispatches these Flits first.

[0113] The route ID in the input buffer (the route ID is the output of the destination ID lookup table, i.e., the destination ID) determines the target output selector for this Flit. Each output selector uses the LRG algorithm to determine the output order of multiple Flits in the input buffer. Under this algorithm, if a Flit is allowed to be sent to the exit of the output selector, the priority of this input buffer will be reduced to the lowest in the queue.

[0114] When the input buffer is empty, that is, there are no Flits to be distributed internally, the output selector will directly perform the default arbitration selection for Flits that arrive at the same time, and distribute these Flits in sequence.

[0115] In the output selector, there can be a maximum of 6 groups of input buffers bridging the gap, representing the inputs from the four cardinal directions (north, south, east, and west) and the inputs from two device nodes. The default arbitration selection method (i.e., the arbitration algorithm) is as follows:

[0116] Fixed-priority arbitration, selected according to the following arbitration priorities.

[0117] ① East-side output selector priority: West-side port, device node 0, device node 1, North-side port, South-side port, East-side port;

[0118] ② West-side output selector priority: East-side port, device node 1, device node 0, South-side port, North-side port, West-side port;

[0119] ③ Priority of North Output Selector: South Port, East Port, West Port, Device Node 0, Device Node 1, North Port;

[0120] ④ Priority of the south output selector: north port, west port, east port, device node 1, device node 0, south port;

[0121] ⑤ Device Node 0 Output Selector: Device Node 1, East Port, West Port, North Port, South Port, Device Node 0;

[0122] ⑥ Device Node 1 Output Selector: Device Node 0, West Port, East Port, South Port, North Port, Device Node 1.

[0123] 3. Routing Path. A routing path is the main communication line between routing nodes, consisting of request channels, response channels, data channels, and listening channels. Each set of channels is bidirectional. These channels can simultaneously support both the CXL.mem and CXL.cache protocols; protocol messages are converted into a unified format at the device node before being transmitted on the routing path.

[0124] For the CXL.mem protocol, the M2S Req channel corresponds to the request channel of the routing path, the M2S RwD channel corresponds to the data channel of the routing path, the M2S BIRsp corresponds to the response channel of the routing path, the S2M NDR corresponds to the response channel of the routing path, the S2M DRS corresponds to the data channel of the routing path, and the S2M BISnp corresponds to the listening channel of the routing path. Similarly, for the CXL.cache protocol, D2H Req corresponds to the request channel of the routing path, D2H Resp corresponds to the response channel of the routing path, and D2H Data corresponds to the data channel of the routing path; H2D Req corresponds to the request channel of the routing path, H2D Resp corresponds to the response channel of the routing path, and H2D Data corresponds to the data channel of the routing path. Depending on the actual design, routing paths can be configured in four ways, such as... Figure 7 As shown:

[0125] (1) Device nodes (such as switch ports) support two channels, CXL.cache and CXL.mem. Routing paths support two channels (channel 0 and channel 1), which transmit CXL.cache and CXL.mem messages respectively.

[0126] (2) The device node supports two channels, CXL.cache and CXL.mem, and the routing path supports one channel (channel 0). At this time, the routing node will arbitrate between CXL.cache and CXL.mem messages and decide which protocol channel to use.

[0127] (3) The device node supports one set of channels, and the routing path supports one set of channels. At this time, the device node is responsible for merging the channels of CXL.cache and CXL.mem, and only one set of channels (channel 0) is used for transmission on the routing node.

[0128] (4) The device node supports one set of channels, and the routing path supports two sets of channels (channel 0 and channel 1). At this time, the device node is responsible for merging the channels of CXL.cache and CXL.mem, and the routing path increases the bandwidth by expanding the number of channels, and performs transmission according to the description in 2.2.

[0129] Example 2

[0130] The transmission process of the routing device on the CXL protocol switching chip is as follows: Figure 8 As shown.

[0131] The switching port sends requests to the routing node, which stores them in the input buffer.

[0132] The destination ID is used to look up the exit direction in the table. The transmission channel is determined according to the configuration algorithm (referring to the routing method, XY routing algorithm, and selection of channel 0 or channel 1 for output based on ID). The transmission channel is then sent to the output selector. The output selector selects the output Flit according to its arbitration algorithm (fixed priority arbitration), and the forwarding transaction is completed.

[0133] The steps described above are further described in detail below:

[0134] Flit sent by the device node or upstream routing node arrives at the input port of the routing node and is stored in the corresponding input buffer;

[0135] The routing node determines its target output port and the available target transmission channel by looking up and calculating the destination node ID information carried by Flit;

[0136] The output selector corresponding to the target output port selects a Flit output from its multiple associated input buffers according to the arbitration logic (i.e., the arbitration algorithm);

[0137] The selected Flit is sent to the next-hop routing node or destination device node through the determined target output port and target transmission channel.

[0138] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A routing device on a CXL protocol switching chip, characterized in that, include: Multiple routing nodes, each of which is connected to other routing nodes or device nodes and transmits messages through a signaling handshake mechanism; The routing node topology is formed by interconnecting multiple routing nodes. The routing path consists of a request channel, a response channel, a data channel, and a listening channel. Each channel is bidirectional and supports both the CXL.mem and CXL.cache protocols. Protocol messages are transmitted on the routing path after being converted to a specified format at the device node, and each channel has a corresponding signaling transmission channel. The routing node includes multiple port input buffers and output selectors. Each input port is configured with 4 sets of input buffers, and the number of input buffers is configured according to the transmission traffic. The routing node uses the XY routing algorithm to ensure the order preservation of Flit transmission between the same source node and destination node, and uses the LRU algorithm to arbitrate the transmission of different source nodes on the shared path. The output selector corresponds to the output ports of the routing node in different directions and the output ports of the device node connected to the routing node, and is used to arbitrate and select the output of the Flit to be sent in multiple input buffers. The signaling handshake mechanism adopts credit-based flow control. Each channel has an independent credit counter. The receiver provides signaling to the sender in advance. The sender consumes one signaling for each Flit sent. The receiver returns a credit token for each Flit successfully received. The sender can only send Flit when the credit counter is greater than zero. The request path, data path, and response path of the routing node are increased to two groups through customization, corresponding to the replication output selector and arbitration logic; all messages sent from the device node are matched and searched according to the ID information of the destination node through a lookup table and assigned to the two groups of channels for transmission. After arriving at the destination node, they are sent to the device node through a two-to-one selector.

2. The routing device on a CXL protocol switching chip according to claim 1, characterized in that: The routing node topology is either a Mesh topology or a Torus ring topology.

3. The routing device on a CXL protocol switching chip according to claim 1, characterized in that, The routing node also includes a destination ID lookup table, an output path selector, and a packet parsing module. The message parsing module is used to decode and parse CXL.cache messages and CXL.mem messages, extract valid fields for table lookup indexing, obtain the destination node ID (destination ID[n]) based on the address field and valid bits, and obtain the coordinates (X[n], Y[n]) of the destination ID[n]. The output path selector is used to select the transmission channel and output port based on the coordinates of the destination ID[n].

4. The routing device on a CXL protocol switching chip according to claim 1, characterized in that: The connection channel between the device node and the routing node selects the transmission channel according to one of the following strategies: 1) Each channel has an independent interface, and the channel correspondence remains unchanged between routing nodes; 2) Designate one channel as the default primary channel and another channel as a backup channel. The backup channel will be activated when the primary channel is congested. 3) Based on the ID information of the destination node, determine and select the corresponding channel for transmission; 4) The transmission channel to be used is determined by the LRG algorithm.

5. The routing device on a CXL protocol switching chip according to claim 1, characterized in that: The output selector performs arbitration at the output port of the routing node, and the arbitration rules are as follows: When there are Flits to be distributed in the input buffer, the priority of the Flits to be distributed is higher than that of the Flits that have just arrived at the routing node, and the output selector will prioritize the distribution of the Flits to be distributed. The destination ID lookup table in the input buffer determines the target output selector of the Flit. Each output selector determines the output order of multiple Flits in the input buffer through the LRG algorithm. The input buffer priority corresponding to the Flit that is allowed to be sent to the output selector's output is reduced to the lowest. When the input buffer is empty, the output selector uses fixed-priority arbitration for simultaneously arriving Flits.

6. The routing device on a CXL protocol switching chip according to claim 1, characterized in that: The routing path channel configuration supports one of the following modes: 1) Device nodes support independent CXL.cache and CXL.mem channels. The routing path is configured with two independent channels to transmit CXL.cache and CXL.mem packets respectively. 2) Device nodes support independent CXL.cache and CXL.mem channels. A set of channels is set up for the routing path, and the routing node arbitrates the CXL.cache and CXL.mem messages and then shares the same set of channels. 3) Device nodes support a set of converged channels, and routing paths are configured with a set of channels to transmit packets; 4) The device node supports a set of converged channels. The routing path is set with two sets of channels, and the channel is selected for transmission according to the ID of the destination node.

7. A transmission method based on a routing device on a CXL protocol switching chip according to any one of claims 1-6, characterized in that, Includes the following steps: The switching port sends a request to the routing node, which stores it in the input buffer. It looks up the outgoing direction in the table based on the destination ID, determines the transmission channel according to the configuration algorithm, and sends it to the output selector. The output selector selects the output Flit according to its arbitration algorithm, and the forwarding transaction is completed.

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