A switch system

Abstract

This application discloses a switch system, relating to the field of switch technology, including a main logic device, a temperature sensing device, and a power supply voltage regulation device. The switch system achieves autonomous monitoring, judgment, identification, alarm, and control of four major hardware indicators—power supply, clock, timing, and temperature—through hardware configuration and hardware logic. This ensures that the entire switch system responds quickly in abnormal states and records relevant data at abnormal moments, reducing dependence on firmware and ensuring that there are autonomous measures to achieve system hardware self-protection in the event of abnormal software process freezes or even system crashes, thereby improving system stability and reliability.

Description

Technical Field

[0001] This application relates to the field of switch technology, and more particularly to a switch system. Background Technology

[0002] Data center operations rely heavily on switching systems. Currently, the core functions of these systems largely depend on firmware to control the hardware. Software logic vulnerabilities or firmware compatibility issues can cause core functions to malfunction during self-operation, or make the system vulnerable to remote malicious code control, disrupting business logic and impacting operations. Furthermore, when core hardware modules malfunction (e.g., clock failures can lead to system crashes, or a voltage regulator chip (VR) losing output can cause a direct power outage and prevent status reporting), the software can no longer log information, significantly hindering maintenance and troubleshooting, and increasing operational costs. Therefore, reducing reliance on firmware versions and operational status, and improving the overall stability of the switch, has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0003] This application provides a switch system to at least solve the problem of excessive dependence on firmware version and operating conditions in related technologies.

[0004] This application provides a switch system, including:

[0005] The system includes a main logic device, a temperature sensing device, and a power supply voltage regulation device; the main logic device includes a power control module, a temperature control module, a clock control module, and a timing control module.

[0006] The power control module is used to monitor the voltage of the power plane connected to the power voltage regulation device. When the voltage is abnormal, it assigns a value to the first register. If the voltage of the power plane is overvoltage, it shuts down the output of the corresponding power voltage regulation device.

[0007] The temperature control module is used to monitor the temperature collected by the temperature sensing device and assign a value to the second register when the temperature is abnormal.

[0008] The clock control module is used to monitor the quality of the external clock source, switch the input external clock source of the main logic device according to the quality of the external clock source, monitor the quality of each clock output by the main logic device, and when any output clock of the main logic device is abnormal, assign a value to the third register and notify the target device to switch to the target clock source automatically.

[0009] The timing control module is used to control the timing of the power supply voltage regulation device.

[0010] The beneficial effects are as follows: The switch system provided in this application embodiment achieves autonomous monitoring, judgment, identification, alarm, and control of four major hardware indicators—power supply, clock, timing, and temperature—through hardware configuration and hardware logic. This enables the hardware system to control the normal operation of the entire machine with high priority, ensuring that the switch system responds quickly and records relevant data at the time of the abnormality in abnormal states. It also ensures that there are autonomous measures to protect the system hardware in cases of software process freezes or even system crashes, thereby improving system stability and reliability. Simultaneously, the fault recording and reporting function helps engineers recover and confirm the hardware status information at the time of the abnormality when the machine is returned for repair. This facilitates quick and accurate identification of the problem area and faster and more efficient location of hardware issues. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of a switch system provided in an embodiment of this application;

[0013] Figure 2 A schematic diagram of a specific switch system provided in this application embodiment;

[0014] Figure 3 A schematic diagram of a power supply hardware monitoring scheme provided in an embodiment of this application;

[0015] Figure 4 A schematic diagram of a power supply hardware monitoring logic provided in an embodiment of this application;

[0016] Figure 5 A schematic diagram of a temperature hardware monitoring scheme provided in an embodiment of this application;

[0017] Figure 6 A schematic diagram of a temperature hardware monitoring logic provided in an embodiment of this application;

[0018] Figure 7 A schematic diagram of a clock quality hardware monitoring scheme provided in an embodiment of this application;

[0019] Figure 8 A schematic diagram of input clock quality monitoring logic provided in an embodiment of this application;

[0020] Figure 9A schematic diagram of output clock quality monitoring logic provided in an embodiment of this application;

[0021] Figure 10 This is a schematic diagram of a timing hardware control method provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0023] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0024] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] The embodiments of this application provide a switch system, which will be described in detail below with reference to the schematic diagram of the switch system.

[0026] refer to Figure 1 As shown in the embodiment of this application, a switch system includes:

[0027] Main logic device, temperature sensing device, and power supply voltage regulation device.

[0028] In related solutions, the excessive reliance on firmware in the switch system reduces the overall reliability and stability of the switch. To improve the hardware independence and reliability of the switch, enable monitoring and hardware-level control of critical hardware parameters in complex application scenarios, and enhance the modularity and portability of the hardware, this application provides a switch system based on a main logic device. The main logic device can be a complex programmable logic device. External hardware configuration of the main logic device enables hardware-level monitoring, alarming, and regulation of some clock, power timing, power voltage, and temperature parameters, thereby reducing dependence on firmware versions and operating conditions and improving the overall stability of the switch system.

[0029] The main logic device supports multi-channel power supply monitoring to achieve hardware monitoring and power-on / off control of external power planes. It supports a built-in phase-locked loop (PLL) and multiple general-purpose input / output (GPIO) pins to monitor external clock inputs and multiple clock outputs to downstream devices, as well as clock source switching in case of clock anomalies. The main logic device supports hardware monitoring of external temperature sensors and responding to hardware alarm reports, enabling thermal shutdown at the hardware level. Furthermore, it supports multiple GPIO pins to configure different durations of external hardware pull-up / pull-down settings for adding delay schemes, and allows the delay scheme to be applied to one or more power planes.

[0030] The main logic devices include a power control module, a temperature control module, a clock control module, and a timing control module.

[0031] The power control module monitors the voltage of the power planes connected to each power supply voltage regulator and assigns a target bit to the first register when the voltage of a power plane is abnormal. The target bit is the bit corresponding to the power plane. Each power plane corresponds to one bit in the first register. For example, when the voltage of a power plane is abnormal, the target bit in the first register is set to 1. If the value of the bit corresponding to the power plane is 0, it indicates that the voltage of that power plane is normal. If the value of the bit corresponding to the power plane is 1, it indicates that the voltage of that power plane is abnormal. In some embodiments, the power control module is also used to trigger the upper-level controller to perform the operation of reading the values ​​of each register (including the first register and other registers) of the main logic device and recording them to the system log. The system log is stored in a non-volatile storage medium. Voltage abnormalities of the power plane include overvoltage and undervoltage. If the voltage of the power plane is overvoltage, the power control module pulls down the enable pin of the corresponding power supply voltage regulator, thereby shutting down the output of the power supply voltage regulator and preventing related load components from being damaged by overvoltage.

[0032] In some embodiments, the power control module is further configured to, when the voltage of the power plane is abnormal, record that the power voltage regulation device can autonomously report a voltage output abnormality if the power voltage regulation device reports a voltage output abnormality; and record that the power voltage regulation device cannot autonomously report a voltage output abnormality if the power voltage regulation device does not report a voltage output abnormality.

[0033] The power supply voltage regulator autonomously reports voltage output abnormalities to the main logic device by triggering alarm or interrupt signals. The power control module determines whether the power supply voltage regulator has autonomously reported the voltage output abnormality based on the alarm or interrupt signal received by the main logic device. For example, if the alarm or interrupt signal is pulled low to logic 0, it indicates that the power supply voltage regulator has reported a voltage output abnormality, and the power control module records that the power supply voltage regulator can autonomously report a voltage output abnormality. If the alarm or interrupt signal is pulled high to logic 1, it indicates that the power supply voltage regulator has not reported a voltage output abnormality, and the power control module records that the power supply voltage regulator cannot autonomously report a voltage output abnormality.

[0034] The power control module records whether a power voltage regulator can autonomously report a voltage output abnormality and whether it cannot. This can be achieved by assigning a value to the corresponding bit in a first preset register. The first preset register records whether a power voltage regulator can autonomously report a voltage output abnormality. Each power voltage regulator corresponds to one bit in the first preset register. For example, if a power voltage regulator can autonomously report a voltage output abnormality, the corresponding bit is set to 1. If a power voltage regulator cannot autonomously report a voltage output abnormality, the corresponding bit is set to 0.

[0035] Recording whether the power supply voltage regulation equipment can autonomously report voltage output abnormalities can facilitate later maintenance and troubleshooting, improve operation and maintenance efficiency, and reduce operation and maintenance costs.

[0036] In some embodiments, the power control module is further configured to record the power plane as overvoltage if the voltage of the power plane is overvoltage, and record the power plane as undervoltage if the voltage of the power plane is undervoltage.

[0037] The overvoltage or undervoltage state of a power plane can be recorded by assigning a value to the corresponding bit in a register used to record overvoltage and undervoltage states. Each power plane corresponds to one bit in this register. For example, if a power plane is overvoltaged, the corresponding bit is set to 1. If a power plane is undervoltaged, the corresponding bit is set to 0.

[0038] Recording the overvoltage and undervoltage states of the power plane facilitates later maintenance and troubleshooting, improves operation and maintenance efficiency, and reduces operation and maintenance costs.

[0039] In some embodiments, the power control module is further configured to monitor whether the voltage of the power plane has returned to normal if the voltage of the power plane is undervoltage, and assign a value to the first register when the voltage of the power plane has returned to normal.

[0040] If the power plane voltage is undervoltage, the power control module continues to monitor whether the power plane voltage returns to the normal threshold in real time. If it returns to normal, the power control module assigns a value to the first register and reports an alarm indicating that the power plane has returned to normal. For example, if it returns to normal, the bit corresponding to the power plane in the first register is set to 0. If it cannot return to normal, the state of the switch system's registers is maintained while the entire switch system is powered on, to preserve the abnormal environment for engineers to troubleshoot, locate, and repair errors.

[0041] refer to Figure 2 As shown, in some embodiments, the power control module includes a power monitoring module and a power control logic module; the power monitoring module corresponds one-to-one with the power voltage regulation device.

[0042] The power monitoring module is used to convert the analog signal of the voltage of the power plane connected to the power voltage regulation device into a digital signal. When the voltage is determined to be abnormal based on the digital signal, a value is assigned to the first register. If the voltage of the power plane is overvoltage, the power plane is recorded as being in an overvoltage state. If the voltage of the power plane is undervoltage, the power plane is recorded as being in an undervoltage state, and the module monitors whether the voltage of the power plane returns to normal. When the voltage of the power plane returns to normal, a value is assigned to the first register.

[0043] The power control logic module is used to shut down the output of the corresponding power voltage regulator if the voltage of the power plane is overvoltage; when the voltage of the power plane is abnormal, if the power voltage regulator reports an abnormal voltage output, it is recorded that the power voltage regulator can autonomously report an abnormal voltage output; if the power voltage regulator does not report an abnormal voltage output, it is recorded that the power voltage regulator cannot autonomously report an abnormal voltage output; and triggers the upper-level controller to perform the operation of reading the values ​​of each register of the main logic device and recording them in the system log.

[0044] Each power monitoring module corresponds one-to-one with a power voltage regulator. One module is responsible for monitoring the voltage of the power plane connected to one power voltage regulator. The module converts the analog voltage signal of the power plane connected to the regulator into a digital signal, and then determines whether the voltage is abnormal based on the converted digital signal. If the voltage is abnormal, a target bit is assigned to it in the first register. The module reports an alarm indicating an abnormality in the power plane by assigning the target bit to the first register. If the voltage of the power plane is overvoltage, the module records it as overvoltage; if the voltage is undervoltage, the module records it as undervoltage and monitors whether the voltage returns to normal. When the voltage returns to normal, a value is assigned to the first register.

[0045] The power control logic module is used to shut down the output of the corresponding power voltage regulator if the voltage of the power plane is overvoltage; when the voltage of the power plane is abnormal, if the power voltage regulator reports a voltage output abnormality, it is recorded that the power voltage regulator can autonomously report a voltage output abnormality; if the power voltage regulator does not report a voltage output abnormality, it is recorded that the power voltage regulator cannot autonomously report a voltage output abnormality; and it triggers the upper-level controller to perform the operation of reading the values ​​of each register of the main logic device and recording them in the system log.

[0046] refer to Figure 3 As shown, one of the power monitoring modules ( Figure 3 Taking the first power monitoring module (hereinafter referred to as the first power monitoring module) as an example, combined with Figure 4 The power supply hardware monitoring logic shown below is illustrated in a specific embodiment.

[0047] Figure 3 The first monitored power plane refers to the power plane monitored by the first power monitoring module. The first power monitoring module primarily converts the analog signal of the voltage from the external first monitored power plane into a digital signal (power monitoring modules with different levels of integration support 8 bits to achieve a minimum resolution voltage accuracy of 256 divisions, or support 16 bits to achieve a minimum resolution voltage accuracy of 65535 divisions). The power control logic module primarily receives interrupts and exceptions reported by the first power monitoring module and controls the status of the external first power voltage regulation device to achieve hardware logic monitoring and control of the power plane. The first power voltage regulation device refers to the power voltage regulation device connected to the first power plane.

[0048] In normal operation mode, the first power monitoring module of the main logic device monitors the voltage value of the first monitored power plane in real time. When it determines that the voltage of the first monitored power plane is abnormal, it assigns a value to the first register, thereby reporting an alarm indicating an abnormality in the power plane. The power control logic module determines whether the first power voltage regulation device autonomously triggers the Alert_N signal (alarm signal) or the INT_N signal (interrupt signal). For example, if the power logic control module determines that the Alert_N signal or the INT_N signal is pulled low to logic 0, it indicates that the first power voltage regulation device has autonomously triggered the Alert_N signal or the INT_N signal, and records that the first power voltage regulation device is normal and can autonomously report voltage output abnormalities. If the power logic control module determines that the Alert_N signal or the INT_N signal is pulled high to logic 1, it indicates that the first power voltage regulation device has not autonomously triggered the Alert_N signal or the INT_N signal, and records that the first power voltage regulation device cannot autonomously report voltage output abnormalities. The first power monitoring module determines whether a voltage anomaly on the power plane is an overvoltage. If so, it records the overvoltage status. The power control logic module actively triggers the upper-level main controller to read the real-time register values ​​of the main logic device and record them in the system log via an interrupt reporting pin configured on the general-purpose input / output pins. The system log is stored in non-volatile storage. If not, it records the undervoltage status. The power control logic module actively triggers the upper-level main controller to read the real-time register values ​​of the main logic device and record them in the system log via an interrupt reporting pin configured on the general-purpose input / output pins. The system log is also stored in non-volatile storage.

[0049] In an overvoltage state, after the upper-layer main controller reads and records the real-time register values ​​of the main logic device, the power logic control module pulls the enable pin of the first power voltage regulator low, causing the first power voltage regulator to shut down its output and prevent damage to the power load IC components of that circuit due to overvoltage. In an undervoltage state, the first power monitoring module continues to monitor in real time whether the voltage of the first monitored power plane has recovered to within the normal voltage threshold. If it has recovered, the first power monitoring module assigns a value to the first register, reports an alarm indicating that the power plane has returned to normal, and returns to the initial state to continue monitoring the power plane; if it cannot recover, the register state of the main logic device is maintained while the entire switch system is powered on, to preserve the abnormal environment for engineers to troubleshoot, locate, and repair errors.

[0050] The temperature control module monitors the temperature collected by the temperature sensing device and assigns a value to the second register when the temperature is abnormal. In some embodiments, the temperature control module also triggers the upper-level controller to read the values ​​of each register (including the second register and other registers) of the main logic device and record them in the system log. The system log is stored in a non-volatile storage medium.

[0051] In some embodiments, the temperature control module is further configured to, when the temperature is abnormal, record that the temperature sensing device can autonomously report a temperature abnormality if the temperature sensing device reports a temperature abnormality, and record that the temperature sensing device cannot autonomously report a temperature abnormality if the temperature sensing device does not report a temperature abnormality.

[0052] The temperature sensing device autonomously reports temperature anomalies by triggering an alarm signal or an interrupt signal. The temperature control module determines whether the temperature sensing device has autonomously triggered an alarm signal or an interrupt signal. If the alarm signal or interrupt signal is pulled low to logic 0, it indicates that the temperature sensing device has reported a temperature anomaly, and the temperature control module records that the temperature sensing device can autonomously report a temperature anomaly. If the alarm signal or interrupt signal is pulled high to logic 1, it indicates that the temperature sensing device has not reported a temperature anomaly, and the temperature control module records that the temperature sensing device cannot autonomously report a temperature anomaly.

[0053] The temperature control module records whether a temperature sensing device can autonomously report temperature anomalies and whether it cannot. This can be achieved by assigning a value to the corresponding bit in a second preset register. The second preset register records whether a temperature sensing device can autonomously report temperature anomalies. Each temperature sensing device corresponds to one bit in the second preset register. For example, if a temperature sensing device can autonomously report a voltage output anomaly, its corresponding bit is set to 1. If a temperature sensing device cannot autonomously report a temperature anomaly, its corresponding bit is set to 0.

[0054] Recording whether temperature sensing devices can autonomously report temperature anomalies facilitates later maintenance and troubleshooting, improves operational efficiency, and reduces operational costs.

[0055] In some embodiments, the temperature control module is further configured to trigger the upper-layer controller to access the main logic device to obtain the temperature value.

[0056] The temperature control module can trigger the upper-level controller to access the main logic device, thereby obtaining the temperature values ​​collected by each temperature sensing device from the main logic device.

[0057] In some embodiments, the temperature control module is further configured to trigger the heat dissipation device to operate at its maximum capacity if the temperature exceeds the limit and the heat dissipation device is not operating at its maximum capacity; and to trigger a thermal shutdown mechanism if the temperature exceeds the limit and the heat dissipation device is already operating at its maximum capacity.

[0058] If the temperature exceeds the limit and the cooling system (e.g., air cooling or liquid cooling) is operating at maximum capacity, it indicates that the ambient temperature cannot be controlled, triggering a thermal shutdown mechanism and initiating a power-down timing strategy to prevent thermal damage to the chip. The hardware logic control implemented in this step of triggering the thermal shutdown mechanism and initiating the power-down timing strategy has higher priority than software control, no longer relying entirely on software thermal management strategies, thereby improving the reliability of the hardware system. If the temperature exceeds the limit and the cooling system is not operating at maximum capacity, the cooling system is triggered to operate at maximum capacity and continuously monitors the temperature.

[0059] In some embodiments, the temperature control module includes:

[0060] The system includes a temperature monitoring module and a temperature sensing control and alarm module; each temperature monitoring module corresponds to a temperature sensing device.

[0061] The temperature monitoring module is used to convert the analog temperature signal collected by the temperature sensing device into a digital signal, and when the temperature is determined to be abnormal based on the digital signal, it assigns a value to the second register.

[0062] The temperature sensing control and alarm module is used to trigger the upper-level controller to read the values ​​of each register of the main logic device and record them in the system log. When the temperature is abnormal, if the temperature sensing device reports a temperature abnormality, it is recorded that the temperature sensing device can autonomously report a temperature abnormality; if the temperature sensing device does not report a temperature abnormality, it is recorded that the temperature sensing device cannot autonomously report a temperature abnormality. The upper-level controller is triggered to access the main logic device to obtain the temperature value. If the temperature exceeds the limit and the heat dissipation device is not operating at maximum capacity, the heat dissipation device is triggered to operate at maximum capacity. If the temperature exceeds the limit and the heat dissipation device is operating at maximum capacity, a thermal shutdown mechanism is triggered.

[0063] refer to Figure 5 As shown, one of the temperature monitoring modules ( Figure 5 Taking the first temperature monitoring module (hereinafter referred to as the first temperature monitoring module) as an example, combined with Figure 6 The temperature sensing hardware monitoring logic shown below is illustrated in a specific embodiment.

[0064] Figure 5 The first temperature sensing device refers to the temperature sensing device monitored by the first temperature monitoring module. The first temperature monitoring module mainly converts the continuous analog temperature signal collected by the external first temperature sensing device into a digital signal. The temperature control and alarm module mainly receives alarms reported by the external first temperature sensing device and, based on the actual temperature and status pins, determines whether the temperature is too high, requiring hardware logic to handle the maximum operating condition of the heat dissipation device or thermal shutdown. The first temperature sensing device can have its temperature alarm threshold set via pull-up / pull-down pins.

[0065] In normal operation mode, the first temperature monitoring module monitors the temperature values ​​collected by the first temperature sensing device in real time. When an abnormal temperature value is detected, it assigns a value to the second register and reports an over-temperature alarm. The temperature control and alarm module determines whether the first temperature sensing device autonomously triggers the Alert_N or INT_N signal. If the temperature control and alarm module determines that the Alert_N or INT_N signal is pulled low to logic 0, it records that the first temperature sensing device is normal and can autonomously report a temperature abnormality; if the temperature control and alarm module determines that the Alert_N or INT_N signal is pulled high to logic 1, it records that the first temperature sensing device cannot autonomously report a temperature abnormality. The first temperature monitoring module instructs the upper-level main controller to access the main logic device through the I2C or LPC interface to obtain the real-time temperature. The temperature control and alarm module triggers an interrupt report through a general-purpose input / output pin, instructing the upper-level main controller to record the real-time register value of the main logic device under the current abnormal environment and record it in the system log. The system log is stored in a non-volatile storage medium. The temperature control and alarm module determines whether the current heat dissipation device (air cooling, liquid cooling) is operating at its maximum capacity. If so, it indicates that the ambient temperature cannot be controlled, and the temperature control and alarm module triggers a thermal shutdown mechanism, initiating a power-down sequence strategy to prevent overheating and thermal damage to the IC chip. If not, it operates at its maximum capacity and continuously monitors the temperature. The thermal shutdown mechanism and power-down sequence strategy prioritize hardware logic control over software regulation, reducing reliance on software-based heat dissipation control and thus improving system hardware reliability.

[0066] The clock control module monitors the quality of the external clock source and switches the input external clock source to the main logic device based on the quality of the external clock source. It also monitors the quality of each clock output from the main logic device; when any output clock of the main logic device is abnormal, it assigns a value to the third register and notifies the target device to automatically switch to the target clock source. In some embodiments, the clock control module is also used to trigger the upper-layer controller to read the values ​​of each register of the main logic device and record them in the system log.

[0067] The target device is the device to which the abnormal output clock is input. The target device is one or more devices connected to the main logic device. The main logic device is a first-level device, and the devices connected to it are second-level devices. The target clock source is an external clock source connected to the target device. Each device connected to the main logic device has its own external clock source.

[0068] In some embodiments, the external clock source includes a first clock source and a second clock source; the first clock source has a higher priority than the second clock source; the clock control module is also used to assign a value to a fourth register if the first clock source is abnormal.

[0069] The first and second clock sources are connected to the main logic device. The first clock source can be a CLK GEN (clock generator). The second clock source can be a Crystal Osc (crystal oscillator). The first clock source has higher priority than the second clock source; that is, the first clock source is used first. The target clock source can be a Crystal Osc. If the first clock source malfunctions, the second clock source is switched on if it is functioning normally. Furthermore, if the first clock source malfunctions, the fourth register is assigned a value. For example, setting the bit corresponding to the first clock source in the fourth register to 1 indicates that the first clock source is malfunctioning.

[0070] In some embodiments, the clock control module is further configured to assign a first value to the fifth register if the second clock source is working normally; the first value indicates that the second clock source is working normally; if the second clock source is abnormal, assign a second value to the fifth register; the second value indicates that the second clock source is abnormal.

[0071] For example, if the second clock source is working normally, the fifth register is set to 1; if the second clock source is abnormal, the fifth register is set to 0.

[0072] In some embodiments, the clock control module is also used to assign a value to the sixth register when any output clock is abnormal.

[0073] When one of the main logic device's output clocks fails, the corresponding bit in the sixth register is assigned a value. For example, when one of the main logic device's output clocks fails, the corresponding bit in the sixth register is assigned a value of 1.

[0074] In some embodiments, the clock control module includes a clock monitoring module and a clock alarm and switching module;

[0075] The clock monitoring module is used to monitor the quality of the external clock source and the quality of each clock output by the main logic device.

[0076] The clock alarm and switching module is used to switch the external clock source input to the main logic device according to the quality of the external clock source; when any output clock of the main logic device is abnormal, it assigns a value to the third register and notifies the target device to switch to the target clock source automatically; it triggers the upper-layer controller to perform the operation of reading the values ​​of each register of the main logic device and recording them to the system log; the external clock source includes a first clock source and a second clock source; if the first clock source is abnormal, it assigns a value to the fourth register; if the second clock source is normal and available, it assigns a first value to the fifth register; the first value indicates that the second clock source is normal; if the second clock source is abnormal, it assigns a second value to the fifth register; the second value indicates that the second clock source is abnormal; when any output clock is abnormal, it assigns a value to the sixth register.

[0077] refer to Figure 7 As shown, the clock monitoring module mainly implements external clock source monitoring, phase-locked loop (PLL), multi-phase output (including multi-phase output after frequency division), and output clock monitoring. The clock alarm and switching module mainly receives the clock alarm status reported by the clock monitoring module and assigns values ​​to the register to indicate the alarm status. Through clock switching and general-purpose input / output pins, it realizes the function of sending out the status of abnormal input clock of secondary devices, informing the secondary devices to switch the clock source autonomously to ensure the reliability of hardware functions.

[0078] refer to Figure 8 As shown, the following describes an embodiment of clock input control.

[0079] The clock monitoring module monitors the quality of the external clock source in real time, including but not limited to jitter and ppm clock frequency deviation. When an anomaly is detected in the first clock source, the clock alarm and switching module assigns a value to the fourth register to report an interrupt alarm. The clock monitoring module determines whether the second clock source is normal and available. If so, the clock alarm and switching module switches the external clock source to the second clock source. After determining that the second clock source is working normally, the fifth register is assigned a logic 0 to indicate normal operation; otherwise, the fifth register is assigned a logic 1 to indicate an anomaly. The clock alarm and switching module triggers an external interrupt through a general-purpose input / output pin to notify the upper-level main controller to actively read the real-time register values ​​of the current main logic device and record them in the system log. The system log is stored in a non-volatile storage medium so that engineers can trace the hardware state at the time of the problem during later debugging.

[0080] refer to Figure 9 As shown, the following describes an embodiment of clock output monitoring.

[0081] The clock monitoring module monitors the quality of the multi-channel output clock after phase-locked loop (PLL) in real time, including but not limited to jitter and ppm clock frequency deviation. When an abnormal output clock is detected on a certain channel, the clock alarm and switching module assigns a value to the sixth register to report an interrupt alarm. The clock alarm and switching module sets the corresponding GPIO to 1 to notify the corresponding secondary device that its clock is abnormal and it needs to switch to its own connected clock source. The secondary device determines whether the clock source switch has been completed. If so, the secondary device sets its own clock abnormality switching status register and triggers an external interrupt to report to the upper-level main controller, which actively reads the real-time register value of the secondary device and records it in the system log. The system log is stored in non-volatile storage. If not, the secondary device may no longer be working properly and cannot report to the upper-level main controller. The clock alarm and switching module reports to the main controller via general-purpose input / output pins to read the real-time register value of the main logic device and record it in the system log. The system log is stored in non-volatile storage so that engineers can trace the hardware state at the time of the problem during later debugging.

[0082] The timing control module is used to control the timing of the power supply voltage regulation device.

[0083] refer to Figure 10 As shown, in some embodiments, the timing control module includes: a clock ladder delay module and a clock delay application module;

[0084] The clock ladder delay module is used to determine the delay duration based on the voltage of the first target general-purpose input / output pin;

[0085] The clock delay application module is used to determine the delay target based on the level state of the second target general-purpose input / output pin.

[0086] The clock ladder delay module determines the delay duration based on specific general-purpose input / output pins, and the clock delay application module determines the delay target based on specific general-purpose input / output pins. In this way, by determining the delay duration and delay target through a hardware solution, highly reliable power-on and power-off timing control can be achieved for power supply voltage regulation equipment.

[0087] The first target general-purpose input / output pin is used to set the delay duration. The second target general-purpose input / output pin is used to set the delay target (i.e., the power supply voltage regulator device to be delayed during power-on or power-off).

[0088] The timing control module mainly includes a clock ladder delay module and a clock delay application module. The clock ladder delay module primarily uses a series of general-purpose input / output pins with specific functions—the first target general-purpose input / output pins—to complete the external hardware delay combination. It can be configured with different high-precision resistor values ​​to divide the voltage range of the GPIO, achieving hardware delay for the power-on timing of each power plane. For example, the GPIO group R1 / R2 can achieve a delay duration configuration of 1µs to 10µs (0V-3.3V ladder configuration), and so on to the remaining R3 to R12. During the hardware design phase, the required number of GPIOs (denoted as i) is configured according to the requirements, thus achieving at least 2... i Delay configuration on the order of magnitude. For example, if the number of GPIOs used to set the delay duration is 6 (i = 6), and each GPIO supports two voltage values, then 2-6 delays can be achieved. 6 The latency configuration is on the order of magnitude. If each GPIO can support three voltage values, then 3 6 The clock delay configuration involves a series of general-purpose input / output pins (GPIOs) with specific functions, i.e., the second target GPIO pins, to combine external hardware for clock delay applications. This can be achieved by configuring pull-up / pull-down combinations to form a hardware state code for this GPIO field, specifying which power planes the delay result is applied to. Logic 0 indicates application, and logic 1 indicates no application. For example, 4 bits of 1001 indicate adding a delay between the first and second power voltage regulators, and between the second and third power voltage regulators. This forms a fixed state code with hardware constraints to ensure highly reliable power-on / off timing control.

[0089] In summary, the switch system provided in this application embodiment achieves autonomous monitoring, judgment, identification, alarm, and control of four major hardware indicators—power supply, clock, timing, and temperature—through hardware configuration and hardware logic. This enables the hardware system to control the normal operation of the entire machine with high priority, ensuring rapid response and recording of relevant data at the time of abnormality in the switch system. It also ensures that autonomous measures are in place to protect the system hardware in cases of software process freezes or even system crashes, thereby improving system stability and reliability. Furthermore, the fault recording and reporting function helps engineers reconstruct and confirm the hardware status information at the time of the abnormality when the machine is returned for repair, facilitating quick and accurate identification of the problem area and faster, more efficient hardware troubleshooting.

[0090] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0091] The present application provides a detailed description of a switching system. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A switching system, characterized in that, include: The system includes a main logic device, a temperature sensing device, and a power supply voltage regulation device; the main logic device includes a power control module, a temperature control module, a clock control module, and a timing control module. The power control module is used to monitor the voltage of the power plane connected to the power voltage regulation device, and assign a value to the first register when the voltage is abnormal. The upper-level controller is triggered to read the values ​​of each register of the main logic device and record them in the system log; if the voltage of the power plane is overvoltage, the output of the corresponding power voltage regulator is shut down; The temperature control module is used to monitor the temperature collected by the temperature sensing device, and assign a value to the second register when the temperature is abnormal; it triggers the upper-level controller to access the main logic device to obtain the temperature value, and triggers the upper-level controller to perform the operation of reading the values ​​of each register of the main logic device and recording them to the system log; If the temperature exceeds the limit and the heat dissipation device is not operating at its maximum capacity, then the heat dissipation device will be triggered to operate at its maximum capacity. If the temperature exceeds the limit and the heat dissipation device is already operating at maximum capacity, the thermal shutdown mechanism will be triggered. The clock control module is used to monitor the quality of the external clock source, switch the input external clock source of the main logic device according to the quality of the external clock source, monitor the quality of each clock output by the main logic device, and when any output clock of the main logic device is abnormal, assign a value to the third register and notify the target device to switch to the target clock source automatically. The upper-level controller is triggered to read the values ​​of each register of the main logic device and record them in the system log. The timing control module is used to control the timing of the power supply voltage regulation device.

2. The switching system according to claim 1, characterized in that, The power control module is also used to record, when the voltage of the power plane is abnormal, if the power voltage regulating device reports a voltage output abnormality, that the power voltage regulating device can autonomously report a voltage output abnormality; if the power voltage regulating device does not report a voltage output abnormality, that the power voltage regulating device cannot autonomously report a voltage output abnormality.

3. The switching system according to claim 1, characterized in that, The power control module is also used to monitor whether the voltage of the power plane has returned to normal if the voltage of the power plane is undervoltage, and to assign a value to the first register when the voltage of the power plane has returned to normal.

4. The switching system according to claim 1, characterized in that, The power control module includes a power monitoring module and a power control logic module; the power monitoring module corresponds one-to-one with the power voltage regulation device. The power monitoring module is used to convert the analog signal of the voltage of the power plane connected to the power voltage regulation device into a digital signal. When the voltage is determined to be abnormal based on the digital signal, a value is assigned to the first register. If the voltage of the power plane is overvoltage, the power plane is recorded as being in an overvoltage state. If the voltage of the power plane is undervoltage, the power plane is recorded as being in an undervoltage state, and the module monitors whether the voltage of the power plane returns to normal. When the voltage of the power plane returns to normal, a value is assigned to the first register. The power control logic module is used to shut down the output of the corresponding power voltage regulator if the voltage of the power plane is overvoltage; when the voltage of the power plane is abnormal, if the power voltage regulator reports an abnormal voltage output, it is recorded that the power voltage regulator can autonomously report an abnormal voltage output; if the power voltage regulator does not report an abnormal voltage output, it is recorded that the power voltage regulator cannot autonomously report an abnormal voltage output. The upper-level controller is triggered to read the values ​​of each register of the main logic device and record them in the system log.

5. The switching system according to claim 1, characterized in that, The timing control module includes: Clock ladder delay module, clock delay application module; The clock ladder delay module is used to determine the delay duration based on the voltage of the first target general-purpose input / output pin; The clock delay application module is used to determine the delay target based on the level state of the second target general-purpose input / output pin.

6. The switching system according to claim 1, characterized in that, The temperature control module is also used to record that the temperature sensing device can autonomously report a temperature abnormality if the temperature sensing device reports a temperature abnormality, and to record that the temperature sensing device cannot autonomously report a temperature abnormality if the temperature sensing device does not report a temperature abnormality.

7. The switching system according to claim 1, characterized in that, The temperature control module includes: The system includes a temperature monitoring module and a temperature sensing control and alarm module; each temperature monitoring module corresponds to a temperature sensing device. The temperature monitoring module is used to convert the analog temperature signal collected by the temperature sensing device into a digital signal, and when the temperature is determined to be abnormal based on the digital signal, it assigns a value to the second register. The temperature sensing control and alarm module is used to trigger the upper-level controller to read the values ​​of each register of the main logic device and record them in the system log. When the temperature is abnormal, if the temperature sensing device reports a temperature abnormality, it is recorded that the temperature sensing device can autonomously report a temperature abnormality; if the temperature sensing device does not report a temperature abnormality, it is recorded that the temperature sensing device cannot autonomously report a temperature abnormality. The upper-level controller is triggered to access the main logic device to obtain the temperature value. If the temperature exceeds the limit and the heat dissipation device is not operating at maximum capacity, the heat dissipation device is triggered to operate at maximum capacity. If the temperature exceeds the limit and the heat dissipation device is operating at maximum capacity, a thermal shutdown mechanism is triggered.

8. The switching system according to claim 1, characterized in that, The external clock source includes a first clock source and a second clock source; the first clock source has a higher priority than the second clock source; the clock control module is also used to assign a value to the fourth register if the first clock source is abnormal.

9. The switching system according to claim 8, characterized in that, The clock control module is further configured to assign a first value to the fifth register if the second clock source is working normally; the first value indicates that the second clock source is working normally; if the second clock source is abnormal, assign a second value to the fifth register; the second value indicates that the second clock source is abnormal.

10. The switching system according to claim 1, characterized in that, The clock control module is also used to assign a value to the sixth register when any output clock is abnormal.

11. The switching system according to claim 1, characterized in that, The clock control module includes a clock monitoring module and a clock alarm and switching module; The clock monitoring module is used to monitor the quality of the external clock source and the quality of each clock output by the main logic device. The clock alarm and switching module is used to switch the external clock source input to the main logic device according to the quality of the external clock source. When any output clock of the main logic device is abnormal, the third register is assigned a value, and the target device is notified to switch to the target clock source automatically. The upper-level controller is triggered to read the values ​​of each register of the main logic device and record them to the system log; the external clock source includes a first clock source and a second clock source; If the first clock source fails, the value is assigned to the fourth register; If the second clock source is available, the fifth register is assigned the first value; the first value indicates that the second clock source is working properly. If the second clock source is faulty, the fifth register is assigned the second value; the second value indicates that the second clock source is faulty; when any output clock is faulty, the sixth register is assigned the value.

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