Intelligent body high-speed bus implementation method and system based on FPGA and dynamic smoothing technology

Abstract

The application relates to the technical field of data communication, and discloses an agent high-speed bus implementation method and system based on FPGA and a dynamic smoothing technology. The method comprises the following steps: constructing a single handshake message through a lightweight protocol, adjusting network indexes by using an exponential smoothing method, constructing a pipeline processing unit on an FPGA card by using VHDL, realizing key update and encryption processing, constructing a three-layer adaptive structure connection subsystem, and optimizing algorithm parameters and resource allocation according to a running state to form a high-performance bus communication system. Under the premise of guaranteeing communication security and reliability, the application significantly reduces network transmission delay and improves data throughput, so that the communication system can meet the emergency linkage and large data transmission requirements in a high real-time requirement scene (such as a rail transit station-level system).

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data communication, and in particular to an agent high-speed bus implementation method and system based on FPGA and dynamic smoothing technology. BACKGROUND

[0002] In the field of traditional communication protocols, TCP / IP and UDP protocols have been widely used in various network communication scenarios. TCP protocol uses a three-way handshake process to establish a connection and provides reliable data transmission services, but has problems such as multiple handshakes, redundant acknowledgments, slow start, and inflexible congestion control, making it difficult to meet real-time response requirements in high-load, low-latency scenarios. UDP protocol, although it omits the handshake process and has low latency, lacks reliability guarantees and has fixed header information in the message, which also cannot meet the large throughput requirement. At the same time, most traditional communication systems use general-purpose CPUs to process protocol stacks, which are limited by serial computing characteristics and are prone to latency fluctuations and packet loss in high-concurrency situations, affecting system response speed and stability. With the development of the Internet of Things and industrial automation, the interconnection demand of various embedded devices is increasing, but existing communication solutions still have many limitations in security, real-time performance, and reliability.

[0003] However, the above technical solutions have obvious shortcomings when faced with emerging high real-time and high throughput scenarios. In particular, in critical infrastructure such as rail transit station-level systems, the delay caused by the traditional protocol handshake process cannot meet the time requirements of emergency response; the efficiency of the protocol stack under the general-purpose CPU processing mode is limited and cannot support high-speed data exchange between a large number of devices; there is a lack of effective adaptive mechanism when network conditions fluctuate, leading to unstable communication quality; in addition, existing technologies generally lack lightweight security solutions for resource-constrained devices, making it difficult to balance performance and security. With the penetration of AI technology in industrial scenarios, the communication demand between devices has increased significantly, and these shortcomings have become more prominent, making it urgent to develop a communication solution that can simultaneously meet low latency, high throughput, reliability, and security requirements. SUMMARY

[0004] An object of the present application is to provide an agent high-speed bus implementation method and system based on FPGA and dynamic smoothing technology, which can significantly reduce network transmission delay and improve data throughput while ensuring communication security and reliability, so that the communication system can meet the emergency response and large data transmission requirements in high real-time scenarios such as rail transit station-level systems.

[0005] To achieve the above object, some embodiments of the present application provide the following aspects:

[0006] In a first aspect, the application provides an agent high-speed bus implementation method based on FPGA and dynamic smoothing technology, comprising: customizing a single handshake message to obtain a lightweight message structure with compressed header; dynamically adjusting a network performance index matrix according to real-time collected network transmission delay data to obtain an adaptive transmission parameter set; constructing a pipeline structure protocol processing unit using the lightweight message structure and the adaptive transmission parameter set to obtain a hardware accelerated protocol stack; and encrypting transmission data based on the hardware accelerated protocol stack to obtain a secure communication guarantee mechanism.

[0007] According to the hardware accelerated protocol stack and the secure communication guarantee mechanism, a three-layer adaptation structure of a physical interface conversion layer, a protocol adaptation layer and a session management layer is constructed to form a subsystem access architecture; and dynamic smoothing algorithm coefficients, cache size and FPGA logic resource allocation are optimized according to the running state of the subsystem access architecture to obtain a high-performance bus communication system.

[0008] In a second aspect, the application provides an agent high-speed bus implementation system based on FPGA and dynamic smoothing technology, comprising:

[0009] A construction module is configured to customize a single handshake message to obtain a lightweight message structure with compressed header;

[0010] An adjustment module is configured to dynamically adjust a network performance index matrix according to real-time collected network transmission delay data to obtain an adaptive transmission parameter set;

[0011] A construction module is configured to construct a pipeline structure protocol processing unit using the lightweight message structure and the adaptive transmission parameter set to obtain a hardware accelerated protocol stack;

[0012] An encryption module is configured to encrypt transmission data based on the hardware accelerated protocol stack to obtain a secure communication guarantee mechanism;

[0013] An access module is configured to construct a three-layer adaptation structure of a physical interface conversion layer, a protocol adaptation layer and a session management layer according to the hardware accelerated protocol stack and the secure communication guarantee mechanism to form a subsystem access architecture;

[0014] A processing module is configured to optimize dynamic smoothing algorithm coefficients, cache size and FPGA logic resource allocation according to the running state of the subsystem access architecture to obtain a high-performance bus communication system.

[0015] The third aspect of the present application provides a computer device, comprising: a memory and at least one processor, the memory having instructions stored therein; the at least one processor invoking the instructions in the memory to cause the computer device to perform the agent high-speed bus implementation method based on FPGA and dynamic smoothing technology.

[0016] The fourth aspect of the present application provides a computer readable storage medium having instructions stored therein, which, when executed on a computer, causes the computer to perform the agent high-speed bus implementation method based on FPGA and dynamic smoothing technology.

[0017] The technical scheme provided in the application has remarkable technical effects. The method successfully simplifies the traditional TCP three-way handshake into a single handshake, reduces the initial connection delay, and greatly improves the communication efficiency and throughput by designing a message compression header to remove redundant control information. The use of the exponential smoothing method to dynamically adjust the network performance index matrix enables the system to accurately perceive network state changes and predict trends. The dynamically generated adaptive transmission parameter set enables the communication process to maintain stable performance when the network conditions fluctuate, effectively reducing the impact of network jitter on communication quality. The protocol processing unit with a pipeline structure is constructed using the VHDL hardware description language on the FPGA card, which migrates the protocol stack from the software layer to the hardware implementation, fully utilizes the parallel computing advantages of FPGA, breaks through the performance bottleneck of traditional CPU serial processing, and improves the protocol processing speed by several times. The low latency characteristics of the hardware-accelerated protocol stack provide reliable protection for real-time control. Through the time-driven key update strategy and the improved AES-GCM mode security communication guarantee mechanism, the communication security is realized while ensuring high-speed data transmission. The periodic key rotation and hardware acceleration of the encryption algorithm minimize the performance overhead of the security mechanism. The three-layer adaptive structure subsystem access architecture design enables devices with different interface standards and protocols to seamlessly access the system, greatly enhancing the interoperability and scalability of the system and solving the problem of heterogeneous system integration. The tuning mechanism of the dynamic smoothing algorithm coefficients, cache size, and FPGA logic resource allocation enables the system to adaptively optimize according to real-time load conditions, ensuring optimal performance under various working conditions. It is particularly worth emphasizing that the dynamic smoothing technology in the present scheme is not just a simple smoothing algorithm application, but a comprehensive intelligent algorithm that combines network performance index matrix analysis, multi-factor weighting processing, and prediction model construction. This algorithm accurately predicts the future network state through deep learning and pattern recognition of network fluctuation characteristics, and then guides the dynamic adjustment of transmission parameters. This way of deeply integrating artificial intelligence algorithm characteristics and communication system makes the communication performance remain highly stable and predictable in complex and variable network environments, providing key technical support for high real-time requirement scenarios such as rail transit. The combination of FPGA reconfigurability and adaptive algorithm enables the system to continuously optimize, significantly improving the overall communication efficiency and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0018] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are included to further provide explanatory embodiments and not limitation to the application, wherein elements having the same reference numbers designate related elements. The figures in the drawings are not necessarily to scale, unless otherwise specifically noted.

[0019] Figure 1 Figure 1 is a schematic diagram of one embodiment of the agent high-speed bus implementation method based on FPGA and dynamic smoothing technology in the embodiments of the present application;

[0020] Figure 2 Figure 2 is a schematic diagram of a hardware platform based on an FPGA card;

[0021] Figure 3 Figure 3 is a schematic diagram of a data processing flow in the embodiments of the present application;

[0022] Figure 4 Figure 4 is a schematic diagram of a single handshake implementation flow in the embodiments of the present application;

[0023] Figure 5 Figure 5 is a schematic diagram of one embodiment of the agent high-speed bus implementation system based on FPGA and dynamic smoothing technology in the embodiments of the present application;

[0024] Figure 6 Figure 6 is a structural schematic block diagram of a computer device in the embodiments of the present application. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0026] Referring to Figure 1 One embodiment of the agent high-speed bus implementation method based on FPGA and dynamic smoothing technology in the embodiments of the present application includes the following steps.

[0027] Step S101, customizing and constructing a single handshake message to obtain a lightweight message structure with a compressed header;

[0028] Step S102, dynamically adjusting a network performance index matrix according to real-time collected network transmission delay data to obtain an adaptive transmission parameter set;

[0029] Step S103, constructing a protocol processing unit with a pipeline structure by using the lightweight message structure and the adaptive transmission parameter set to obtain a hardware accelerated protocol stack;

[0030] Step S104, performing encryption processing on transmission data based on the hardware accelerated protocol stack to obtain a secure communication guarantee mechanism;

[0031] Step S105, according to the hardware acceleration protocol stack and the security communication guarantee mechanism, a three-layer adaptation structure of a physical interface conversion layer, a protocol adaptation layer and a session management layer is constructed to form a subsystem access architecture;

[0032] Step S106, according to the running state of the subsystem access architecture, a dynamic smoothing algorithm coefficient, a cache size and a FPGA logic resource allocation are optimized to obtain a high-performance bus communication system.

[0033] It can be understood that the execution subject of the present application can be an intelligent agent high-speed bus implementation system based on FPGA and dynamic smoothing technology, and can also be a terminal or a server, which is not limited here. The server is taken as an example for description in the embodiments of the present application.

[0034] Specifically, the customization and construction of the lightweight protocol stack single handshake message is the basic link of the method. By cutting the traditional TCP / UDP protocol and removing redundant control fields, a more compact message structure is formed. Specifically, the handshake identifier (HS_FLAG) as the key identification part of the message contains the communication identity and session parameter encoding, and the authentication credential is generated based on the pre-shared key using the HMAC algorithm to ensure the identity of the communication parties is trusted. In practical applications, such as rail transit control systems, the handshake process of the original TCP protocol requires three message exchanges, totaling about 240 bytes of protocol header information, while the optimized single handshake message only needs one exchange, the header information is compressed to about 64 bytes, and the payload part can directly carry the initial control instruction. The dynamic smoothing technology is the core innovation point of the whole scheme. This technology adjusts the network performance index matrix in real time through the exponential smoothing method. When the network collects delay data, it first calculates the original delay sampling sequence, then constructs the time correlation matrix, and extracts the delay fluctuation characteristics. The key of the exponential smoothing method is to apply different weights to historical data, and the more recent the data, the greater the weight, so as to obtain a more accurate network state prediction. In the rail transit control system, the real-time collected network delay data may show a fluctuation from 5ms to 25ms. After dynamic smoothing processing, the transmission window adjustment coefficient is calculated immediately, such as adjusting the original window size to 65% of the original, and generating a rate change gradient to ensure that data transmission can respond to sudden situations and maintain overall stability.

[0035] Based on the first two steps, FPGA hardware acceleration is the key to achieve high performance. Lightweight message structure and adaptive transmission parameters are implemented on FPGA through VHDL hardware description language, and a hardware acceleration protocol stack including message parsing state machine, dynamic parameter register group and multi-stage pipeline is constructed. The parallel computing capability of FPGA changes the traditional software serial execution of message processing into hardware parallel processing, greatly reducing the delay. In fact, the message parsing state machine divides the received message into multiple stages of pipeline according to the steps of header parsing and payload processing, and each stage of pipeline can run in parallel to process different parts of different messages, significantly improving the processing efficiency.

[0036] In terms of security, the time-driven key update strategy and the improved AES-GCM mode ensure the security of communication. The key derivation function KDF is constructed based on the session identifier and the time seed to generate the initial key, and the key rotation is triggered according to the data transmission volume accumulated by the hardware counter. The improved AES-GCM mode randomizes the initial value of the counter to prevent attackers from guessing the sequence of encrypted packets. In high-speed communication scenarios, the key update threshold is usually set to trigger key update once every 10 GB of data transmission or 24 hours of operation, greatly improving the security of communication.

[0037] The subsystem access architecture adopts a three-layer adaptive structure design. The physical interface conversion layer supports different interface standards such as Ethernet and PCIe, the protocol adaptation layer realizes the format conversion between external protocols and lightweight messages, and the session management layer is responsible for maintaining the state information between subsystems. This design enables the entire communication system to seamlessly interface with different devices and protocols, greatly enhancing the system compatibility and expandability.

[0038] Based on the running state of the subsystem access architecture, the dynamic smoothing algorithm coefficients, cache size and FPGA logic resources are optimized to form a high-performance bus communication system. Through performance monitoring probes, system performance indicators are collected to optimize the smoothing algorithm parameters and cache strategy, and finally a resource allocation diagram is formed and deployed to FPGA. In actual application, performance monitoring data may show that some data flow paths are congested, and the system will automatically adjust the corresponding cache allocation ratio and reconfigure the FPGA logic resources to allocate more hardware resources to frequently used functional modules, thereby ensuring the optimal overall performance of the system.

[0039] In an actual rail transit station level system application scenario, the emergency linkage response needs to complete the entire communication process within 50 milliseconds. After adopting the scheme, a single handshake only needs about 3 milliseconds to complete connection establishment, dynamic smoothing technology reduces the delay fluctuation caused by network jitter by about 75%, FPGA hardware acceleration reduces the protocol processing time from 15 milliseconds of the traditional scheme to less than 1 millisecond, the security mechanism only increases the processing overhead by about 0.5 milliseconds while ensuring data security, and finally the total delay of the entire communication process is controlled within 10 milliseconds, fully meeting the real-time requirements of the emergency linkage, and the throughput is more than 3 times that of the traditional scheme.

[0040] In the embodiments of the present application, the core of the system hardware architecture adopts a hardware platform based on an FPGA card, which internally integrates a high-speed MAC layer interface, a customized protocol conversion module, a dynamic smoothing module, a hardware acceleration unit and a security encryption module. Each subsystem (such as BAS, FAS, etc.) is directly connected to the FPGA card through a dedicated adapter to realize low-latency and high-throughput data exchange. As shown in Figure 2 , it is a schematic diagram of the hardware platform based on the FPGA card.

[0041] After the data is collected by each subsystem, it is accessed through the MAC layer interface of the FPGA card. The protocol conversion module processes the data packets, eliminates redundant control information, and reconstructs them into a lightweight single handshake format. The dynamic smoothing module monitors the data transmission delay in real time and adaptively adjusts the sending window and the cache according to the network conditions. The hardware acceleration module transmits data at high speed to the target system through parallel processing to ensure continuous and stable data transmission. The security module performs encryption processing during transmission to ensure data integrity and security. As shown in Figure 3 , it is a flowchart of data processing in the present application;

[0042] The implementation process of the single handshake mechanism is as follows, as shown in Figure 4 , it is a schematic diagram of the implementation process of the single handshake mechanism in the embodiments of the present application;

[0043] Client: constructs a single handshake message (including HS_FLAG, sequence number, timestamp, authentication credentials, initial data), sends it to the target node, and transmits it through the FPGA hardware high-speed channel; starts a timeout timer to wait for confirmation

[0044] Server: after receiving the message, detects HS_FLAG, and verifies the authentication information using the pre-shared key; establishes a connection state, updates the session cache, and processes the initial data; sends a simplified acknowledgment message (ACK) back to complete the handshake.

[0045] Retransmission and dynamic adjustment: if there is no confirmation within the timeout, the client automatically retransmits, and the dynamic smoothing module adjusts the window parameters to adapt to the network conditions.

[0046] In the embodiments of the present application, the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology has significant technical effects. By customizing a single handshake message through a lightweight protocol stack, the method successfully simplifies the traditional TCP three-way handshake to a single handshake, reduces the initial connection delay, and at the same time, the message compression header design removes redundant control information, greatly improving the communication efficiency and throughput. The technical means of dynamically adjusting the network performance index matrix by using the exponential smoothing method enables the system to accurately perceive the network state changes and predict the trend, and the dynamically generated adaptive transmission parameter set enables the communication process to maintain stable performance when the network condition fluctuates, effectively reducing the influence of network jitter on communication quality. The protocol processing unit with a pipeline structure is constructed on the FPGA card using the VHDL hardware description language, which migrates the protocol stack from the software layer to the hardware implementation, fully utilizes the parallel computing advantage of FPGA, breaks through the performance bottleneck of traditional CPU serial processing, and improves the protocol processing speed by several times. The low-latency characteristics of the hardware-accelerated protocol stack provide reliable protection for real-time control. Through the time-driven key update strategy and the improved AES-GCM mode security communication guarantee mechanism, the communication security is realized while ensuring high-speed data transmission, and the performance overhead of the security mechanism is minimized by periodic key rotation and hardware acceleration of the encryption algorithm. The three-layer adaptive structure subsystem access architecture design enables devices with different interface standards and protocols to seamlessly access the system, greatly enhancing the interoperability and scalability of the system and solving the problem of heterogeneous system integration. The tuning mechanism of the dynamic smoothing algorithm coefficient, cache size and FPGA logic resource allocation enables the system to adaptively optimize according to the real-time load condition, ensuring the optimal performance under various working conditions. It is particularly worth emphasizing that the dynamic smoothing technology in the present scheme is not only the application of a simple smoothing algorithm, but also a comprehensive intelligent algorithm combined with network performance index matrix analysis, multi-factor weighting processing and prediction model construction. Through deep learning and pattern recognition of network fluctuation characteristics, the algorithm accurately predicts the future network state, and then guides the dynamic adjustment of the transmission parameters. This way of deeply integrating artificial intelligence algorithm characteristics and communication system makes the communication performance remain highly stable and predictable in complex and variable network environments, providing key technical support for high real-time requirement scenarios such as rail transit. At the same time, the combination of FPGA reconfigurability and adaptive algorithm gives the system the ability to continuously optimize, significantly improving the overall communication efficiency and reliability.

[0047] It should be noted that the main innovation in the embodiments of the present application is: lightweight protocol stack customization and single handshake mechanism, protocol improvement: for the TCP protocol, the handshake process is optimized to simplify the traditional three-way handshake to a single handshake, reducing the initial connection delay.

[0048] For UDP protocol, add simple reliability control (such as HMAC-based authentication, lightweight retransmission if necessary) at the application layer to complement its reliability defects.

[0049] Message optimization: eliminate unnecessary control fields in traditional protocols, compress header information, reduce message overhead, and provide more data load space for high-throughput transmission.

[0050] Dynamic smoothing technology: the core idea is to monitor network transmission delay in real time, and use smoothing filter algorithm (such as exponential smoothing method) to dynamically adjust sending window, cache queue and transmission rate.

[0051] Implementation: embed dynamic smoothing module in data transmission link, use real-time delay data for smoothing processing, automatically adjust sending strategy; when network has sudden delay, system can quickly reduce sending rate, and gradually speed up after delay recovery, ensuring data continuity and stability.

[0052] Application of FPGA card and hardware acceleration, protocol stack hardware implementation: realize customized lightweight TCP / UDP protocol stack (HolleyBurstIP class) on FPGA card, use hardware parallel processing to greatly reduce protocol analysis and message processing delay. Use hardware description language (such as VHDL or Verilog) to design data path, ensure that MAC layer data interface and protocol conversion module have high-speed real-time response capability.

[0053] Single handshake mechanism detailed implementation: pre-shared key and state cache: pre-distribute shared key between communication nodes, and save session state in FPGA built-in cache. Handshake message design: optimize message structure, only include necessary handshake identifier (HS_FLAG), sequence number, timestamp, authentication credentials (such as HMAC check code) and initial data load.

[0054] Handshake process: the initiator sends a single handshake message to the target node and starts a short timeout timer; the receiver detects HS_FLAG, verifies the authentication information in the message, and immediately establishes a connection state, updates the cache, and processes the initial data; the receiver sends a simplified acknowledgement message (ACK) as a subsequent fault tolerance mechanism to confirm the completion of the handshake.

[0055] Hardware acceleration support: use the parallel processing unit built-in FPGA card, cooperate with DPDK or RDMA technology, realize high-speed data packet processing and memory management. FPGA card can be dynamically reconfigured according to actual network state, realize flexible adjustment and real-time optimization.

[0056] On the basis of lightweight protocol, a dynamic key management module and lightweight encryption algorithm are embedded to ensure identity authentication and data integrity in the handshake and data transmission process, and to prevent replay attacks and man-in-the-middle attacks. A special soft protocol adapter is developed to ensure that the protocol stack can run on different operating systems (Linux, Windows, Harmony, etc.), facilitating unified deployment and interconnection in various devices.

[0057] In a specific embodiment, the process of performing step S101 can specifically include the following steps:

[0058] The traditional TCP / UDP protocol is disassembled by a protocol analyzer, and redundant control fields are removed to form a set of lightweight protocol fields;

[0059] A handshake identification field HS_FLAG is constructed according to the set of lightweight protocol fields, and the communication identity identification and session parameters are encoded into a binary sequence to obtain a compact handshake identification;

[0060] The pre-shared key and session information are hashed using the HMAC algorithm to generate a secure authentication credential;

[0061] The initial data payload is sorted according to the timestamp priority, and the key business data is embedded in the header of the handshake message to realize the advancement of data transmission;

[0062] The header information of the message is rearranged through bit field compression technology to reduce the space occupied by control information, and a compressed header structure is obtained;

[0063] The compact handshake identification, secure authentication credential, and compressed header structure are byte-aligned and encapsulated to obtain a lightweight message structure with a compressed header.

[0064] Specifically, in the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology, the construction of single handshake message is the basic link of the whole communication scheme. First, when the traditional TCP / UDP protocol is deconstructed by the protocol analyzer, the binary level analysis of the standard protocol header is needed to identify and mark the function and necessity of each control field. In actual operation, the TCP protocol analysis shows that the header contains the source port (16 bits), target port (16 bits), sequence number (32 bits), acknowledgement number (32 bits), data offset (4 bits), reserved (6 bits), flag bit (6 bits), window size (16 bits), checksum (16 bits), urgent pointer (16 bits) and option (up to 40 bytes) fields. The protocol analyzer will evaluate the function and necessity of each field, for example, in the single handshake scenario, the acknowledgement number field becomes unnecessary, and the MSS, window scaling, etc. in the option field can also be simplified, so as to eliminate these redundant control fields and form a lightweight protocol field set containing only basic connection information. When constructing the handshake identification field HS_FLAG according to the lightweight protocol field set, it is essentially to re-encode the identities of the communication parties and the core parameters required for session establishment. In the specific processing process, the communication identity identification (including the sender ID and the receiver ID, each 8 bits) and the session parameters (including the session type 4 bits, the priority 4 bits, and the timeout time 8 bits) are packaged in binary, and the bit concatenation technology is used to connect these parameters into a 32-bit binary sequence. For example, in the rail transit control system, the sender ID value is 10 (binary 00001010), the receiver ID value is 15 (binary 00001111), the session type is data transmission (0010), the priority is high (0001), and the timeout time is 100 milliseconds (01100100). These values are spliced in the predefined order to obtain the binary sequence 00001010000011110010000101100100, that is, the compact handshake identification.

[0065] The generation of the security authentication credential adopts the HMAC algorithm, which processes the session information M based on the hash function H and the pre-shared key K. The HMAC algorithm first fills the key K to the data block size of the hash function, and if the length of K exceeds the block size, the K is first hashed to obtain a fixed length value. Then the processed key is XORed with two constants ipad and opad respectively to obtain two key blocks, and then the first key block is connected with the message M for hashing, and finally the second key block is connected with the first hashing result for hashing again to obtain the final HMAC value as the security authentication credential. In the FPGA implementation, the pre-shared key is stored in the security area of the FPGA, the session information includes the handshake identification, the timestamp, the random number, etc., and the length of the authentication credential generated by the HMAC is usually 16 bytes, which ensures the security of the handshake process.

[0066] In the initial data payload processing, the timestamp priority is sorted to realize the early transmission of key data. This step first marks all the data to be transmitted, records the time sensitivity of each block of data, and then sorts the data blocks according to the time sensitivity value. The higher the time sensitivity, the higher the priority. After sorting, the key service data in the front line is directly embedded in the header of the handshake message, without waiting for the connection to be completely established before sending data, so as to realize the early transmission of data. In the specific processing, the time sensitivity is divided into multiple levels, such as emergency control instructions, regular state updates, and non-real-time data. The sorting algorithm calculates the final priority value according to the sensitivity level and the data generation time. The data block with the highest priority value will be selected and embedded in the handshake message.

[0067] Bit field compression technology is a method of efficiently encoding message header information. This technology first analyzes the value range and actual demand of each field, and then performs variable-length encoding or bit reduction on the originally fixed-length field. For example, the 32-bit sequence number field in many scenarios has a value range much smaller than 32 bits, so it can be compressed to 16 bits with a wrap-around counting mechanism. At the same time, multiple small fields are combined and encoded, such as combining multiple 1-bit flag bits into a byte, each bit representing a different flag state. For variable-length fields, prefix encoding is used to reduce space occupation in the default value case. Through these technical means, the message header is compressed from the original 20-60 bytes to about 10-20 bytes, resulting in a more compact compressed header structure.

[0068] Aligning and packaging the compact handshake identifier, security authentication credentials, and compressed header structure is a key step to get the final lightweight message structure. Byte alignment processing ensures the access efficiency of each part of the data in memory and transmission, usually with 8 bits (1 byte) as the basic unit for boundary alignment. In the packaging integration process, each data part will be arranged in a predefined order. First, the compressed header structure (including basic protocol information), then the compact handshake identifier (HS_FLAG), then the security authentication credentials (HMAC value), and finally the initial data payload. Length indicators or separators may be added between each part to allow the receiving side to correctly parse each field. The final lightweight message structure has low overhead and security, and is particularly suitable for high-speed implementation in FPGA environment.

[0069] For example, in the emergency linkage scenario of the rail transit station-level system, a certain control node needs to send an emergency stop instruction to an execution node. Through the traditional TCP protocol, it needs to first complete the three-way handshake to establish a connection (about 150 ms), and then send the control instruction (about 50 ms), totaling about 200 ms. Using the single handshake message of the present scheme, the whole process is as follows: after the protocol analyzer analyzes the TCP protocol, it eliminates the acknowledgement number, redundant options and other fields, and retains the necessary fields such as the source port, target port, sequence number, etc., to form a lightweight protocol field set; the node constructs a handshake identifier HS_FLAG, encodes the control node ID (0x01), the execution node ID (0x05), the emergency session type (0x01) and other information into a binary sequence; based on the pre-shared key "TrainCtrl_Key" between nodes, the HMAC-SHA256 algorithm is used to calculate the 16-byte authentication credentials of the handshake identifier and the current timestamp; the "emergency stop instruction" is directly embedded as the initial data payload in the handshake message; through bit field compression, the connection-related control information is compressed to 16 bytes; finally, the above parts are aligned according to the 8-byte boundary and integrated and packaged to obtain a lightweight message structure with a total length of only about 40 bytes. After the FPGA high-speed processing of the message, the whole process from connection establishment to instruction transmission can be completed in about 20 ms, greatly improving the system response speed.

[0070] The handshake identifier field HS_FLAG also includes:

[0071] A multi-level session priority mapping table is established, a priority decision tree is constructed according to the business type and the emergency degree, and a dynamic priority code is allocated to different session types; through the priority preemption mechanism, when a high-priority session request is detected, the priority promotion algorithm is triggered to real-time re-encode the priority field in HS_FLAG; the cyclic redundancy check CRC algorithm is used to verify the integrity of HS_FLAG, an 8-bit check code is appended at the end of HS_FLAG, and the receiver verifies the check code to ensure that the handshake identifier has not been tampered with in the transmission process.

[0072] Specifically, the multi-level session priority mapping table divides the service type into four main categories of emergency braking, safety linkage, state monitoring and data transmission, and each category is divided into three sub-levels, forming 12 priority combinations. The priority decision tree automatically matches the optimal priority code according to the real-time service characteristics, for example, in the rail transit scene, the priority code of emergency braking service is 1111 (highest), the priority code of regular state monitoring is 0100 (medium), and the priority code of non-real-time data transmission is 0001 (lowest). When the system detects an emergency braking signal, the priority promotion algorithm immediately promotes the HS_FLAG priority field of the current session from the original value to 1111, and triggers the fast retransmission mechanism. The CRC check uses the CRC-8 polynomial to calculate, and the first 24 bits of HS_FLAG are checked to generate an 8-bit check code attached to the end. The receiver uses the same algorithm to verify, if the verification fails, the packet is discarded and retransmission is requested, ensuring the integrity and reliability of the handshake identifier. In actual application, when the emergency evacuation linkage of a fire alarm system is triggered, the regular session with the original priority code of 0110 is immediately adjusted to 1110 by the priority promotion algorithm, and the HS_FLAG is expanded from the original 32 bits to 40 bits (8 bits of CRC check are added), the entire priority re-encoding and verification process on the FPGA only takes less than 50 nanoseconds, ensuring the absolute priority processing right of emergency services.

[0073] In a specific embodiment, the process of performing step S102 can specifically include the following steps:

[0074] The transmission and reception times of the network data packet are calculated by the timestamp difference calculation method to obtain an original delay sampling sequence;

[0075] Based on the original delay sampling sequence, a time sequence correlation matrix is constructed using a sliding window technique to extract delay fluctuation characteristics;

[0076] A multi-factor weighted exponential smoothing algorithm is used to smooth the delay fluctuation characteristics to generate a network state prediction curve;

[0077] According to the network state prediction curve, a transmission window size adjustment coefficient and a rate change gradient are calculated to form a dynamic adjustment vector;

[0078] The network burst delay is identified by a mutation detection threshold to trigger a fast response mechanism to generate an emergency control instruction;

[0079] The dynamic adjustment vector and the emergency control instruction are combined and processed according to priority to obtain a set of adaptive transmission parameters.

[0080] Specifically, in the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology, the key to obtaining the adaptive transmission parameter set lies in the accurate perception and prediction of network state. First, the difference between the transmission and reception times of network data packets is calculated by the timestamp difference calculation method to obtain the original delay sampling sequence, which is the basis for network monitoring. In specific implementation, the sending timestamp T_send is recorded in the FPGA before the data packet is sent, and the receiving timestamp T_recv is recorded when the corresponding acknowledgement packet is received. The difference between the two is the single round-trip time (RTT). To avoid clock synchronization problems, the sender can embed the timestamp in the data packet, and the receiver can immediately return it after receiving it. The sender calculates the RTT based on this to form a series of delay values at different time points, which is the original delay sampling sequence.

[0081] Based on the obtained original delay sampling sequence, the processing step of constructing the time sequence correlation matrix using the sliding window technique is very critical. The sliding window technique refers to selecting a fixed length W of consecutive sampling points as an observation window, and as new samples arrive, the window continuously slides forward. At each window position, the mean, variance, and trend slope of the delay values in the window are calculated and recorded in the corresponding position of the matrix. The time sequence correlation matrix contains the statistical characteristics of multiple time windows, with each row representing a time window and each column representing a statistical characteristic. By analyzing the change patterns of these characteristics, the delay fluctuation characteristics such as periodic changes, sudden changes, and trend changes are extracted. The core of the dynamic smoothing technique is to use a multi-factor weighted exponential smoothing algorithm to smooth the delay fluctuation characteristics. This algorithm takes into account multiple influencing factors (factors) and assigns different weights to historical data, with more recent data having a larger weight, thereby generating a smoothed prediction trend. Unlike simple exponential smoothing, multi-factor weighted exponential smoothing considers multiple network indicators such as delay, packet loss rate, and jitter, each with a corresponding smoothing factor. The algorithm first performs exponential smoothing on each indicator separately, and then combines the smoothed results according to the importance of the indicators. In specific calculations, the prediction value of a certain indicator at time t is obtained by combining the actual value and the prediction value at time t-1 according to the weight, and the weight coefficient is dynamically adjusted according to the historical prediction accuracy. The final generated network state prediction curve can accurately reflect the future short-term network state change trend.

[0082] The calculation of the transmission window size adjustment coefficient and the rate change gradient according to the network state prediction curve is a key step in regulating network transmission behavior. The window size adjustment coefficient determines the amount of data that can be sent at one time, while the rate change gradient determines how the window size changes over time. The calculation process first determines the basic window size, and then sets the adjustment coefficient according to the predicted network state curve slope and volatility. When the network state is predicted to be good, the adjustment coefficient is greater than 1, and the window gradually expands; when the network state is predicted to be bad, the adjustment coefficient is less than 1, and the window shrinks. The rate change gradient controls the speed of window adjustment, usually adopting a slow growth strategy when the network state improves, and a rapid reduction strategy when the network state deteriorates. Such asymmetric adjustment strategy forms a dynamic adjustment vector.

[0083] The process of identifying network burst delay through mutation detection threshold is an important mechanism to deal with network mutations. Mutation detection is based on the principle of statistical outlier detection, and sets multiple threshold values to monitor the change of delay value. When the monitored real-time delay value exceeds the preset threshold value, a rapid response mechanism is triggered. The rapid response mechanism includes strategies such as immediately reducing the transmission window, suspending non-critical data transmission, starting backup routing, and generating corresponding emergency control instructions. The threshold setting is usually based on the mean value plus multiple standard deviations of historical delay statistics, and multiple threshold values correspond to different severity of network anomalies, triggering different levels of emergency response.

[0084] The priority merging of dynamic adjustment vector and emergency control instruction is a key link to form the final adaptive transmission parameter set. The merging process first compares the priority of the two, and the emergency control instruction usually has a higher priority, which will override the parameters of the regular dynamic adjustment vector in the case of network mutation. When the network state returns to normal, the emergency control instruction is invalid, and the system reverts to the dynamic adjustment vector as the dominant control parameter. The merged adaptive transmission parameter set includes window size, sending rate, retransmission timeout, congestion control parameters, and other settings, which directly affect the running state of the protocol processing unit on the FPGA, ensuring efficient and stable data transmission under various network conditions.

[0085] For example, in the rail transit station-level system, the communication between the control center and the field device is realized by the intelligent body high-speed bus based on FPGA and dynamic smoothing technology. The initial network delay is monitored and displayed in real time, and the delay is stable between 5-8 milliseconds. The original delay sampling sequence is [5.2, 6.1, 5.8, 7.2, 6.5, 5.9] milliseconds. The sliding window technology (window length is 4) is applied to analyze these data, and the statistical feature matrix is obtained. The mean of the first window [5.2, 6.1, 5.8, 7.2] is 6.08 milliseconds, the variance is 0.73, and the trend slope is 0.6; the mean of the second window [6.1, 5.8, 7.2, 6.5] is 6.4 milliseconds, the variance is 0.41, and the trend slope is 0.13. The time correlation matrix is formed in this way. The multi-factor weighted exponential smoothing algorithm is used to process these features, the current delay factor weight is set to 0.7, the historical trend factor weight is set to 0.3, and the next time delay is predicted to be about 6.2 milliseconds. Based on this prediction, the transmission window adjustment coefficient is calculated to be 1.05 (slightly increased), and the rate change gradient is calculated to be 0.02 (slowly increased), forming a dynamic adjustment vector. At this time, the network suddenly appears a delay of 25 milliseconds, which exceeds the preset 15-millisecond mutation threshold, triggering the fast response mechanism immediately, generating emergency control instructions, changing the window adjustment coefficient to 0.5 (significantly reduced), and changing the rate change gradient to-0.1 (rapidly reduced). After priority merging processing, the emergency control instruction covers the regular adjustment vector, and the final adaptive transmission parameter set adopts the emergency parameter, so that the protocol processing unit on the FPGA quickly adjusts the working state, avoids network congestion, and gradually restores the transmission parameters when the network returns to normal, ensuring smooth and stable communication.

[0086] The multi-factor weighted exponential smoothing algorithm is used to smooth the delay fluctuation characteristics, which also includes:

[0087] An adaptive weight adjustment mechanism is constructed to dynamically correct the weight coefficients of each factor according to the prediction error. The prediction accuracy index is calculated by comparing the deviation between the predicted value and the actual measured value through the feedback correction algorithm. When the prediction error exceeds the preset tolerance threshold, the weight reconstruction process is started, and the gradient descent method is used to iteratively optimize the weights of the delay factor, the packet loss rate factor, and the jitter degree factor. A weight update history table is established to track the optimal weight combination under different network conditions, forming a weight knowledge base. Based on the weight knowledge base, a pattern matching algorithm is used to quickly identify the current network state type, and the corresponding optimal weight configuration is directly called to realize fast convergence of the weight.

[0088] Specifically, the adaptive weight adjustment mechanism evaluates the error in a sliding time window unit, each time window contains ten consecutive prediction periods. The prediction accuracy indicator is derived by calculating the mean absolute percentage error of the actual value and the predicted value, and the weight reconstruction is triggered when the error exceeds the tolerance threshold of fifteen percent. Gradient descent method with a learning step of one thousandth is used for iteration to update the delay factor weight, packet loss rate factor weight and jitter degree factor weight. The update process gradually adjusts the weight value according to the gradient direction of the prediction error function, and the upper limit of the iteration number is set to fifty times or the error converges to less than five percent. The weight knowledge base uses hash table structure to store, taking the network state feature vector including average delay interval, packet loss rate level, jitter amplitude level as the index key, and the corresponding weight combination as the value. The current has accumulated two hundred groups of typical scene weight configuration. In practical application, the network load of a rail transit system increases sharply during the morning peak period, and the initial weight configuration leads to a prediction error of twenty percent. The adaptive mechanism is immediately started, and after fifteen iterations, the delay factor weight is adjusted from 0.7 to 0.85, the packet loss rate factor weight is adjusted from 0.2 to 0.1, and the jitter degree factor weight remains unchanged from 0.1. The adjusted prediction error is reduced to eight percent, and the weight configuration is recorded in the knowledge base and marked as the peak period mode. When similar network conditions are encountered in the future, the system directly calls the weight combination, and the response time is shortened from three hundred milliseconds required by fifteen iterations to five milliseconds required by pattern matching, significantly improving the real-time adaptability of the dynamic smoothing algorithm.

[0089] In a specific embodiment, the process of performing step S103 can specifically include the following steps:

[0090] According to the lightweight message structure definition, the internal data path specification of the FPGA is defined, the hardware circuit schematic diagram is drawn, and the protocol processing circuit blueprint is formed;

[0091] The protocol processing circuit blueprint is converted into a register transfer level description through VHDL language, and a message parsing state machine is constructed;

[0092] According to the adaptive transmission parameter set, a dynamic parameter register group is designed to realize a real-time parameter updating mechanism;

[0093] The message parsing state machine is divided into four pipeline stages of message receiving, header parsing, payload processing and message encapsulation to generate parallel execution units;

[0094] The key path in the parallel execution unit is optimized through lookup table technology to construct a high-speed data path that meets timing constraints;

[0095] Based on the high-speed data path, a DMA transmission controller and a cache manager are designed to obtain a hardware accelerated protocol stack.

[0096] Specifically, in the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology, the implementation of the hardware acceleration protocol stack is the key to the high performance of the entire system. First, according to the lightweight message structure, the data path specification of FPGA is defined, which requires detailed analysis of the message structure to determine the bit width of each field and processing requirements. Specifically, the data path specification definition includes bit width definition, timing requirements, and interface definition. Bit width definition determines the width of the data bus, which is usually determined according to the maximum field width or processing unit alignment requirements. For example, for a 32-bit FPGA architecture, the data path selects 32-bit width or its integer multiple. Timing requirements define clock domains, delay constraints, handshaking mechanisms, etc., to ensure correct data transmission between modules. Interface definition covers control signals, data valid signals, handshake signals, etc. These specifications are drawn into a circuit diagram through hardware description, including receiving buffer, parsing engine, processing unit, sending buffer, and their interconnection, to finally form a protocol processing circuit blueprint. Converting the protocol processing circuit blueprint into a register transfer level description through VHDL language is a key step from conceptual design to actual circuit. VHDL (VHSIC Hardware Description Language) is a hardware description language that allows hardware behavior and structure to be described through code. Register transfer level (RTL) description refers to expressing circuit behavior as inter-register data transfer operations, which is a detailed design before actual synthesis into a circuit. In this process, first, each functional module in the circuit blueprint is written in VHDL entity and architecture, defining input and output ports and internal logic. Then, a message parsing state machine is written, which is the core of protocol processing, responsible for controlling the message parsing process. A typical message parsing state machine includes IDLE (idle), HEADER_DETECT (header detection), PARSE_HEADER (header parsing), PROCESS_PAYLOAD (payload processing), GENERATE_RESPONSE (response generation), etc. The transition between states is triggered by message features and processing results.

[0097] Designing dynamic parameter register set according to adaptive transmission parameter set is the key mechanism to realize network adaptability. Adaptive transmission parameter set contains window size adjustment coefficient, rate change gradient and other parameters generated in the previous steps, and needs to establish corresponding storage structure in FPGA. Dynamic parameter register set adopts double buffering structure, one set of registers is used for current operation, and the other set is used for updating, which avoids data confusion in parameter updating process. Parameter updating adopts interrupt driven mechanism, when the software side calculates new adaptive parameters, it notifies FPGA through interrupt signal to trigger parameter loading process. After parameter loading is completed, the active register set pointer is switched to make the new parameters take effect immediately. At the same time, parameter validity checking logic is added to prevent system abnormality caused by error parameters.

[0098] Dividing the packet parsing state machine into four pipeline stages of packet receiving, header parsing, payload processing and packet encapsulation is an important means to improve processing parallelism. Pipeline technology allows multiple processing stages to work simultaneously and process different data parts. The packet receiving stage receives raw data stream from the physical layer, performs data frame boundary identification and verification; the header parsing stage identifies and extracts each field information in the packet header, such as handshake identifier, authentication credentials, etc.; the payload processing stage processes the actual data content in the packet, including decryption, verification and other operations; the packet encapsulation stage constructs the response packet according to the processing result. The four stages are connected through FIFO buffer and work independently to form parallel execution units. In actual implementation, each stage is designed as an independent state machine with its own control logic and data path, but shares global control signals and clock. Optimizing the critical path in parallel execution unit through look-up table technology is an important method to meet timing constraints. The critical path is the longest path in the circuit, which determines the maximum working frequency. Look-up table (LUT) technology is to precompute the results of complex calculations and store them in a table, and directly look up the table to get the results during execution, avoiding the delay caused by real-time calculation. In FPGA architecture, LUT is the basic logic unit, and specific logic functions are realized by configuring LUT content. For key operations in packet processing such as CRC check, hash calculation, etc., look-up table method is used instead of bit-by-bit calculation, which significantly reduces the calculation delay. The critical path optimization process first identifies the critical path through timing analysis tools, then focuses on applying look-up table optimization to these paths, and finally verifies whether the optimized timing meets the constraint requirements. The optimized data path can work stably at a higher frequency, providing higher data processing throughput.

[0099] Based on high-speed data path, the design of DMA transmission controller and cache manager is the key to form a hardware acceleration protocol stack. DMA (Direct Memory Access) transmission controller allows FPGA to directly access system memory without CPU intervention, greatly improving data transmission efficiency. DMA controller design includes address generator, transmission counter, and state controller, which receives transmission instructions through the host interface and autonomously completes data transfer between memory and FPGA. The cache manager is responsible for the caching and scheduling of FPGA internal data, using a multi-level cache structure. The first level cache uses high-speed Block RAM to provide low-latency access, and the second level cache uses off-chip DDR memory to provide large-capacity storage. The cache management strategy is based on data access patterns and priority design, with priority caching for critical control data and high-frequency access data. The DMA controller and cache manager work together to form a complete data path, enabling efficient protocol processing on FPGA, and ultimately obtaining a hardware acceleration protocol stack with excellent performance.

[0100] Taking the rail transit station-level control system as an example, the implementation process of the agent high-speed bus implementation method based on FPGA and dynamic smoothing technology is demonstrated. A station-level control system needs to process real-time data from 100 sensors and send control instructions to 50 execution devices, with an end-to-end delay of no more than 10 milliseconds. First, a 64-bit wide data path is defined based on the lightweight message structure to meet the maximum field width and processing efficiency requirements. Then, the protocol processing module is written in VHDL language, and the message parsing state machine contains 5 main states and 12 sub-states, responsible for parsing lightweight messages. Next, a double-buffered parameter register group is designed, containing 32 32-bit registers, storing adaptive parameters obtained from the dynamic smoothing module. The entire processing flow is divided into four stages of pipeline, each running independently in a 150MHz clock domain. For computationally intensive CRC checksum and HMAC verification, a 16KB lookup table is used instead of bit-by-bit calculation, reducing the critical path delay from 35ns to 8ns. Finally, a DMA controller supporting 4KB burst transmission and a three-level cache system with a total capacity of 512KB are implemented to form a complete hardware acceleration protocol stack. This scheme achieves a throughput of 100,000 messages per second with a resource occupancy rate of no more than 45%, and an end-to-end delay of less than 3 milliseconds, fully meeting the real-time requirements of the system.

[0101] In a specific embodiment, the process of performing step S104 can specifically include the following steps:

[0102] Based on the communication session identifier and the time seed, a key derivation function KDF is constructed to generate a session initial key;

[0103] The hardware counter is used to accumulate the data transmission amount, a key update threshold is set, and a time-driven trigger condition is formed;

[0104] When the time-driven trigger condition is met, a new key material is generated by the key derivation function KDF, and the key rotation is completed;

[0105] The counter initial value in the improved AES-GCM mode is randomized to generate an unpredictable encryption packet sequence;

[0106] For the data packets transmitted by the hardware acceleration protocol stack, the pipeline method is used for packet encryption and authentication tag calculation to generate an encrypted data stream;

[0107] The encrypted data stream is associated with the key version number and packaged to form a verifiable secure communication data packet, and a secure communication guarantee mechanism is obtained.

[0108] Specifically, in the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology, the secure communication guarantee mechanism is a key component to ensure the security and integrity of data transmission. To implement this mechanism, a key derivation function KDF needs to be constructed based on the communication session identifier and the time seed, which is used to generate the initial session key. The key derivation function KDF is an algorithm that generates a specific purpose key from a master key material. In this scheme, KDF receives two key inputs: communication session identifier and time seed. The communication session identifier is a unique identifier generated by combining the device ID, session type and session establishment time of the communication parties, ensuring the uniqueness of each session. The time seed is the current value taken from the high-precision counter inside the FPGA, ensuring that even if the same device establishes multiple sessions, the generated keys are different each time. The specific processing flow of KDF is to concatenate the session identifier and the time seed, and then iterate through multiple rounds of hash functions (such as SHA-256), and finally truncate the required length of the key material as the initial session key. After generating the initial key, a key update mechanism needs to be established to ensure the security of long-term communication sessions. The accumulation of data transmission amount by the hardware counter is the basis for implementing this mechanism. The hardware counter integrated inside the FPGA is specifically used to track the amount of data transmitted in the current session. Every time a data packet is successfully transmitted, the counter value increases by the byte size of the data packet. At the same time, a key update threshold is set, which is usually determined based on security policies, such as when the amount of transmitted data reaches a certain number of bytes (such as 1GB) or the duration of the session reaches a certain length of time (such as 8 hours). These thresholds, together with the current value of the counter, form the time-driven trigger condition. When the counter value exceeds the pre-set threshold, the key update process is triggered.

[0109] When the time-driven trigger condition is met, new key material is generated by a key derivation function KDF, completing the key rotation. The key rotation process first suspends the current data transmission, saves the session state, then generates a new round of session key through the KDF by taking the current session identifier, new time seed (current counter value) and last round key as input. The key lies in the introduction of a new time seed each time the rotation is performed, ensuring the unpredictability of the key material. After the new key is generated, the key version number is incremented, the key material in the FPGA internal secure storage area is updated, and the communication partner is notified to synchronize the key update. After both parties complete the key synchronization, the statistical counter is reset and data transmission is resumed.

[0110] Randomizing the counter initial value in the improved AES-GCM mode is an important means to enhance encryption security. AES-GCM (Advanced Encryption Standard-Galois Counter Mode) is an encryption mode that provides confidentiality and integrity at the same time. The traditional GCM mode uses a fixed initial vector (IV) and a sequentially incremented counter value, while the improved version introduces a counter initial value randomization mechanism. The specific process is to obtain random numbers from the FPGA built-in true random number generator (TRNG) or high-quality pseudo-random number generator (PRNG), mix them with the session identifier and the current timestamp, and then process them into a fixed length value through a hash function to serve as the counter initial value. This randomization process ensures that even if the same key is used to encrypt the same plaintext, the generated ciphertext is completely different each time, effectively resisting statistical analysis attacks.

[0111] For the data packets transmitted by the hardware-accelerated protocol stack, a pipeline method is used for packet encryption and authentication tag calculation to generate an encrypted data stream. Data processing first groups the original data, with each group usually being 128 bits (16 bytes) to match the size of the AES encryption block. The pipeline encryption process includes multiple parallel processing stages: the first stage generates a counter, calculating a unique counter value for each data block; the second stage performs AES encryption to encrypt the counter value into a key stream; the third stage combines the key stream and the plaintext data block through an XOR operation to generate ciphertext; and the fourth stage calculates authentication data in parallel to generate an authentication tag for verifying data integrity. The parallel computing capability of the FPGA enables these stages to process different data blocks simultaneously, greatly improving throughput. After all data blocks are processed, the ciphertext data blocks are connected into a continuous data stream, with the authentication tag attached to form an encrypted data stream. The final step is to associate and package the encrypted data stream with the key version number to form a verifiable secure communication data packet. This step first adds a key version number field to the encrypted data stream, which is usually 2-4 bytes, identifying the current key version for the receiving party to select the correct key for decryption. At the same time, session identifiers, timestamps, sequence numbers, and other auxiliary information are added to form a complete secure communication data packet header. The data packet tail adds a checksum or authentication tag for the receiving party to verify data integrity. The final secure communication data packet contains both encrypted business data and necessary security verification information, achieving security protection in high-speed communication.

[0112] For example, in the rail transit emergency braking system, the control center needs to send an emergency braking command to the train while ensuring communication safety and real-time performance. The security mechanism implementation process of the intelligent body high-speed bus implementation method based on FPGA and dynamic smoothing technology is as follows: when the train and the control center establish a communication session, the system first generates a session identifier "Train001_Control_Emergency", combines the current FPGA counter time value "1678952341" as the time seed, and generates a 256-bit initial session key through the KDF function. Subsequently, the system starts the hardware counter to record the data transmission volume and sets the key update threshold to 500 MB or 4 hours of communication time. As the communication proceeds, the hardware counter continuously accumulates the amount of data transmitted. When an emergency occurs, the control center needs to send a braking command, the system checks the time-driven condition, if the counter shows that the amount of data transmitted is 480 MB, which does not reach the update threshold, the current key is continued to be used; if it has reached 600 MB, which exceeds the threshold, the key rotation is triggered immediately, and a new key is generated through the KDF using a new time seed and the current session identifier. The braking command data is encrypted using the improved AES-GCM mode, and the FPGA obtains the value "0xA7F9E32D" from the built-in random source as the initial value of the counter to ensure that the encryption process is unpredictable. The 16-byte braking command data is processed in parallel through a four-stage pipeline: counter generation, AES encryption, XOR mixing, and authentication tag calculation, which is completed in less than 100 microseconds on the FPGA. Finally, the encrypted braking command data, the current key version number "5", the authentication tag, and the necessary session information are packaged to form a secure communication data packet with a total length of about 64 bytes, which is sent to the train control system through the high-speed bus to achieve safe and real-time emergency braking control.

[0113] In a specific embodiment, the process of performing step S105 can specifically include the following steps:

[0114] An interface mapping table is designed according to the communication interface characteristics of different subsystems, and a physical interface conversion layer supporting the Ethernet and PCIe interface standards is constructed;

[0115] The signals between the physical interface conversion layer and the hardware acceleration protocol stack are mapped and converted through an interface description language to form a unified interface standard;

[0116] Based on the unified interface standard, the external protocol packet and the lightweight message structure are format-converted to establish a protocol adaptation layer;

[0117] A security communication guarantee mechanism is embedded in the protocol adaptation layer to securely encapsulate and decapsulate data streams and generate a secure channel;

[0118] A session management layer is constructed by using a distributed state synchronization algorithm to maintain the session state information between subsystems.

[0119] The physical interface conversion layer, the protocol adaptation layer and the session management layer are vertically integrated, various functional modules are connected through an interconnection bus, and a subsystem access architecture is formed.

[0120] Specifically, in the intelligent agent high-speed bus implementation method based on the FPGA and the dynamic smoothing technology, the subsystem access architecture is a key link for realizing the interconnection and intercommunication of different devices. First, for the communication interface characteristics of different subsystems, designing an interface mapping table is basic work for constructing the physical interface conversion layer. The interface mapping table is essentially a structured database, which records the signal characteristics and conversion rules of various physical interfaces. In the specific implementation process, the interface mapping table includes three main parts: interface characteristic description, signal mapping rule and timing parameter. The interface characteristic description records basic information such as interface type, pin definition and electrical characteristics; the signal mapping rule defines the corresponding relationship between different interface signals; and the timing parameter specifies the timing requirements of signal conversion. The Ethernet interface part records the MAC address filtering rule, the frame structure analysis method, the register mapping relationship of the Ethernet controller and the like; and the PCIe interface part contains the transaction layer protocol processing, the base register configuration, the interrupt mapping mechanism and the like. Based on this information, the physical interface conversion circuit is realized on the FPGA, including the clock domain conversion module, the data alignment buffer, the trigger signal generator and the like functional units, forming the physical interface conversion layer supporting the Ethernet and PCIe interface standards.

[0121] Next, the signals between the physical interface conversion layer and the hardware acceleration protocol stack are mapped and converted through the interface description language, forming a unified interface standard. The interface description language (IDL) is a formal language specially used for describing interface specifications, which is mainly used to establish the communication contract between different modules in the present scheme. The IDL description includes data structure definition, interface function declaration, error handling mechanism and the like. First, a unified data packet structure is defined, which specifies that the data transmitted between all internal modules must conform to the structure; then a control signal set is defined, including request signals, confirmation signals, state indication signals and the like; and finally, timing rules are defined, which explicitly specify the valid time and response time of each signal. The IDL compiler converts these descriptions into hardware description language code, automatically generating a signal conversion module, which processes the original signals input by the physical interface and converts them into internal signals conforming to the unified interface standard, and vice versa. This standardized processing ensures that the data of different physical interfaces is processed in a unified format inside the FPGA, simplifying the design complexity of subsequent modules.

[0122] Based on the unified interface standard, the format conversion between external protocol packets and lightweight packet structure is the core work of establishing the protocol adaptation layer. The protocol adaptation layer mainly solves the interoperability problem between different protocols, and the process is divided into four steps: protocol identification, packet analysis, format conversion, and packet reconstruction. Protocol identification first identifies the protocol type of the input data by checking the packet characteristic field; packet analysis extracts the field information of the packet according to the identified protocol type, including the packet header, control information, and payload data; format conversion reorganizes the extracted field information according to the requirements of the lightweight packet structure, such as compressing the TCP / IP complex header into a simplified header in the lightweight packet; and packet reconstruction generates a complete packet according to the target format requirements. The entire processing process establishes the protocol adaptation layer, which can automatically identify multiple input protocols and seamlessly convert them into the internal unified lightweight packet format, realizing the interoperability at the protocol level.

[0123] Embedding the secure communication guarantee mechanism into the protocol adaptation layer and performing secure encapsulation and decapsulation on the data stream is the key to generating a secure channel. The secure encapsulation process first obtains the current valid session key and security parameters, then performs encryption on the original data, and finally adds an authentication tag to generate a secure data packet. In specific processing, the original data is first grouped, and each group is divided according to the block size required by the encryption algorithm; then each data block is sent into the encryption engine along with the key and counter value for processing; finally, the authentication tag is calculated and attached to the encrypted data. The decapsulation process is the opposite, first verifying the authentication tag to confirm data integrity, then decrypting the data to recover the original content, and finally checking the security control field to confirm the authorization legality. This design embeds security processing into the protocol conversion process, avoiding additional data duplication and processing delay, forming an efficient secure channel.

[0124] Maintaining session state information between subsystems using a distributed state synchronization algorithm is the basis for building the session management layer. The distributed state synchronization algorithm is based on a consensus mechanism to ensure the consistency of state information between multiple nodes. The algorithm includes three main links: state detection, change broadcast, and conflict resolution. State detection continuously monitors local session state, including connection status, session parameters, authentication information, etc.; once a state change is detected, change broadcast is triggered to send new state information to all related nodes; when receiving state updates from other nodes, conflict resolution strategy is executed to determine the final state according to timestamp, priority, and other rules. This mechanism ensures that each subsystem maintains a consistent session view even in a distributed environment, supporting seamless switching and fault tolerance in complex scenarios. The session management layer is thus built, responsible for managing the life cycle of all active sessions, performing session establishment, maintenance, termination, and other operations.

[0125] The physical interface conversion layer, the protocol adaptation layer and the session management layer are vertically integrated, various functional modules are connected through an interconnection bus to form a complete subsystem access architecture. The vertical integration adopts a hierarchical design method, each layer is responsible for a specific function, and the layers communicate through standardized interfaces. The interconnection bus is a common channel for data exchange between layers, adopts a time-division multiplexing mechanism, and supports concurrent access of multiple functional modules. The bus arbiter is responsible for scheduling access requests to ensure timely response to high-priority operations. At the same time, a unified control plane is established to be responsible for configuration management, state monitoring and fault handling to ensure the coordinated work of various layers. This vertically integrated architecture has good modular characteristics, ensuring the integrity of the functions and providing flexible scalability, and finally forming a subsystem access architecture supporting multiple device access.

[0126] Taking a rail transit station-level system as an example, the system needs to integrate a fire alarm system (FAS), an environmental control system (ECS) and a security monitoring system (SMS) and other multiple subsystems. The implementation process of the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology is as follows: first, for the RS485 interface of the FAS, the Ethernet interface of the ECS and the PCIe interface of the SMS, an interface mapping table is designed, which records the 9600 baud rate-8 data bit-1 stop bit configuration parameters of RS485, the MAC frame analysis rules of Ethernet and the base register mapping relationship of PCIe and other information in detail, and accordingly the physical interface conversion circuit is implemented on the FPGA. Then the IDL is used to describe the characteristics of each interface signal, such as defining the differential signal of RS485 as {RS485_A, RS485_B, DataValid, Direction}, and finally generating the interface conversion code to realize the mapping and conversion of the physical signal to the internal unified bus signal. Then the protocol adaptation layer converts the messages of different systems, such as converting the Modbus protocol message of the FAS into an internal lightweight format, extracting the key fire alarm information field and reorganizing it. In the embedding process of the security mechanism, AES-128 encryption is applied to the FAS fire alarm information and an HMAC authentication tag is attached to form a secure communication channel. In order to maintain the system state, the distributed state algorithm continuously synchronizes the session information of each subsystem, such as when the FAS alarm session state changes to "emergency", it is immediately broadcast to the ECS and SMS to trigger the linkage response. Finally, the three-layer architecture is vertically integrated through the AXI interconnection bus, realizes the rapid transmission of fire alarm information from the FAS to other subsystems in emergency, completes the whole process from detection to response, the overall end-to-end delay is controlled within 5 milliseconds, and the real-time transmission of critical safety information is ensured.

[0127] In a specific embodiment, the process of performing step S106 can specifically include the following steps:

[0128] The performance monitoring probe acquisition subsystem accesses the throughput, latency fluctuation, and resource occupancy data of the architecture to form a system performance index set;

[0129] Based on the system performance index set, the weighted coefficients and time window size of the dynamic smoothing algorithm are calculated to construct a smoothing parameter optimization matrix;

[0130] According to the communication traffic pattern analysis, the cache allocation strategy is adjusted hierarchically to generate a cache configuration scheme;

[0131] The combination effect of the smoothing parameter optimization matrix and the cache configuration scheme is evaluated using a regression analysis method, and the optimal parameter combination is selected;

[0132] According to the optimal parameter combination, the FPGA internal logic units are dynamically reconfigured to generate a resource allocation graph;

[0133] The resource allocation graph is deployed to the FPGA card to rebuild the data path and processing pipeline, and a high-performance bus communication system is obtained.

[0134] Specifically, in the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology, performance optimization and dynamic adjustment are the key links to ensure efficient operation of the system. The first step to achieve dynamic optimization is to access the performance data of the architecture through the performance monitoring probe acquisition subsystem. The performance monitoring probe is an embedded monitoring device placed at the key nodes inside the FPGA, responsible for collecting performance indicators at runtime. Specifically, the probe collects three types of core data: throughput data includes the number of data packets processed per second, the number of bytes transmitted per second, queue occupancy, etc.; latency fluctuation data includes end-to-end delay, processing delay, queue waiting time, and its standard deviation, etc.; resource occupancy data includes the utilization rate of each functional module in the FPGA, cache hit rate, bus bandwidth occupancy, etc. The acquisition process uses a non-intrusive design, and the probe works in a sampling manner without interfering with the normal data flow. These raw data are preliminarily processed, including outlier filtering, data standardization, and time alignment, to finally form a structured system performance index set, providing a data basis for subsequent analysis.

[0135] The calculation of the key parameters of the dynamic smoothing algorithm based on the system performance index set is the core step of the tuning process. The two key parameters of the dynamic smoothing algorithm are the weighting coefficient and the time window size. The weighting coefficient determines the weight proportion of historical data and current data in the prediction calculation, directly affecting the sensitivity of the smoothing effect; the time window size determines the amount of historical data involved in the calculation, affecting the stability and response speed of the prediction. The calculation process first performs time series analysis on the time delay data in the performance index set, identifies periodic fluctuations, random fluctuations, and trend changes, etc. characteristics; then according to different types of fluctuation characteristics, establish parameter mapping relationship, for example, for high-frequency random fluctuations, set a small weighting coefficient and a large time window, and for obvious trend changes, set a large weighting coefficient and a small time window. In this way, the most suitable parameter combination is calculated for different network conditions, and is arranged according to different network state types to form a smoothing parameter optimization matrix, which contains the optimal parameter settings under various network conditions, providing a decision basis for dynamic adjustment. According to the communication traffic mode analysis, the hierarchical adjustment of the cache allocation strategy is an important step in the optimization of memory resources. The communication traffic mode analysis first extracts the traffic characteristics from the performance index set, including data flow size distribution, burstiness, periodicity, etc. attributes, and then matches these characteristics with pre-defined traffic mode templates to identify the current traffic mode. The cache allocation strategy needs to be adjusted accordingly for different traffic modes. For example, for bursty large traffic mode, increase the receive buffer capacity to absorb bursty data; for multiple small traffic concurrent mode, increase the cache partition number to improve parallel processing capability; for delay-sensitive traffic, prioritize low-latency access to critical path cache. This hierarchical adjustment mechanism dynamically allocates the limited cache resources within the FPGA to the most needed location according to the actual demand, forming an optimal cache configuration scheme for the current traffic characteristics.

[0136] The combination effect of the smoothing parameter optimization matrix and the cache configuration scheme is evaluated by using a regression analysis method, which is a scientific way to select the optimal parameters. Regression analysis is a method of predicting and evaluating system performance under different parameter combinations by establishing a functional relationship between the dependent variable and the independent variable. In this scheme, the dependent variable is the key performance indicators of the system, such as total delay, throughput, etc., and the independent variable is the smoothing parameter and the cache configuration parameter. In specific implementation, firstly, the corresponding relationship between the parameter combination and the performance indicator is extracted from the historical running data to establish the initial training set; then a prediction model is established using a multiple regression algorithm, which can predict system performance according to a given parameter combination; then the model is used to predict the performance of all possible combinations of the smoothing parameter optimization matrix and the cache configuration scheme; finally, according to the pre-defined optimization objective function (usually the weighted combination of delay and throughput), the optimal parameter combination is selected from all combinations as the final selection. This data-driven method avoids blind parameter tuning and ensures the scientificity and effectiveness of parameter selection.

[0137] According to the optimal parameter combination, dynamic reconfiguration of the internal logic unit of the FPGA is a key technology to achieve adaptive optimization. FPGA dynamic reconfiguration refers to the technology of reconfiguring part of the internal logic resources of the FPGA without interrupting the system operation. In specific operation, firstly, the optimal parameter combination is converted into FPGA configuration instructions, including logic unit function definition, interconnection structure setting, clock domain division, etc.; then the area to be reconfigured is identified, which is usually the performance bottleneck module or the part with unbalanced resource utilization; then the partial reconfiguration bitstream is generated, which is the configuration data required for reconfiguring the specific area of the FPGA; finally, a detailed resource allocation diagram is generated, which accurately describes the function allocation, interconnection relationship and clock allocation of each logic unit, etc., and is the direct basis for FPGA reconfiguration.

[0138] Reconfiguring the data path and processing pipeline is the last step to implement a high-performance bus communication system. The deployment process first converts the resource allocation graph into partial reconfiguration bitstreams that can be directly loaded into the FPGA; then loads these bitstreams through the internal configuration access port to complete the reconfiguration of the target area; then updates the relevant control registers to make the new configuration take effect; finally, the reconfiguration result is verified to ensure that all functional modules are working properly. After reconfiguration, the FPGA forms a data path and processing pipeline based on the latest parameter optimization, including optimized buffer distribution, dynamic smoothing processing units, and efficient interconnections between functional modules, thereby implementing a high-speed bus communication system with optimal performance. Taking the rail transit control system as an example, the performance optimization process of the agent high-speed bus implementation method based on FPGA and dynamic smoothing technology in practical application is as follows: Performance monitoring probes are deployed at key nodes such as the MAC interface, protocol processing unit, and dynamic smoothing module within the FPGA, and performance data is collected every 100 microseconds. Through continuous monitoring, it is found that during the morning and evening peak periods, the system throughput increases from an average of 4 Gbps to 7 Gbps, the latency fluctuation increases from a standard deviation of 2 ms to 5 ms, and the receive buffer occupancy rate reaches 85%. Based on these performance indicators, the most suitable weighted coefficient for the dynamic smoothing algorithm during the peak period is calculated to be 0.3 (0.7 for normal), and the time window size is 12 sampling points (8 for normal), forming a parameter optimization matrix corresponding to high, medium, and low load states. Traffic analysis shows that during the peak period, there is a burst of high traffic, and accordingly, the receive buffer allocation strategy is adjusted from uniform distribution to skewed distribution, and the receive buffer occupancy ratio is increased from 40% to 60%. Through regression analysis, the optimal combination is determined from 30 parameter combinations: weighted coefficient 0.35, window size 10, and receive buffer occupancy ratio 55%. This combination can reduce the peak period latency fluctuation by 40% in model prediction. Accordingly, the FPGA reconfiguration scheme is generated, and the protocol processing unit, buffer allocation, and dynamic smoothing module are partially reconfigured, and the data path is redesigned, and a dedicated parallel processing channel for the peak period is added. After deployment, the actual latency fluctuation of the system during the peak period is reduced to 2.2 ms, and the throughput is increased to 8 Gbps, fully meeting the real-time control requirements in emergency situations.

[0139] The agent high-speed bus implementation method based on FPGA and dynamic smoothing technology in the embodiments of the present application is described above, and the agent high-speed bus implementation system based on FPGA and dynamic smoothing technology in the embodiments of the present application is described below. Please refer to Figure 5 An embodiment of the agent high-speed bus implementation system based on FPGA and dynamic smoothing technology in the embodiments of the present application includes:

[0140] A construction module is configured to customize a single handshake message through a lightweight protocol stack, the single handshake message containing a handshake identifier, authentication credentials and an initial data payload, to obtain a lightweight message structure with a compressed header;

[0141] An adjustment module is configured to dynamically adjust a network performance index matrix through an exponential smoothing method according to real-time collected network transmission delay data, to obtain an adaptive transmission parameter set;

[0142] A construction module is configured to construct a protocol processing unit with a pipeline structure on an FPGA card through a VHDL hardware description language by using the lightweight message structure and the adaptive transmission parameter set, to obtain a hardware accelerated protocol stack;

[0143] An encryption module is configured to encrypt transmission data through a time-driven key update strategy and an improved AES-GCM mode based on the hardware accelerated protocol stack, to obtain a secure communication guarantee mechanism;

[0144] An access module is configured to construct a three-layer adaptation structure of a physical interface conversion layer, a protocol adaptation layer and a session management layer according to the hardware accelerated protocol stack and the secure communication guarantee mechanism, to form a subsystem access architecture;

[0145] A processing module is configured to perform tuning processing on a dynamic smoothing algorithm coefficient, a cache size and FPGA logic resource allocation according to a running state of the subsystem access architecture, to obtain a high-performance bus communication system.

[0146] Through the cooperation of the above various components, the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology has significant technical effects. By customizing a single handshake message through a lightweight protocol stack, the method successfully simplifies the traditional TCP three-way handshake to a single handshake, reduces the initial connection delay, and at the same time, the message compression header design removes redundant control information, greatly improving the communication efficiency and throughput. The technical means of dynamically adjusting the network performance index matrix using the exponential smoothing method enables the system to accurately perceive network state changes and predict trends, and the dynamically generated adaptive transmission parameter set enables the communication process to maintain stable performance when the network conditions fluctuate, effectively reducing the impact of network jitter on communication quality. The protocol processing unit with a pipeline structure is constructed on the FPGA card using the VHDL hardware description language, which migrates the protocol stack from the software layer to the hardware implementation, fully utilizes the parallel computing advantages of FPGA, breaks through the performance bottleneck of traditional CPU serial processing, and improves the protocol processing speed by several times. At the same time, the low latency characteristics of hardware-accelerated protocol stack provide reliable protection for real-time control. Through the time-driven key update strategy and the improved AES-GCM mode security communication guarantee mechanism, the communication security is realized while ensuring high-speed data transmission, and the performance overhead of the security mechanism is minimized by periodic key rotation and hardware acceleration of the encryption algorithm. The three-layer adaptive structure subsystem access architecture design enables devices with different interface standards and protocols to seamlessly access the system, greatly enhancing the interoperability and scalability of the system and solving the problem of heterogeneous system integration. The tuning mechanism of the dynamic smoothing algorithm coefficients, cache size and FPGA logic resource allocation enables the system to adaptively optimize according to the real-time load conditions, ensuring optimal performance under various working conditions. It is particularly worth emphasizing that the dynamic smoothing technology in the present scheme is not only the application of a simple smoothing algorithm, but also a comprehensive intelligent algorithm combining network performance index matrix analysis, multi-factor weighting processing and prediction model construction. Through deep learning and pattern recognition of network fluctuation characteristics, the algorithm accurately predicts the future network state, and then guides the dynamic adjustment of transmission parameters. This way of deeply integrating artificial intelligence algorithm characteristics and communication system makes the communication performance remain highly stable and predictable in complex and variable network environments, providing key technical support for high real-time requirement scenarios such as rail transit. At the same time, the combination of FPGA reconfigurability and adaptive algorithm gives the system the ability to continuously optimize, significantly improving the overall communication efficiency and reliability.

[0147] With reference Figure 6 In the embodiment of the present application, a computer device, which can be a server, is also provided. The internal structure of the computer device can be as follows: Figure 6The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium. The database of the computer device is configured to store corresponding data in the embodiment. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement the above method.

[0148] Those skilled in the art can understand that, Figure 6 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied.

[0149] The computer readable storage medium in the embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0150] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, system and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described herein.

[0151] The integrated unit, if realized in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical scheme of the present application or the whole or part of the technical scheme which essentially contributes to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0152] The above-described embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for implementing a high-speed bus for intelligent agents based on FPGA and dynamic smoothing technology, characterized in that, include: Custom-construct a single handshake message to obtain a lightweight message structure with a compressed header; Based on real-time collected network transmission delay data, the network performance index matrix is ​​dynamically adjusted to obtain an adaptive transmission parameter set. This includes: calculating the difference between the transmission and reception times of network data packets using a timestamp difference method to obtain an original delay sampling sequence; constructing a time-series correlation matrix using a sliding window technique based on the original delay sampling sequence to extract delay fluctuation characteristics; smoothing the delay fluctuation characteristics using a multi-factor weighted exponential smoothing algorithm to generate a network state prediction curve; calculating the transmission window size adjustment coefficient and rate change gradient based on the network state prediction curve to form a dynamic adjustment vector; identifying sudden network delays using a mutation detection threshold to trigger a rapid response mechanism and generate emergency control commands; and prioritizing and merging the dynamic adjustment vector and emergency control commands to obtain the adaptive transmission parameter set. Utilizing the lightweight message structure and adaptive transmission parameter set, a pipelined protocol processing unit is constructed to obtain a hardware-accelerated protocol stack. This includes: defining the FPGA internal data path specifications based on the lightweight message structure, drawing a hardware circuit diagram, and forming a protocol processing circuit blueprint; converting the protocol processing circuit blueprint into a register-transfer level description using VHDL to construct a message parsing state machine; designing a dynamic parameter register group based on the adaptive transmission parameter set to implement a real-time parameter update mechanism; dividing the message parsing state machine into a four-stage pipeline of message reception, header parsing, payload processing, and message encapsulation to generate parallel execution units; optimizing the critical path in the parallel execution units using lookup table technology to construct a high-speed data path that satisfies timing constraints; designing a DMA transfer controller and a buffer manager based on the high-speed data path to obtain the hardware-accelerated protocol stack; and encrypting the transmitted data based on the hardware-accelerated protocol stack to obtain a secure communication guarantee mechanism. Based on the hardware acceleration protocol stack and secure communication guarantee mechanism, a three-layer adaptation structure consisting of a physical interface conversion layer, a protocol adaptation layer, and a session management layer is constructed to form a subsystem access architecture. Based on the operating status of the subsystem access architecture, the dynamic smoothing algorithm coefficients, cache size, and FPGA logic resource allocation are optimized to obtain a high-performance bus communication system.

2. The method for implementing a high-speed intelligent agent bus based on FPGA and dynamic smoothing technology according to claim 1, characterized in that, The customized single-handshake message structure yields a lightweight message structure with a compressed header, including: The traditional TCP / UDP protocol is deconstructed using a protocol analyzer, and redundant control fields are removed to form a lightweight protocol field set; Based on the lightweight protocol field set, a handshake identifier field HS_FLAG is constructed, and the communication identity identifier and session parameters are encoded into a binary sequence to obtain a compact handshake identifier. The HMAC algorithm is used to hash the pre-shared key and session information to generate secure authentication credentials; The initial data payload is sorted according to timestamp priority, and key business data is embedded in the handshake message header to achieve data transmission in advance. By reorganizing and arranging the message header information using bit-field compression technology, the space occupied by control information is reduced, resulting in a compressed header structure. The compact handshake identifier, security authentication credentials, and compressed header structure are byte-aligned and encapsulated to obtain the lightweight message structure of the compressed header.

3. The method for implementing a high-speed intelligent agent bus based on FPGA and dynamic smoothing technology according to claim 1, characterized in that, The mechanism for encrypting transmitted data based on the hardware acceleration protocol stack to obtain a secure communication guarantee includes: Based on the communication session identifier and time seed, a key derivation function (KDF) is constructed to generate the initial session key; A hardware counter is used to accumulate and count the amount of data transmitted, and a key update threshold is set to form a time-driven trigger condition. When the time-driven triggering condition is met, new key material is generated through the key derivation function KDF to complete the key rotation; The initial value of the counter in the improved AES-GCM mode is randomized to generate an unpredictable sequence of encrypted blocks. For the data packets transmitted by the hardware acceleration protocol stack, a pipelined approach is used to perform block encryption and authentication tag calculation to generate an encrypted data stream; The encrypted data stream is associated with and packaged with the key version number to form a verifiable secure communication data packet, thus obtaining the secure communication guarantee mechanism.

4. The method for implementing a high-speed intelligent agent bus based on FPGA and dynamic smoothing technology according to claim 1, characterized in that, Based on the hardware acceleration protocol stack and secure communication guarantee mechanism, a three-layer adaptation structure consisting of a physical interface conversion layer, a protocol adaptation layer, and a session management layer is constructed to form a subsystem access architecture, including: For the communication interface characteristics of different subsystems, an interface mapping table is designed, and a physical interface conversion layer supporting Ethernet and PCIe interface standards is constructed. The signals between the physical interface conversion layer and the hardware acceleration protocol stack are mapped and converted using an interface description language to form a unified interface standard. Based on the unified interface standard, the format of external protocol messages and the lightweight message structure is converted to establish a protocol adaptation layer. The secure communication guarantee mechanism is embedded in the protocol adaptation layer to perform secure encapsulation and decapsulation of the data stream and generate a secure channel. A distributed state synchronization algorithm is used to maintain the session state information between subsystems, and a session management layer is constructed. The physical interface conversion layer, protocol adaptation layer, and session management layer are vertically integrated, and the functional modules are connected through an interconnect bus to form the subsystem access architecture.

5. The method for implementing a high-speed intelligent agent bus based on FPGA and dynamic smoothing technology according to claim 1, characterized in that, The process involves optimizing the dynamic smoothing algorithm coefficients, cache size, and FPGA logic resource allocation based on the subsystem access architecture's operational status to obtain a high-performance bus communication system, including: The system collects throughput, latency fluctuation, and resource utilization data of the subsystem access architecture using performance monitoring probes to form a system performance index set. Based on the system performance index set, the weighting coefficients and time window size of the dynamic smoothing algorithm are calculated, and a smoothing parameter optimization matrix is ​​constructed. Based on the analysis of communication traffic patterns, the cache allocation strategy is adjusted in stages to generate a cache configuration scheme. The combined effect of the smoothing parameter optimization matrix and the cache configuration scheme is evaluated using regression analysis, and the optimal parameter combination is selected. Based on the optimal parameter combination, the internal logic units of the FPGA are dynamically reconfigured to generate a resource allocation diagram; The resource allocation diagram is deployed to the FPGA card, and the data path and processing pipeline are reconstructed to obtain the high-performance bus communication system.

6. A high-speed bus implementation system for intelligent agents based on FPGA and dynamic smoothing technology, used to implement the high-speed bus implementation method for intelligent agents based on FPGA and dynamic smoothing technology as described in any one of claims 1-5, characterized in that, include: The construction module is used to customize the construction of a single handshake message, resulting in a lightweight message structure with a compressed header. The adjustment module is used to dynamically adjust the network performance index matrix based on real-time collected network transmission delay data to obtain an adaptive transmission parameter set. This includes: performing a difference calculation on the transmission and reception times of network data packets using a timestamp difference calculation method to obtain an original delay sampling sequence; constructing a time-series correlation matrix based on the original delay sampling sequence using a sliding window technique to extract delay fluctuation characteristics; smoothing the delay fluctuation characteristics using a multi-factor weighted exponential smoothing algorithm to generate a network state prediction curve; calculating the transmission window size adjustment coefficient and rate change gradient based on the network state prediction curve to form a dynamic adjustment vector; identifying sudden network delays using a mutation detection threshold to trigger a rapid response mechanism and generate emergency control commands; and prioritizing and merging the dynamic adjustment vector and emergency control commands to obtain the adaptive transmission parameter set. A construction module is used to build a pipelined protocol processing unit using the lightweight message structure and adaptive transmission parameter set to obtain a hardware-accelerated protocol stack. This includes: defining the FPGA internal data path specifications based on the lightweight message structure, drawing a hardware circuit diagram, and forming a protocol processing circuit blueprint; converting the protocol processing circuit blueprint into a register-transfer level description using VHDL to build a message parsing state machine; designing a dynamic parameter register group based on the adaptive transmission parameter set to implement a real-time parameter update mechanism; dividing the message parsing state machine into a four-stage pipeline of message reception, header parsing, payload processing, and message encapsulation to generate parallel execution units; optimizing the critical path in the parallel execution units using lookup table technology to construct a high-speed data path that satisfies timing constraints; designing a DMA transfer controller and a buffer manager based on the high-speed data path to obtain the hardware-accelerated protocol stack; and encrypting the transmitted data based on the hardware-accelerated protocol stack to obtain a secure communication guarantee mechanism. The encryption module is used to encrypt the transmitted data based on the hardware acceleration protocol stack to obtain a secure communication guarantee mechanism. The access module is used to construct a three-layer adaptation structure of physical interface conversion layer, protocol adaptation layer and session management layer based on the hardware acceleration protocol stack and secure communication guarantee mechanism, forming a subsystem access architecture. The processing module is used to optimize the dynamic smoothing algorithm coefficients, cache size, and FPGA logic resource allocation according to the operating status of the subsystem access architecture, so as to obtain a high-performance bus communication system.

7. A computer device, characterized in that, The method includes a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology as described in any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, the computer program causing a processor, when executed by a processor, to perform the intelligent agent high-speed bus implementation method based on FPGA and dynamic smoothing technology as described in any one of claims 1 to 5.

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