Demodulation circuit, audio playing device and audio playing system

Abstract

The invention discloses a demodulation circuit, an audio playing device and an audio playing system. The demodulation circuit comprises a demodulation module, a shift register, a clock conversion module and a first buffer. The input end of the demodulation module is electrically connected with an amplitude modulation signal end; the input end of the shift register is electrically connected with the output end of the demodulation module; the input end of the clock conversion module is electrically connected with the output end of the shifting register, the clock conversion module is used for generating a second clock signal, and the clock frequency of the second clock signal is 1 / N of the clock frequency of the first clock signal; the control end of the first buffer is electrically connected with the output end of the clock conversion module, the input end of the first buffer is electrically connected with the output end of the shifting register, and the output end of the first buffer serves as the signal output end of the demodulation circuit. According to the embodiment of the invention, when the amplitude-modulated signal is processed, the problems of signal distortion, data loss and dislocation and the like can be avoided, the correctness of writing the data into the storage module can be ensured, and the subsequent audio playing effect is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to a demodulation circuit, an audio playing device and an audio playing system. BACKGROUND

[0002] In the existing audio playing device and audio playing system, the demodulation circuit as a key component for receiving and processing the amplitude modulation signal directly affects the decoding quality and playing effect of the audio data.

[0003] The traditional demodulation circuit often adopts a relatively simple architecture, which can realize the basic signal demodulation function, but when processing high-speed and high-density amplitude modulation signals, it is prone to problems such as signal distortion, data loss and data misplacement, and cannot guarantee the correctness of data writing into the storage module, thereby affecting the subsequent audio playing effect. SUMMARY

[0004] The present application provides a demodulation circuit, an audio playing device and an audio playing system, which can avoid problems such as signal distortion, data loss and data misplacement when processing high-speed and high-density amplitude modulation signals, can guarantee the correctness of data writing into the storage module, and improves the subsequent audio playing effect.

[0005] In a first aspect, the present application provides a demodulation circuit, comprising: a demodulation module, an input end of which is electrically connected with an amplitude modulation signal end, for extracting a target serial signal from an amplitude modulation signal transmitted from the amplitude modulation signal end in response to a first clock signal and outputting; a shift register, an input end of which is electrically connected with an output end of the demodulation module, for converting the target serial signal into a parallel signal with N branches and outputting in response to the first clock signal, N being a positive integer greater than 1; a clock conversion module, an input end of which is electrically connected with an output end of the shift register, for generating a second clock signal and outputting, the clock frequency of the second clock signal being 1 / N of the clock frequency of the first clock signal; a first buffer, a control end of which is electrically connected with an output end of the clock conversion module, an input end of which is electrically connected with an output end of the shift register, and an output end of which serving as a signal output end of the demodulation circuit, for capturing the target parallel signal in response to the second clock signal.

[0006] In a possible embodiment of the first aspect, the clock conversion module comprises: a data packet header identification module, an input end of which serving as the input end of the clock conversion module, for identifying preset packet header information in the parallel signal output by the shift register; The frequency division counting module is electrically connected with the output end of the data packet head identification module, and its output end is used as the output end of the clock conversion module, for counting in cycles according to the clock period of the first clock signal as the counting unit when the data packet head identification module identifies the preset packet head information, and obtaining the second clock signal.

[0007] In a possible embodiment of the first aspect, the counting range of the cycle counting is 0 to N-1.

[0008] In a possible embodiment of the first aspect, the transistor in the demodulation circuit is a thin film transistor.

[0009] Based on the same inventive concept, in the second aspect, the embodiments of the present application further provide an audio playing device, comprising the demodulation circuit according to any one of the embodiments of the first aspect, and: The read-write control module is electrically connected with the signal output end of the demodulation circuit; The storage module is electrically connected with the data transmission end of the read-write control module, and its address input end is electrically connected with the address output end of the read-write control module; The audio playing module is electrically connected with the output end of the read-write control module, and its first output end is electrically connected with the read address control end of the read-write control module, and its second output end is used as the music playing end; The read-write control module is used for writing the target parallel signal output by the demodulation circuit into the storage module in the data receiving stage, and is also used for reading the target parallel signal from the storage module and transmitting it to the audio playing module in the audio playing stage.

[0010] In a possible embodiment of the second aspect, the read-write control module comprises: The data line gate is electrically connected with the data transmission end of the storage module, and its output end is used as the output end of the read-write control module; In the data receiving stage, the data line gate is used for transmitting the target parallel signal inputted by its input end to its data transmission end, so as to write the target parallel signal of its data transmission end into the storage module; In the audio playing stage, the data line gate is used for reading the target parallel signal from the storage module through its data transmission end, and transmitting the target parallel signal to the audio playing module through its output end; The address line gate is used as the address output end of the read-write control module; The write address counter is electrically connected with the first input end of the address line gate; The read address counter is electrically connected with the second input end of the address line gate, and its read address control end is electrically connected with the first output end of the audio playing module; In the data receiving stage, the address line gate is configured to transmit the write address information outputted by the write address counter connected to the first input end of the address line gate to the address output end of the address line gate, so that the address output end of the address line gate transmits the write address information to the storage module. In the audio playing stage, the address line gate is configured to transmit the read address information outputted by the read address counter connected to the second input end of the address line gate to the address output end of the address line gate, so that the address output end of the address line gate transmits the read address information to the storage module.

[0011] In a possible embodiment of the second aspect, the output end of the clock conversion module in the demodulation circuit is further electrically connected to the control end of the data line gate, and is configured to provide a data write clock signal.

[0012] In a possible embodiment of the second aspect, the transistor in the audio playing device is a thin film transistor.

[0013] In a possible embodiment of the second aspect, the audio playing module comprises: a second buffer, an input end of which is configured as an input end of the audio playing module; a beat counter, an input end of which is electrically connected to a first type of output end of the second buffer, and an output end of which is configured as a first output end of the audio playing module; a multiplexer, a control end of which is electrically connected to a second type of output end of the second buffer, and an output end of which is configured as a second output end of the audio playing module; wherein the second buffer is configured to split the target parallel signal to obtain beat quantity information, scale information and section information, and output the beat quantity information through the first type of output end and output the scale information and the section information through the second type of output end.

[0014] In a possible embodiment of the second aspect, the counting stop point of the beat counter is greater than or equal to the beat quantity information.

[0015] In a possible embodiment of the second aspect, the second type of output end of the second buffer comprises a first sub-output end and a second sub-output end; and the multiplexer comprises: a first type of multiplexer, a control end of which is electrically connected to the first sub-output end of the second buffer, and an input end of which is electrically connected to a scale signal end; a second type of multiplexer, a control end of which is electrically connected to the second sub-output end of the second buffer, an input end of which is electrically connected to the output end of the first type of multiplexer, and an output end of which is configured as the output end of the multiplexer.

[0016] In a possible embodiment of the second aspect, the first type of multiplexer comprises: The first gate has an input end electrically connected with the first type of scale signal end, a control end electrically connected with the first sub-output end of the second buffer, and an output end electrically connected with a first input end of the second type of multiplex gate; The second gate has an input end electrically connected with the second type of scale signal end, a control end electrically connected with the first sub-output end of the second buffer, and an output end electrically connected with a second input end of the second type of multiplex gate; The third gate has an input end electrically connected with the third type of scale signal end, a control end electrically connected with the first sub-output end of the second buffer, and an output end electrically connected with a third input end of the second type of multiplex gate.

[0017] In a possible implementation of the second aspect, The first type of scale signal end, the second type of scale signal end, and the third type of scale signal end are configured to input clock signals of different frequencies. Alternatively, the first type of scale signal end, the second type of scale signal end, and the third type of scale signal end are configured to input analog voltage signals of different frequencies.

[0018] In a possible implementation of the second aspect, The operational amplifier module has an input end electrically connected with the second output end of the audio playing module, and an output end serving as a music playing end of the audio playing device.

[0019] Based on the same inventive concept, in a third aspect, embodiments of the present application further provide an audio playing system, which comprises: The coil has a first output end for outputting a periodic clock signal, a second output end for outputting an alternating power supply signal, and a third output end serving as an amplitude modulation signal end; The clock extraction module has an input end electrically connected with the first output end of the coil, and is configured to extract a first clock signal based on the periodic clock signal. The power supply module has an input end electrically connected with the second output end of the coil, and is configured to rectify the alternating power supply signal to obtain a logic power supply signal. and the audio playing device as described in any one of the embodiments of the second aspect.

[0020] The demodulation circuit, the audio playing device and the audio playing system provided by the embodiments of the present application, wherein the demodulation circuit can comprise a demodulation module, a shift register, a clock conversion module and a first buffer. The input end of the demodulation module is electrically connected with the amplitude modulation signal end, and is used for extracting a target serial signal from the amplitude modulation signal transmitted from the amplitude modulation signal end in response to the first clock signal. The input end of the shift register is electrically connected with the output end of the demodulation module, and is used for converting the target serial signal into a parallel signal with N branches in response to the first clock signal. The input end of the clock conversion module is electrically connected with the output end of the shift register, and is used for generating a second clock signal with a clock frequency of 1 / N of the first clock signal. By introducing the clock conversion module, the second clock signal with a frequency of 1 / N of the first clock signal can be generated according to the branch number N of the parallel signal, so as to ensure that the subsequent first buffer can obtain accurate timing control in the process of capturing the parallel signal, thereby the parallel signal can be accurately intercepted, and the problems of data interception error and data misplacement are avoided. The control end of the first buffer is electrically connected with the output end of the clock conversion module, the input end of the first buffer is electrically connected with the output end of the shift register, and the output end of the first buffer serves as the signal output end of the demodulation circuit, and is used for capturing the target parallel signal in response to the second clock signal. The introduction of the first buffer further enhances the stability and reliability of the demodulation circuit, and the target parallel signal in the parallel signal can be captured and output in response to the second clock signal, so as to ensure that the target serial signal is correctly intercepted into individual target parallel signals and correctly written into the subsequent storage module, without the occurrence of data loss or data damage in the target serial signal, and finally the high-quality audio playing effect is realized. BRIEF DESCRIPTION OF DRAWINGS

[0021] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings, in which like references denote like features, and in which:

[0022] Figure 1 is a circuit structure schematic diagram of the demodulation circuit provided by the embodiments of the present application; Figure 2 is another circuit structure schematic diagram of the demodulation circuit provided by the embodiments of the present application; Figure 3 is a circuit structure schematic diagram of the audio playing device provided by the embodiments of the present application; Figure 4 is another circuit structure schematic diagram of the audio playing device provided by the embodiments of the present application; Figure 5 is a circuit structure schematic diagram of the audio playing module in the audio playing device provided by the embodiments of the present application; Figure 6is a system architecture schematic diagram of an audio playing system provided by an embodiment of the present application; Figure 7-A is a system state switching schematic diagram of an audio playing system provided by an embodiment of the present application; Figure 7-B is a system state control timing schematic diagram of an audio playing system provided by an embodiment of the present application; Figure 8 is another system architecture schematic diagram of an audio playing system provided by an embodiment of the present application; Figure 9 is a schematic diagram of a generation process of a demodulation circuit generating a second clock signal based on a first clock signal provided by an embodiment of the present application; Figure 10 is a schematic diagram of a count process of a beat counter provided by an embodiment of the present application; Figure 11 is another system architecture schematic diagram of an audio playing system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. To make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application, and are not configured to limit the present application. The present application can be implemented without some of the specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0024] It should be noted that, in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, and do not necessarily require or imply that there is any such actual relationship or order between these entities or actions. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed or other elements inherent to such processes, methods, articles or devices. Without more limitations, the elements defined by the statement "comprising" do not exclude the presence of additional identical elements in the process, method, article or device including the elements.

[0025] It should be understood that the term "and / or" as used herein merely describes an associated relationship between associated objects, and can represent three relationships, for example, A and / or B can represent three cases of A alone, A and B together, and B alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0026] Various modifications and changes can be made to the application in matters of detail, without departing from the spirit and scope of the application, which will be apparent to one skilled in the art. Accordingly, the application is intended to embrace all modifications and changes that fall within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the application can be combined with each other without contradiction.

[0027] Before describing the technical solutions provided by the embodiments of the application, in order to facilitate the understanding of the embodiments of the application, the application first specifically describes the problems existing in the related art: In related audio playing devices and audio playing systems, the demodulation circuit as a key component for receiving and processing amplitude modulation signals directly affects the decoding quality and playing effect of audio data in terms of performance and accuracy.

[0028] The related demodulation circuit often adopts a relatively simple architecture, although it can realize basic signal demodulation functions, but when processing high-speed and high-density amplitude modulation signals, it is easy to encounter problems such as signal distortion, data loss and data misplacement, which cannot guarantee the correctness of data writing into the storage module SRAM, thereby affecting the subsequent audio playing effect.

[0029] Specifically, the related demodulation circuit usually does not have a design for parallel processing of high-speed serial signals, which makes it difficult to accurately control the timing in the subsequent processing process, thereby increasing the risk of data misplacement and loss. In addition, due to the lack of effective clock management mechanism, the related demodulation circuit is prone to timing mismatch when capturing and storing serial signals, further increasing the possibility of data misplacement and loss.

[0030] In addition, since flexible electronic technology is an emerging technology, devices that can be manufactured using thin film transistor (TFT), capacitor, resistor, etc. array process cannot form large-scale integrated circuits, and cannot build too complex electronic systems, therefore, the related art also has the problem of lacking a clear and detailed system architecture of a full-fledged audio playing system.

[0031] Based on this, the embodiment of the present application provides a demodulation circuit, an audio playing device and an audio playing system, which can avoid signal distortion, data loss and data misplacement and the like when processing high-speed and high-density amplitude modulation signals, can ensure the correctness of data writing into a storage module, improve the subsequent audio playing effect, and can also construct the system architecture of a full-flexible audio playing system.

[0032] The demodulation circuit provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0033] Figure 1 is a circuit structure schematic diagram of a demodulation circuit provided by the embodiment of the present application, as shown in the figure, the demodulation circuit 10 can include a demodulation module 11, a shift register 12, a clock conversion module 13 and a first buffer 14. Figure 1

[0034] The input end of the demodulation module 11 is electrically connected with the amplitude modulation signal end, for extracting a target serial signal from the amplitude modulation signal transmitted from the amplitude modulation signal end in response to the first clock signal and outputting.

[0035] Among them, the amplitude modulation signal end can be configured with an amplitude modulation signal. The amplitude modulation signal is generated after the amplitude change of an audio signal or other low-frequency signal is modulated to the amplitude of a high-frequency carrier signal, and the amplitude modulation signal can be transmitted in communication. The original audio signal or other low-frequency signal can be restored by demodulating the amplitude modulation signal.

[0036] The target serial signal is the audio signal or other low-frequency signal extracted from the amplitude modulation signal by the demodulation module 11. The serial signal is a signal form, and data can be transmitted one bit after another on a single channel.

[0037] Specifically, the demodulation module 11 receives the amplitude modulation signal, and under the trigger of the first clock signal, extracts the target serial signal from the amplitude modulation signal, that is, extracts the original audio or low-frequency signal, and the target serial signal is transmitted one bit after another on a single channel at the output end of the demodulation module 11.

[0038] The input end of the shift register 12 is electrically connected with the output end of the demodulation module 11, for converting the target serial signal into a parallel signal with N branches and outputting in response to the first clock signal, N is a positive integer greater than 1.

[0039] ​The shift register 12 has a data shift function, can shift the input data in a specific direction (such as left shift or right shift) under the triggering of the first clock signal, and can output the shifted data at the same time, and can be used for serial-parallel conversion of data. It can be simply understood that the shift register 12 has an input end and N output ends, and one bit of digital signal at the input end can be shifted to one output end of the N output ends in each clock cycle, and the cycle is repeated.

[0040] The parallel signal is opposite to the serial signal, and the data can be transmitted on multiple channels or branches at the same time.

[0041] Specifically, the input end of the shift register 12 is electrically connected with the output end of the demodulation module 11, and is used for converting the target serial signal output by the demodulation module 11 into a parallel signal containing N parallel transmission paths under the driving of the first clock signal.

[0042] The input end of the clock conversion module 13 is electrically connected with the output end of the shift register 12, and is used for generating and outputting a second clock signal, and the clock frequency of the second clock signal is 1 / N of the clock frequency of the first clock signal.

[0043] The second clock signal is the output clock signal generated by the clock conversion module 13, and has different frequency characteristics compared with the first clock signal. The clock frequency of the second clock signal is 1 / N of the clock frequency of the first clock signal, where N is the number of branches in the parallel signal output by the shift register. For example, N is 8, the clock frequency of the first clock signal is 100MHZ, and the clock frequency of the second clock signal is 12.5MHZ.

[0044] Specifically, the clock conversion module 13 generates a second clock signal with a clock frequency of 1 / N of the clock frequency of the first clock signal by receiving the parallel signal from the output end of the shift register 12 and based on the number N of branches of the parallel signal.

[0045] The control end of the first buffer 14 is electrically connected with the output end of the clock conversion module 13, the input end of the first buffer 14 is electrically connected with the output end of the shift register 12, and the output end of the first buffer 14 is used as the signal output end of the demodulation circuit 10, and is used for capturing the target parallel signal in response to the second clock signal.

[0046] The target parallel signal is a specific parallel signal in the multiple parallel signals output by the shift register 12.

[0047] Specifically, the first buffer 14 can receive the target parallel signal from the parallel signal output by the shift register 12 as the output signal of the demodulation circuit 10 under the trigger of the second clock signal output by the clock conversion module 13. In other words, the first buffer 14 can be used to capture the target parallel signal output by the shift register 12 when the shift register 12 sequentially shifts the N serial signals in the target serial signal to the N output ends thereof.

[0048] According to the demodulation circuit 10 provided by the embodiments of the present application, the demodulation circuit 10 can include a demodulation module 11, a shift register 12, a clock conversion module 13, and a first buffer 14. The input end of the demodulation module 11 is electrically connected with the amplitude modulation signal end, and is configured to extract a target serial signal from the amplitude modulation signal transmitted from the amplitude modulation signal end in response to a first clock signal. The input end of the shift register 12 is electrically connected with the output end of the demodulation module 11, and is configured to convert the target serial signal into a parallel signal having N branches in response to the first clock signal. The input end of the clock conversion module 13 is electrically connected with the output end of the shift register 12, and is configured to generate a second clock signal having a clock frequency of 1 / N of the first clock signal. By introducing the clock conversion module, the second clock signal having a frequency of 1 / N of the first clock signal can be generated according to the number N of branches of the parallel signal, so as to ensure that the subsequent first buffer 14 can obtain accurate timing control in the process of capturing the parallel signal, thereby being able to accurately intercept the parallel signal and avoiding the problems of data interception error and data misplacement. The control end of the first buffer 14 is electrically connected with the output end of the clock conversion module 13, the input end of the first buffer 14 is electrically connected with the output end of the shift register 12, and the output end of the first buffer 14 serves as a signal output end of the demodulation circuit 10, and is configured to capture a target parallel signal in response to the second clock signal. The introduction of the first buffer 14 further enhances the stability and reliability of the demodulation circuit 10, and the first buffer 14 can capture and output the target parallel signal in the parallel signal in response to the second clock signal, so as to ensure that the target serial signal is correctly intercepted into the target parallel signal and correctly written into the subsequent storage module, without the occurrence of data loss or data damage in the target serial signal, and finally realizing a high-quality audio playing effect.

[0049] Figure 2 is another circuit structure schematic diagram of the demodulation circuit 10 provided by the embodiments of the present application.

[0050] In some embodiments, as shown in Figure 2 the clock conversion module 13 can include a data packet header identification module 131 and a frequency division counting module 132.

[0051] The input end of the data packet header identification module 131 serves as the input end of the clock conversion module 13, and is configured to identify preset packet header information in the parallel signal output by the shift register 12.

[0052] Specifically, the input end of the data packet header identification module 131 can receive each parallel signal output from the shift register 12 under the driving of the first clock signal, and can identify whether the parallel signal contains preset packet header information.

[0053] The input end of the frequency division counting module 132 is electrically connected with the output end of the data packet header identification module 131, and the output end of the frequency division counting module 132 serves as the output end of the clock conversion module 13, for performing cycle counting according to the clock period of the first clock signal as a counting unit in the case where the data packet header identification module 131 identifies the preset packet header information, to obtain a second clock signal.

[0054] Specifically, when the data packet header identification module 131 detects the preset packet header information, the frequency division counting module 132 is started immediately and performs cycle counting by taking each clock period of the first clock signal as a counting reference, for example, the counting range of cycle counting is 0 to N-1, and each counting process from 0 to N-1 corresponds to a complete period of the second clock signal. In this way, the frequency division counting module 132 generates the second clock signal with a clock frequency of 1 / N of the clock frequency of the first clock signal and outputs the second clock signal, where the second clock signal can serve as a clock reference for the target parallel signal capture of the first buffer 14.

[0055] The embodiment of the present application can generate the second clock signal with a clock frequency of 1 / N of the first clock signal by taking each clock period of the first clock signal as a counting reference for cycle counting after identifying the specific preset packet header information, so as to provide a stable and reliable clock reference for the first buffer 14 to capture the target parallel signal, ensure the accuracy of the target serial signal interception, avoid the data loss or data damage in the target serial signal, and thus realize a high-quality audio playing effect.

[0056] In some embodiments, the counting range of cycle counting is 0 to N-1. For example, N is 8, and the counting range of cycle counting is 0 to 7. In the embodiment of the present application, the counting range of the frequency division counting module 132 in cycle counting is set to start from 0 and increase to N-1, where N is the number of branches of the parallel signal. This counting range constitutes a complete cycle, and each time the counting reaches N-1, it will start from 0 again, and so on, so as to form a stable cycle, so as to generate the second clock signal with a clock frequency of 1 / N of the first clock signal periodically.

[0057] In some embodiments, the transistor in the demodulation circuit 10 is a thin film transistor.

[0058] The thin film transistor (TFT) can drive the AMOLED display screen and can also realize relatively simple circuit functions, for example, constructing a basic analog circuit, a digital circuit and a power supply circuit. In the array process of the panel factory, a low temperature poly-silicon (LTPS) thin film transistor can be made, and an indium gallium zinc oxide (IGZO) thin film transistor can also be made. Therefore, a CMOS type circuit can be constructed by using a P-type low temperature poly-silicon (LTPS) thin film transistor and an N-type low temperature poly-silicon (LTPS) thin film transistor, and a CMOS type circuit can also be constructed by using a P-type low temperature poly-silicon (LTPS) thin film transistor and an N-type indium gallium zinc oxide (IGZO) thin film transistor.

[0059] The embodiment of the present application establishes the circuit architecture of the full-flexible demodulation circuit, so that the demodulation circuit 10 can be constructed by using the devices made by the array process of the thin film transistor (TFT), the capacitor and the resistor, and full-flexible construction of the demodulation circuit 10 is realized.

[0060] It should be noted that the specific internal circuit structure of each module in the demodulation circuit 10 can adopt a known circuit structure, and the specific parameters of each component can be set according to actual needs, and the present application does not limit this.

[0061] Figure 3 FIG. 1 is a circuit structure schematic diagram of an audio playing device provided by the embodiment of the present application.

[0062] Based on the same inventive concept, the embodiment of the present application also provides an audio playing device 100, as shown in FIG. 1, which can include a demodulation circuit 10, a read-write control module 20, a storage module 30 and an audio playing module 40. Figure 3

[0063] The input end of the read-write control module 20 is electrically connected with the output end of the demodulation circuit 10.

[0064] ​Specifically, the read-write control module 20 is responsible for coordinating the write and read operations of the data. In the data receiving stage, the read-write control module 20 writes the target parallel signal output by the demodulation circuit 10 into the storage module 30. In the audio playing stage, the read-write control module 20 reads the target parallel signal from the storage module 30 and transmits it to the audio playing module 40 for playing.

[0065] The read-write control module 20 is configured to write the target parallel signal output by the demodulation circuit 10 into the storage module 30 in the data receiving stage, and read the target parallel signal from the storage module 30 and transmit it to the audio playing module 40 in the audio playing stage.

[0066] The data transmission end of the storage module 30 is electrically connected with the data transmission end of the read-write control module 20, and the address input end of the storage module 30 is electrically connected with the address output end of the read-write control module 20.

[0067] Specifically, the storage module 30 is a data storage area of the audio playing device 100, configured to store the target parallel signal output by the demodulation circuit 10, which is waiting to be read by the read-write control module 20 and transmitted to the audio playing module 40 for playing.

[0068] For example, the storage module 30 can be a static memory SRAM, the data transmission end has an 8-bit parallel data bus, and the address input end has a plurality of parallel address buses, wherein the number of address bus bits can be determined according to actual needs. Each address space of the storage module 30 can store 8-bit data, and each bit of the 8-bit data stores 1 binary data.

[0069] The input end of the audio playing module 40 is electrically connected with the output end of the read-write control module 20, the first output end of the audio playing module 40 is electrically connected with the read address control end of the read-write control module 20, and the second output end of the audio playing module 40 serves as a music playing end.

[0070] Specifically, the audio playing module 40 is an output component of the audio playing device 100, responsible for converting the received digital audio signal (i.e. the target parallel signal) into an analog audio signal and playing it at the music playing end.

[0071] The audio playing device 100 provided by the embodiment of the present application integrates the demodulation circuit 10, the read-write control module 20, the storage module 30 and the audio playing module 40, realizes the complete process of demodulating the demodulated signal to obtain the original audio signal, intercepting and storing the audio signal into the storage module 30, and then reading and playing the audio signal, and ensures the accurate transmission and smooth playing of the audio data.

[0072] Figure 4Fig. 2 is another circuit structure schematic diagram of the audio playing device provided by the embodiment of the present application.

[0073] In some embodiments, as shown in Fig. 1, the read-write control module 20 comprises a data line gate 21, an address line gate 22, a write address counter 23 and a read address counter 24. Figure 4

[0074] The input end of the data line gate 21 is the input end of the read-write control module 20, the data transmission end of the data line gate 21 is electrically connected with the data transmission end of the storage module 30, and the output end of the data line gate 21 is the output end of the read-write control module 20.

[0075] In the data receiving stage, the data line gate 21 is used to transmit the target parallel signal connected to the input end of the data line gate 21 to the data transmission end of the data line gate 21, so that the target parallel signal of the data transmission end of the data line gate 21 is written into the storage module 30.

[0076] In the audio playing stage, the data line gate 21 is used to read the target parallel signal from the storage module 30 through the data transmission end of the data line gate 21, and transmit the target parallel signal to the audio playing module 40 through the output end of the data line gate 21.

[0077] Specifically, the data line gate 21 receives the target parallel signal and writes it into the storage module 30 in the data receiving stage, and reads the target parallel signal from the storage module 30 and transmits it to the audio playing module 40 in the audio playing stage, thereby realizing the bidirectional transmission function of data.

[0078] The output end of the address line gate 22 is the address output end of the read-write control module 20.

[0079] The output end of the write address counter 23 is electrically connected with the first input end of the address line gate 22.

[0080] The output end of the read address counter 24 is electrically connected with the second input end of the address line gate 22, and the read address control end of the read address counter 24 is electrically connected with the first output end of the audio playing module 40.

[0081] In the data receiving stage, the address line gate 22 is used to transmit the write address information output by the write address counter 23 connected to the first input end of the address line gate 22 to the address output end of the address line gate 22, so that the address output end of the address line gate 22 transmits the write address information to the storage module 30.

[0082] ​In the audio playing stage, the address line gate 22 is used to transmit the read address information outputted by the read address counter 24 to the address output end of the address line gate 22, so that the address output end transmits the read address information to the storage module 30.

[0083] Specifically, the address line gate 22 transmits the write address information outputted by the write address counter 23 to the storage module 30 in the data receiving stage, and transmits the read address information outputted by the read address counter 24 to the storage module 30 in the audio playing stage, so as to control the storage and reading positions of the data.

[0084] The audio playing device 100 provided by the embodiment of the present application realizes the bidirectional and efficient transmission of the data and the accurate control of the storage and reading positions of the data by integrating the read-write control module 20 including the data line gate 21, the address line gate 22, the write address counter 23 and the read address counter 24, thereby improving the fluency and accuracy of the audio playing.

[0085] In some embodiments, the output end of the clock conversion module 13 in the demodulation circuit 10 is also electrically connected with the control end of the data line gate 21, for providing the data writing clock signal. The embodiment of the present application electrically connects the output end of the clock conversion module 13 in the demodulation circuit 10 with the control end of the data line gate 21, which can efficiently provide the accurate clock signal for the data writing process, thereby optimizing the synchronization and stability of the data transmission.

[0086] In some embodiments, the transistor in the audio playing device 100 is a thin film transistor. The embodiment of the present application establishes the circuit architecture of the full-flexible audio playing device, so that the audio playing device 100 can be constructed by the devices manufactured by the array process of the thin film transistor (TFT), the capacitor, the resistor and the like, thereby realizing the full-flexible construction of the audio playing device 100.

[0087] In some embodiments, referring to Figure 4 , the audio playing module 40 can include the second buffer 41, the beat counter 42 and the multiplexer 43.

[0088] The input end of the second buffer 41 is used as the input end of the audio playing module 40.

[0089] The input end of the beat counter 42 is electrically connected with the first type of output end of the second buffer 41, and the output end of the beat counter 42 is used as the first output end of the audio playing module 40.

[0090] The control end of the multiplexer 43 is electrically connected with the second type output end of the second buffer 41, and the output end of the multiplexer 43 serves as the second output end of the audio playing module 40.

[0091] The second buffer 41 is configured to split the target parallel signal to obtain the beat number information, the scale information and the tone information, and output the beat number information through the first type output end of the second buffer 41 and output the scale information and the tone information through the second type output end of the second buffer 41.

[0092] It should be noted that the target parallel signal can contain complete information of one note, including the scale information of the note, the tone information of the note and the beat number information of the note.

[0093] The audio playing module 40 provided by the embodiment of the present application can efficiently split the received target parallel signal into beat, scale and tone information by integrating the second buffer 41, the beat counter 42 and the multiplexer 43, and output the target parallel signal to the beat counter 42 and the multiplexer 43 respectively, so as to realize accurate playing and control of the audio.

[0094] In one example, the target parallel signal is 8-bit data D0-D7, wherein D7-D5 represent the scale information, D4-D3 represent the tone information, and D2-D0 represent the beat number information.

[0095] The specific meaning of D7-D5 can be seen from Table 1.

[0096] Table 1 As shown in Table 1, D7-D5 represent the scale, and data 000 represents no sound, and data 001-111 represent 7 scales.

[0097] The specific meaning of D4-D3 can be seen from Table 2.

[0098] Table 2 As shown in Table 2, D4-D3 represent the tone, 01 represents low tone, 10 represents middle tone, and 11 represents high tone.

[0099] D2-D0 represent the beat number, and the specific meaning of D2-D0 can be seen from Table 3.

[0100] Table 3 The target parallel signal in the embodiment of the application is 8-bit data D0~D7, and through allocating bit segments (D7~D5 represent 7 scales and a reset state, D4~D3 distinguish bass segments, middle segments and treble segments, and D2~D0 define 1 to 7 beats and a reset state), accurate encoding and efficient transmission of the audio signal are realized, the flexibility and accuracy of signal processing are significantly improved, and a basis is provided for audio synthesis and rhythm control.

[0101] In some embodiments, the count end point of the beat counter is greater than or equal to the beat quantity. For example, the count end point of the beat counter is 4 times the beat quantity information. For another example, the count end point of the beat counter is 8 times the beat quantity information.

[0102] In the embodiment of the application, when audio playing is performed on each note, the clock can be counted, the count end point of the beat counter is set to be greater than or equal to the beat quantity, for example, several times (such as 4 times, 8 times, etc.) of the beat quantity corresponding to the scale are taken as the count end point, the low-frequency clock obtained by frequency division of the system clock can be better adapted in the case that the note playing time is unchanged. And the beat end signal is generated at the count end time. The beat end signal makes the read address counter 24 of the read-write control module 20 increase the read address by 1, the storage module 30 outputs the data corresponding to the next read address, and then the audio playing module 40 starts playing the next note. The beat is re-counted when the next note is played, and the cycle is repeated. The automatic address updating and automatic playing of the specified time length are realized, the accuracy of playing each note according to the preset beat is ensured, and the automatic transition to the next scale after playing is ended, the fluency and accuracy of music playing are enhanced.

[0103] Figure 5 FIG. 8 is another circuit structure schematic diagram of the audio playing device provided by the embodiment of the application.

[0104] In some embodiments, as shown in FIG. 9, the second type of output end of the second buffer includes a first sub-output end and a second sub-output end; and the multiplexer 43 includes a first type of multiplexer 431 and a second type of multiplexer 432. Figure 5

[0105] The control end of the first type of multiplexer 431 is electrically connected with the first sub-output end of the second buffer 41, and the input end of the first type of multiplexer 431 is electrically connected with the scale signal end.

[0106] The control end of the second type of multiplexer 432 is electrically connected with the second sub-output end of the second buffer 41, the input end of the second type of multiplexer 432 is electrically connected with the output end of the first type of multiplexer 431, and the output end of the second type of multiplexer 432 serves as the output end of the multiplexer 43. ​

[0107] The second type of output end of the second buffer 41 can include a first sub-output end and a second sub-output end, and is connected to control ends of the first type of multiplexer 431 and the second type of multiplexer 432, respectively. Meanwhile, the input end of the first type of multiplexer 431 is connected to the scale signal end, and the input end of the second type of multiplexer 432 is connected to the output end of the first type of multiplexer 431, so that the target scale signal in the plurality of scale signals can be selected and output according to the scale information and the section information output by the second buffer 41, and the flexibility and accuracy of audio playing are enhanced.

[0108] In some embodiments, the first type of multiplexer 431 can include a first gate 4311, a second gate 4312, and a third gate 4313. Figure 5

[0109] The input end of the first gate 4311 is electrically connected to the first type of scale signal end, the control end of the first gate 4311 is electrically connected to the first sub-output end of the second buffer 41, and the output end of the first gate 4311 is electrically connected to the first input end of the second type of multiplexer 432.

[0110] The input end of the second gate 4312 is electrically connected to the second type of scale signal end, the control end of the second gate 4312 is electrically connected to the first sub-output end of the second buffer 41, and the output end of the second gate 4312 is electrically connected to the second input end of the second type of multiplexer 432.

[0111] The input end of the third gate 4313 is electrically connected to the third type of scale signal end, the control end of the third gate 4313 is electrically connected to the first sub-output end of the second buffer 41, and the output end of the third gate 4313 is electrically connected to the third input end of the second type of multiplexer 432.

[0112] Specifically, the first type of multiplexer 431 is composed of three gates (the first gate 4311, the second gate 4312, and the third gate 4313), which respectively receive scale signals of different categories, and selectively transmit these scale signals to the input end of the second type of multiplexer 432 according to the scale information provided by the first sub-output end of the second buffer 41.

[0113] ​For example, the first type of scale signal terminal is configured with the first type of scale signal, and the first type of scale signal includes scale signals corresponding to La, Si, Do, Re, Mi, Fa, and Sol of the bass section. The second type of scale signal terminal is configured with the second type of scale signal, and the second type of scale signal includes scale signals corresponding to La, Si, Do, Re, Mi, Fa, and Sol of the middle section. The third type of scale signal terminal is configured with the third type of scale signal, and the third type of scale signal includes scale signals corresponding to La, Si, Do, Re, Mi, Fa, and Sol of the high section.

[0114] The first type of multiplexer 431 includes three multiplexers (the first multiplexer 4311, the second multiplexer 4312, and the third multiplexer 4313) that respectively select corresponding scale signals according to the scale information (see Table 1) output by the second buffer 41 and output the scale signals to the second type of multiplexer 432. Then, the second type of multiplexer 432 selects a target scale signal from the three scale signals output by the first type of multiplexer 431 (the first multiplexer 4311, the second multiplexer 4312, and the third multiplexer 4313) according to the section information (see Table 2) output by the second buffer 41. Thus, the target scale signal can be flexibly selected and output from multiple scale signals according to the scale information and the section information output by the second buffer 41, which enhances the flexibility and accuracy of audio playback.

[0115] In one example, the first multiplexer 4311 selects the scale signal corresponding to Do of the bass section according to the scale information (D7-D5=011) output by the second buffer 41, the second multiplexer 4312 selects the scale signal corresponding to Do of the middle section according to the scale information (D7-D5=011) output by the second buffer 41, and the third multiplexer 4313 selects the scale signal corresponding to Do of the high section according to the scale information (D7-D5=011) output by the second buffer 41. Then, the second type of multiplexer 432 selects the scale signal corresponding to Do of the high section according to the section information (D4-D3=11) output by the second buffer 41. The first type of multiplexer 431 can accurately select the Do scale signals of the bass, middle, and high sections from multiple scale signals according to the input scale information (D7-D5=011), and the second type of multiplexer can select the Do signal of the high section according to the section information (D4-D3=11), which realizes accurate selection and output of the audio signal and improves the flexibility and accuracy of audio processing.

[0116] In some embodiments, The first type of scale signal terminal, the second type of scale signal terminal, and the third type of scale signal terminal are configured to input clock signals of different frequencies.

[0117] Alternatively, the first, second and third tone signal terminals are configured to input different analog voltage signals. The audio playing module 40 can further include a clock selection module 44. An input terminal of the clock selection module 44 is electrically connected to an output terminal of the multiplexer 43, and an output terminal of the clock selection module 44 serves as a second output terminal of the audio playing module 40.

[0118] The first, second and third tone signal terminals are directly connected to clock signals of different frequencies, or are connected to different analog voltage signals and then the clock selection module 44 selects clock signals of corresponding frequencies, so that the audio playing diversity and accuracy can be achieved.

[0119] In some embodiments, the audio playing device 100 can further include an operational amplifier module 50.

[0120] An input terminal of the operational amplifier module 50 is electrically connected to the second output terminal of the audio playing module 40, and an output terminal of the operational amplifier module 50 serves as a music playing terminal of the audio playing device 100.

[0121] In the embodiment, the operational amplifier module 50 is added to the audio playing module 40, and the input terminal of the operational amplifier module 50 is connected to the second output terminal of the audio playing module 40, so that the audio signal can be amplified, the power and clarity of the audio output are enhanced, and the overall effect of the audio playing is improved.

[0122] Figure 6 FIG. 1 is a system structure schematic diagram of an audio playing system 1000 provided by an embodiment of the present application.

[0123] Based on the same inventive concept, an embodiment of the present application further provides an audio playing system 1000, as shown in FIG. 1, which can include the audio playing device 100, the coil 200, the clock extraction module 300 and the power module 400 according to any of the above embodiments. Figure 6

[0124] The first output terminal of the coil 200 is used to output a periodic clock signal, the second output terminal of the coil 200 is used to output an alternating current power signal, and the third output terminal of the coil 200 serves as an amplitude modulation signal terminal.

[0125] The input terminal of the clock extraction module 300 is electrically connected to the first output terminal of the coil, and is used to extract a first clock signal based on the periodic clock signal.

[0126] The input terminal of the power module 400 is electrically connected to the second output terminal of the coil, and is used to rectify the alternating current power signal to obtain a logic power signal.

[0127] ​The embodiment of the present application provides an audio playing system 1000, which integrates a coil 200 capable of outputting a periodic clock signal, an alternating current power signal and an amplitude modulation signal, a clock extraction module 300 capable of extracting a required clock signal (such as a system clock signal, a first clock signal, a low-frequency clock signal required by a beat counter, etc.) based on the periodic clock signal output by the coil 200, a power module 400 capable of rectifying the alternating current power signal output by the coil 200 to obtain a logic power signal (such as VDD), and an audio playing device 100 capable of demodulating and playing the amplitude modulation signal output by the coil 200, so that the integration design of audio playing, power supply and clock signal extraction is realized, and the integration and operation efficiency of the audio playing system 1000 are significantly improved.

[0128] The audio playing system 1000 comprises the audio playing device 100 provided in any of the above-mentioned embodiments, so that the audio playing system 1000 has all the beneficial effects of the audio playing device 100.

[0129] Figure 7-A FIG. 1 is a schematic diagram of system state switching of the audio playing system 1000 provided by the embodiment of the present application.

[0130] In one example, as shown in FIG. 2, the working state of the audio playing system 1000 mainly comprises three stages: a reset stage, a data receiving stage and an audio playing stage. Figure 7-A

[0131] 1) Reset stage After the system is powered on (the power module 400 generates the logic power signal VDD), the reset stage is automatically entered, and all modules are reset to the initial state.

[0132] In one example, the audio playing system 1000 can further comprise a reset module for generating a global reset signal GL_RST. The global reset signal GL_RST can maintain a low level for a short time after the VDD is generated, so that the whole system is restarted to the initial state. The system state machine WR is high in the initial state. The system state machine WR=H and the global reset signal GL_RST=L, which means that the system is in the reset stage.

[0133] 2) Data receiving stage The system state machine WR=H and the global reset signal GL_RST=H, which means that the system enters the data receiving stage.

[0134] In the data receiving stage, the system receives the audio data transmitted by the wireless coil and stores the audio data in the embedded storage module 30. When the storage module 30 is full, the Data_rdy signal becomes high (Data_rdy=H). ​

[0135] 3) Audio playback stage The system state machine has WR=L and Data_rdy=H, indicating that the system has entered the audio playback stage.

[0136] During the audio playback phase, the system reads audio data from storage module 30, playing it as it reads. After the data from storage module 30 is read and played, it starts reading again from the beginning and plays it in a loop.

[0137] In one example, referring to 7-A, during the audio playback phase, if a high-level pulse appears in the external signal PStop, the system returns to the data receiving mode. After returning to data receiving mode, audio data can be received again, refreshing the data stored in storage module 30. That is, when the playback stop signal PStop is high, the data in storage module 30 needs to be cleared before receiving and reading data; therefore, the data receiving phase WR=H needs to be entered. When the Data_rdy signal is high, it indicates that the data is full and needs to be read and played; therefore, the audio playback phase WR=L needs to be entered.

[0138] Figure 7-B This is a system state control timing diagram of an audio playback system provided in an embodiment of this application.

[0139] In one example, such as Figure 7-B As shown, the Data_rdy and PStop signals are ORed and then inverted to form the State_CLK signal. Using State_CLK as the clock, a D flip-flop can generate the system state machine WR signal, which changes between high and low levels on the rising edge of State_CLK, thus completing the system state transition.

[0140] Simply put, music starts playing when the data is full (for example, when Data_rdy is high, WR will switch from high to low, indicating that data needs to be read, and thus the audio playback stage begins); after the user presses the "next track" button, data is rewritten and then played (for example, when the PStop signal is high, WR will switch from low to high, indicating that data needs to be written, and thus the data receiving stage begins).

[0141] Figure 8 This is a schematic diagram of the system architecture of the audio playback system 1000 provided in the embodiments of this application.

[0142] In one example, such as Figure 8As shown, the audio playback system 1000 can include an audio playback device 100, a coil 200, a clock extraction module 300, and a power supply module 400. The first type of scale signal end, the second type of scale signal end, and the third type of scale signal end are configured with different analog voltage signals (such as analog voltage 1-analog voltage 21). The audio playback module 40 can also include a clock selection module 44. Specifically: 1) Coil 200 The coil 200 is the input window of the entire system, and can obtain an alternating signal, generally a sine wave, through electromagnetic induction. The system can obtain an alternating current power signal, a periodic clock signal, and an amplitude modulation signal carrying a carrier signal through the coil 200.

[0143] It should be noted that using the array process of the display panel factory, thin film transistors and metal traces can be made, and capacitor devices, resistor devices, and OLED light-emitting devices can be made. Based on N-type thin film transistors (TFT) and P-type thin film transistors (TFT), analog circuits and digital circuits can be designed, and power supply circuits can also be designed. Using the array process, coils and capacitor devices can be made using metal traces.

[0144] It should also be noted that the embodiments of the present application can use N-type thin film transistors (TFT), P-type thin film transistors (TFT), capacitors, resistors, coils, and other devices to construct an audio playback system based on the array process of the panel factory. The system architecture is newly developed, and the circuit functions of each module are clearly defined. The appearance of the audio playback system is fully flexible, light, thin, and small. The system architecture of the embodiments of the present application can be refined into an array mask layout, and after array process, a light, thin, and soft product is produced.

[0145] Through the radio transmission coil, there is no need to use a wired connection, and the power supply and the signal are both transmitted wirelessly.

[0146] 2) Clock extraction module 300 The clock extraction module 300 can convert the sine wave signal into a square wave clock signal GL CLK, which can be used as a global base clock for the system to work. The clock domain of the entire system is the GL CLK clock domain. The clock extraction module 300 can also perform loop counting with GL CLK as the clock to generate a new clock signal, such as the first clock signal ASK CLK. The clock extraction module 300 can also perform loop counting with GL CLK as the clock to generate a new low-frequency clock signal LF CLK, which is the working clock of the beat counter 42 of the audio playback module 40.

[0147] 3) Power module 400.

[0148] The power module 400 can convert a sine wave alternating current power signal into a direct current power signal. For example, the power module 400 can include a bridge rectifier module, an amplitude limiting protection module, and a low dropout regulator (LDO). The sine wave alternating current power signal is rectified by the rectifier module to obtain a power signal with an unstable size and a large ripple. Then, the amplitude limiting protection module can limit the amplitude of the direct current power signal to avoid damage to other modules due to overvoltage. Then, the low dropout regulator can convert the direct current power signal into a logic direct current power signal VDD required for system operation. Due to the conversion functions of the amplitude limiting protection module and the low dropout regulator, the voltage of the logic direct current power signal is stable and the ripple is small.

[0149] 4) Audio playing device 100 The audio playing device 100 can include a demodulation circuit 10, a read-write control module 20, a storage module 30, and an audio playing module 40.

[0150] 4.1) Demodulation circuit 10 The demodulation circuit 10 can include a demodulation module 11, a shift register 12, a clock conversion module 13, and a first buffer 14.

[0151] In the data receiving stage, the demodulation module 11 can demodulate the audio signal to form a single-wire target serial signal ASK_OUT.

[0152] The shift register 12 includes 8-stage D flip-flops connected in series, and the first clock signal is used as the trigger clock. In the data receiving stage, the shift register 12 intercepts the target serial signal (denoted as ASK_OUT) into an 8-bit wide parallel signal (denoted as SR[7:0]). Since the parallel signal (SR[7:0]) bus is clocked by ASK_CLK, it is not completely parallel data. SR[7:0] passes through the 8-bit wide first buffer 14. Since the 8-bit wide first buffer 14 is triggered by the second clock signal (denoted as DP_CLK), the target parallel signal (denoted as DP[7:0]) can be output.

[0153] The clock conversion module 13 can include a data packet header identification module 131 and a frequency division counting module 132.

[0154] 4.1.1) Data packet header identification module 131 The data packet header identification module 131 can be used to monitor the SR[7:0] bus, and output a signal DP_CNT_EN. When the header data appears on the bus, the data packet header identification module 131 generates a pulse signal PA_FLAG. The DP_CNT_EN signal is generated by a D flip-flop using the PA_FLAG as a clock. The initial state of the DP_CNT_EN signal is low, and it becomes high after being triggered by the PA_FLAG. The waveform is shown in Figure 9 The data packet header identification can avoid data truncation errors during the serial-parallel conversion.

[0155] In other words, the data packet header identification module is created to generate a flag signal. The flag signal and the first clock signal are used to control the frequency division counting module 132, so that the frequency division counting module 132 generates a second clock signal, which can avoid parallel data truncation errors and ensure the correctness of the data written into the storage module 30.

[0156] 4.1.2) Frequency division counting module 132 The frequency division counting module 132 (DP_CNT) performs cyclic counting using the first clock signal ASK_CLK as a clock, with a bit width of 3 bits and a counting range of 0-7. The second clock signal DP_CLK is output. When DP_CNT_EN is low, the counter stays at data 0; when DP_CNT_EN is high, the counter starts cyclic counting and generates the DP_CLK clock. The second clock signal DP_CLK generated in this way has an aligned phase with the target serial data packet, so there is no problem of parallel data truncation error. The second clock signal DP_CLK is the sampling clock of the first buffer 14, so that the first buffer 14 can capture the target parallel data DP[7:0] from the parallel data SR[7:0].

[0157] 4.2) Read-write control module 20 The read-write control module 20 can include a data line gate 21, an address line gate 22, a write address counter 23, and a read address counter 24.

[0158] The data line gate 21 is used to generate the data bus DS[7:0] of the storage module 30. When the system state is in the data receiving phase, the data line gate 21 connects DP[7:0] and DS[7:0] bit by bit; when the system state is in the music playing phase, the data line gate 21 connects DL[7:0] and DS[7:0] bit by bit.

[0159] The write address counter 23 generates ADDR_W[x:0] using the second clock signal DP_CLK as a clock, and only counts in the data receiving phase.

[0160] The read address counter 24 generates ADDR_R[x:0] with the low frequency clock signal LF CLK as the clock, and only counts in the music playing stage.

[0161] The address line strobe 22 is used to generate the address bus ADDR[x:0] of the storage module 30. When the system is in the data receiving stage, the strobe will respectively conduct ADDR_W[x:0] and ADDR[x:0] bit by bit; when the system is in the music playing mode, the address line strobe 22 will respectively conduct ADDR_R[x:0] and ADDR[x:0] bit by bit.

[0162] 4.3) Storage module 30 The address input end of the storage module 30 receives the address signal through the address bus ADDR[x:0], and the data transmission end of the storage module 30 transmits the data signal through the data bus DS[7:0].

[0163] 4.4) Audio playing module 40 The audio playing module 40 can include a second buffer 41, a beat counter 42 and a multiplexer 43.

[0164] The multiplexer 43 can include a first type of multiplexer 431 and a second type of multiplexer 432. The first type of multiplexer 431 can include a first strobe 4311, a second strobe 4312 and a third strobe 4313.

[0165] In the music playing stage, the output data DL[7:0] of the read-write controller becomes the Data[7:0] bus after passing through the 8-bit second buffer 41. The second buffer 41 uses the low frequency clock signal LF CLK as the clock to make DL[7:0] delay for one period to obtain Data[7:0].

[0166] The first strobe 4311, the second strobe 4312 and the third strobe 4313 are all 8-to-1 functions, controlled by Data[7:5], and respectively select one of the eight analog voltages to output. The output signal of the first strobe 4311 is OUT1, the output signal of the second strobe 4312 is OUT2, and the output signal of the third strobe 4313 is OUT3.

[0167] The second type of strobe 432 is a 3-to-1 function, controlled by Data[4:3], and selects one of OUT1, OUT2 and OUT3 to output. The finally output voltage signal enters the clock selection module 44. The clock selection module 44 generates clock signals of different frequencies according to different input voltages. The clock signal is output after passing through the operational amplifier module, and can be played through the wired earphone or the buzzer.

[0168] The beat counter 42 receives the Data[2:0] and counts the beats at 4 times (or other times) of the data value. During the counting, the system plays the current scale. When the counting is finished, the beat counter 42 makes the flag signal JP_END appear a low level pulse. When the JP_END low level enters the read address counter 24, it prompts the read address counter to add 1, and then the storage module 30 outputs the next address data, and the system starts to play the next scale. This cycle is repeated. The length of time for each scale to be played is controlled by the Data[2:0]. During the JP_END high level, the read address counter 24 remains unchanged and does not add 1.

[0169] Taking 2 beats / 1 beat / 3 beats as an example, the data is amplified by 4 times, and the beat counter threshold values are 8, 4 and 12 respectively, and the waveform is as shown in Figure 10

[0170] The system architecture of the audio playing system 1000 provided by the embodiment of the present application utilizes the coil 200 to receive the wireless power supply and signal, converts the clock signal through the clock extraction module 300, stabilizes the power supply through the power supply module 400, and comprises the demodulation circuit 10, the read-write control module 20, the storage module 30 and the audio playing module 40, so as to realize the flexible, thin, small and delicate audio playing solution. The demodulation circuit 10 can ensure correct data reception, the read-write control module 20 can accurately control data reading and writing, the storage module 30 can store audio data, and the audio playing module 40 can accurately control audio playing according to the stored data, thereby providing high-quality audio playing experience. The whole system architecture can be refined into an array mask layout, so as to facilitate the production of light, thin and soft products, and there is no need for wired connection, which greatly improves the convenience and flexibility of use.

[0171] In another example, as shown in Figure 11 , the first type of scale signal end, the second type of scale signal end and the third type of scale signal end of the audio playing system 1000 are configured with clock signals of different frequencies. The system architecture is further optimized, the efficiency and response speed of audio playing are improved, and the flexibility and high-quality audio playing experience of the system are maintained.

[0172] It should be noted that, Figure 11 The difference between Figure 8 lies in that each analog voltage becomes a clock circuit, and the lower clock selection module 44 of the second type of gate 432 is cancelled, so that the second type of gate 432 is directly connected with the operational amplifier module 50.

[0173] ​It should be understood that, in the embodiments of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. It should also be understood that the determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0174] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A demodulation circuit, characterized in that, include: The demodulation module has its input terminal electrically connected to the amplitude modulation signal terminal, and is used to extract the target serial signal from the amplitude modulation signal transmitted from the amplitude modulation signal terminal in response to the first clock signal and output it. A shift register, whose input is electrically connected to the output of the demodulation module, is used to convert the target serial signal into a parallel signal with N branches in response to the first clock signal and output it, where N is a positive integer greater than 1. The clock conversion module has its input terminal electrically connected to the output terminal of the shift register, and is used to generate and output a second clock signal. The clock frequency of the second clock signal is 1 / N of the clock frequency of the first clock signal. The first buffer has its control terminal electrically connected to the output terminal of the clock conversion module, its input terminal electrically connected to the output terminal of the shift register, and its output terminal serving as the signal output terminal of the demodulation circuit, used to capture the target parallel signal in response to the second clock signal.

2. The demodulation circuit according to claim 1, characterized in that, The clock conversion module includes: The data packet header recognition module, whose input terminal serves as the input terminal of the clock conversion module, is used to identify preset packet header information in the parallel signal output by the shift register; The frequency division counting module has its input terminal electrically connected to the output terminal of the data packet header recognition module, and its output terminal serves as the output terminal of the clock conversion module. It is used to perform cyclic counting according to the clock period of the first clock signal as the counting unit when the data packet header recognition module recognizes the preset packet header information, so as to obtain the second clock signal. Preferably, the counting range of the cyclic counter is 0 to N-1; Preferably, the transistor in the demodulation circuit is a thin-film transistor.

3. An audio playback device, characterized in that, Includes the demodulation circuit as described in claim 1 or 2, and: The input terminal of the read / write control module is electrically connected to the signal output terminal of the demodulation circuit. The storage module has its data transmission terminal electrically connected to the data transmission terminal of the read / write control module, and its address input terminal electrically connected to the address output terminal of the read / write control module. An audio playback module has its input terminal electrically connected to the output terminal of the read / write control module, its first output terminal electrically connected to the read address control terminal of the read / write control module, and its second output terminal serving as a music playback terminal. The read / write control module is used to write the target parallel signal output by the demodulation circuit into the storage module during the data receiving stage, and is also used to read the target parallel signal from the storage module and transmit it to the audio playback module during the audio playback stage.

4. The audio playback device according to claim 3, characterized in that, The read / write control module includes: The data line selector has its input terminal serving as the input terminal of the read / write control module, its data transmission terminal being electrically connected to the data transmission terminal of the storage module, and its output terminal serving as the output terminal of the read / write control module. During the data receiving phase, the data line selector is used to transmit the target parallel signal connected to its input terminal to its data transmission terminal, so that the target parallel signal at its data transmission terminal is written into the storage module. During the audio playback phase, the data line selector is used to read the target parallel signal from the storage module through its data transmission end, and to transmit the target parallel signal to the audio playback module through its output end; The address line selector, whose output terminal serves as the address output terminal of the read / write control module; Write the address counter, the output of which is electrically connected to the first input of the address line selector; The address read counter has its output terminal electrically connected to the second input terminal of the address line selector, and its address read control terminal is electrically connected to the first output terminal of the audio playback module. During the data receiving phase, the address line selector is used to transmit the write address information output by the write address counter connected to its first input terminal to its address output terminal, so that its address output terminal transmits the write address information to the storage module. During the audio playback phase, the address line selector is used to transmit the read address information output by the read address counter connected to its second input terminal to its address output terminal, so that its address output terminal transmits the read address information to the storage module. Preferably, the output of the clock conversion module in the demodulation circuit is also electrically connected to the control terminal of the data line selector to provide a data writing clock signal; Preferably, the transistor in the audio playback device is a thin-film transistor.

5. The audio playback device according to claim 3, characterized in that, The audio playback module includes: The second buffer has its input terminal serving as the input terminal of the audio playback module; A beat counter, the input of which is electrically connected to the first type of output of the second buffer, and the output of which serves as the first output of the audio playback module; A multiplexer, the control terminal of which is electrically connected to the second type of output terminal of the second buffer, and its output terminal serves as the second output terminal of the audio playback module; The second buffer is used to split the target parallel signal to obtain beat count information, scale information and segment information, and output the beat count information through its first type of output terminal, and output the scale information and segment information through its second type of output terminal; Preferably, the counting cutoff point of the beat counter is greater than or equal to the number of beats.

6. The audio playback device according to claim 5, characterized in that, The second type of output terminal of the second buffer includes a first sub-output terminal and a second sub-output terminal; the multiplexer includes: The first type of multiplexer has its control terminal electrically connected to the first sub-output terminal of the second buffer, and its input terminal electrically connected to the pitch signal terminal. The second type of multiplexer has its control terminal electrically connected to the second sub-output terminal of the second buffer, its input terminal electrically connected to the output terminal of the first type of multiplexer, and its output terminal serving as the output terminal of the multiplexer.

7. The audio playback device according to claim 6, characterized in that, The first type of multiplexer includes: The first selector has its input terminal electrically connected to the first type of pitch signal terminal, its control terminal electrically connected to the first sub-output terminal of the second buffer, and its output terminal electrically connected to the first input terminal of the second type of multiplexer. The second selector has its input terminal electrically connected to the second type of pitch signal terminal, its control terminal electrically connected to the first sub-output terminal of the second buffer, and its output terminal electrically connected to the second input terminal of the second type of multiplexer. The third selector has its input terminal electrically connected to the third type of pitch signal terminal, its control terminal electrically connected to the first sub-output terminal of the second buffer, and its output terminal electrically connected to the third input terminal of the second type of multiplexer.

8. The audio playback device according to claim 7, characterized in that, The first type of scale signal terminal, the second type of scale signal terminal, and the third type of scale signal terminal are configured to input clock signals of different frequencies; Alternatively, the first type of scale signal terminal, the second type of scale signal terminal, and the third type of scale signal terminal are configured to input different analog voltage signals; The audio playback module further includes a clock selection module, whose input terminal is electrically connected to the output terminal of the multiplexer, and whose output terminal serves as the second output terminal of the audio playback module.

9. The audio playback device according to claim 3, characterized in that, Also includes: The operational amplifier module has its input terminal electrically connected to the second output terminal of the audio playback module, and its output terminal serves as the music playback terminal of the audio playback device.

10. An audio playback system, characterized in that, include: The coil has a first output terminal for outputting a periodic clock signal, a second output terminal for outputting an AC power signal, and a third output terminal for serving as an amplitude modulation signal terminal. A clock extraction module, whose input terminal is electrically connected to the first output terminal of the coil, is used to extract a first clock signal based on the periodic clock signal; A power module, whose input terminal is electrically connected to the second output terminal of the coil, is used to rectify the AC power signal to obtain a logic power signal; And the audio playback device as described in any one of claims 3 to 9.

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