Chip, semiconductor device, and electronic apparatus

Abstract

The invention relates to a chip, a semiconductor device and electronic equipment, the chip comprises a chip body and an annular structure, the annular structure is arranged around the outer circumference of the chip body, and the annular structure comprises a first metal interconnection structure, a substrate and a second metal interconnection structure which are stacked in the thickness direction of the annular structure; wherein the substrate is provided with a connecting hole, and the connecting hole is connected with the first metal interconnection structure and the second metal interconnection structure. According to the technical scheme, the chip provided by the invention can ensure that the chip has a relatively high stress supporting effect and a relatively high heat dissipation effect, so that the chip can stably run at a safe temperature in a high-performance manner.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a chip, semiconductor device, and electronic device. Background Technology

[0002] In related technologies, improving the heat dissipation and reliability of chips to ensure their high-performance operation has become a research goal for industry professionals. Summary of the Invention

[0003] The purpose of this disclosure is to provide a chip, semiconductor device, and electronic device, which has high stress support and heat dissipation effects, and can ensure that the chip operates stably and with high performance at a safe temperature.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a chip comprising: The chip itself; and A ring structure is arranged around the outer periphery of the chip body. The ring structure includes a first metal interconnect structure, a substrate, and a second metal interconnect structure stacked along its own thickness direction. The substrate has a connection hole that connects to the first metal interconnect structure and the second metal interconnect structure.

[0005] Optionally, the connection hole is constructed as a through-silicon via (TSV), which extends along the thickness direction of the substrate and penetrates the substrate, and the first metal interconnect structure and the second metal interconnect structure are connected through the TSV.

[0006] Optionally, the substrate is provided with a plurality of connection holes, which are arranged in a circular pattern around the outer periphery of the chip body and spaced apart.

[0007] Optionally, a first contact portion is formed at the connection between the first metal interconnect structure and the connecting hole, and the structural dimensions of the first contact portion are larger than the structural dimensions of the connecting hole; and / or, A second contact portion is formed at the connection between the second metal interconnect structure and the connection hole, and the structural dimensions of the second contact portion are larger than the structural dimensions of the connection hole.

[0008] Optionally, the number of the first contact portions is one or more, and a single first contact portion covers at least one of the connecting holes; and / or, The number of the second contact portion is one or more, and a single second contact portion covers at least one of the connection holes.

[0009] Optionally, the number of the first contact portions is multiple, and each first contact portion covers a corresponding connection hole; and / or, The number of the second contact portions is multiple, and each second contact portion covers a corresponding connection hole.

[0010] Optionally, the first metal interconnect structure includes a first wiring layer, a second wiring layer, and a third wiring layer stacked along the thickness direction of the annular structure, wherein the third wiring layer is located between the second wiring layer and the substrate, and the first contact portion is formed on the side of the third wiring layer facing the substrate; and / or, The second metal interconnect structure includes a fourth wiring layer, the substrate is located between the fourth wiring layer and the first metal interconnect structure, and the fourth wiring layer has a second contact portion formed on the side facing the substrate.

[0011] Optionally, the first metal interconnect structure further includes a metal protective layer connected to the side of the first wiring layer opposite to the second wiring layer.

[0012] Optionally, the substrate is provided with a first dielectric layer and a second dielectric layer at both ends along the thickness direction of the annular structure, wherein the first dielectric layer contains the first metal interconnect structure and the second dielectric layer contains the second metal interconnect structure.

[0013] A second aspect of this disclosure provides a semiconductor device including the chip provided in the first aspect.

[0014] A third aspect of this disclosure provides an electronic device including the semiconductor device provided in the second aspect above.

[0015] Through the aforementioned technical solution, namely the chip provided in this disclosure, the chip, by arranging a ring structure around the outer periphery of the chip body, can achieve protection of the chip body and provide stress support. This reduces the possibility of internal chip damage due to stress during chip packaging, for example, thus improving chip packaging yield. Furthermore, since the ring structure includes a first metal interconnect structure, a substrate, and a second metal interconnect structure stacked along its thickness direction, and the substrate has connection holes connecting the first and second metal interconnect structures, this arrangement improves the overall structural reliability of the chip, ensuring a high stress support effect. This facilitates meeting the design application requirements of high-density chip packaging in scenarios such as 3DIC (three-dimensional integrated circuit). Additionally, since the first and second metal interconnect structures are connected through connection holes, the heat generated during chip operation can be simultaneously transferred to the metal interconnect structures on both sides (e.g., the first and second metal interconnect structures), achieving vertical heat conduction along the thickness direction of the ring structure. This helps ensure a high heat dissipation effect, ensuring stable and high-performance operation of the chip at a safe temperature.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a chip provided in an exemplary embodiment of this disclosure, wherein the arrangement of multiple connection holes is illustrated exemplary. Figure 2 This is a schematic diagram showing the connection hole of the chip and the third wiring layer provided in an exemplary embodiment of this disclosure; Figure 3 yes Figure 1 A cross-sectional schematic diagram at position AA in the middle, wherein, by way of example, a first metal interconnect structure, a substrate, and a second metal interconnect structure are arranged in a stacked manner.

[0018] Explanation of reference numerals in the attached figures 1-Chip body; 2-Ring structure; 210-First metal interconnect structure; 211-First contact portion; 212-First wiring layer; 213-Second wiring layer; 214-Third wiring layer; 215-Metal protective layer; 220-Substrate; 230-Second metal interconnect structure; 231-Second contact portion; 232-Fourth wiring layer; 240-Connection hole; 250-First dielectric layer; 260-Second dielectric layer; 270-First region; 280-Second region. Detailed Implementation

[0019] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0020] In this disclosure, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower dimensions within the space of the chip when it is in use. "Inner" and "outer" refer to the inner and outer dimensions relative to the outline of the component or structure itself. Furthermore, it should be noted that terms such as "first" and "second" are used to distinguish one element from another and do not indicate sequence or importance. Additionally, in the description with reference to the accompanying drawings, the same reference numerals in different drawings denote the same elements.

[0021] According to a first aspect of this disclosure, a chip is provided, with reference to... Figures 1 to 3 As shown, the chip includes a chip body 1 and a ring structure 2. The ring structure 2 is arranged around the outer periphery of the chip body 1. The ring structure 2 includes a first metal interconnect structure 210, a substrate 220 and a second metal interconnect structure 230 stacked along its own thickness direction. The substrate 220 is provided with a connection hole 240, which is connected to the first metal interconnect structure 210 and the second metal interconnect structure 230.

[0022] Through the above-described technical solution, namely the chip provided in this disclosure, the chip, by arranging the annular structure 2 around the outer periphery of the chip body 1, can achieve the function of protecting the chip body 1 and providing stress support. Thus, during chip packaging, for example, the possibility of internal chip damage due to stress can be reduced, improving chip packaging yield. Furthermore, since the annular structure 2 is configured to include a first metal interconnect structure 210, a substrate 220, and a second metal interconnect structure 230 stacked along its own thickness direction, and the substrate 220 is provided with connection holes 240 connecting the first metal interconnect structure 210 and the second metal interconnect structure 230, this arrangement can improve, for example, the overall structural reliability of the chip and ensure a high stress support effect. Therefore, in design scenarios such as 3DIC (three-dimensional integrated circuit), it is convenient to meet the design application requirements of high-density chip packaging. In addition, since the first metal interconnect structure 210 and the second metal interconnect structure 230 are connected through the connection hole 240, the heat generated during chip operation can be transferred to the metal interconnect structures on both sides (e.g., the first metal interconnect structure 210 and the second metal interconnect structure 230) at the same time, so as to conduct heat up and down along the thickness direction of the ring structure 2, which is beneficial to ensure a high heat dissipation effect and ensure that the chip operates stably and with high performance at a safe temperature.

[0023] It should be noted that the chip body 1 and the ring structure 2 can be integrally formed. The purpose is to ensure that the ring structure 2 is stably connected to the chip body 1 and positioned around its outer periphery, thereby ensuring stable and high-performance operation of the chip at a safe temperature. The specific forming process can be carried out using any suitable forming method in the art, and will not be elaborated upon here. Furthermore, Figure 3 The arrows in the diagram exemplify the direction of heat transfer.

[0024] In some possible implementations, refer to Figure 3As shown, the connection hole 240 can be constructed as a through-silicon via (TSV). That is, the substrate 220 can be, for example, a silicon substrate, and the through-silicon via (TSV) extends along the thickness direction of the substrate 220 and penetrates the substrate 220. The first metal interconnect structure 210 and the second metal interconnect structure 230 are connected through the through-silicon via (TSV). In this way, by setting the through-silicon via (TSV), in a design scenario such as 3DIC (three-dimensional integrated circuit), the first metal interconnect structure 210 and the second metal interconnect structure 230, which are vertically stacked along the thickness direction of the ring structure 2, can be directly connected vertically through the through-silicon via (TSV). This can not only improve the overall structural reliability of the chip and ensure a high stress support effect, but also effectively shorten the heat transfer path between the first metal interconnect structure 210 and the second metal interconnect structure 230, making it easier to conduct heat vertically along the thickness direction of the ring structure 2. This is beneficial to ensuring a high heat dissipation effect and ensuring that the chip operates stably and with high performance at a safe temperature.

[0025] It should be noted that a through-silicon via (TSV) can be a via directly formed on a substrate 220 (e.g., a silicon wafer) of a chip, and filled with a thermally conductive material (e.g., including but not limited to copper). This allows the copper-filled via to connect the first metal interconnect structure 210 and the second metal interconnect structure 230. Since the copper-filled via has high support strength, it can improve the overall structural reliability of the chip and ensure a high stress support effect. Furthermore, filling the via with a thermally conductive material such as copper can efficiently transfer the heat generated during chip operation to both metal interconnect structures (e.g., the first metal interconnect structure 210 and the second metal interconnect structure 230) simultaneously, achieving vertical heat conduction along the thickness direction of the annular structure 2. This facilitates the rapid dissipation of heat accumulated inside the chip to the outside, ensuring high stress support and heat dissipation, and guaranteeing stable and high-performance operation of the chip at a safe temperature.

[0026] In addition, since the through silicon via (TSV) extends along the thickness direction of the substrate 220 and penetrates the substrate 220, it is convenient to connect the first metal interconnect structure 210 and the second metal interconnect structure 230 through a shorter path. That is, the vertical connection channel formed by the through silicon via (TSV) extends vertically from, for example, the side where the first metal interconnect structure 210 is located to the side where the second metal interconnect structure 230 is located, thereby achieving the purpose of connecting the first metal interconnect structure 210 and the second metal interconnect structure 230, ensuring that the chip operates stably and with high performance at a safe temperature.

[0027] Furthermore, the specific embodiment of the substrate 220 being a silicon substrate is exemplary. In other alternative embodiments, the substrate 220 may also be a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate. Those skilled in the art can adapt the design according to actual application requirements. The purpose is to ensure that, for example, the chip has a high stress support effect and heat dissipation effect by adding the above-mentioned connection hole 240 on the substrate 220, so as to ensure that the chip operates stably and with high performance at a safe temperature.

[0028] In some possible implementations, refer to Figure 1 As shown, a plurality of connection holes 240 can be provided on the substrate 220. The plurality of connection holes 240 are arranged in a ring around the outer periphery of the chip body 1 and are spaced apart. This arrangement can ensure that the chip has a high stress support effect and heat dissipation effect, and ensure that the chip operates stably and with high performance at a safe temperature.

[0029] This disclosure does not specify the exact number of the multiple connection holes 240, the structural shape and size of each connection hole 240, or the spacing between any two adjacent connection holes 240. Those skilled in the art can design them adaptively according to actual application requirements.

[0030] In order to improve the overall reliability of the chip, in some possible implementations, reference is made to... Figure 2 and Figure 3 As shown, a first contact portion 211 can be formed at the connection between the first metal interconnect structure 210 and the connection hole 240. The structural size of the first contact portion 211 is larger than the structural size of the connection hole 240. In this way, by making the structural size of the first contact portion 211 larger than the structural size of the connection hole 240, the connection between the first metal interconnect structure 210 and the connection hole 240 is ensured to have a high supporting structural strength, which can ensure that the chip has a high stress support effect and heat dissipation effect, so as to achieve the purpose of stable and high-performance operation of the chip at a safe temperature.

[0031] For example, such as Figure 2 and Figure 3 As shown, the position of the first contact portion 211 can be configured to be opposite to the position of the connecting hole 240, and in the direction perpendicular to the thickness of the annular structure 2 (refer to...). Figure 3 The first direction (refer to the top and bottom directions of the middle image) Figure 1 The left and right directions of the middle picture or Figure 1In the vertical direction of the middle drawing, the structural size of the first contact portion 211 is larger than the structural size of the connection hole 240, ensuring that the connection between the first metal interconnect structure 210 and the connection hole 240 has a high supporting structural strength, which can ensure that the chip has a high stress support effect and heat dissipation effect, so as to achieve the purpose of the chip operating stably and with high performance at a safe temperature.

[0032] Additionally, in some implementations, references Figure 2 and Figure 3 As shown, a second contact portion 231 can be formed at the connection between the second metal interconnect structure 230 and the connection hole 240. The structural size of the second contact portion 231 is larger than the structural size of the connection hole 240. By arranging the second contact portion 231 to be larger than the structural size of the connection hole 240, the connection between the second metal interconnect structure 230 and the connection hole 240 is ensured to have high structural strength. This ensures that the chip has high stress support and heat dissipation effects, achieving the goal of stable and high-performance operation of the chip at a safe temperature.

[0033] For example, such as Figure 2 and Figure 3 As shown, the second contact portion 231 can be configured to be positioned opposite to the connection hole 240, and in the direction perpendicular to the thickness of the annular structure 2 (refer to...). Figure 3 The first direction (refer to the top and bottom directions of the middle image) Figure 1 The left and right directions of the middle picture or Figure 1 In the vertical direction of the middle drawing, the structural size of the second contact portion 231 is larger than the structural size of the connection hole 240, ensuring that the connection between the second metal interconnect structure 230 and the connection hole 240 has a high supporting structural strength, which can ensure that the chip has a high stress support effect and heat dissipation effect, so as to achieve the purpose of the chip operating stably and with high performance at a safe temperature.

[0034] In some possible implementations, the number of first contact portions 211 can be one or more, and a single first contact portion 211 covers at least one connection hole 240. This arrangement is to ensure that the chip has a high stress support effect and heat dissipation effect, so that the chip can operate stably and with high performance at a safe temperature.

[0035] Exemplarily, in some implementations, reference is made to Figure 1 and Figure 2 As shown, there can be multiple first contact portions 211, each covering a corresponding connection hole 240. This arrangement ensures that the chip has high stress support and heat dissipation effects, while also simplifying the overall chip structure and meeting the requirements for lightweight chip design. This disclosure is not limited thereto.

[0036] In addition, in some possible implementations, the number of second contact portions 231 may be one or more, and a single second contact portion 231 may cover at least one connection hole 240. This arrangement is to ensure that the chip has a high stress support effect and heat dissipation effect, so that the chip can operate stably and with high performance at a safe temperature.

[0037] For example, in some embodiments, there may be multiple second contact portions 231, each second contact portion 231 covering a corresponding connection hole 240. This arrangement ensures that the chip has a high stress support effect and heat dissipation effect, while also simplifying the overall chip structure and meeting the requirements of lightweight chip design. This disclosure is not limited thereto.

[0038] In some possible implementations, refer to Figure 3 As shown, the first metal interconnect structure 210 may include a first wiring layer 212, a second wiring layer 213, and a third wiring layer 214 stacked along the thickness direction of the annular structure 2. The third wiring layer 214 is located between the second wiring layer 213 and the substrate 220, and a first contact portion 211 is formed on the side of the third wiring layer 214 facing the substrate 220. By constructing the first metal interconnect structure 210 with a multi-layer wiring structure, the physical protection capability of the annular structure 2 can be improved, thereby increasing the structural strength of the annular structure 2. This is beneficial for improving, for example, the overall reliability of the chip structure and ensuring a high stress support effect. In addition, by forming the first contact portion 211 on the side of the third wiring layer 214 facing the substrate 220 near the connection hole 240, the integrity and reliability of the connection between the first metal interconnect structure 210 and the connection hole 240 are facilitated.

[0039] Those skilled in the art can adapt the specific structure of the first contact portion 211 according to actual application requirements. For example, in some embodiments, refer to Figure 2 As shown, the first contact portion 211 can be constructed in, for example, a rectangular block shape, and the corresponding connection hole 240 can be constructed in, for example, a circular hole shape. In this way, by covering the corresponding circular hole-shaped connection hole 240 with the rectangular block-shaped first contact portion 211, the integrity and reliability of the connection between the first metal interconnect structure 210 and the connection hole 240 are ensured, while also facilitating on-site processing and fabrication.

[0040] Additionally, in some possible implementations, refer to Figure 3As shown, the second metal interconnect structure 230 may include a fourth wiring layer 232, and a substrate 220 is located between the fourth wiring layer 232 and the first metal interconnect structure 210. The fourth wiring layer 232 has a second contact portion 231 on the side facing the substrate 220. This arrangement ensures the integrity and reliability of the connection between the second metal interconnect structure 230 and the connection hole 240. Since the second metal interconnect structure 230 is usually located, for example, on the back of the chip, compared to the first metal interconnect structure 210 located, for example, on the front of the chip, the second metal interconnect structure 230 usually adopts a thicker structural design. Therefore, by constructing the second metal interconnect structure 230 as a single-layer wiring layer structure, it is possible to ensure high-strength physical support, simplify the design complexity of the chip, and ensure that the chip has a high stress support effect and heat dissipation effect.

[0041] Those skilled in the art can adapt the specific structure of the second contact portion 231 according to the actual application requirements. For example, in some embodiments, the second contact portion 231 can also be constructed in the form of a rectangular block, and the corresponding connection hole 240 can be constructed in the form of a circular hole. In this way, by covering the corresponding circular hole-shaped connection hole 240 with the rectangular block-shaped second contact portion 231, the integrity and reliability of the connection between the second metal interconnect structure 230 and the connection hole 240 are ensured, while also facilitating on-site processing and preparation.

[0042] It should be noted that this disclosure does not specifically limit the specific structure and material of the aforementioned wiring layers (e.g., the first wiring layer 212, the second wiring layer 213, the third wiring layer 214, and the fourth wiring layer 232). Those skilled in the art can adapt the design according to actual application requirements. For example, the wiring layers can all be constructed as, for example, copper layers, and refer to... Figure 2 As shown, the first region 270 of the wiring layer near the chip body 1 can be designed with a relatively small and dense overall structure, while the second region 280 far from the chip body 1 can be designed with a relatively thick and sparse overall structure, to ensure high heat dissipation and stress support, which is conducive to ensuring that the chip operates stably and with high performance at a safe temperature.

[0043] Additionally, refer to Figure 2 As shown, the positions of the first contact portion 211 and the second contact portion 231 can be set in the corresponding wiring layer, for example, the second region 280, to ensure the integrity and reliability of the connection and facilitate on-site processing and fabrication.

[0044] In some possible implementations, refer to Figure 3As shown, the first metal interconnect structure 210 may further include a metal protective layer 215. The metal protective layer 215 is connected to the side of the first wiring layer 212 away from the second wiring layer 213. Thus, by setting the metal protective layer 215, the wiring layer located in the first metal interconnect structure 210 on, for example, the front side of the chip can be protected and stress can be borne, ensuring that the chip operates with high performance.

[0045] The metal protective layer 215 may include, but is not limited to, an aluminum wire layer, to ensure a high level of protection and facilitate on-site processing and preparation.

[0046] Additionally, in some possible implementations, refer to Figure 3 As shown, a first dielectric layer 250 and a second dielectric layer 260 can be respectively disposed at both ends of the substrate 220 along the thickness direction of the annular structure 2. The first dielectric layer 250 is provided with a first metal interconnect structure 210, and the second dielectric layer 260 is provided with a second metal interconnect structure 230. This arrangement can ensure that the annular structure 2 has high structural strength, realize the protection of the chip body 1, and has high reliability, which is conducive to meeting the design requirements of high-density chip packaging.

[0047] It should be noted that the first dielectric layer 250 and the second dielectric layer 260 can be formed by dielectric materials such as, but not limited to, silicon dioxide. In addition, the specific fabrication process of forming the first metal interconnect structure 210 and the second metal interconnect structure 230 in the dielectric layer (e.g., the first dielectric layer 250 and the second dielectric layer 260) can be formed by any suitable fabrication process in the art, and will not be described in detail here.

[0048] According to a second aspect of this disclosure, a semiconductor device is provided, comprising the chip provided in the first aspect. Furthermore, the semiconductor device also possesses all the beneficial effects of the chip provided in the first aspect, which will not be elaborated further herein.

[0049] According to a third aspect of this disclosure, an electronic device is provided, which includes the semiconductor device provided in the second aspect above. Furthermore, the electronic device also possesses all the beneficial effects of the semiconductor device provided in the second aspect above, which will not be elaborated further herein.

[0050] In some possible implementations, the aforementioned electronic device may be, for example, a mobile phone, a personal computer, a server, a computing device, a smart car, etc. This disclosure is not limited thereto.

[0051] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0052] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0053] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A chip, characterized by The chip comprises: a chip body; and a ring structure arranged around the outer periphery of the chip body, the ring structure comprising a first metal interconnection structure, a substrate and a second metal interconnection structure arranged in a stacked manner along the thickness direction of the ring structure; wherein the substrate is provided with a connecting hole connected to the first metal interconnection structure and the second metal interconnection structure. The connecting hole is configured as a through silicon via extending along the thickness direction of the substrate and penetrating through the substrate, and the first metal interconnection structure and the second metal interconnection structure are connected through the through silicon via.

2. The chip according to claim 1, characterized in that, The substrate is provided with a plurality of connecting holes arranged in a circle around the outer periphery of the chip body and spaced apart.

3. The chip according to claim 1 or 2, characterized in that, The first metal interconnection structure and the connecting hole are formed with a first contact portion, and the structural size of the first contact portion is greater than that of the connecting hole; and / or 4. The chip of claim 1, wherein The second metal interconnection structure and the connecting hole are formed with a second contact portion, and the structural size of the second contact portion is greater than that of the connecting hole. The number of the first contact portions is one or more, and a single first contact portion covers at least one connecting hole; and / or 5. The chip of claim 4, wherein, The number of the second contact portions is one or more, and a single second contact portion covers at least one connecting hole. The number of the first contact portions is a plurality, and each first contact portion covers a corresponding connecting hole; and / or 6. The chip of claim 5, wherein, The number of the second contact portions is a plurality, and each second contact portion covers a corresponding connecting hole. The first metal interconnection structure comprises a first wiring layer, a second wiring layer and a third wiring layer arranged in a stacked manner along the thickness direction of the ring structure, the third wiring layer is located between the second wiring layer and the substrate, and the side of the third wiring layer facing the substrate is formed with the first contact portion; and / or 7. The chip of claim 4, wherein The second metal interconnection structure comprises a fourth wiring layer, the substrate is located between the fourth wiring layer and the first metal interconnection structure, and the side of the fourth wiring layer facing the substrate is formed with the second contact portion. The first metal interconnection structure further comprises a metal protection layer connected to the side of the first wiring layer away from the second wiring layer.

8. The chip of claim 7, wherein, The substrate is provided with a first dielectric layer and a second dielectric layer at both ends along the thickness direction of the ring structure, wherein the first metal interconnection structure is arranged in the first dielectric layer, and the second metal interconnection structure is arranged in the second dielectric layer.

9. The chip of claim 1, wherein, The chip comprises any one of claims 1-9.

10. A semiconductor device, characterized by comprising: The semiconductor device comprises claim 10.

11. An electronic device, comprising: ​

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