Laser alignment and support clamp

Abstract

An apparatus comprising (a) a distributed feedback laser (DFL), (b) a photonic integrated circuit (PIC) comprising a PIC trench within which the DFL is positioned, (c) PIC trench contacts formed within the PIC trench, (d) an adapter wherein the adapter is attached to a region of the PIC and the DFL using one or more bonding elements, and (e) one or more traps, and an adapter for receiving excess bonding material formed during attachment of the adapter to at least one of the areas of the DFL and the PIC, and preventing the excess bonding material from electrically coupling the DFL distal contact to the DFL proximal contact.

Description

Background of the Invention

[0001] There is an increasing need to attach lasers to photonic integrated circuits (ICs).

[0002] Figure 1 An example of a distributed feedback (DFB) laser attached to a photonic integrated circuit (PIC) is shown.

[0003] The DFB laser (DFL)20 is an electrically bipolar diode with a typical thickness of 100 μm.

[0004] DFL20 includes DFL distal contact 21, DFL proximal contact 22, DFL body (or core) 27, and laser waveguide 23.

[0005] The first wire bonding 11 is connected to the DFL distal contact 21.

[0006] Conductive bonding material 36 is used to attach DFL proximal contact 22.

[0007] The second lead junction 12 is connected to a metallized pad 34 (formed on the PIC), which is electrically coupled to the DFL proximal contact 22.

[0008] A refractive index matching material 30 is located between the DFL and the sidewalls formed within the PIC. The PIC includes a PIC waveguide 32 aligned with the DFL waveguide 23.

[0009] The cross-sectional view (cut along plane AA) shows that, due to the attachment of the DFL to the PIC, there is an excess of bonding material 36-1 that electrically couples the distal contact 21 of the DFL to the proximal contact 22 of the DFL.

[0010] Figure 1 The arrangement has some drawbacks: a. The area on top of the DFL available for picking up and placing tools is very small, approximately 200μm × 600μm, thus requiring expensive holding tools.

[0011] b. It is nearly impossible to test DFL using standard methods before assembly, therefore it is impossible to pick out faulty lasers.

[0012] c. Wire joints are detrimental to DFLs and often lead to defects in laser waveguides and their operation.

[0013] d. When the laser anode is placed with its anode facing upward (the laser anode may include or be coupled to the DFL distal contact 21), there is a temperature difference from the top to the bottom of the DFL, which results in mechanical stress and thus the laser is prone to mode hopping and degraded relative intensity noise (RIN) that is harmful to optical signals used, for example, in optical communications.

[0014] e. When the laser anode is placed "face down" (as opposed to...) Figure 1 (As shown in the reverse position), while improving heat dissipation, the bonding material is highly likely to short-circuit the laser at the sidewalls because the distance from the top of the laser (anode) to the waveguide where a short circuit might occur is on the order of several micrometers. Therefore, laser operation is hindered.

[0015] Furthermore, when attaching the laser to the electrical contacts, there is a risk of excessive bonding material creeping up the sides of the laser (see Figure 36-1). Due to the vertical structure of the DFB, the close proximity of the P and N contacts, and the singulation process that exposes the N contacts at the sidewalls, this excessive bonding material creepage poses a risk of creating an electrical short circuit between the two polarities of the laser. See also Figure 2 The cross section AA in the middle.

[0016] As mentioned above, the use of small lasers leads to testing problems. DFB laser screening tests performed at the supplier are insufficient to predict yield losses and resolve early failures. Testing laser devices at the bare die level is impractical due to the inherently high thermal resistance between the very small die and the substrate of the test fixture it rests on.

[0017] Therefore, after a DFB laser is combined with a PIC (a chip consisting of the laser and the coupled PIC-photonics IC), laser performance and aging tests are typically performed at the chip level.

[0018] For the reasons mentioned above, some yield loss at the chip level is to be expected, especially for applications that integrate multiple DFB laser sources, such as DR8 or CWDM TX applications.

[0019] DFB laser screening tests conducted at the supplier are insufficient to predict yield loss and address early failures.

[0020] Testing laser devices at the bare die level is impractical due to the inherently high thermal resistance between the very small die and the substrate of the test fixture on which it rests.

[0021] In addition, there is the issue of trench metallization. In order to integrate a DFB laser within the laser trench, metal contacts must be fabricated within the trench.

[0022] Fabricating metal contacts within laser trenches is extremely difficult due to the inherent trenches within the wafer. Standard CMOS processes require masking, photolithography, metallization, and cleaning. All of these processes carry an inherent risk of wafer contamination, which can be catastrophic and lead to complete wafer failure. This contamination is also difficult to detect, as even particles on the tens of nanometer scale can cause device malfunction.

[0023] Below are some examples of existing literature. These are considered irrelevant: U.S. Patent 10,976,488, U.S. Patent 11,163,126, U.S. Patent 5,544,184, and Packaging of Laser Bars, K. BOUCKE, 2011, DOI:10.1007 / 978-3-642-14177-5_13. Brief description of the attached diagram

[0024] The subject matter of the invention is specifically pointed out and clearly claimed at the end of the specification. However, the organization and operation of the invention, as well as its objects, features, and advantages, can be best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 An example of the existing technology DFL attached to a photonic IC is shown; Figures 3-6 Examples of DFLs and devices are shown; and Figure 7 The test of DFL is shown. Detailed description of the attached figures

[0025] The term "proximal" refers to the area closer to the photonic integrated circuit (PIC), while "far-side" refers to the area further away from the PIC. Figures 2-6 In the middle, the near side refers to the bottom, while the far side refers to the top.

[0026] According to an embodiment, an apparatus is provided, comprising: a. Distributed feedback laser (DFL), which includes a DFL waveguide and a DFL distal contact (see example...). Figure 6 (see attached figure 21) and DFL proximal contact (see, for example) Figure 6 (See figure 22).

[0027] b. Photonic integrated circuits (PICs), which include PIC trenches (see example...) Figure 3 (See attached figure 81), where the DFL is positioned within the PIC groove.

[0028] c. PIC trench contacts formed within the PIC trench (see example) Figure 3 (See attached figure 82).

[0029] d. Interface (also known as a shim or clamp—see example) Figure 2 and Figure 3 (See reference numeral 60 in the figure), where when assembling the equipment—using one or more connecting elements (see, for example) Figure 3 The reference numerals 36, 73 and 36) attach the connector to the area of ​​the PIC and the DFL.

[0030] e. One or more traps for receiving excess bonding material formed during at least one of the areas of the connector being attached to the DFL and PIC, and for preventing the excess bonding material from electrically coupling the distal DFL contact to the proximal DFL contact.

[0031] According to an embodiment, the connector includes a first trapping portion (see example...). Figure 3 (Ref. 101 in the figure) The first trapping section is configured to receive excess bonding material formed during the attachment of the joint to the DFL.

[0032] According to an embodiment, the first trapping portion comprises one or more engaging recesses (see example...). Figure 3 The figure (reference numerals 61 and 62) is formed. The coupling includes a main protrusion attached to the distal contact of the DFL (see, for example...). Figure 2 (See attached figure 66) and the subprotrusions attached to the area of ​​the PIC (see, for example) Figure 3 (See figures 64 and 65).

[0033] According to an embodiment, the device includes a second collection unit (see example...). Figure 3 (Ref. 102 in the accompanying drawings) The second trapping section is configured to receive excess bonding material formed during the attachment of the joint to the PIC area.

[0034] According to an embodiment, the second trapping section includes a grating of metal and dielectric elements (see, for example...). Figure 5 (The grating elements in the figure - reference numerals 51, 52, 53 and 54).

[0035] According to an embodiment, the second collecting section includes one or more capillary conduits—the conduits are composed of… Figure 5 The dielectric element represented as 52 is formed.

[0036] According to an embodiment, the device includes a third collection unit (see example...). Figure 6 Reference numeral 103 in the figure is configured to receive excess bonding material formed during the attachment of the DFL to the PIC trench contact.

[0037] According to an embodiment, a third trapping section is formed in the PIC groove (see example...). Figure 6 In the accompanying drawing reference numeral 81), and including one or more additional recesses formed on one or more sides of the PIC groove contact (see, for example) Figure 6 (Figure reference numerals 88 and 89).

[0038] According to an embodiment, the connector includes a distal portion of the connector and a proximal portion of the connector electrically coupled to the distal portion of the connector, wherein the proximal portion of the connector is attached to the distal contact of the DFL.

[0039] According to an embodiment, the area of ​​the distal surface of the distal portion of the connector exceeds the area of ​​the DFL. This difference allows for easy access to the distal surface—even when the proximal surface is small. According to an embodiment, this difference facilitates the delivery of an electrical signal to the distal contact of the DFL and allows for easy testing of the DFL.

[0040] According to an embodiment, the device includes a refractive index matching material located between the DFL waveguide output and the PIC trench (see, for example...). Figure 6 (See attached figure 91).

[0041] According to an embodiment, the device includes a fourth collection unit (see example...). Figure 6 (Ref. 104 in the accompanying drawings), the fourth collecting section is configured to receive excess refractive index matching material formed during the provision of refractive index matching material. Figure 6 In this configuration, the fourth trapping section 104 includes sidewalls 99-1 and 99-2, which are located on both sides of the silicon fin 93 and spaced apart from it to form two cavities 98-1 and 98-2 for receiving excess refractive index matching material. The silicon fin includes a portion of a PIC waveguide.

[0042] According to an embodiment, the connector includes a distal portion of the connector, a main protrusion, and a secondary protrusion.

[0043] According to an embodiment, the primary and secondary protrusions extend from the distal portion (see, for example...). Figure 2 Reference numeral 65 extends from the figure. The distal portion 65 includes the distal surface 95-1. Figure 7 As shown, the DFL can be tested by contacting the distal surface before being attached to the PIC.

[0044] According to an embodiment, the main protrusion is longer than the secondary protrusion.

[0045] According to an embodiment, the lateral distance between the subprotrusions (measured from the center of the subprotrusion) exceeds the width of the PIC groove.

[0046] A solution (device and / or method) is provided regarding an adapter (such as a clamp) designed to help align and secure the DFL in its proper position on the PIC during the process of docking and coupling a tapered waveguide into the PIC.

[0047] Once applied, this solution repeatedly achieves high production line yield standards under various mechanical, temperature, and other environmental stresses, aligning the beam emitted from the side edge of the DFL into the PIC waveguide for high coupling efficiency without reducing coupling efficiency, without creating conditions for unacceptable mode jumps in the DFL, and most importantly, keeping the RIN at the required level.

[0048] To achieve this goal, high-precision pick-and-place tools were used.

[0049] After obtaining an acceptable alignment result, the process of attaching the DFL to its appropriate position in the PIC is then carried out.

[0050] Figure 2 This is an example of an adapter 60, which includes a distal portion 65 and a proximal portion. The distal portion 65 has a distal surface 65-1 that can be contacted by a probe. The proximal portion is closer to the DFL and includes a primary protrusion 66, secondary protrusions 64 and 65, and recesses or channels (such as side channels 61 and 62) formed between the protrusions.

[0051] Figure 2 DFL20 and bonding material 37 are also shown.

[0052] Figure 3 and Figure 4 The diagram shows a cross-sectional view and a top view of the DFL combined on the PIC. Figure 5 The second trapping section is shown (in) Figure 3 A cross-sectional view and a top view of a portion of (represented by 102).

[0053] Figure 5 A second trapping section 102 is shown, which includes a bonding region forming a cavity on the PIC. In this design, the bonding region is fabricated by at least one metal layer consisting of an inner rectangular pad-shaped portion and a surrounding rectangular annular-shaped portion. In another design, the metallized pads are covered by a passivation dielectric stack fabricated from nit and ox layers. Figure 4 (shown at point D). The passivation layer behind is etched and opened above the metal layer, thereby creating a patterned topographic region consisting of top dielectric elements (represented by 52 and 54) and bottom exposed metal layers (represented by 51 and 53).

[0054] This "grating" design allows for size adjustments, enabling precise control of the wetting of conductive bonding material droplets to the desired size, shape, and height, thus achieving a high-precision and repeatable in-situ bonding process.

[0055] This design also ensures that there is no UV epoxy residue on the PIC trench, DFL waveguide, and all other areas on the PIC. This allows for better precision, preventing conductive bonding materials from "mixing" during the bonding process, and enables the use of opaque UV conductive bonding materials because the UV is guaranteed not to contact the DFL endface. Note that in this particular design, the spacer is bonded to the Si chip along its two sides, as... Figure 3 and 4 As shown.

[0056] The fixture, DFL, and PIC can be assembled in the following manner: a. Before aligning and attaching the DFL to the Si chip, attach the DFL to a custom fixture to provide mechanical support, electrical contact, and an efficient heat dissipation path for the DFL. The active area of ​​the DFL can be attached near the fixture or on the other side.

[0057] b. DFL—Clamp attachment can be achieved through standard industrial bonding methods used for active semiconductor components.

[0058] c. Two channels are fabricated in the fixture and, once attached to the DFL, are (at least partially) positioned to the sides of the DFL. These channels allow excess bonding material to be transferred within the channel volume rather than contaminating the sidewalls of the DFL (industrially known as bonding "rounding"). Contaminated DFL sidewalls are undesirable as they cause electrical short circuits in the active area.

[0059] d. At this stage of the process, faulty equipment can be easily screened out. Using a fixture, electrical probes on the fixture and the cathode side of the DFL can be touched to activate the DFL for testing.

[0060] e. Next, the alignment process is performed using an alignment signal generated by the activated DFL itself or by an external source when the DFL is passive. Once a satisfactory alignment signal is obtained, the unit is assembled in the appropriate position.

[0061] f. In this stage, a transparent, refractive index-matching epoxy resin can be applied between the DFL and the SiN waveguide, as some applications require this. See also Figure 6 .

[0062] It should be noted that, unlike channels, recesses can be formed in fixtures.

[0063] The clamp can be made of various materials, such as: a. A material exhibiting high conductivity, thus providing good ohmic contact when tested face-to-face from the fixture. For this purpose, any metal or highly conductive metallized semiconductor (e.g., Si) is acceptable.

[0064] b. It can have a coefficient of thermal expansion that matches that of DFL.

[0065] c. For example, InP or AlN can be used because they have a coefficient of thermal expansion (CTE, 4.6 ppm / °C) that matches that of InP-based DFL.

[0066] d. In some applications, the use of AlN materials may be beneficial due to their excellent thermal conductivity.

[0067] Figure 6 One solution is shown, which includes preparing a dedicated volumetric portion that will serve as an expansion buffer for the bound waste material. a. At the wafer fabrication level, etch a cavity around the location of the DFL on the PIC, leaving a raised ridge on which the DFL is placed.

[0068] b. Etch the cavity from the three sides of the DFL, see [reference]. Figure 6 .

[0069] c. On the front side of the DFL, where the DFL output aligns with the waveguide, a recess is etched in the wall facing the DFL, leaving a slender, tapered ridge (also known as a silicon fin) at the center of the wall to support the waveguide. Therefore, when the DFL is placed, the bonding waste from the front of the DFL can expand to the side of this tapered ridge.

[0070] All accompanying figures may or may not be drawn to scale. Any values ​​shown in any of the accompanying figures are merely examples.

[0071] For example, the maximum thickness of the fixture can range from 100 micrometers to 500 micrometers. Similarly, the channel width can range from 150 micrometers to 390 micrometers, or even from 200 micrometers to 325 micrometers. The coating thickness can range from 0.1 micrometers to 35 micrometers—for example, it could be 20 micrometers.

[0072] In another embodiment, the etching direction of the cavity of the third trapping section is vertical relative to the PIC trench contact 82 region, such as... Figure 6 As shown. As previously described, these cavity regions are formed in the PIC trench on one or more sides of the PIC trench contact (see, for example...). Figure 6(see reference numeral 81 in the figure), and includes one or more additional recesses on one or more sides of the PIC groove contact (see, for example) Figure 6 (Ref. 88 and 89 in the accompanying drawings). This can be accomplished by anisotropically etching the Si around the area of ​​the PIC trench contact at an etching angle that can vary from 90 degrees to 45 degrees relative to the PIC trench contact. In this design, the area of ​​the DFL proximal contact 22 can be less than, equal to, or greater than the area of ​​the PIC trench contact 82, and as a result, its size is not limited to the size of the area of ​​the PIC trench contact 82.

[0073] Figure 7 An example of a DFL tested by probes 101, 102, and 103 is shown, with probes 101, 102, and 103 making electrical contact with the adapter's subprotrusions 64 and 65 and the DFL's distal contact 21.

[0074] In the foregoing detailed description, numerous specific details have been set forth in order to provide a thorough understanding of the invention. However, those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known methods, processes, and components have not been described in detail so as not to obscure the invention.

[0075] The subject matter of the invention is specifically pointed out and clearly claimed at the end of the specification. However, the organization and operation of the invention, as well as its objects, features, and advantages, can be best understood by reading the following detailed description in conjunction with the accompanying drawings.

[0076] It will be understood that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be enlarged relative to others. Furthermore, where deemed appropriate, reference numerals may be repeated in multiple figures to indicate corresponding or similar elements.

[0077] Because the illustrated embodiments of the present invention can be largely implemented using electronic components and circuits known to those skilled in the art, no further explanation will be given on the details than that described above, in order to understand and recognize the basic concepts of the present invention and to avoid obscuring or departing from the teachings of the present invention.

[0078] Any references to the method in the specification should be adapted, as appropriate, to any device capable of performing the method.

[0079] Any references to the equipment in the instruction manual should be adapted, as appropriate, to methods that can be performed by the equipment.

[0080] In the foregoing description, the invention has been described with reference to specific examples of embodiments thereof. However, it will be apparent that various modifications and variations may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

[0081] Furthermore, the terms “front,” “back,” “top,” “bottom,” “above,” “below,” and similar terms (if any) used in the specification and claims are for descriptive purposes and are not necessarily used to describe unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, enabling embodiments of the invention described herein to operate, for example, in orientations other than those illustrated or otherwise described herein.

[0082] The connections discussed herein can be of any type suitable for transmitting signals from or to a corresponding node, unit, or device, for example, via an intermediate device. Therefore, unless implied or otherwise stated, a connection can be, for example, a direct connection or an indirect connection. Connections can be shown or described with reference to a single connection, multiple connections, unidirectional connections, or bidirectional connections. However, different embodiments can vary the implementation of the connection. For example, a single unidirectional connection can be used instead of a bidirectional connection, and vice versa. Furthermore, multiple connections can be replaced by a single connection that transmits multiple signals serially or in a time-multiplexed manner. Similarly, a single connection carrying multiple signals can be separated into various different connections carrying subsets of these signals. Therefore, there are many options available for transmitting signals.

[0083] Although specific conductivity types or potential polarities have been described in the examples, it should be understood that conductivity types and potential polarities can be reversed.

[0084] Each signal described herein can be designed as either positive or negative logic. In the case of a negative logic signal, the signal is active low, where a true logic state corresponds to logic level zero. In the case of a positive logic signal, the signal is active high, where a true logic state corresponds to logic level one. Note that any signal described herein can be designed as either a negative or positive logic signal. Therefore, in alternative embodiments, those signals described as positive logic signals can be implemented as negative logic signals, and those signals described as negative logic signals can be implemented as positive logic signals.

[0085] Furthermore, the terms "assert" or "set" and "negate" (or "deassert" or "clear") are used herein to refer to presenting a signal, status bit, or similar device as its logical true or logical false state, respectively. If the logical true state is logic level one, then the logical false state is logic level zero. And if the logical true state is logic level zero, then the logical false state is logic level one.

[0086] Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative, and that alternative implementations may combine logic blocks or circuit elements, or perform optional functional decomposition across various logic blocks or circuit elements. Therefore, it should be understood that the architecture depicted herein is merely exemplary, and many other architectures that achieve the same functionality can actually be implemented.

[0087] Any arrangement of components that perform the same function is effectively “associated” so that the desired function is achieved. Therefore, any two components combined in this document to achieve a specific function can be considered “associated” with each other so that the desired function is achieved, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” to each other to achieve the desired function.

[0088] Furthermore, those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Additionally, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be varied in various other embodiments.

[0089] Furthermore, for example, in one embodiment, the illustrated example can be implemented as a circuit located on a single integrated circuit or within the same device. Alternatively, the example can be implemented as any number of separate integrated circuits or separate devices, which are interconnected with each other in an appropriate manner.

[0090] However, other changes, variations, and alternatives are also possible. Accordingly, the specification and drawings should be considered illustrative rather than restrictive.

[0091] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in the claims. Furthermore, the terms “a” or “an” as used herein are defined as one or more. Moreover, the use of introductory phrases in the claims (e.g., “at least one” and “one or more”) should not be construed as implying that the introduction of another claim element by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrase “one or more” or “at least one” and an indefinite article (e.g., “a” or “an”). The same applies to the use of definite articles. Unless otherwise specified, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate temporal or other priority of such elements. The fact that certain measures are listed in mutually different claims does not indicate that combinations of these measures cannot be used advantageously.

[0092] Although certain features of the invention have been shown and described herein, many modifications, substitutions, alterations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and alterations falling within the true spirit of the invention.

Claims

1. An apparatus comprising: A distributed feedback laser (DFL) consists of a DFL waveguide output, a DFL distal contact, and a DFL proximal contact. A photonic integrated circuit (PIC) includes a PIC trench, wherein the DFL is positioned within the PIC trench; PIC groove contact, which is formed within the PIC groove; adapter; The adapter is attached to the area of ​​the PIC and the DFL using one or more coupling elements; and The device includes one or more traps for receiving excess bonding material formed by the one or more bonding elements during the attachment of the adapter to at least one of the regions of the PIC and the DFL, and for preventing the excess bonding material from electrically coupling the distal contact of the DFL to the proximal contact of the DFL.

2. The device according to claim 1, wherein, The one or more trapping sections include a first trapping section formed in the adapter, wherein the first trapping section is configured to receive excess bonding material formed during attaching the adapter to the DFL.

3. The device according to claim 2, wherein, The first trapping portion is formed by one or more adapter recesses, wherein the adapter further includes a main protrusion attached to the distal contact of the DFL and a secondary protrusion attached to the region of the PIC.

4. The device according to claim 1, wherein, The one or more trapping sections include a second trapping section configured to receive excess bonding material formed during the attachment of the adapter to the PIC region.

5. The device according to claim 4, wherein, The second trapping section includes a grating of metal and dielectric elements formed on the PIC region.

6. The device according to claim 4, wherein, The second collecting section includes one or more capillary tubes.

7. The device of claim 1, further comprising a third trapping unit configured to receive excess bonding material formed during the attachment of the DFL to the PIC trench contact.

8. The device according to claim 7, wherein, The third trapping portion is formed in the PIC groove and includes one or more additional recesses formed on one or more sides of the PIC groove contact.

9. The device according to claim 1, wherein, The adapter includes a distal portion of the adapter and a proximal portion of the adapter electrically coupled to the distal portion of the adapter, wherein the proximal portion of the adapter is attached to the distal contact of the DFL.

10. The device according to claim 9, wherein, The area of ​​the distal surface of the distal portion of the adapter exceeds the area of ​​the distal surface of the DFL.

11. The device of claim 1, further comprising a refractive index matching material located between the DFL waveguide output and the PIC trench.

12. The apparatus of claim 11, further comprising a fourth trapping unit configured to receive excess refractive index matching material formed during the provision of the refractive index matching material.

13. The device according to claim 1, wherein, The adapter includes a distal portion of the adapter, a main protrusion, and a secondary protrusion.

14. The device according to claim 13, wherein, The main protrusion and the secondary protrusion extend from the distal portion.

15. The device according to claim 13, wherein, The main protrusion is longer than the secondary protrusion.

16. The device according to claim 13, wherein, The lateral distance between the subprotrusions exceeds the width of the PIC groove.

17. The device according to claim 1, wherein, The bonding material to which the adapter is attached to the DFL is conductive.

18. The device according to claim 1, wherein, The bonding material used to attach the adapter to the PIC area is electrically insulating.

19. A kit comprising: A distributed feedback laser (DFL) includes a DFL distal surface, a DFL waveguide output, a DFL distal contact, and a DFL proximal contact. and An adapter includes a first trapping portion, a distal portion of the adapter, a main protrusion, and a secondary protrusion, wherein the first trapping portion is configured to receive excess bonding material formed during attachment of the adapter to the DFL and to prevent the excess bonding material from electrically coupling the distal contact of the DFL to the proximal contact of the DFL; and The adapter is wider than the DFL.

20. A method for assembling equipment, the method comprising: (a) The adapter is first attached to a distributed feedback laser (DFL), the distributed feedback laser (DFL) including a DFL waveguide output, a DFL distal contact and a DFL proximal contact; (b) Excess bonding material formed during the first attachment by the first receiving element of the first collecting section; (c) Position the DFL within the PIC trench of the photonic integrated circuit (PIC) and align the DFL waveguide with the PIC waveguide; (d) Attach the adapter second to a PIC region located outside the PIC trench; as well as (e) Excess bonding material formed during the second attachment by the second receiving element of the second collecting section; and Steps (b) and (e) prevent any excess bonding material from electrically coupling the distal DFL contact to the proximal DFL contact.

21. The method of claim 20, further comprising testing the DFL using the adapter between completing the first reception and before the second attachment.

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