Dynamic compensation clamp for current mode control

Abstract

The invention relates to dynamic compensation clamping for current mode control. Described embodiments include a voltage regulator circuit (400) having an amplifier (134) having an input coupled to a feedback voltage terminal (133) and a reference voltage terminal (138). A comparator (112) has a first comparator input coupled to the amplifier output, a second comparator input, and a comparator output. A current sense circuit (118) is coupled between an output voltage terminal and the second comparator input and provides a voltage proportional to the output current at a current sense output. A waveform generator (116) is coupled between the second comparator input and ground. A first latch input (108R) is coupled to the comparator output. A clock generator (114) is coupled between the second latch input and ground.

Description

Technical Field

[0001] This specification relates to voltage clamping circuits, particularly for compensation circuits used in current-mode control, for example, in switching voltage regulators. Background Technology

[0002] When a switching voltage regulator includes a current-mode control loop, it may generate a significantly large voltage spike on the output voltage line when recovering from a voltage drop condition or an overcurrent condition.

[0003] Voltage spikes can be caused by the use of fixed voltage compensation clamping on the voltage control loop error amplifier when the output voltage drops below a specified output voltage, and by subsequent relatively large changes in the control loop compensation voltage upon recovery from a dropout or overcurrent condition. Previous solutions to the output voltage overshoot problem upon exiting a dropout condition involved responding to and limiting the output voltage by controlling the high-side and low-side drive transistors. However, this can lead to continuous oscillations in the output voltage due to the inherent race condition between the output voltage and the compensation loop. Summary of the Invention

[0004] In a first example, a voltage regulator circuit includes an amplifier having first and second amplifier inputs and an amplifier output. The first amplifier input is coupled to a feedback voltage terminal, and the second amplifier input is coupled to a reference voltage terminal. A comparator has first and second comparator inputs and a comparator output. The first comparator input is coupled to the amplifier output.

[0005] The current sensing circuit has a current sensing input and a current sensing output. The current sensing input is coupled to an output voltage terminal, and the current sensing output is coupled to a second comparator input. The current sensing circuit is configured to provide a voltage at the current sensing output that is proportional to the current being delivered to the output voltage terminal.

[0006] A waveform generator is coupled between the second comparator input and ground. The waveform generator is configurable to provide a waveform signal at the switching frequency. A latch has first and second latch inputs and first and second latch outputs. The first latch input is coupled to the comparator output. A clock generator is coupled between the second latch input and ground. The clock generator is configurable to provide a clock signal at the switching frequency.

[0007] The voltage clamping circuit has first and second voltage clamping inputs and a voltage clamping output. The first voltage clamping input is coupled to a current sensing output. The second voltage clamping input is coupled to a fixed voltage source. The voltage clamping output is coupled to a first comparator input. The voltage clamping circuit can be configured to limit the voltage at the first comparator input to a clamping voltage that varies in response to the voltage at the current sensing output.

[0008] In a second example, a method for controlling a voltage converter circuit includes connecting a first field-effect transistor (FET) and a second FET in series between an input voltage terminal and a ground terminal. An inductor is coupled between a switching terminal and an output voltage terminal, wherein the output voltage terminal provides an output voltage, and the first and second FETs are connected at the switching terminal.

[0009] A compensation current is generated at the compensation terminal. This compensation current is proportional to the difference between a reference voltage and a voltage proportional to the output voltage, which generates a compensation voltage that tracks the current flowing through the inductor. A waveform signal and a clock signal, both in phase and having the same frequency, are generated. The compensation voltage is limited to not exceeding a clamping voltage. The clamping voltage is equal to the sum of the maximum voltage of the waveform signal, the minimum compensation voltage required to trigger the switching of the first and second FETs, and the current-sensing voltage proportional to the current flowing through the inductor.

[0010] A comparator with a comparator output is used to compare the compensation voltage with a comparison voltage. The comparison voltage is equal to the sum of the maximum voltage of the waveform signal and the minimum compensation voltage required to trigger the switching of the first and second FETs. The first and second FETs are controlled in response to the comparator output. Attached Figure Description

[0011] Figure 1 A schematic diagram illustrating an example of a switching voltage regulator with a fixed voltage clamp on the compensation signal.

[0012] Figure 2 The timing diagrams of the compensation voltage and output voltage signals in an example switching voltage regulator with a fixed voltage clamping circuit are shown.

[0013] Figure 3 The example dynamic voltage clamping circuit displays a voltage-time curve of the signal.

[0014] Figure 4 A schematic diagram of an example switching voltage regulator with dynamic voltage clamping circuitry is shown. Detailed Implementation

[0015] In this specification, the same reference numerals depict the same or similar (functional and / or structural) features. The figures are not necessarily drawn to scale.

[0016] When a switching voltage regulator containing a current-mode control loop recovers from a dropout condition or an overcurrent condition, it can generate a significantly large voltage spike at the output voltage terminal. A common condition that can cause a large voltage spike at the output voltage terminal is the regulator's recovery after the output voltage terminal has been shorted to ground.

[0017] A second common condition that can cause a large voltage spike at the output voltage terminals is when the switching voltage regulator attempts to deliver more current to the load than it is capable of providing. This condition can cause a sudden drop in the output voltage. A third condition that can cause a large voltage spike at the output voltage terminals is when the input voltage drops below the specified nominal output voltage. In this case, when the switching voltage regulator is operating at its maximum duty cycle, the output voltage V... OUT It will follow the input voltage.

[0018] Figure 1 This diagram illustrates an example of a switching voltage regulator 100. Input voltage source 102 provides the input voltage V. IN Transistor 104 is coupled between input voltage source 102 and switch terminal 105. Transistor 106 is coupled between switch terminal 105 and ground terminal. In this example, transistor 104 operates as the high-side switch of switching voltage regulator 100 and transistor 106 operates as the low-side switch of the switching voltage regulator. Inductor 110 is coupled between switch terminal 105 and output voltage terminal V. O Between 130 and 130. Current I L The current flows through inductor 110. Capacitor C O 126 and resistor R O 128 are connected in parallel to the output voltage terminal V O Between 130 and the ground terminal. Capacitor C O 126 and resistor R O 128 represent the load capacitor and load resistor on the output, respectively.

[0019] Resistor 132 is coupled to the output voltage terminal V O Resistor 130 is connected between the output voltage feedback terminal 133 and the output voltage feedback terminal 133. Resistor 136 is coupled between the output voltage feedback terminal 133 and the ground terminal. Resistors 132 and 136 are connected between the output voltage V and the ground terminal. O A voltage divider is formed on top. The voltage at the output voltage feedback terminal 133 is V. FB The inverting input of amplifier 134 is coupled to the output voltage feedback terminal 133 and receives voltage V. FB Reference voltage source 138 is coupled between the non-inverting input of amplifier 134 and ground terminal, and provides voltage V. REF When the output voltage V O When 130 is at the specified nominal output voltage, the voltage V REF It is set to be equal to the voltage V at the output voltage feedback terminal 133. FB The reference voltage.

[0020] In at least one instance, amplifier 134 is a transconductance amplifier. Amplifier 134 outputs the voltage V at the feedback terminal 133. FB With reference voltage V REF Compare and provide a value similar to V at its output. FB and V REF The signal is proportional to the difference between the two. Clamping circuit 140 is coupled between the output of amplifier 134 and the ground terminal. The purpose of clamping circuit 140 is to ensure the compensation voltage V COMP 135 does not exceed the specific fixed clamping voltage V Clamp The clamping circuit 140 can be a Zener diode, or any other type of circuit that provides a fixed maximum voltage and is capable of pulling down any voltage above the fixed maximum voltage to the fixed maximum voltage.

[0021] The current sensing circuit 118 is coupled to the output voltage terminal V. O Between the first non-inverting input of comparator 112 and 130. Current sensing circuit 118 senses the current flowing through inductor 110 and provides a voltage proportional to the current flowing through inductor 110 to the first non-inverting input of comparator 112. Slope Comp generator 116 is coupled between the second non-inverting input of comparator 112 and ground. Slope Comp generator 116 provides a slope-compensated waveform at the frequency of the switching voltage regulator. In at least one instance, the slope-compensated waveform is a sawtooth waveform.

[0022] The current-sensing signal provided by the current-sensing circuit 118 is summed with the slope-compensated waveform from the Slope Comp generator 116 to provide a signal to the non-inverting input of comparator 112. The output of amplifier 134 is coupled to the inverting input of comparator 112, thereby providing a signal V at the inverting input of comparator 112. COMP 135. Resistor R COMP 120 is coupled to the output of amplifier 134 with capacitor C COMP Between the first terminals of capacitor C (122). COMP The second terminal of capacitor 122 is coupled to the ground terminal. Capacitor C O_EA 124 is coupled between the output of amplifier 134 and the ground terminal. Resistor R COMP 120. Capacitor C COMP 122 and capacitor C O_EA 124 forms a Type II compensation filter, which is typically used in current-mode control circuits.

[0023] Capacitor C COMP 122 sets the crossover frequency of the Type II compensation filter. Resistor R COMP 120 and capacitor CCOMP 122 series coupling, and provides a zero point in the type II compensated filter. Capacitor C O_EA Capacitors 124 typically have small capacitance values ​​(e.g., 10pF) and are primarily used to filter high-frequency noise rather than to provide stability to the control loop. The stability of the control loop is mainly determined by capacitor C. COMP 122 and resistor R COMP Provided by 120.

[0024] Comparator 112 is shown as having three inputs, but it can also be shown as having a summation terminal coupled to a single non-inverting input of comparator 112, wherein the current-sensing signal from current-sensing circuit 118 is summed with the slope-compensated waveform from SlopeComp generator 116, and the summed signal is provided to the non-inverting input of comparator 112. Comparator 112 then sums this signal with the compensation voltage V. COMP The 135 performs a comparison and provides the output signal to the Reset input of latch 108. In at least one instance, latch 108 is an RS flip-flop.

[0025] Clock generator 114 is coupled between the Set input of latch 108 and the ground terminal. Clock generator 114 provides a clock signal with the same frequency as the switching frequency of switching voltage regulator 100. In at least one instance, the clock signal is a square wave signal. The clock signal generated by clock generator 114 has the same frequency as and is in phase with the slope-compensated waveform generated by slope compensating generator 116.

[0026] The Q output of latch 108 is coupled to the control terminal of transistor 104 and controls the switching on and off of transistor 104. The QN output of latch 108, which is an inverted Q output, is coupled to the control terminal of transistor 106 and controls the switching on and off of transistor 106. In some embodiments, additional first drive stages (not shown) and second drive stages (not shown) are coupled between the Q output of latch 108 and the control terminal of transistor 104, and between the QN output of latch 108 and the control terminal of transistor 106, respectively, to ensure sufficient drive is provided to the control terminals of transistors 104 and 106 to turn them on.

[0027] Problems can occur in switching voltage regulators using peak current mode control if the switching duty cycle exceeds 50%. When the switching duty cycle exceeds 50%, subharmonic oscillations can occur, potentially destabilizing the control loop. To allow the current-mode controlled voltage regulator to operate at any duty cycle (including those above 50%), some type of slope compensation can be included to help avoid subharmonic oscillations.

[0028] The Slope Comp signal provided by the Slope Comp generator 116 in the switching voltage regulator 100 helps avoid subharmonic oscillations and ensures that the switching voltage regulator remains stable across all duty cycles. The Slope Comp signal can be a sawtooth waveform with the same frequency as the switching frequency of the voltage regulator. When the Slope Comp signal from the Slope Comp generator 116 is turned on, it is summed with the output of the current sensing circuit 118, and then summed with the compensation voltage V. COMP Compare 135.

[0029] When transistor 104 is turned on, the Slope Comp signal begins to increase, eventually causing comparator 112 to switch and provide a logic high at its output. The logic high signal provided at the Reset input of latch 108 resets latch 108, which pulls down the voltage at the gate of transistor 104. Therefore, latch 108 remains reset and transistor 104 remains off until the next cycle when transistor 104 is turned on again, and then the cycle repeats.

[0030] Whenever the current through inductor 110 becomes high enough that the voltage at the output of current sensing circuit 118 becomes higher than the compensation voltage V COMP At time 135, the output of comparator 112 resets latch 108. A continuously running clock signal, provided by clock generator 114, is supplied to the Set input of latch 108. The clock signal can be a square wave or have another waveform. This clock signal triggers transistor 104 to turn on. The rising edge of the clock signal sets latch 108. Then, transistor 104 turns on, and the current through inductor 110 begins to increase. The Slope Comp signal, provided by Slope Comp generator 116, also begins to increase.

[0031] When the sum of the Slope Comp signal and the output voltage of the current sensing circuit 118 equals the compensation voltage V COMP At time 135, the output of comparator 112 goes high and resets latch 108. Resetting latch 108 turns off transistor 104. This control loop regulates the peak current through inductor 110. The loop then repeats starting from the rising edge of the clock signal from clock generator 114. Transistor 104 then turns on and remains on until the current through inductor 110 becomes high enough to turn off transistor 104.

[0032] Clamping circuit 140 is coupled between the output of amplifier 134 and ground. Clamping circuit 140 provides compensation voltage V. COMP 135 cannot rise above its upper limit or clamping voltage V. ClampAs long as the switching voltage regulator 100 is operating in the nominal controlled state, the compensation voltage V COMP 135 reflects the magnitude of the current passing through inductor 110. Under this controlled condition, the compensation voltage V COMP The current-sensing voltages at the outputs of circuits 135 and 118 track each other. The higher compensation voltage V... COMP 135 is equivalent to the higher current passing through inductor 110.

[0033] However, there are conditions that could cause the voltage regulator control loop to enter an open loop and the voltage regulation control loop to no longer be closed and under control. When this happens, V COMP The voltage can go to the high-side voltage rail or the low-side voltage rail, depending on whether the output voltage is below or above its specified nominal value. Examples of conditions that can cause the voltage regulator control loop to enter open loop include the output voltage terminal being shorted to ground, the voltage regulator attempting to deliver more current to the load than it can provide, resulting in a sudden drop in the output voltage level, and the input voltage being at or below the specified nominal output voltage.

[0034] By providing a reference voltage V REF 138 and then compare it with the output voltage V formed by resistors 132 and 136. O The output feedback voltage V provided by the resistor divider on the 130 FB 133 is used for comparison to adjust the voltage regulator control loop. Ideally, the output feedback voltage V... FB 133 is always almost equal to the reference voltage V. REF 138. If the output feedback voltage V FB 133 is lower than the reference voltage V REF 138, then the compensation voltage V COMP The voltage increases from 135. In the absence of clamping circuit 140, the compensation voltage V... COMP 135 will rise to and remain at the upper supply rail voltage, thereby creating an open-loop condition in the voltage control loop.

[0035] Set compensation voltage V COMP The upper limit of the clamping voltage V is 135. Clamp It should be set high enough that it does not affect the performance of the switching voltage regulator during normal operation. However, to ensure the clamping voltage V... Clamp The clamping voltage V is high enough to not affect the performance of the switching voltage regulator under all normal conditions. Clamp It is usually set to a voltage much higher than the voltage at which the voltage control loop will be closed.

[0036] If the output feedback voltage VFB 133 remains below the reference voltage V for a sufficiently long time. REF 138, then the compensation voltage V COMP 135 will rise to the clamping voltage and remain there for the duration the voltage regulator holds in that state. When exiting this state, a long recovery period may be required before the voltage regulator control loop can regain full control. This recovery period is due to the capacitance C. COMP 122 and C O_EA 124. The time required for charging or discharging. During the recovery cycle, the output voltage V... O 130 may cause significant overshoot. In one example, the output voltage V O The 130 overshoot is 60% higher than its specified nominal voltage.

[0037] In this situation, the output voltage V occurs. O Overshoot at 130, due to compensation voltage V COMP 135 is charged via amplifier 134 until it reaches the clamping voltage V under voltage drop conditions. Clamp Then, when the input voltage V IN 102 is increased enough to become higher than the specified nominal output voltage and the voltage drop condition ends, the output voltage V O 130 may be overshooting because of the compensation voltage V COMP 135 from clamping voltage V Clamp To accurately control the output voltage V O 130 The required recovery time for the voltage it needs to be at, the voltage regulator control loop has not yet recovered and regained control.

[0038] If the clamping voltage V Clamp If set to a fixed value, that fixed value should be high enough to prevent clamping from interfering with the voltage control loop during normal operation. Compensation voltage V COMP 135 also depends on the magnitude of the current through inductor 110 and the duty cycle of the switching voltage regulator. In one example, the compensation voltage V during regulated operation... COMP The voltage range of the 135 varies from 0.6V to 1.6V.

[0039] Therefore, if V Clamp If a single fixed clamping voltage is set, then the clamping voltage must be set high enough to avoid interfering with normal operation under any circumstances. For example, if the compensation voltage V... COMP During normal operation, the 135 operates at approximately 800mV. When a voltage drop condition occurs, the voltage can be charged to approximately 2.1V. Then, when the voltage regulator recovers from the voltage drop condition, the compensation voltage V... COMPThe voltage will inevitably drop from 2.1V to 800mV before the voltage control loop can regain control. This recovery time may take tens or hundreds of microseconds. During this recovery time, the output voltage V... OUT Significant overshoot can occur. Compensation voltage V COMP The recovery time required for a voltage change of 135 results in a decrease in the output voltage V. O 130 overshoot problem.

[0040] Figure 2 Timing diagram 200 shows the compensation voltage and output voltage in an example switching voltage regulator with a fixed voltage clamping circuit. Curve 210 represents the compensation voltage V in the switching voltage regulator 100. COMP The voltage-time curve of 135. Curve 220 is the output voltage V in the switching voltage regulator 100. O Voltage-time curve at 130V.

[0041] At 222, in response to the switching voltage regulator due to the input voltage V IN 102 drops below the specified nominal output voltage V OUT(nom) When the voltage drop condition is entered, the output voltage V OUT The input voltage V decreases. IN 102 drops below the specified nominal output voltage V OUT(nom) At that time, it causes the output feedback voltage V FB 133 drops below the reference voltage V REF 138, which causes the compensation voltage V COMP The clamping voltage rises from 135 to 212. During the cycle from 222 to 224, the voltage control loop loses control, therefore the output voltage V... OUT It is not properly regulated and will follow the input voltage V IN In a buck voltage regulator, the output voltage V OUT The highest achievable voltage is equal to the input voltage V. IN .

[0042] At position 224, the input voltage V IN The circuit recovers, and the switching voltage regulator disengages from the voltage drop condition. Output voltage V OUT The voltage increases, but at the specified nominal output voltage V OUT(nom) The voltage will not stop rising. In fact, the output voltage V... OUT The overshoot at 226 points is significantly higher than the specified nominal output voltage V. OUT(nom) The peak voltage. When the switching voltage regulator is out of the voltage drop condition, the compensation voltage V COMP The clamping voltage at point 214 begins to decrease from 135. However, the compensation voltage V... COMPThe discharge from the clamping voltage at 135 to its steady-state value at 216 requires recovery time. The time between 214 and 216 is the recovery time.

[0043] When the compensation voltage V COMP When 135 reaches its steady-state value, the voltage control loop regains control, and the output voltage VOUT will reach the specified nominal output voltage V at 228. OUT(nom) In this case, the compensation voltage V COMP The 135 must discharge from 2.1V to 0.65V, which requires a recovery time of over 150 microseconds. During this recovery time, the output voltage VOUT overshoots its specified nominal output voltage of 5V by more than 3V. This overshoot problem occurs during the recovery time and is attributed to the clamping voltage and the compensation voltage VOUT. COMP The significant voltage difference between the steady-state voltages of 135.

[0044] One possible solution to the overshoot problem is to make the clamping voltage dynamic, adjusting as conditions change, rather than setting the clamping voltage to a fixed value. The switching voltage regulator circuit provides sufficient information to determine and generate a dynamically compensated clamping voltage that limits the compensation voltage V. COMP The required voltage discharge on 135 helps limit the output voltage V. O Overshoot at 130.

[0045] Clamping voltage V Clamp It can be set to dynamically maintain just above the compensation voltage V. COMP The voltage that should be maintained during normal operation. This helps ensure that voltage clamping has no impact on circuit performance during normal operation, but it does affect the compensation voltage V when the switching voltage regulator enters a dropout condition. COMP Clamping is performed. This allows compensation voltage V to be applied. COMP Recovery from voltage drop conditions is faster. Compensation voltage V COMP It can recover faster because it only requires a smaller amount of movement (e.g., 100mV instead of 1-2V) compared to a fixed voltage clamping circuit.

[0046] The compensation voltage V can be set as a limit. COMP Clamping voltage V Clamp This allows the clamping voltage V to be applied. Clamp Configured to dynamically track and maintain just above the compensation voltage V COMP It is possible to control the output voltage V OUT Recovery from the voltage drop condition occurs more quickly with fewer interruptions. Then, if the switching voltage regulator enters the voltage drop condition, the compensation voltage V... COMP Recovery from voltage drop conditions is faster because of the compensation voltage V COMPIt is not necessary to discharge too much to regain control of the voltage control loop.

[0047] This can be achieved by adjusting the clamping voltage V. Clamp This depends on the sensed current flowing through inductor 110 sensed by current sensing circuit 118. A minimum compensation voltage V is required. COMP 135 is used to trigger switching in the voltage regulator. In one instance, the minimum compensation voltage V that triggers the switching is... COMP_Offset It was determined to be 600mV. However, in other systems, V COMP_Offset It can be at different voltages. The maximum voltage V of the Slope Comp signal from the Slope Comp generator 116 when operating at or near 100% duty cycle can be determined for any given system. MAX_Slope_Comp In an instance system, V MAX_Slope_Comp It was determined to be 340mV. However, in other systems, V MAX_Slope_Comp The values ​​can be different.

[0048] The base voltage V used for compensating voltage clamping Base_Clamp By adjusting the minimum compensation voltage V COMP_Offset With the maximum slope compensation voltage V MAX_Slope_Comp The values ​​are determined by addition. In some instances, a safety margin voltage V can be added. margin This ensures that clamping on the compensation voltage will never interfere with the normal operation of the voltage regulator. With a safety margin voltage added, the base voltage V used for compensation voltage clamping... Base_Clamp Equal to minimum compensation voltage V COMP_Offset The maximum slope compensation voltage V when operating at 100% duty cycle MAX_Slope_Comp and safety margin voltage V margin sum.

[0049] To determine the clamping voltage, the inductor current ripple is sensed and added to the base voltage V used to compensate for the voltage clamping. Base_Clamp In at least one example system, the sensed inductor current signal is added to the base voltage V used for compensating voltage clamping. Base_Clamp Previously rectified. Rectifying the inductor current signal improves performance because the peak inductor current is being regulated. Thus, the compensation voltage V... COMP It should be kept above the peak value. Ideally, the clamping voltage V Clamp The peak inductor current is tracked because information from the remaining portion of the ramp-compensation waveform is not needed. Therefore, the sensed inductor current signal can be added to the base voltage V used for voltage clamping compensation. Base_ClampPreviously, the sensed inductor current signal was rectified to determine a more accurate clamping voltage, but this is not necessary.

[0050] Figure 3 The example dynamic voltage clamping circuit is shown in voltage-time curve 300. Voltage 310 is V. COMP_Offset It is the minimum compensation voltage V required to trigger the switching in the voltage regulator. COMP 135. Voltage 320 is V. MAX_Slope_Comp This is the maximum voltage of the SlopeComp signal from the SlopeComp generator 116 when the voltage regulator is running at 100% duty cycle. Voltage 330 is V. margin This is a safety margin voltage, which can be added in some cases to ensure that clamping on the compensation voltage will never interfere with the normal operation of the voltage regulator. Voltage V margin The addition of 330 is optional, and in some systems V margin 330 can be zero.

[0051] 340 is V Base_Clamp It is equal to V COMP_Offset 310, V MAX_Slope_Comp 320 and safety margin voltage V margin The sum of 330. Curve 350 is for V. ISENSE The voltage-time curve, V ISENSE It is the current-sensing voltage from the current-sensing circuit 118 and is proportional to the current passing through the inductor 110. Curve 360 ​​is for V. Clamp The voltage-time curve, V Clamp It is the compensation voltage V COMP 135 cannot rise above its upper limit or clamping voltage. Clamping voltage V Clamp 360 is the base voltage V used for compensating for voltage clamping. Base_Clamp 340 and current sensing voltage V ISENSE The sum of 350. Clamping voltage V Clamp 360 is set by clamping circuit 140.

[0052] Clamping voltage V Clamp 360 equals a fixed value V Base_Clamp 340 plus the sensed inductor current V ISENSE 350 scaled-down type. Clamping voltage V Clamp 360 is set to remain above the compensation voltage V COMP 135, ensuring it will never interfere with the normal operation of the voltage regulator. Clamping voltage V Clamp360 is set just above its required voltage, so that if the voltage regulator enters the control loop, it enters the open loop and compensates for the voltage V. COMP 135 rises to clamping voltage V Clamp In the case of 360°, it does not have a large voltage to discharge in order to regain control and regulate the output voltage.

[0053] Clamping voltage V Clamp 360° follow and just above the compensation voltage V COMP 135. Clamping voltage V Clamp 360 depends on the sensed inductor current. If the voltage regulator is operating with a lower output current and the inductor current is low, the clamping voltage V Clamp 360 is at a lower voltage. Similarly, if the voltage regulator is operating at a higher output current and the inductor current is high, the clamping voltage V Clamp 360 is at a higher voltage.

[0054] Figure 4 A schematic diagram of an example switching voltage regulator 400 with dynamic voltage clamping circuitry is shown. Input voltage source 102 provides the input voltage V. IN Transistor 104 is coupled between the input voltage source 102 and the switching terminal 105, and acts as the high-side switch of the voltage regulator. Transistor 106 is coupled between the switching terminal 105 and the ground terminal, and acts as the low-side switch of the voltage regulator. Inductor 110 is coupled between the switching terminal 105 and the output voltage terminal V. O Between 130 and 130. Current I L The current flows through inductor 110. Capacitor C O 126 and resistor R O 128 are connected in parallel to the output voltage terminal V O Between 130 and the ground terminal. Capacitor C O 126 and resistor R O 128 represent the load capacitor and load resistor on the output, respectively.

[0055] Resistor 132 is coupled to the output voltage terminal V O Resistor 130 is connected between the output voltage feedback terminal 133 and the output voltage feedback terminal 133. Resistor 136 is coupled between the output voltage feedback terminal 133 and the ground terminal. Resistors 132 and 136 are connected between the output voltage V and the ground terminal. O A voltage divider is formed on 130. The voltage at the output voltage feedback terminal 133 is V. FB The inverting input of amplifier 134 is coupled to the output voltage feedback terminal 133 and receives voltage V. FB Reference voltage source 138 is coupled between the non-inverting input of amplifier 134 and the ground terminal, and provides a reference voltage V.REF Voltage V REF It is a reference voltage that represents the specified nominal output voltage of the switching voltage regulator 400.

[0056] In at least one instance, amplifier 134 is a transconductance amplifier. Amplifier 134 outputs the voltage V at the feedback terminal 133. FB With reference voltage V REF Compare and provide a value similar to V at its output. FB and V REF The current is proportional to the difference between them. Clamping circuit 140 is coupled between the output of amplifier 134 and the ground terminal. The purpose of clamping circuit 140 is to ensure the compensation voltage V COMP 135 does not exceed the clamping voltage V dynamically generated in the clamping circuit 140. Clamp Clamping voltage V Clamp Equal to a fixed voltage and the sensed inductor current V ISENSE Summation of 350 in scaled form.

[0057] The current sensing circuit 118 is coupled to the output voltage terminal V. O Between 130 and the first non-inverting input of comparator 112. Current sensing circuit 118 senses the current flowing through inductor 110 and provides a voltage V proportional to the current flowing through inductor 110. ISENSE 350. The Slope Comp generator 116 is coupled between the second non-inverting input of comparator 112 and the ground terminal. The Slope Comp generator 116 provides a slope-compensated waveform at the frequency of the switching voltage regulator.

[0058] The current sensing signal V from the current sensing circuit 118 ISENSE 350 is summed with the ramp-compensated waveform from Slope Comp generator 116 to form the non-inverting input of comparator 112. The output of amplifier 134 is coupled to the inverting input of comparator 112, thereby providing signal V at the inverting input of comparator 112. COMP 135. Resistor R COMP 120 is coupled to the output of amplifier 134 with capacitor C COMP Between the first terminals of capacitor C (122). COMP The second terminal of capacitor 122 is coupled to the ground terminal. Capacitor C O_EA 124 is coupled between the output of amplifier 134 and the ground terminal. Resistor R COMP 120. Capacitor C COMP 122 and capacitor C O_EA 124 forms a Type II compensation filter, which is typically used in current-mode control circuits.

[0059] Capacitor C COMP 122 sets the crossover frequency of the Type II compensation filter. Resistor R COMP 120 and capacitor C COMP 122 series coupling, and provides a zero point in the type II compensated filter. Capacitor C O_EA Capacitors 124 typically have small capacitance values ​​(e.g., 10pF) and are primarily used to filter high-frequency noise rather than to provide stability to the control loop. The stability of the control loop is mainly determined by capacitor C. COMP 122 and resistor R COMP Provided by 120.

[0060] Comparator 112 is shown as having three inputs, but it can also be shown as having a summing terminal coupled to a single non-inverting input of comparator 112, wherein the current sensing signal V ISENSE 350 with slope-compensated wave V from Slope Comp generator 116 SLOPE_COMP The summation is then provided as a non-inverting input to comparator 112. Comparator 112 sums this signal with the compensation voltage V. COMP The 135 performs a comparison and provides the output signal to the Reset input of latch 108. In at least one instance, latch 108 is an RS flip-flop.

[0061] Clock generator 114 is coupled between the Set input of latch 108 and the ground terminal. The clock generator provides a square wave signal with the same frequency as the switching frequency of the switching voltage regulator 400. The square wave signal generated by clock generator 114 has a slope-compensated waveform V generated by slope compensator 116. SLOPE_COMP It has the same frequency and is in phase with the slope compensation waveform.

[0062] The Q output of latch 108 is coupled to the control terminal of transistor 104 and controls the switching on and off of transistor 104. The QN output of latch 108, which is an inverted Q output, is coupled to the control terminal of transistor 106 and controls the switching on and off of transistor 106. In several instances, additional first drive stages (not shown) and second drive stages (not shown) are coupled between the Q output of latch 108 and the control terminal of transistor 104, and between the QN output of latch 108 and the control terminal of transistor 106, respectively, to ensure sufficient drive is provided to the control terminals of transistors 104 and 106 to turn them on.

[0063] Clamping circuit 140 includes buffer amplifier 442, summer 446, rectifier 448, amplifier 450, and transistor 452. In some example systems, rectifier 448 may be omitted. Buffer amplifier 442 has an input coupled to the output of current sensing circuit 118, which receives signal V. ISENSE 350. The output of buffer amplifier 442 is coupled to the first input of summer 446, which receives V ISENSE The buffered type of 350. The second input of the summer 446 receives a constant voltage V. Base_Clamp 340, which is equal to V COMP_Offset 310, V MAX_Slope_Comp 320 and safety margin voltage V margin The sum of 330.

[0064] The output of summer 446 is coupled to the input of rectifier 448. The output of rectifier 448 is coupled to the inverting input of amplifier 450. In some example systems, rectifier 448 is omitted, in which case the output of summer 446 is directly coupled to the inverting input of amplifier 450. Rectifying the inductor current improves performance because it adds the peak inductor current to V. Base_Clamp 340 provides the most accurate clamping voltage V Clamp 360. Ideally, the clamping voltage V Clamp The peak inductor current is tracked 360° and is provided by rectifying the inductor current sensing signal. However, rectifying the inductor current sensing signal is not necessary.

[0065] In this specification, the terms “terminal,” “node,” “interconnect,” “lead,” and “pin” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnections or terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0066] In this specification, “grounding” includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification.

[0067] In this specification, the term "coupling" may encompass a connection, link, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0068] In this specification, even though operations are described in a specific order, some operations may be optional and need not be performed in the specified order to achieve the intended result. In some instances, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the embodiments described above is not necessarily required in all embodiments.

[0069] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are possible.

Claims

1. A voltage regulator circuit, comprising: An amplifier having first and second amplifier inputs and an amplifier output, wherein the first amplifier input is coupled to a feedback voltage terminal and the second amplifier input is coupled to a reference voltage terminal; A comparator having first and second comparator inputs and a comparator output, wherein the first comparator input is coupled to the amplifier output; A current sensing circuit having a current sensing input and a current sensing output, wherein the current sensing input is coupled to an output voltage terminal, the current sensing output is coupled to a second comparator input, and the current sensing circuit is configured to provide a current sensing voltage at the current sensing output that is proportional to the current being delivered to the output voltage terminal. A waveform generator coupled between the input of the second comparator and a ground terminal, wherein the waveform generator can be configured to provide a waveform signal at a switching frequency; A latch having first and second latch inputs and first and second latch outputs, wherein the first latch input is coupled to the comparator output; A clock generator coupled between the second latch input and the ground terminal, the clock generator being configurable to provide a clock signal at the switching frequency; as well as A voltage clamping circuit having first and second voltage clamping inputs and a voltage clamping output, wherein the first voltage clamping input is coupled to the current sensing output, the second voltage clamping input is coupled to a fixed voltage source, the voltage clamping output is coupled to the first comparator input, and the voltage clamping circuit can be configured to limit the voltage at the first comparator input to a clamping voltage that varies in response to the current sensing voltage.

2. The voltage regulator circuit according to claim 1, wherein the waveform signal is a sawtooth waveform.

3. The voltage regulator circuit according to claim 1, wherein the waveform signal and the clock signal are in phase.

4. The voltage regulator circuit according to claim 1, wherein the latch is a trigger, the first latch input is a reset input, and the second latch input is a set input.

5. The voltage regulator circuit of claim 1, wherein the fixed voltage source provides a fixed voltage, the fixed voltage being the sum of the maximum voltage of the waveform signal and the minimum voltage at the input of the first comparator required to trigger a switch in the latch.

6. The voltage regulator circuit according to claim 1, wherein the voltage regulator circuit further comprises: A resistor and a first capacitor are coupled in series between the first comparator input and the ground terminal; as well as A second capacitor is coupled between the input of the first comparator and the ground terminal.

7. The voltage regulator circuit of claim 6, wherein the amplifier is a first amplifier, the amplifier output is a first amplifier output, and the voltage clamping circuit comprises: A buffer having a buffer input and a buffer output, wherein the buffer input is coupled to the current sensing output; A summer having first and second summer inputs and a summer output, wherein the first summer input is coupled to the buffer output and the second summer input is coupled to the fixed voltage source; A second amplifier has third and fourth amplifier inputs and a second amplifier output, wherein the third amplifier input is coupled to the summer output and the fourth amplifier input is coupled to the first comparator input; as well as A transistor coupled between the input of the fourth amplifier and the ground terminal.

8. The voltage regulator circuit of claim 7, further comprising a rectifier circuit coupled between the summer output and the third amplifier input.

9. The voltage regulator circuit of claim 7, wherein the fixed voltage source provides a fixed voltage, the fixed voltage being the sum of the maximum voltage of the waveform signal and the minimum voltage at the first comparator input required to trigger a switch in the latch.

10. The voltage regulator circuit according to claim 1, further comprising: The first transistor is coupled between the input voltage source and the switching terminal, and has a first control terminal coupled to the output of the first latch. as well as The second transistor is coupled between the switch terminal and the ground terminal, and has a second control terminal coupled to the output of the second latch.

11. The voltage regulator circuit of claim 10, further comprising an inductor coupled between the switching terminal and the output voltage terminal.

12. The voltage regulator circuit according to claim 11, further comprising: A first resistor is coupled between the output voltage terminal and the feedback voltage terminal; as well as A second resistor is coupled between the feedback voltage terminal and the ground terminal.

13. A method for controlling a voltage converter circuit, comprising: The first field-effect transistor (FET) and the second FET are connected in series between the input voltage terminal and the ground terminal; An inductor is coupled between a switch terminal and an output voltage terminal, wherein the output voltage terminal provides an output voltage, and the first and second FETs are connected at the switch terminal; A current is generated at the compensation terminal, the current being proportional to the difference between a reference voltage and a voltage proportional to the output voltage, the voltage proportional to the output voltage generating a compensation voltage that tracks the current passing through the inductor. Generate waveform signals and clock signals that are of the same frequency and in phase. The compensation voltage is limited to not exceeding the clamping voltage, wherein the clamping voltage is equal to the sum of the maximum voltage of the waveform signal, the minimum compensation voltage required to trigger the switching of the first and second FETs, and the current sensing voltage proportional to the current passing through the inductor; The compensation voltage is compared with a comparison voltage using a comparator with a comparator output, wherein the comparison voltage is equal to the sum of the maximum voltage of the waveform signal and the minimum compensation voltage required to trigger the switching of the first and second FETs; as well as The first and second FETs are controlled in response to the comparator output.

14. The method of claim 13, wherein limiting the compensation voltage comprises: The current-sensing voltage is provided to the first input of a summing circuit having a summer output; A constant voltage is provided to the second input of the summing circuit, wherein the constant voltage includes the maximum voltage of the waveform signal and the minimum compensation voltage required to trigger the switching of the first and second FETs; as well as The summer output is coupled to the first input of the amplifier, and the compensation terminal is coupled to the second input of the amplifier; as well as The transistor is coupled between the compensation terminal and the ground terminal, and the output of the amplifier is coupled to the control terminal of the transistor.

15. The method of claim 14, wherein limiting the compensation voltage further comprises coupling the input of the rectifier circuit to the summer output and coupling the output of the rectifier circuit to the first input of the amplifier.

16. The method of claim 14, wherein the current-sensing voltage is buffered using a buffer amplifier before being provided to the first input of the summing circuit.

17. The method of claim 13, further comprising filtering the compensation voltage using a compensation filter.

18. The method of claim 17, wherein the compensation filter comprises at least one pole and one zero.

19. The method of claim 13, wherein the waveform signal is a sawtooth waveform.

20. The method of claim 19, wherein the voltage converter circuit is a buck voltage converter circuit.

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