Active historical read adaptation without test read

Abstract

The invention provides a method for reading data from a memory and an associated memory system. The method and memory system: perform a read operation on a memory while recording a historical set of entries of voltage used to read the memory as a read retry (RR) bias; selecting an RR bias from the historical entry set for a subsequent read operation without performing the test operation using any RR bias prior to the subsequent read operation of the memory; in the subsequent reading operation, reading the memory by utilizing one or more RR offsets in the historical entry set; when the failure bit count of the subsequent reading operation is higher than a threshold value, deleting a worst entry from the historical entry set, and introducing a new historical entry into the historical entry set; and updating the RR bias based on the new historical entry.

Description

Technical Field

[0001] This invention relates to reading data from a solid-state drive (SSD) memory device. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices (i.e., data storage devices). Data storage devices serve as either primary or secondary memory devices in portable electronic devices. Because data storage devices using memory devices have no moving parts, they offer excellent stability, durability, high data access speeds, and low power consumption. Examples of data storage devices with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs).

[0003] An SSD may include flash memory and a controller, the controller including electronics that bridge the flash memory to the SSD input / output (I / O) interface. The SSD controller may include an embedded processor capable of executing functional components such as firmware. These SSD functional components are device-specific and, in most cases, updatable. Two main types of flash memory are named after NAND and NOR logic gates. Individual flash memory cells exhibit internal characteristics similar to their corresponding gates. NAND flash memory can be written to and read in blocks (or pages), which are typically much smaller than the entire storage space. NOR flash memory allows individual machine words (bytes) to be written to erased locations or read independently. NAND flash memory is primarily used in memory cards, USB flash drives, solid-state drives, and similar products for general data storage and transfer.

[0004] Against this backdrop, embodiments of the present invention have emerged. Summary of the Invention

[0005] According to one embodiment of the present invention, a method for reading data from a memory is provided. The method includes: performing a read operation on the memory while recording a historical set of voltage entries used for reading the memory as a read retry (RR) bias; selecting an RR bias from the historical set for subsequent read operations without using any RR bias to perform a test operation before subsequent read operations on the memory; reading the memory using one or more RR biases from the historical set during the subsequent read operation; deleting the worst entry from the historical set and introducing a new historical entry into the historical set when the failure bit count of the subsequent read operation exceeds a threshold; and updating the RR bias based on the new historical entry.

[0006] According to another embodiment of the present invention, a memory system is provided, including a memory and a controller configured to read data from the memory. The controller is configured to: perform a read operation on the memory while recording a historical set of voltage entries used for reading the memory as a read retry (RR) bias; select an RR bias from the historical set for subsequent read operations without using any RR bias to perform a test operation before subsequent read operations on the memory; in subsequent read operations, read the memory using one or more RR biases from the historical set; when the failure bit count of the subsequent read operation is higher than a threshold, delete the worst entry from the historical set and introduce a new historical entry into the historical set; and update the RR bias based on the new historical entry. Attached Figure Description

[0007] Figure 1 This is a high-level block diagram illustrating an error correction system according to an embodiment of the present invention.

[0008] Figure 2 This is a block diagram schematically illustrating a memory system according to an embodiment of the present invention.

[0009] Figure 3 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0010] Figure 4A This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention.

[0011] Figure 4B This is a diagram illustrating an example of Gray encoding for a three-layer cell (TLC) according to another embodiment of the present invention.

[0012] Figure 4C This is a diagram illustrating the state distribution of a page in a three-layer cell (TLC) according to another embodiment of the present invention.

[0013] Figure 5 This is a diagram illustrating a storage system including an in-NAND descrambler according to an embodiment of the present invention.

[0014] Figure 6 This is a diagram illustrating the format of codewords to be stored in a storage system according to an embodiment of the present invention.

[0015] Figure 7 This is a diagram illustrating the concurrent Quality of Service (QoS) requirements for solid-state drives.

[0016] Figure 8This is a diagram showing the decodeable region of the least significant bit page.

[0017] Figure 9 This is a flowchart illustrating a method for reading data from a storage device according to an embodiment of the present invention.

[0018] Figure 10 This is a flowchart illustrating a method for updating a read retry bias according to an embodiment of the present invention.

[0019] Figure 11 This is a flowchart illustrating another method for updating the read retry bias according to an embodiment of the present invention. Detailed Implementation

[0020] Various embodiments will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same parts in the various figures and embodiments of the invention.

[0021] This invention can be embodied in a variety of ways, including as a component of a process, apparatus, system, or substance; a computer program product contained on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided by memory coupled to the processor. In this specification, these embodiments or any other form of the invention that may take the form of the invention may be referred to as technology. Generally, within the scope of this invention, the order of steps of the disclosed process may be varied. Components described as suitable for performing a task, such as processors or memory, unless otherwise stated, may be implemented as general-purpose components temporarily adapted to perform a task at a given time or as specific components manufactured for performing a task. As used herein, the term "processor" means one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0022] The following provides a detailed description of one or more embodiments of the present invention, along with accompanying drawings illustrating the principles of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention includes many alternatives, modifications, and equivalent examples. To provide a thorough understanding of the invention, numerous specific details are set forth in the following description. These details are provided for illustrative purposes, and the invention may be practiced without some or all of these specific details, as claimed. For clarity, technical materials known in the art related to the invention have not been described in detail, so that the invention will not be unnecessarily obscured.

[0023] Figure 1 This is a high-level block diagram illustrating an error correction system 2 according to an embodiment of the present invention. More specifically, Figure 1 The high-level block diagram shows that the error correction system 2 includes an encoder 5 and a decoder 15 using, for example, LDPC encoding and decoding algorithms. That is, the error correction system 2 may include LDPC encoder 5 and LDPC decoder 15, but other encoding and decoding algorithms may also be used.

[0024] LDPC encoder 5 can receive data including data that is desired to be stored in storage system 10 (such as...). Figure 2 The information bits of data in the memory system 20 are encoded by the LDPC encoder 5 to output LDPC encoded data. The LDPC encoded data from the LDPC encoder 5 can be written to the storage device or memory device of the storage system 10. In various embodiments, the storage device may include various storage types or media. In some embodiments, data is transmitted and received via wired and / or wireless channels during writing to or reading from the storage device. In this case, errors in the received codewords may have been introduced during the transmission of the codewords.

[0025] When data stored in storage system 10 is requested or otherwise needed (e.g., requested or needed by the application or user storing the data), LDPC decoder 15 can perform LDPC decoding on data received from storage system 10, which may include some noise or errors. In various embodiments, LDPC decoder 15 may use decision and / or reliability information of the received data to perform LDPC decoding. The decoded bits generated by LDPC decoder 15 are sent to the appropriate entity (e.g., the user or application that requested it). Through appropriate encoding and decoding, the information bits are matched with the decoded bits.

[0026] Figure 2 This is a block diagram schematically illustrating a memory system 20 according to an embodiment of the present invention.

[0027] Reference Figure 2 The memory system 20 may include a memory controller 100 and a semiconductor memory device 200.

[0028] The memory controller 100 can control the overall operation of the semiconductor memory device 200.

[0029] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Control signals may include command latch enable (CLE), address latch enable (ALE), chip enable (CE), write enable (WE), and read enable (RE) signals, etc.

[0030] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as an SSD. The solid-state drive can include a storage device for storing data therein. When the memory system 20 is used with an SSD, the operating speed of a host (not shown) connected to the memory system 20 can be significantly improved.

[0031] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device to configure memory cards such as: PC cards of the Personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC), Reduced Size Multimedia Cards (RS-MMC), Miniature Version of MMC (Micro MMC), Secure Digital (SD) cards, Mini Secure Digital (Mini SD) cards, Micro Secure Digital (Micro SD) cards, Secure Digital High Capacity (SDHC) cards, and Universal Flash Memory (UFS).

[0032] For another example, the memory system 20 may be provided as one of a variety of components, including electronic devices such as: computers, ultra-mobile PCs (UMPCs), workstations, netbook computers, personal digital assistants (PDAs), portable computers, network tablet PCs, cordless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital image recorders, digital image players, digital video recorders, digital video players, storage devices for data centers, devices capable of receiving and transmitting information in a wireless environment, one of the electronic devices for a home network, one of the electronic devices for a computer network, one of the electronic devices for a telematics network, radio frequency identification (RFID) devices, or component devices for computing systems.

[0033] Figure 3 These are detailed block diagrams illustrating various embodiments of a memory system 30 according to one embodiment of the present invention. For example, Figure 3 The memory system 30 can be described Figure 1 The storage system 10 shown or Figure 2 The memory system 20 shown is shown.

[0034] Reference Figure 3 The memory system 30 may include a memory controller 100 and a semiconductor memory device 200. The memory system 30 can operate in response to a request from a host device, and in particular, stores data to be accessed by the host device.

[0035] The host device can be implemented using any of a variety of electronic devices. In some embodiments, the host device may include electronic devices such as desktop computers, workstations, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital image recorders, digital image players, digital video recorders, and digital video players. In some embodiments, the host device may include portable electronic devices such as mobile phones, smartphones, e-book readers, MP3 players, portable multimedia players (PMPs), and portable game consoles.

[0036] The memory device 200 can store data to be accessed by the host device.

[0037] The memory device 200 can be implemented using volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM), or using non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM, electrically erasable programmable ROM, ferroelectric random access memory (FRAM), phase-change RAM, magnetoresistive RAM and resistive RAM.

[0038] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from the host. The controller 100 can provide data read from the memory device 200 to the host, and store data provided by the host into the memory device 200.

[0039] The controller 100 may include a storage unit 110, a control unit 120, an error correction code (ECC) unit 130, a host interface (I / F) 140, and a memory interface (I / F) 150 connected via a bus 160.

[0040] Storage unit 110 can be used as working memory for storage system 10 and controller 100, and stores data for driving storage system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage unit 110 can store data for operations such as read operations, write operations, programming operations and erase operations performed by controller 100 and memory device 200.

[0041] Storage cell 110 can be implemented using volatile memory. Storage cell 110 can be implemented using static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage cell 110 can store data used by the host device in storage device 200 for read and write operations. For storing data, storage cell 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0042] Reference Figure 3 The control unit 120 can control the overall operation of the memory system 30 and the write or read operations of the memory device 200 in response to write or read requests from the host device. The control unit 120 can drive firmware called the Flash Translation Layer (FTL) to control the overall operation of the memory system 30. For example, the FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and bad block handling. L2P mapping is called logical block addressing (LBA).

[0043] During a read operation, the ECC unit 130 can detect and correct errors in the data read from the memory device 200. When the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC unit 130 may not correct the error bits and may output an error correction failure signal indicating that the correction of error bits has failed.

[0044] In some embodiments, the ECC unit 130 may perform error correction operations based on coding modulation such as LDPC codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The ECC unit 130 may include all circuitry, systems, or devices for error correction operations.

[0045] like Figure 3As shown, host interface 140 can communicate with host devices through one or more of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0046] Memory interface 150 provides an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from a host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control unit (e.g., CPU) 120. When memory device 200 is flash memory, such as NAND flash memory, memory interface 150 can generate control signals for memory and process data under the control of control unit 120.

[0047] Memory device 200 may include memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250, column decoder 260, and input / output circuitry 270. Memory cell array 210 may include a plurality of memory blocks 211, in which data may be stored. In one embodiment of the invention, control circuitry 220 includes a checksum calculator module 220a (described in more detail below). Voltage generation circuitry 230, row decoder 240, page buffer 250, column decoder 260, and input / output circuitry 270 form peripheral circuitry for memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on memory cell array 210. Control circuitry 220 may control the peripheral circuitry.

[0048] The voltage generation circuit 230 can generate operating voltages with various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages with various levels, such as erase voltage and pass voltage.

[0049] The row decoder 240 can be connected to the voltage generation circuit 230 and a plurality of memory blocks 211. In response to the row address RADD generated by the control circuit 220, the row decoder 240 can select at least one memory block among the plurality of memory blocks 211 and send the operating voltage supplied from the voltage generation circuit 230 to the selected memory block among the plurality of memory modules 211.

[0050] Page buffer 250 can be connected to memory cell array 210 via bit line BL (not shown). Page buffer 250 can precharge bit line BL with a positive voltage in response to a page buffer control signal generated by control circuitry 220, send / receive data to / from a selected memory block during programming and read operations, or temporarily store the sent data.

[0051] The column decoder 260 can send data to / receive data from the page buffer 250, or send data to / receive data from the input / output circuit 270.

[0052] The input / output circuit 270 can send commands and addresses transmitted from an external device (e.g., memory controller 100) to the control circuit 220, send data from an external device to the column decoder 260, or output data from the column decoder 260 to an external device via the input / output circuit 270.

[0053] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0054] Figure 4A This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 4A The storage block can be Figure 3 Storage block 211 of the memory cell array 210 shown.

[0055] Reference Figure 4A The memory block 211 may include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). Multiple memory cells or memory cell transistors may be connected in series between the select transistors DST and SST. Each of the memory cells MC0 to MCn-1 may be formed by a multilayer cell (MLC) that stores multiple bits of data information in each cell. The cell strings 221 may be electrically connected to the corresponding bit lines BL0 to BLm-1 respectively.

[0056] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to NAND flash memory, but may include NOR flash memory, hybrid flash memory that combines two or more types of memory cells, and integrated NAND flash memory with the controller embedded in the memory chip.

[0057] Return to reference Figure 3 and Figure 4AThe memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). Figure 4A As shown, memory cells are arranged in an array of rows and columns. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, the data to be written ("1" or "0") is provided on the bit line, and the word line is addressed. During a read operation, the word line is addressed again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, multiple pages include a Most Significant Bit (MSB) page and a Least Significant Bit (LSB) page. When the memory cell is implemented using Three-Level Cell (TLC), multiple pages include an MSB page, a Center Significant Bit (CSB) page, and an LSB page. When the memory cell is implemented using Four-Level Cell (QLC), multiple pages include an MSB page, a Center Most Significant Bit (CMSB) page, a Center Least Significant Bit (CLSB) page, and an LSB page. The memory cells can be programmed, for example, using an encoding scheme (e.g., Gray encoding), to increase the capacity of the storage system 10, such as an SSD.

[0058] Figure 4B This is a diagram illustrating an example of Gray encoding for a three-layer cell (TLC).

[0059] Reference Figure 4B TLCs can be programmed using Gray code. A TLC can have eight programming states, including an erase state E (or P0) and first programming states P1 through seventh programming states P7. Eraser state E (or P0) can correspond to "111". First programming state P1 can correspond to "011". Second programming state P2 can correspond to "001". Third programming state P3 can correspond to "000". Fourth programming state P4 can correspond to "010". Fifth programming state P5 can correspond to "110". Sixth programming state P6 can correspond to "100". Seventh programming state P7 can correspond to "101".

[0060] In TLC, such as Figure 4CAs shown, there are three types of pages: LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds are VT0 and VT4. Threshold VT0 distinguishes between erase state E and the first programming state P1, and threshold VT4 distinguishes between the fourth programming state P4 and the fifth programming state P5. For CSB pages, the three thresholds are VT1, VT3, and VT5. VT1 distinguishes between the first programming state P1 and the second programming state P2. VT3 distinguishes between the third programming state P3 and the fourth programming state P4. VT5 distinguishes between the fifth programming state P5 and the sixth programming state P6. For LSB pages, the two thresholds are VT2 and VT6. VT2 distinguishes between the second programming state P2 and the third programming state P3. VT6 distinguishes between the sixth programming state P6 and the seventh programming state P7.

[0061] Figure 5 This is a diagram illustrating a storage system according to an embodiment of the present invention. (Refer to...) Figure 5 The NAND module 500 may include NAND memory 550 as a storage device and includes a NAND processor 505, which includes a checksum calculator 510. The NAND processor 505 can perform read operations on data in the NAND memory 550. During a read operation, it may be necessary to descramble the data to the correct format in order to calculate the checksum. The checksum calculator 510 is then able to calculate the checksum to estimate the RBER.

[0062] When the number of error bits is greater than or equal to the threshold number of correctable error bits, an error correction failure signal can be output, indicating that the error bit correction has failed. This failure may require the information bits from the host to be resent to the NAND memory 550. Therefore, the checksum calculator 510 can be used to provide an estimate of the RBER in the data to be stored in the NAND memory 550.

[0063] In various embodiments, Figure 5 The NAND module 500 shown can be implemented using various technologies, including application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and / or general-purpose processors (e.g., advanced RISC machine (ARM) cores).

[0064] As background technology Figure 6 This is a diagram illustrating the format of codeword 600 to be stored in the storage system. (See reference...) Figure 6 The codeword 600 may include information data 610 (information bits or user data) and LDPC parity data 620. In some embodiments, the codeword 600 may be generated from the LDPC code described above.

[0065] Information data 610 may include user data with data path protection (DPP) 612, metadata 614, and cyclic redundancy check (CRC) parity bits 616. CRC codes are error detection codes commonly used in digital networks and storage devices to detect accidental alterations to the original data.

[0066] In a typical LDPC decoder, decoding can terminate if the LDPC checksum is zero. After LDPC decoding, a CRC parity bit 616 is calculated based on the decoded user data 612 and metadata 614. If the calculated CRC parity bit matches the decoded CRC parity bit, decoding may be successful. Otherwise, an error correction may be declared.

[0067] To perform these tasks more efficiently, in one embodiment of the invention, the semiconductor memory device 200 ( Figure 3 (middle) or NAND module 500 ( Figure 5 (In the middle) can measure the checksum to estimate the number of errors in the stored data. This embedded NAND module that calculates RBER can improve SSD performance / power consumption by eliminating the need to transfer stored data to the SOC when the RBER is acceptable.

[0068] This invention recognizes that in SSD Quality of Service (QoS) requirements for solid-state drives (e.g., PCIe Gen 6 enterprise-class SSDs), the 6th-9th percentile latency is limited to 100µs. Considering the worst-case scenario, the latency per read is approximately 55µs, meaning all reads must be successfully decoded on the first or second read. If successful with low latency, a second read is allowed. Beyond the 6th-9th percentile, there is no opportunity for a third read.

[0069] This invention recognizes that the defense algorithm operates in a passive manner, meaning that the read bias setting is not updated until a read fails. This operation further challenges SoC design because determining better first and second read bias settings may require violating QoS 6-9 requirements.

[0070] Therefore, in one embodiment of the invention, proactive history read adaptation is used to determine better first and second read bias settings instead of test reads. Compared to existing defense algorithms, this proactive history read adaptation scheme provides better QoS and reliability.

[0071] QoS requirements

[0072] Figure 7 This is a diagram illustrating the concurrent QoS requirements of a solid-state drive. More specifically, Figure 7The QoS requirements for PCIe Gen 6 enterprise-class SSDs (eSSDs) are shown. For read commands, the worst latency is approximately 50µs. Clearly, 99.9999% of read commands need to be successfully decoded on the first read attempt. A second read may be allowed if it can be decoded with a latency of less than 45µs. A third read is not permitted at the 6th-9th QoS percentile because the previous two read failures have already consumed 110µs of latency.

[0073] Figure 7 The Gen-6 eSSD QoS requirements shown indicate that defense algorithms for solid-state drives, such as PCIe Gen 6 enterprise-class SSDs, need to focus on the first two reads. Any optimizations to read retries (RR) after the second read will not provide a meaningful improvement to QoS.

[0074] Decodeable area

[0075] Figure 8 This is a diagram of the decodeable region of the LSB page. The choice of read bias affects the failure bit count (FBC) at the decoder input. Figure 8 In the diagram, as shown by the dashed outline, the boundary map of the decodeable region is defined as the choice of V2 and V6 (as the read bias of the LSB page), which gives an FBC with acceptable ECC correction capability. The decodeable region spans approximately 0.3V in the V2 dimension (from 0.35V to 0.65V) and 0.2V in the V6 dimension (from 3.15V to 3.35V). Considering the 20mV steps used for read bias changes in NAND devices, there are approximately 150 different combinations of V2 and V6 that fall within the decodeable region defined by the dashed outline.

[0076] Active history reading adaptation

[0077] To prevent read failures, one embodiment of the present invention performs historical read bias optimization in a proactive manner. This can be achieved by using... Figure 3 The first read bias optimization is performed using the FBC obtained from the ECC unit 130 or the checksum information obtained from the control circuit 220.

[0078] While test reads can be used, this invention recognizes that test reads may introduce additional traffic and may conflict with host reads, thus degrading QoS. The extent of the QoS impact depends on the probability of the conflict. In one embodiment of this invention, test reads are not used, although a limited number of test reads may be employed.

[0079] For storage blocks undergoing host reads, in one embodiment, the invention relies on host reads to adjust historical read biases to acceptable bias values, where the FBC is acceptable. For storage blocks without ongoing or planned host reads, in one embodiment, the invention performs read bias optimization based on the embedded NAND partial checksum (PCS). There is no conflict between the sensing operations of host reads and embedded NAND PCS calculations because no host reads the NAND medium.

[0080] Adaptive strategy for host read

[0081] In a storage block with ongoing host read traffic, the read bias is adjusted to historical reads using host reads instead of test reads. In one embodiment, instead of using only one read retry (RR) entry as a historical read, the invention utilizes multiple RRs as multiple historical read biases, such as three RRs, denoted as historical read-0 (HR0), historical read-1 (HR1), and historical read-2 (HR2).

[0082] In one embodiment, historical reads HR0, HR1, and HR2 are performed at voltage threshold Vth (e.g., ...). Figure 4C The Vth shown (VT0, VT1, VT2, VT3, VT4, VT5, and VT6) are close to each other in terms of Euclidean distance. History reads can be recorded per die, per block, or per WL group, depending on any trade-off between complexity / memory footprint and accuracy. In one embodiment, the performance of multiple history reads such as HR0, HR1, and HR2 can be selected randomly or in a deterministic manner, such as polling, so that each entry has an equal chance of use.

[0083] Once successfully decoded, the host reads accurate FBC information. When the FBC of any of the three HR entries exceeds a certain threshold, such as 70% of the ECC correction capability, the worst HR is popped, and a new HR is inserted into the three HR entries. This popping and insertion can occur at a low frequency, such as once every hour, thereby reducing the CPU load on the algorithm.

[0084] An exemplary method for finding HR entries to insert is described below.

[0085] This HR entry search problem can be viewed as a numerical gradient calculation problem. Assume the last FBC in HR0, HR1, and HR2 is FBC0, FBC1, and FBC2. More specifically, assume the LSB page has two read threshold levels (V2, V6) and tracks three distinct historical reads (HR0, HR1, HR2). For each HRi, i∈{0,1,2}, the stored read threshold level is (V2i, V6i), and the corresponding failure bit count is FBCi. Then, the numerical gradients dFBC / dV2 and dFBC / dV6 can be calculated as:

[0086] dFBC / dV2={(FBC0-FBC1) / (V20-V21)+(FBC1-FBC2) / (V21-V22)+ (FBC2-FBC0) / (V22-V20)} / 3, where FBC0, FBC1, and FBC2 are the failure bit counts at V20, V21, and V22 (V20, V21, and V22 are the voltages offset from the voltage threshold V2), and...

[0087] dFBC / dV6 = {(FBC0'-FBC1') / (V60-V61)+(FBC1'-FBC2') / (V61-V62)+ (FBC2'-FBC0') / (V62-V60)} / 3, where FBC0', FBC1', and FBC2' are the failure bit counts at V60, V61, and V62 (V60, V61, and V62 are voltages offset from the voltage threshold V6). In other words, in one embodiment, the numerical gradient is calculated based on the difference in failure bit counts of data read at various voltage offsets from voltage thresholds V2 and V6.

[0088] In one embodiment of the invention, after calculating the numerical gradient, a new entry, namely the voltage threshold level, can be obtained. ),as follows:

[0089] ( ) = ( ),in( The HR is the highest FBC among HR0, HR1, and HR2, where the hyperparameter (i.e., delta) is the step size of the gradient descent algorithm, which can be set, for example, during the implementation and / or optimization of the operation of ECC unit 130 or control circuit 220.

[0090] Adaptive strategy for hostless read

[0091] In NAND memory block regions where no host read commands are in progress, no HR entries are triggered, and no FBC information is available for adaptation. The underlying programming voltage (PV) distribution may still change over time, leading to retention-related issues. In such cases, these solutions, according to different embodiments of the invention, can help mitigate retention-related problems.

[0092] A counter for each block can be used to track retention time. When the retention time exceeds a preset time (e.g., exceeding the maximum allowed time), the block will be reclaimed.

[0093] Test reads can be used in conjunction with an active history read adaptive scheme to adapt to the HR entries for each block. Embedded NAND checksum calculations can be used to estimate the FBC and update HR entries without test reads.

[0094] Computerized methods

[0095] In one embodiment of the present invention, a method for reading data from a memory (e.g.) is provided. Figure 9 (As shown). This method can be used in... Figure 2 This is implemented in the ECC unit 130 or control circuit 220. At 901, a read operation is performed on the memory, and a set of historical entries for the voltage used to read the memory is recorded as a read retry (RR) bias. At 903, the method selects an RR bias from the historical entry set for subsequent read operations without using any RR bias during a test operation prior to the subsequent read operation. At 905, in the subsequent read operation, the method reads the memory using one or more RR biases from the historical entry set. At 907, when the failure bit count of the subsequent read operation exceeds a threshold, the method removes the worst entry from the historical entry set and introduces a new historical entry into the historical entry set. At 909, the method updates the RR bias based on the new historical entry and the excluded worst entry.

[0096] In one embodiment, the method further includes recording a historical read set for each die, each block, or each WL group.

[0097] In one embodiment, the method further includes: randomly selecting an RR bias from a historical read set to read the memory in a subsequent read operation.

[0098] In one embodiment, the method further includes: selecting RR biases from a historical read set for reading the memory in subsequent read operations, such that each RR bias has an equal chance of being used.

[0099] In one embodiment, the method further includes determining a new historical entry based on the difference gradient between voltage thresholds used to read a page in memory that has the lowest failure bit count (FBC).

[0100] In one embodiment of the method, the memory includes a three-level cell (TLC), and the voltage threshold is a voltage associated with reading one or more of the most significant bit page, the center significant bit page, and the least significant bit page.

[0101] In one embodiment of the method, the voltage thresholds are the voltages V2 and V6 used to read the least significant bit page.

[0102] In one embodiment of the method, the new history entry is determined as ( ), where dFBC / dV2 and dFBC / dV6 are the numerical gradients of the failure bit count (FBC) at voltage thresholds V2 and V6, and delta is a constant that defines the gradient step size.

[0103] In one embodiment of the method, a numerical gradient is calculated based on the difference in the failure bit counts of data read at various voltage offsets from voltage thresholds V2 and V6.

[0104] In one embodiment, the method further includes: performing a test operation using one or more RR biases after updating the RR bias, and adjusting the voltage in the historical entry set.

[0105] In another embodiment of the invention, a method for reading data from a memory (such as...) is provided. Figure 10 (As shown). This method can be used in... Figure 2 Implemented in ECC unit 130 or control circuit 220. At 1001, for memory with no ongoing host reads, the method (hereinafter referred to as the non-host read method for distinction rather than limitation) uses a counter for each block to track the corresponding retention time since each block was read. At 1003, when any retention time exceeds a threshold, the method identifies the reclaimed memory block exceeding the threshold and reclaims it by adjusting the previous history read set used to read the reclaimed block. At 1005, the method tests the read of the reclaimed memory block using one or more read retry RR biases from the history read set and performs a checksum calculation to estimate the failure bit count. At 1007, when the failure bit count is higher than the threshold, the method removes the worst entry from the previous history read set and introduces a new history entry into the history entry set. At 1009, the method updates the RR bias for subsequent read operations based on the new history entry and the previous history read set excluding the worst entry.

[0106] The above-mentioned non-host reading method can be combined with the above text. Figure 9 Any operation described.

[0107] In one embodiment, the non-host read method further includes forming a previous history read set by recording the read bias for each die, each block, or each WL group.

[0108] In one embodiment, the non-host read method further includes randomly selecting an RR bias from a previous historical read set to read the memory in subsequent read operations.

[0109] In one embodiment, the non-host read method further includes selecting RR biases from the historical read set for reading the memory in subsequent read operations, such that each RR bias has an equal chance of being used.

[0110] In one embodiment, the non-host read method further includes determining new historical entries based on the difference gradient between voltage thresholds used to read historical entries in memory that have the lowest failure bit count (FBC).

[0111] In one embodiment of the non-host read method, the memory includes a three-level cell (TLC), and the voltage threshold is a voltage associated with reading one or more of the most significant bit page, the center significant bit page, and the least significant bit page.

[0112] In one embodiment of the non-host read method, the voltage thresholds are the voltages V2 and V6 used to read the least significant bit page.

[0113] In one embodiment of the method, the new history entry is determined as ( ), where dFBC / dV2 and dFBC / dV6 are the numerical gradients of the failure bit count (FBC) at voltage thresholds V2 and V6, and delta is a constant that defines the gradient step size.

[0114] In one embodiment of the non-host read method, a numerical gradient is calculated based on the difference in the failure bit counts of data read at various voltage offsets from voltage thresholds V2 and V6.

[0115] In one embodiment, the non-host read method further includes performing a test operation with one or more RR biases after updating the RR bias and adjusting the voltage in the historical entry set.

[0116] In another embodiment of the invention, a method for reading data from a memory (such as...) is provided. Figure 11 (As shown). This method can be used in... Figure 2This is implemented in the ECC unit 130 or control circuit 220. At 1101, the method (hereinafter referred to as the history adaptive read method for distinction and not limitation) determines the read retry (RR) bias based on the initial history read set used to read the memory. At 1103, the method determines whether the failure bit count during a memory read is higher than a threshold. At 1105, the method removes the worst entry from the initial history read set and introduces a new history entry into the history entry set to generate an adaptive history read set. At 1107, the method updates the RR bias used for subsequent read operations based on the adaptive history read set.

[0117] The above-mentioned adaptive historical reading method can utilize the above-mentioned Figure 9 Any operation described in the document.

[0118] In one embodiment, the history adaptive read method further includes forming an initial history read set by recording the read bias for each die, each block, or each WL group.

[0119] In one embodiment, the history adaptive read method further includes randomly selecting an RR bias from an initial history read set to read the memory in subsequent read operations.

[0120] In one embodiment, the history adaptive read method further includes selecting RR biases from an initial history read set used for reading the memory in subsequent read operations, such that each RR bias has an equal chance of being used.

[0121] In one embodiment, the history adaptive read method further includes determining new history entries based on the difference gradient between voltage thresholds used to read history entries in memory that have the lowest failure bit count (FBC).

[0122] In one embodiment of the history adaptive read method, the memory includes a three-level cell (TLC), and the voltage threshold is a voltage associated with reading one or more of the most significant bit page, the center significant bit page, and the least significant bit page.

[0123] In one embodiment of the history adaptive read method, the voltage thresholds are the voltages V2 and V6 used to read the least significant bit page.

[0124] In one embodiment of the method, the new history entry is determined as ( ), where dFBC is the difference in FBC between the data read at voltage thresholds V2 and V6, and delta is a constant. dFBC / dV2 and dFBC / dV6 are the numerical gradients of the failure bit count (FBC) at voltage thresholds V2 and V6, respectively, and delta is a constant defining the gradient step size.

[0125] In one embodiment of the history adaptive read method, a numerical gradient is calculated based on the difference in the failure bit counts of data read at various voltage offsets from voltage thresholds V2 and V6.

[0126] In one embodiment, the history adaptive read method further includes performing a test operation using one or more RR biases after updating the RR bias and adjusting the voltage in the history entry set.

[0127] Memory system

[0128] In another embodiment of the invention, a memory system (such as...) is provided. Figure 3 As shown, the device includes: a memory; and a controller coupled to the memory and configured to read data from the memory. The controller is configured to: perform a read operation on the memory while recording a historical set of voltage entries used for reading the memory as a read retry (RR) bias; select an RR bias from the historical set for subsequent read operations without using any RR bias to perform a test operation before subsequent read operations on the memory; in subsequent read operations, read the memory using one or more RR biases from the historical set; when the failure bit count of the subsequent read operation is higher than a threshold, delete the worst entry from the historical set and introduce a new historical entry into the historical set; and update the RR bias based on the new historical entry.

[0129] In one embodiment of the memory system, the controller is configured to record the historical read set for each die, each block, or each WL group.

[0130] In one embodiment of the memory system, the controller is configured to randomly select the RR bias from the historical read set for reading the memory in subsequent read operations.

[0131] In one embodiment of the memory system, the controller is configured to select RR biases from the historical read set for reading the memory in subsequent read operations, such that each RR bias has an equal chance of being used.

[0132] In one embodiment of the memory system, the controller is configured to determine new historical entries based on the difference gradient between voltage thresholds used to read historical entries in the memory that have the lowest failure bit count (FBC).

[0133] In one embodiment of the memory system, the memory includes a three-level cell (TLC), and the voltage threshold is a voltage associated with reading one or more of the most significant bit page, the center significant bit page, and the least significant bit page.

[0134] In one embodiment of the memory system, the voltage thresholds are the voltages V2 and V6 used to read the least significant bit page.

[0135] In one embodiment of the memory system, the controller is configured to identify new history entries as ( ), where dFBC / dV2 and dFBC / dV6 are the numerical gradients of the failure bit count (FBC) at voltage thresholds V2 and V6, and delta is a constant that defines the gradient step size.

[0136] In one embodiment of the memory system, the controller is configured to calculate a numerical gradient based on the difference in the failure bit counts of data read at respective voltage offsets from voltage thresholds V2 and V6.

[0137] In one embodiment of the memory system, the controller is configured to perform a test operation using one or more RR biases after updating the RR bias and to adjust the voltage in the historical entry set.

[0138] In one different embodiment of the invention, a memory system (such as...) is provided. Figure 3 The example (shown) includes: a memory; and a controller, coupled to the memory and configured to read data from the memory. The controller is configured to: use a counter for each block to track the corresponding retention time since each block was read when there is no ongoing host read. (For distinction and not limitation, this example is referred to below as the non-host read example.) The controller is configured to: a) identify reclaimable blocks exceeding a threshold when any retention time is longer than a threshold, and reclaim the reclaimable block by adjusting the previous historical read set used to read the reclaimable block; b) test the reclaimable block with one or more read retry RR biases from the historical read set and perform checksum calculations to estimate the failure bit count; c) when the failure bit count is higher than the threshold, remove the worst entry from the previous historical read set and introduce a new historical entry into the historical entry set; and d) update the RR bias for subsequent read operations based on the new historical entry and the excluded worst entry.

[0139] In this non-host read embodiment of the memory system, the controller is configured to determine the previous history read set by the read bias of each die, each block, or each WL group.

[0140] In this non-host read embodiment, the controller is configured to randomly select the RR bias from the previous historical read set for reading the memory in subsequent read operations.

[0141] In this non-host read embodiment, the controller is configured to select RR biases from the historical read set for reading the memory in subsequent read operations, such that each RR bias has an equal chance of being used.

[0142] In this non-host read embodiment, the controller is configured to determine new historical entries based on the difference gradient between voltage thresholds used to read historical entries in memory that have the lowest failure bit count (FBC).

[0143] In this non-host read embodiment, the memory includes a three-level cell (TLC), and the voltage threshold is a voltage associated with reading one or more of the most significant bit page, the center significant bit page, and the least significant bit page.

[0144] In this non-host read embodiment, the voltage thresholds are the voltages V2 and V6 used to read the least significant bit page.

[0145] In this non-host read embodiment, the controller is configured to identify new history entries as ( ), where dFBC / dV2 and dFBC / dV6 are the numerical gradients of the failure bit count (FBC) at voltage thresholds V2 and V6, and delta is a constant that defines the gradient step size.

[0146] In this non-host read embodiment, the controller is configured to calculate a numerical gradient based on the difference in the failure bit counts of data read at various voltage offsets from voltage thresholds V2 and V6.

[0147] In this non-host read embodiment, the controller is configured to perform a test operation using one or more RR biases after updating the RR bias and adjust the voltage in the historical entry set.

[0148] In another embodiment of the invention, a memory system (such as...) is provided. Figure 3 As shown, the embodiment includes: a memory; and a controller coupled to the memory and configured to read data from the memory. (For distinction and not limitation, this embodiment is hereinafter referred to as the history adaptive read embodiment). The controller is configured to determine a read retry (RR) bias based on an initial history read set used for reading the memory, determine whether the failure bit count when reading a memory block is higher than a threshold, remove the worst entry from the initial history read set, introduce new history entries into the history entry set to generate an adaptive history read set, and update the RR bias for subsequent read operations based on the adaptive history read set.

[0149] In this history-adaptive read embodiment of the memory system, the controller is configured to determine the initial history read set by recording the read bias for each die, each block, or each WL group.

[0150] In this history-adaptive read embodiment, the controller is configured to randomly select the RR bias from the initial history read set to read the memory in subsequent read operations.

[0151] In this history-adaptive read embodiment, the controller is configured to select RR biases from the history read set for reading the memory in subsequent read operations, such that each RR bias has an equal chance of being used.

[0152] In this history adaptive read embodiment, the controller is configured to determine new history entries based on the difference gradient between voltage thresholds used to read history entries in memory that have the lowest failure bit count (FBC).

[0153] In this history adaptive read embodiment, the memory includes a three-level cell (TLC), and the voltage threshold is a voltage associated with reading one or more of the most significant bit page, the center significant bit page, and the least significant bit page.

[0154] In this history adaptive read embodiment, the voltage thresholds are the voltages V2 and V6 used to read the least significant bit page.

[0155] In this history adaptive reading embodiment, the controller is configured to identify new history entries as ( ), where dFBC / dV2 and dFBC / dV6 are the numerical gradients of the failure bit count (FBC) at voltage thresholds V2 and V6, and delta is a constant that defines the gradient step size.

[0156] In this history adaptive read embodiment, the controller is configured to calculate a numerical gradient based on the difference in the failure bit counts of the data read at various voltage offsets from voltage thresholds V2 and V6.

[0157] In this history adaptive read embodiment, the controller is configured to perform a test operation using one or more RR biases after updating the RR bias and adjust the voltage in the history entry set.

[0158] Although the embodiments described above have been given in detail for clarity of understanding, the invention is not limited to the details provided. Many alternative methods of carrying out the invention are possible. The disclosed embodiments are illustrative and not restrictive. The invention is intended to cover all modifications and alternatives to the disclosed embodiments. Furthermore, the disclosed embodiments can be combined to form additional embodiments.

[0159] In fact, the implementation of the subject matter and functional operations described in this patent application can be implemented in various systems, digital electronic circuits, computer software, firmware, or hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of these. Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more computer program instruction modules encoded on a tangible and non-transient computer-readable medium for execution by or control of the operation of a data processing apparatus. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of substances affecting machine-readable propagation signals, or one or more of these. The terms "data processing unit" or "data processing apparatus" include all means, devices, and machines for processing data, such as a programmable processor, a computer, or a plurality of processors or computers. In addition to hardware, the apparatus may also include code that creates an execution environment for the computer program in question, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

[0160] Computer programs (also known as programs, software, software applications, scripts, or code) can be written in any programming language, including compiled or interpreted languages, and can be deployed in any form, including as standalone programs or as modules, components, subroutines, or other units suited to a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored as part of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), or as a single file dedicated to the program in question, or as multiple coordinating files (e.g., a file storing one or more modules, subroutines, or code sections). Computer programs can be deployed to execute on a single computer, located at a single site, or distributed across multiple sites interconnected by a communication network.

[0161] The processes and logic flows described in this specification can be executed by one or more programmable processors, which execute one or more computer programs to perform functions by manipulating input data and generating outputs. These processes and logic flows can also be executed by dedicated logic circuits, and the device can be implemented as dedicated logic circuits, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits).

[0162] For example, processors suitable for executing computer programs include general-purpose and special-purpose microprocessors, as well as any one or more processors in any type of digital computer. Typically, the processor receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include, or be operatively coupled to, receiving data from or transferring data to one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data, or both. However, a computer does not need to have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices. The processor and memory may be supplemented or integrated within dedicated logic circuitry.

[0163] While this patent application contains numerous details, these details should not be construed as limiting any invention or the scope of any possible claims, but rather as descriptions of features that may be characteristic of particular embodiments of a particular invention. Certain features described in this patent application within the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described within the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although the foregoing features may be described as functioning in certain combinations, in some cases one or more features in the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0164] Similarly, although the operations are depicted in a specific order in the figures, this should not be construed as requiring these operations to be performed in the specific order or sequence shown, or requiring all of the operations shown to achieve the desired result. Furthermore, the separation of various system components in the embodiments described in this patent application should not be construed as requiring such separation in all embodiments.

[0165] Only a few implementations and examples are described, and other implementations, enhancements and variations may be made based on what is described and shown in this patent application.

Claims

1. A method for reading data from a memory, comprising: A read operation is performed on the memory, and the historical entry set of the voltage used to read the memory is recorded as the read retry bias, i.e., RR bias. If a test operation is performed without using any of the RR biases before a subsequent read operation of the memory, an RR bias for the subsequent read operation is selected from the set of historical entries. In the subsequent read operation, the memory is read using one or more of the RR biases in the history entry set; When the failure bit count of the subsequent read operation exceeds a threshold, the worst entry is removed from the history entry set, and a new history entry is introduced into the history entry set; and The RR bias is updated based on the new historical entry.

2. The method according to claim 1, further comprising: Record the history read set for each die, each block, or each word line group.

3. The method according to claim 1, further comprising: The RR bias is randomly selected from the historical read set to read the memory in the subsequent read operation.

4. The method according to claim 1, further comprising: The RR bias is selected from the historical read set for reading the memory in the subsequent read operation, such that each RR bias has an equal chance of being used.

5. The method of claim 1, further comprising: The new historical entry is determined based on the difference gradient between the voltage thresholds used to read the page in the memory that has the lowest failure bit count, i.e., the lowest FBC.

6. The method according to claim 5, wherein, The memory comprises a three-level cell (TLC), and the voltage threshold is a voltage associated with reading one or more of the most significant bit page, the center significant bit page, and the least significant bit page.

7. The method according to claim 6, wherein, The voltage thresholds are the voltages V2 and V6 used to read the least significant bit page.

8. The method of claim 7, further comprising: The new historical entry is identified as ( ), where dFBC / dV2 and dFBC / dV6 are the failure bit counts at the voltage thresholds V2 and V6, i.e., the numerical gradients of FBC, and delta is a constant that defines the gradient step size.

9. The method according to claim 8, wherein, The numerical gradient is calculated based on the difference in the failure bit counts of the data read at each voltage offset from the voltage thresholds V2 and V6.

10. The method of claim 5, further comprising: After updating the RR bias, the test operation is performed using one or more of the RR biases to adjust the voltage in the set of historical entries.

11. A memory system, comprising: Memory; A controller is connected to and reads data from the memory, wherein the controller: A read operation is performed on the memory, and the historical entry set of the voltage used to read the memory is recorded as the read retry bias, i.e., RR bias. Without using any of the RR biases to perform a test operation before subsequent read operations of the memory, the RR bias for the subsequent read operation is selected from the set of historical entries; In the subsequent read operation, the memory is read using one or more of the RR biases in the history entry set; When the failure bit count of the subsequent read operation exceeds a threshold, the worst entry is removed from the history entry set, and a new history entry is introduced into the history entry set; and The RR bias is updated based on the new historical entry.

12. The memory system according to claim 11, wherein, The controller records the historical read set for each die, each block, or each word line group.

13. The memory system according to claim 11, wherein, The controller randomly selects the RR bias from the historical read set to read the memory in the subsequent read operation.

14. The memory system according to claim 11, wherein, The controller selects the RR bias from the historical read set for reading the memory in the subsequent read operation, such that each RR bias has an equal chance of being used.

15. The memory system according to claim 11, wherein, The controller determines the new historical entry based on the difference gradient between voltage thresholds used to read the page in the memory that has the lowest failure bit count, i.e., the lowest FBC.

16. The memory system according to claim 15, wherein, The memory comprises a three-level cell (TLC), and the voltage threshold is a voltage associated with reading one or more of the most significant bit page, the center significant bit page, and the least significant bit page.

17. The memory system according to claim 16, wherein, The voltage thresholds are the voltages V2 and V6 used to read the least significant bit page.

18. The memory system according to claim 17, wherein, The new historical entry was identified as ( ), where dFBC / dV2 and dFBC / dV6 are the failure bit counts at the voltage thresholds V2 and V6, i.e., the numerical gradients of FBC, and delta is a constant that defines the gradient step size.

19. The memory system according to claim 18, wherein, The controller calculates the numerical gradient based on the difference in the failure bit counts of the data read at each voltage offset from the voltage thresholds V2 and V6.

20. The memory system of claim 19, wherein, After updating the RR bias, the controller performs the test operation using one or more of the RR biases to adjust the voltage in the historical entry set.

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