Interrupt service execution method and microcontroller unit
By establishing an interrupt vector table and allocating registers in the microcontroller unit, multiple interrupt service requests are executed synchronously, solving the problems of insufficient interrupt service speed and inconsistent latency in the microcontroller unit, and achieving faster and more consistent interrupt service processing.
Patent Information
- Application Number
- CN202411669518.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-16
- Filing Date
- 2024-11-21
- Publication Date
- 2026-03-03
AI Technical Summary
Existing microcontroller units suffer from insufficient speed and inconsistent latency when processing multiple interrupt service requests from different sources.
By establishing an interrupt vector table and allocation register, the interrupt vector of each interrupt group is recorded, and the interrupt vector of the interrupt service request is written into the jump address temporary storage area of the allocation register within a specific time. The jump instruction is executed to jump to the corresponding interrupt service code address, thereby realizing the synchronous execution of multiple interrupt service requests.
This achieves consistency in latency for multiple interrupt service requests, improves the interrupt service processing speed of the microcontroller unit, and avoids latency differences caused by different firmware code writing styles.
Smart Images
Figure CN121597355A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a technique for a microcontroller unit to perform interrupt services for multiple interrupt service requests issued by multiple interrupt service request sources, and more particularly to an interrupt service execution method and microcontroller unit that enables multiple interrupt service sources in the same interrupt group to have the same latency time when interrupted by the microcontroller unit. Background Technology
[0002] With the advent of the artificial intelligence era, the requirements for response speed are no less stringent than those for execution speed. Coupled with input from multiple peripheral sensors, the demands on the diverse interrupt response speeds of microcontroller units are even more stringent. Microcontroller units have multiple pins, and the hardware device electrically connected to each pin can be considered a source of interrupt service requests. Existing microcontroller units may have more than 100 pins, but the number of interrupt service requests a microcontroller unit can receive at one time is limited, for example, 64. Therefore, current practices group multiple interrupt service request sources, that is, divide multiple interrupt service request sources into multiple interrupt groups.
[0003] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a microcontroller unit performing interrupt services in the prior art. Since the number of interrupt service requests that a microcontroller unit can receive at one time is limited, multiple interrupt service request sources are divided into multiple interrupt groups. The interrupt service request sources of the fourth interrupt group are the hardware devices electrically connected to the eight general purpose input / output pins GPIO_0000 to GPIO_0007. The interrupt service requests issued by the interrupt service request sources of the eight general purpose input / output pins GPIO_0000 to GPIO_0007 are processed by a logic module 101 (which may be implemented in hardware or software) through a logical OR operation.
[0004] The microcontroller unit establishes an interrupt vector table 100, which records multiple group interrupt vectors IRQ1 to IRQ5. Each group interrupt vector IRQ1 to IRQ5 corresponds to an interrupt group from multiple interrupt service request sources. For example, group interrupt vector IRQ4 corresponds to an interrupt group composed of interrupt service request sources from eight general-purpose input / output pins GPIO_0000 to GPIO_0007. Each group interrupt vector IRQ1 to IRQ5 is actually a code storage space address value, so each group interrupt vector IRQ1 to IRQ5 points to an address in the microcontroller unit's code storage space 102. For example, if the code storage space address of group interrupt vector IRQ4 is 0x00120, then as long as one of the interrupt service request sources from the eight general-purpose input / output pins GPIO_0000 to GPIO_0007 issues an interrupt service request, the microcontroller unit will execute the group interrupt service code IRQ4_FCN at address 0x00120 in the code storage space.
[0005] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the signal waveforms of a microcontroller unit executing an interrupt service in the prior art. Taking a processor with a Cortex M3 or M4 as an example, after the microcontroller unit receives an interrupt service request, the corresponding signal INTISR[2] changes from logic low to logic high. During the first 12 clock signals CLK of the microcontroller unit, the group interrupt service code corresponding to the interrupt service will not be executed. The group interrupt service code is executed at the 13th clock signal CLK, where the signal CURRPRI[0:7] corresponding to the execution of the interrupt service is converted to a specific value C at the 13th clock signal CLK. After receiving the interrupt service request, at the 5th clock signal CLK, the microcontroller unit prepares to read the interrupt group vector address value of the interrupt group vector of the interrupt group of the interrupt service request (the signal HRDATA[0:31] is converted to a specific value A), and at the 7th clock signal CLK, the microcontroller unit prepares to read the group interrupt service code of the code storage space address pointed to by the interrupt group vector (the signal HRDATA[0:31] is converted to a specific value B). In other words, before the group interrupt service code is executed, multiple preparatory actions consume the frequency time of multiple clock signals CLK.
[0006] Please refer to Figure 1 , Figure 3 , Figure 3This is a timing diagram illustrating the execution of interrupt services by a prior art microcontroller unit. The group interrupt service code is firmware code. Typically, in prior art, multiple interrupt service request sources are sequentially detected to determine which one issued the interrupt service request, and then the interrupt service code containing the address value of the source of the issued interrupt service request is executed. For example... Figure 1 In this context, if the group interrupt service code sequentially checks the interrupt service request sources of the eight general-purpose input / output pins GPIO_0000 to GPIO_0007, the delay time (compared to the time when the group interrupt service code is executed, i.e., when the signal ISR_EX transitions to logic high) for each interrupt service request source will be different. Figure 3 The execution delay times of the interrupt service requests originating from general-purpose input / output pins GPIO_0000 to GPIO_0007, specifically the interrupt service requests originating from GPIO_0000 to GPIO_0007, are all different. The execution delay time of the interrupt service request originating from the general-purpose input / output pin GPIO_0007, specifically GPIO_0007_ISR, is even longer, reaching a time value T07. With current technology, the speed at which the microcontroller unit processes interrupt services is insufficient and difficult to meet current requirements. Summary of the Invention
[0007] As can be understood from the above description, the purpose of this invention is to solve the technical problem that the speed of microcontroller units in the prior art is insufficient in processing interrupt services, and it is expected that the delay time for the execution of interrupt services from multiple interrupt service request sources can be the same, and that there will be no different delay times due to different firmware code writing.
[0008] Based on one objective of the present invention, an embodiment of the present invention provides an interrupt service execution method, which is executed in a microcontroller unit and includes the following steps: establishing an interrupt vector table, wherein the interrupt vector table records multiple group interrupt vectors, each group interrupt vector corresponds to multiple interrupt groups from which interrupt service requests originate, and each group interrupt vector is an allocation register address value of an allocation register, wherein each allocation register has a jump instruction temporary storage area and a jump address temporary storage area for storing jump instruction code; establishing multiple allocation vector tables, wherein each allocation vector table records multiple interrupt vectors from multiple interrupt service request sources of a corresponding interrupt group; receiving at least one interrupt service request issued by at least one of the multiple interrupt service request sources of one of the multiple interrupt groups; within a specific time period, causing the corresponding allocation vector table to write the interrupt vector from the interrupt service request source of the interrupt group that issued the interrupt service request into the jump address temporary storage area of the corresponding allocation register; after the specific time period, executing the jump instruction of the allocation register pointed to by the interrupt group vector of the interrupt group that issued the interrupt service request to jump to the jump address pointed to by the interrupt vector stored in the jump address temporary storage area of the allocation register, and executing the interrupt service code at the jump address.
[0009] Based on one of the objectives of this invention, an embodiment of this invention provides a microcontroller unit, including multiple hardware circuits electrically connected to each other, wherein the multiple hardware circuits execute firmware code to perform the above-described interrupt service execution method.
[0010] As described above, the interrupt service execution method and microcontroller unit provided by this invention can ensure that the delay time for the execution of interrupt services from multiple interrupt service request sources is the same, and there will be no different delay time due to different firmware code writing. In addition, it can also improve the speed of microcontroller unit in processing interrupt services. Attached Figure Description
[0011] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:
[0012] Figure 1 This is a schematic diagram of a microcontroller unit performing interrupt services in the prior art;
[0013] Figure 2 This is a schematic diagram of the signal waveforms of a microcontroller unit performing an interrupt service in the prior art;
[0014] Figure 3 This is a timing diagram of a microcontroller unit executing an interrupt service in the prior art;
[0015] Figure 4This is a timing diagram illustrating the interrupt service execution method and the microcontroller unit's execution of interrupt services according to an embodiment of the present invention;
[0016] Figure 5 This is a schematic diagram of the interrupt service execution method and the microcontroller unit executing interrupt services according to an embodiment of the present invention;
[0017] Figure 6 This is a schematic diagram of an interrupt service execution method and a microcontroller unit executing an interrupt service according to another embodiment of the present invention;
[0018] Figure 7 This is a flowchart illustrating the interrupt service execution method in an embodiment of the present invention. Detailed Implementation
[0019] The primary objective of this invention is to ensure that the delay time when interrupt services from multiple interrupt service request sources are executed by the microcontroller unit is identical. This avoids situations where different firmware code implementations result in varying delay times, thereby further improving the speed at which the microcontroller unit processes interrupt services. The following detailed description, in conjunction with the accompanying drawings, illustrates possible embodiments of this invention. However, it should be noted that these details are not intended to limit the scope of the claims made in this invention, but are merely provided to facilitate understanding by those skilled in the art.
[0020] First, please refer to Figure 4 , Figure 4 This is a timing diagram illustrating the interrupt service execution method and the execution of interrupt services by the microcontroller unit according to an embodiment of the present invention. Figure 4 The present invention aims to make the delay time (based on the time when the group interrupt service code is executed, i.e. when the signal ISR_EX transitions to logic high level) of the interrupt service request sources of multiple general-purpose input / output pins GPIO_0000 to GPIO_0007 be the same, for example, all being a time value T.
[0021] In order to achieve Figure 4 The purpose of this invention is actually to [achieve something] within a specific time period, for example... Figure 2The frequency of the 12th clock signal CLK in the allocation register writes the interrupt vector of the interrupt service request originating from the interrupt service request into the jump address buffer. The interrupt vector is the address of the interrupt service code originating from the interrupt service request in the code storage space. The jump instruction buffer of the allocation register stores the jump instruction, which is the machine code of the unconditional jump instruction. Therefore, as soon as the microcontroller unit reads the corresponding group interrupt vector, it executes the jump instruction in the allocation register pointed to by the group interrupt vector, and thus jumps to the jump address pointed to by the interrupt vector written to the jump address buffer. Then, it executes the interrupt service code at this jump address. Furthermore, the aforementioned specific time is a multiple of the frequency of the microcontroller unit's clock signal and depends on the type of microcontroller unit. When the microcontroller unit is a Cortex M0 processor, Cortex M0+ processor, Cortex M3 processor, or Cortex M4 processor, it takes 16, 15, 12, or 12 clock signals of preparation time before executing the group interrupt service code of the group interrupt vector. Therefore, the specific time can be 12 to 16 times the frequency of the microcontroller unit's clock signal, depending on the type of Cortex processor.
[0022] Please refer to Figure 5 and Figure 7 , Figure 5 This is a schematic diagram illustrating the interrupt service execution method and the microcontroller unit executing interrupt services according to an embodiment of the present invention. Figure 7 This is a flowchart illustrating the interrupt service execution method according to an embodiment of the present invention. In this invention, the microcontroller unit includes multiple hardware circuits electrically connected to each other. These hardware circuits execute firmware code to perform the interrupt service execution method. In this invention, the interrupt vector table 200 can be implemented using existing registers of the microcontroller unit, the logic module 201 can be implemented using hardware or software of the microcontroller unit, and each of the allocation register 202 and the allocation vector table 203 can be implemented using existing registers of the microcontroller unit, or additional registers can be added to the microcontroller unit; however, this invention is not limited thereto.
[0023] First, in step S01, the microcontroller unit establishes an interrupt vector table 200 based on the firmware code during the initial stage. The interrupt vector table 200 records multiple group interrupt vectors IRQ1 to IRQ5. Each group interrupt vector IRQ1 to IRQ5 corresponds to multiple interrupt groups from which interrupt service requests originate. For example, the interrupt service request source for the interrupt group IRQ4 is the interrupt service request source for the eight general purpose input / output pins GPIO_0000 to GPIO_0007. Each group interrupt vector IRQ1 to IRQ5 points to the allocation register address of the allocation register. For example, group interrupt vector IRQ4 points to the allocation register address of allocation register 202; that is, group interrupt vectors IRQ1 to IRQ5 are allocation register address values. Incidentally, each allocation register has a jump instruction temporary storage area (storing the machine code of the jump instruction) and a jump address temporary storage area (used to store the jump address value where the jump instruction will jump to). For example, the jump instruction temporary storage area and the jump address temporary storage area of allocation register 202 store the machine code OP of the jump instruction and the jump address value OFFSET_ADDRESS, respectively. Allocation register 202 can be a 32-bit register, and the jump address value can have 24 bits, so the jump instruction can perform an address jump of 16M. However, this invention is not limited by the bit count of allocation register 202 and the jump address value; the bit count of allocation register 202 and the jump address value can be designed according to actual needs.
[0024] In step S02, the microcontroller unit also establishes multiple allocation vector tables in the initial stage. Each allocation vector table records multiple interrupt vectors from multiple interrupt service request sources of the corresponding interrupt group, and the interrupt vector is the code storage address value of the interrupt service code of the corresponding interrupt service source in the code storage space of the microcontroller unit. For example, allocation vector table 203 corresponds to the interrupt group of interrupt vector IRQ4 and records the interrupt vectors GPIO_0000_VEC to GPIO_0007_VEC from the interrupt service request sources of the eight general-purpose input / output pins GPIO_0000 to GPIO_0007. The interrupt vectors GPIO_0000_VEC to GPIO_0007_VEC represent the code storage address value of the interrupt service code of the interrupt service request source of the eight general-purpose input / output pins GPIO_0000 to GPIO_0007 in the code storage space.
[0025] Next, in step S03, the microcontroller unit receives at least one interrupt service request from at least one of the multiple interrupt service request sources of one of the multiple interrupt groups. Then, in step S04, within a specific time period, the microcontroller unit causes the corresponding allocation vector table to write the interrupt vector of the interrupt service request source of the interrupt group that issued the interrupt service request into the jump address temporary storage area of the corresponding allocation register.
[0026] For example, if the interrupt service request sources of general-purpose input / output pins GPIO_0000 and GPIO_0007 issue service requests in sequence, it indicates that interrupt group vector IRQ4 will be executed. In step S04, if the allocation vector table 203 does not have the priority order rules for multiple interrupt service request sources in its corresponding interrupt group, the microcontroller unit will overwrite the interrupt vectors GPIO_0000_VEC and GPIO_0007_VEC of the allocation vector table 203 into the jump address temporary storage area of the allocation register 202 according to the time sequence. Therefore, the jump address temporary storage area of the allocation register 202 stores the interrupt vector GPIO_0007_VEC of the last interrupt service request source (the interrupt service request source of general-purpose input / output pin GPIO_0007). If the allocation vector table 203 has a priority order rule for multiple interrupt service request sources in its corresponding interrupt group, then according to the priority order rule (assuming that the interrupt service request source of the general-purpose input / output pin GPIO_0000 has the lowest priority), the microcontroller unit will overwrite the interrupt vectors GPIO_0000_VEC and GPIO_0007_VEC of the allocation vector table 203 into the jump address temporary storage area of the allocation register 202. Therefore, the jump address temporary storage area of the allocation register 202 stores the interrupt vector GPIO_0007_VEC of the interrupt service request source with the highest priority (the interrupt service request source of the general-purpose input / output pin GPIO_0007).
[0027] Next, after a specific time, in step S05, the microcontroller unit executes the jump instruction of the allocation register pointed to by the interrupt group vector of the interrupt group that issued the interrupt service request, to jump to the jump address pointed to by the interrupt vector stored in the jump address temporary storage area of the allocation register, and executes the interrupt service code of the jump address. In the example above, the jump address temporary storage area of allocation register 202 stores the interrupt vector GPIO_0007_VEC, which is the source of the interrupt service request from the general-purpose input / output pin GPIO_0007, and it is the jump address value OFFSET_ADDRESS. In step S05, the microcontroller unit executes the group interrupt vector IRQ4, which points to the allocation register address of allocation register 202. Therefore, the jump instruction of allocation register 202 is executed, and jumps to the jump address (i.e., jumps to the code storage space address where the interrupt service code of the general-purpose input / output pin GPIO_0007 is stored) to execute the interrupt service code of the source of the interrupt service request from the general-purpose input / output pin GPIO_0007.
[0028] Furthermore, in this invention, the multiple interrupt service request sources of the interrupt group in the interrupt vector table and the multiple interrupt service request sources in the allocation vector table can be adjusted by firmware code execution in flash memory or read-only memory through masking, so as to change at runtime. Please refer to... Figure 5 and Figure 6 , Figure 6 This is a schematic diagram of an interrupt service execution method and a microcontroller unit executing interrupt services according to another embodiment of the present invention, compared to... Figure 5 ,At Figure 6 In the interrupt group interrupt vector IRQ4, the sources of multiple interrupt service requests for the interrupt group have been changed to the sources of interrupt service requests for general purpose input / output pins GPIO_0000, integrated bus pins I2C, general purpose input / output pins GPIO_0002 to GPIO_0006, and timer pin TIMER_0. The corresponding allocation vector table has also been changed to record interrupt vectors GPIO_0000_VEC, I2C_VEC, GPIO_0002_VEC to GPIO_0006_VEC, and TIMER_0_VEC.
[0029] In summary, the interrupt service execution method and microcontroller unit provided by this invention can pre-fill the address value of the stored interrupt service code into the jump address temporary storage area of the allocation register as the jump address value before executing the interrupt service code from the source of the interrupt service request that issued the interrupt service request. The jump instruction and jump address value stored in the allocation register can be read by the microcontroller unit, allowing the microcontroller unit to directly jump to the jump address and execute the interrupt service code at the jump address. In this way, the execution delay time of interrupt services from multiple interrupt service request sources can be the same, without different delay times due to different firmware code writing, and the speed of interrupt service processing by the microcontroller unit can also be improved. In addition, the multiple interrupt vectors of multiple interrupt service request sources in the interrupt vector table interrupt group and multiple interrupt service request sources in the allocation vector table can be adjusted by masking the firmware code execution in flash memory or read-only memory, so as to change during execution.
[0030] This invention is disclosed herein only by preferred embodiments. However, it should be understood by any person skilled in the art that the above embodiments are for illustrative purposes only and are not intended to limit the scope of the patent rights claimed by this invention. Any variations or substitutions that are equivalent or equivalent to the above embodiments should be interpreted as being covered within the spirit or scope of this invention. Therefore, the scope of protection of this invention should be based on the claims.
Claims
1. An interrupt service execution method, executed in a microcontroller unit, characterized in that, The interrupt service execution method includes the following steps: An interrupt vector table is established, wherein the interrupt vector table records multiple group interrupt vectors, each group interrupt vector corresponds to multiple interrupt groups from which interrupt service requests originate, and each group interrupt vector is the allocation register address value of the allocation register, wherein each allocation register has a jump instruction temporary storage area and a jump address temporary storage area for storing jump instruction codes. Multiple allocation vector tables are established, wherein each allocation vector table records multiple interrupt vectors from the sources of the multiple interrupt service requests of the corresponding interrupt group; Receive at least one interrupt service request from at least one of the multiple interrupt service request sources of the multiple interruption groups; Within a specific time period, the corresponding allocation vector table writes the interrupt vector from the interrupt service request source of the interrupt group that issued the interrupt service request into the jump address temporary storage area of the corresponding allocation register; After the specified time, a jump instruction is executed in the allocation register pointed to by the interrupt group vector of the interrupt group that issued the interrupt service request, to jump to the jump address pointed to by the interrupt vector stored in the jump address temporary storage area of the allocation register, and to execute the interrupt service code at the jump address.
2. The interrupt service execution method as described in claim 1, characterized in that, The specific time is a multiple of the frequency of the clock signal of the microcontroller unit.
3. The interrupt service execution method as described in claim 2, characterized in that, The microcontroller unit is a Cortex processor, and the specific time is 12 to 16 times the frequency of the clock signal of the microcontroller unit.
4. The interrupt service execution method as described in claim 1, characterized in that, The allocation register is a 32-bit register, the jump instruction temporary storage area is used to store the jump instruction, and the interrupt vector is the jump address value of the jump instruction, which has 24 bits.
5. The interrupt service execution method as described in claim 1, characterized in that, When the allocation vector table does not have a priority order rule for the multiple interrupt service request sources in the corresponding interrupt group, and within the specific time period, the multiple interrupt service request sources in the interrupt group issue multiple interrupt service requests, then in chronological order, the multiple interrupt vectors corresponding to the multiple interrupt service request sources that issued the multiple interrupt service requests are overwritten and written to the jump address temporary storage area of the corresponding allocation register, so that the jump address temporary storage area stores the interrupt vector corresponding to the last interrupt service request source that issued the interrupt service request.
6. The interrupt service execution method as described in claim 1, characterized in that, When the allocation vector table has a priority order rule for the multiple interrupt service request sources in the corresponding interrupt group, and within the specific time period, the multiple interrupt service request sources in the interrupt group issue multiple interrupt service requests, then according to the priority order rule, the interrupt vector corresponding to the interrupt service request source that issued the interrupt service request is overwritten and written to the jump address temporary storage area of the corresponding allocation register, so that the jump address temporary storage area stores the interrupt vector corresponding to the one with the highest priority among the multiple interrupt service request sources that issued the multiple interrupt service requests.
7. The interrupt service execution method as described in claim 1, characterized in that, The multiple interrupt service request sources of the interrupt group and the multiple interrupt vectors of the multiple interrupt service request sources in the allocation vector table corresponding to the interrupt group are adjusted by firmware code execution on the mask of flash memory or read-only memory.
8. A microcontroller unit comprising a plurality of hardware circuits electrically connected to each other, the plurality of hardware circuits executing firmware code to perform an interrupt service execution method, characterized in that, The interrupt service execution method includes: An interrupt vector table is established, wherein the interrupt vector table records multiple group interrupt vectors, each group interrupt vector corresponds to multiple interrupt groups from which interrupt service requests originate, and each group interrupt vector is the allocation register address value of the allocation register, wherein each allocation register has a jump instruction temporary storage area and a jump address temporary storage area for storing jump instruction codes. Multiple allocation vector tables are established, wherein each allocation vector table records multiple interrupt vectors from the sources of the multiple interrupt service requests of the corresponding interrupt group; Receive at least one interrupt service request from at least one of the multiple interrupt service request sources of the multiple interruption groups; Within a specific time period, the corresponding allocation vector table writes the interrupt vector from the interrupt service request source of the interrupt group that issued the interrupt service request into the jump address temporary storage area of the corresponding allocation register; After the specified time, a jump instruction is executed in the allocation register pointed to by the interrupt group vector of the interrupt group that issued the interrupt service request, to jump to the jump address pointed to by the interrupt vector stored in the jump address temporary storage area of the allocation register, and to execute the interrupt service code at the jump address.
9. The microcontroller unit as described in claim 8, characterized in that, When the allocation vector table does not have a priority order rule for the multiple interrupt service request sources in the corresponding interrupt group, and within the specific time period, the multiple interrupt service request sources in the interrupt group issue multiple interrupt service requests, then in chronological order, the multiple interrupt vectors corresponding to the multiple interrupt service request sources that issued the multiple interrupt service requests are overwritten and written to the jump address temporary storage area of the corresponding allocation register, so that the jump address temporary storage area stores the interrupt vector corresponding to the last interrupt service request source that issued the interrupt service request.
10. The microcontroller unit as claimed in claim 8, characterized in that, When the allocation vector table has a priority order rule for the multiple interrupt service request sources in the corresponding interrupt group, and within the specific time period, the multiple interrupt service request sources in the interrupt group issue multiple interrupt service requests, then according to the priority order rule, the interrupt vector corresponding to the interrupt service request source that issued the interrupt service request is overwritten and written to the jump address temporary storage area of the corresponding allocation register, so that the jump address temporary storage area stores the interrupt vector corresponding to the highest priority among the multiple interrupt service request sources that issued the multiple interrupt service requests.