Multichannel multiplexing device, chip and electronic equipment
By using a multi-path multiplexing device to reuse normal UCIIE interface routing access tasks, memory access obstacles caused by UCIIE interface failures can be resolved, chip area and power consumption can be reduced, data transmission efficiency can be improved, and packaging costs can be reduced.
Patent Information
- Application Number
- CN202511756303.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-03-03
AI Technical Summary
Lane failures in the uCie interface can cause memory access problems. Existing technologies cannot effectively solve this problem or require increased chip area and power consumption. Furthermore, lane number downgrading or redundancy repair does not support access problems.
By using a multi-path multiplexing device and cooperating with the first and second control circuits, normal ucie interface routing access tasks can be multiplexed, avoiding the introduction of backup lane design and reducing chip area and power consumption.
It effectively solves memory access problems caused by UCIIE interface failures, reduces chip area and power consumption, improves data transmission efficiency, and reduces chip packaging costs.
Smart Images
Figure CN121597484A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic technology, specifically relating to a multi-channel multiplexing device, chip, and electronic device. Background Technology
[0002] The chip connects to external IO dies (input / output dies) used as storage media via a UCIE (Universal Chiplet Interconnect Express) interface. Each IO Die corresponds to 16 UCIE interfaces, and each UCIE interface is a high-speed channel with x16 lanes (16 differential transmission units). If any lane in the UCIE interface fails, and the UCIE interface has no redundancy repair mechanism and does not support lane number downgrading (such as downgrading from x16 to x8 or x4), or even if it supports lane number downgrading but the multiple failed lanes are scattered, then the UCIE interface will be completely unusable.
[0003] Furthermore, lane failures not only render the corresponding UCIIE interface (the failed UCIIE interface) unusable, but in systems with multiple masters interleaved access to the IO Die, they can also cause other access obstacles. Since the 16 UCIIE interfaces need to support fine-grained interleaving access modes, if the interleaving granularity is too fine, all masters may frequently use the failed UCIIE interface, resulting in all masters being unable to access the IO Die. If the interleaving granularity is too coarse, only some masters that rely on the failed UCIIE interface will be affected, but this will still prevent these masters from accessing the storage resources in the IO Die normally. Summary of the Invention
[0004] Therefore, the purpose of this application is to provide a multi-path multiplexing device, chip, and electronic device to improve the memory access problem caused by the inability to use the corresponding ucie interface due to lane failure.
[0005] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a multi-path multiplexing device for connecting n master devices and n UCIE interfaces, where n is an integer greater than or equal to 2. The multi-path multiplexing device includes a transmitting module, wherein the transmitting module includes: a first control circuit, n first circuits, and n second circuits; the n first circuits are used to connect the n master devices, and one first circuit is connected to one master device; each first circuit is configured to send an access task from the master device to the first control circuit or the second circuit; the n second circuits are used to connect the n UCIE interfaces, and one second circuit is connected to one UCIE interface; the second circuits are configured to output the access task from the first circuit or the first control circuit; the first control circuit is connected to the n first circuits and the n second circuits respectively; the first control circuit is configured to, when some UCIE interfaces among the n UCIE interfaces are faulty, reroute the received access task originally transmitted through the faulty UCIE interface to the second circuit corresponding to the normal UCIE interface by reusing the normal UCIE interface.
[0006] In the above embodiments, the multipath multiplexing device with the above structure connects multiple UCIIE interfaces. When some UCIIE interfaces fail due to lane failure, the first circuit, the first control circuit, and the second circuit cooperate to reroute the access tasks originally transmitted through the failed UCIIE interface to the normal UCIIE interface by multiplexing (partially multiplexing) the normal UCIIE interface. This completes the access to the IODE connected to the UCIIE interface, thereby improving the memory access obstacle caused by the inability to use the corresponding UCIIE interface due to lane failure when lane redundancy repair is not supported. At the same time, since multiple UCIIE interfaces share a single multipath multiplexing device, and there is no need to introduce a spare lane design in the UCIIE interface, there is no need to set up a switch switching circuit in the UCIIE interface (for the x16+1 lane redundancy scheme, 18 switch switching circuits and corresponding control logic are usually required). Compared with the scheme that introduces a spare lane design in the UCIIE interface, this application can also reduce the chip area and power consumption, as well as the chip packaging cost increased by introducing a spare lane design.
[0007] In one possible implementation of the first aspect embodiment, when some of the n UCIE interfaces are faulty, the target first circuit among the n first circuits is configured to send the received access task to the first control circuit, wherein the target first circuit is the first circuit corresponding to the faulty UCIE interface and the first circuit corresponding to the reused UCIE interface; the first control circuit is specifically configured to add the identity identifier of the corresponding master device to the received access task and send the access task with the added identity identifier to the second circuit corresponding to the reused UCIE interface.
[0008] In the above embodiments, by sending access tasks from the target first circuit (the first circuit corresponding to the faulty UCIE interface and the first circuit corresponding to the reused UCIE interface) to the first control circuit, the first control circuit reroutes the access tasks originally transmitted through the faulty UCIE interface to the normal UCIE interface by reusing the normal UCIE interface, thereby completing the transmission of the access tasks. At the same time, in order to make it easier to know which master device the access task of the reused UCIE interface comes from, the corresponding master device's identity identifier is added to the received access task, so that the first control circuit can identify the master device corresponding to the identity identifier after receiving the task response and accurately return the task response to the master device corresponding to the identity identifier.
[0009] In one possible implementation of the first aspect embodiment, when all n ucie interfaces are normal, each of the first circuits is configured to send the received access task to the second circuit.
[0010] In the above embodiment, when all n ucie interfaces are normal, the first circuit directly sends the received access task to the second circuit (commonly known as data pass-through), without the need for control by the first control circuit. This reduces the impact of bandwidth reduction (i.e. performance loss) caused by the first control circuit reusing the ucie interface, and effectively improves the efficiency of data transmission.
[0011] In one possible implementation of the first aspect embodiment, the second circuit is a switching circuit; the first control circuit includes: a first arbitrator, which is connected to the n first circuits and the n second circuits respectively; the first arbitrator is configured to add the identity identifier of the corresponding master device to the received access task and send the access task with the added identity identifier to each second circuit; the target switching circuit among the n second circuits is configured to select the access task output from the first arbitrator, and the target switching circuit is the second circuit corresponding to the multiplexed ucie interface.
[0012] In the above embodiments, when the first arbitrator sends an access task with added identity identifier to each second circuit, the target switching circuit within the second circuit can be configured to select the access task output from the first arbitrator, while the remaining second circuits select the access task output from the first circuit. This avoids sending duplicate access tasks while achieving normal multiplexing (partial multiplexing) of the ucie interface. Simultaneously, in addition to adding the corresponding master device's identity identifier to the received access tasks, the first arbitrator also arbitrates access tasks from different first circuits. Arbitration can be based on a PQ (Priority Queuing) + RR (Round-Robin) arbitration strategy. For example, PQ arbitration is used for access tasks with different priorities, and RR arbitration is used for access tasks with the same priority. Furthermore, the arbitrator can support a starvation prevention mechanism. For instance, during multiplexing, if a master device transmits high-priority tasks for an extended period, the arbitrator can dynamically adjust low-priority tasks to prevent low-priority tasks on other master devices from being starved.
[0013] In one possible implementation of the first aspect embodiment, the first control circuit includes: a first arbitrator and a first selection circuit; the first arbitrator is connected to the n first circuits and the first selection circuit respectively, and the first selection circuit is connected to the n second circuits; the first arbitrator is configured to add the identity identifier of the corresponding master device to the received access task and send the access task with the added identity identifier to the first selection circuit; the first selection circuit is configured to send the received access task to the second circuit corresponding to a normal ucie interface.
[0014] In the above embodiments, a first selection circuit can be added between the first arbitrator and the n second circuits. The first selection circuit selects which normal ucie interface-corresponding second circuit to send the received access task to. This has the characteristics of high flexibility. At the same time, there is no need to add selection control logic at each second circuit, which simplifies the selection control logic process.
[0015] In one possible implementation of the first aspect embodiment, the multiplexing device further includes a receiving module; wherein the receiving module includes: a second control circuit, n third circuits, and n fourth circuits; the n third circuits are used to connect the n UCIE interfaces, and one third circuit is connected to one UCIE interface; each third circuit is configured to send a task response from the UCIE interface to the second control circuit or the fourth circuit; the n fourth circuits are used to connect the n master devices, and one fourth circuit is connected to one master device; the fourth circuits are configured to output a task response from the third circuit or the second control circuit; the second control circuit is connected to the n third circuits and the n fourth circuits respectively; the second control circuit is configured to, when some UCIE interfaces among the n UCIE interfaces are faulty, reroute the task response of the access task originally from the target master device corresponding to the faulty UCIE interface to the fourth circuit corresponding to the target master device by reusing the normal UCIE interface.
[0016] In the above embodiments, the receiving module with the above structure, when some UCIE interfaces fail due to lane failure, will, through the cooperation of the third circuit, the second control circuit and the fourth circuit, reroute the task response of the access task originally from the target master device corresponding to the faulty UCIE interface to the fourth circuit corresponding to the target master device by reusing the normal UCIE interface, so as to ensure that the task response can be correctly returned to the source master device.
[0017] In one possible implementation of the first aspect embodiment, when some of the n UCIE interfaces are faulty, the target third circuit among the n third circuits is configured to send a task response from the multiplexed UCIE interface to the second control circuit, wherein the target third circuit is the third circuit corresponding to the multiplexed UCIE interface; the second control circuit is specifically configured to send the task response to the fourth circuit corresponding to the master device to which the identity carries in the received task response.
[0018] In the above embodiment, it is only necessary to configure the target third circuit among the n third circuits to send the task response from the multiplexed ucie interface to the second control circuit. The second control circuit then sends the task response to the fourth circuit corresponding to the master device to which the identity is carried in the task response, so as to ensure that the task response can be correctly returned to the source master device.
[0019] In one possible implementation of the first aspect embodiment, when all n ucie interfaces are normal, each of the third circuits is configured to send the received task response to the corresponding fourth circuit.
[0020] In the above embodiment, when all n ucie interfaces are normal, the third circuit directly sends the received task response to the fourth circuit (commonly known as data pass-through), without the need for control by the second control circuit, which effectively improves the efficiency of data transmission.
[0021] In one possible implementation of the first aspect embodiment, the second control circuit includes: a second arbitrator and a second selection circuit; the second arbitrator is connected to the n fourth circuits and the second selection circuit respectively, and the second selection circuit is connected to the n third circuits; the second selection circuit is configured to select and output the task response received by the third circuit corresponding to the multiplexed ucie interface; the second arbitrator is configured to send the task response to the fourth circuit corresponding to the master device to which the identity carries in the received task response.
[0022] In the above embodiments, the second control circuit with the above structure allows the transmitting module and the receiving module to share a single arbiter, thereby reducing chip area and cost. By adding a second selection circuit between the second arbiter and the n third circuits, the second selection circuit can select the task response of the third circuit corresponding to the multiplexed ucie interface to send to the second control circuit, which has the characteristics of high flexibility. At the same time, there is no need to add selection control logic at each fourth circuit, which simplifies the selection control logic process.
[0023] Secondly, embodiments of this application also provide a multi-path multiplexing device for connecting n master devices and n UCIE interfaces, where n is an integer greater than or equal to 2. The multi-path multiplexing device includes a receiving module; wherein the receiving module includes: a second control circuit, n third circuits, and n fourth circuits; the n third circuits are used to connect the n UCIE interfaces, and one third circuit is connected to one UCIE interface; each third circuit is configured to send a task response from the UCIE interface to the second control circuit or the fourth circuit; the n fourth circuits are used to connect the n master devices, and one fourth circuit is connected to one master device; the fourth circuits are configured to output a task response from the third circuit or the second control circuit; the second control circuit is connected to the n third circuits and the n fourth circuits respectively; the second control circuit is configured to, when some UCIE interfaces among the n UCIE interfaces are faulty, reroute the task response of the access task originally from the target master device corresponding to the faulty UCIE interface to the fourth circuit corresponding to the target master device by reusing the normal UCIE interface.
[0024] In the above embodiments, the receiving module with the above structure, when some UCIE interfaces fail due to lane failure, will, through the cooperation of the third circuit, the second control circuit and the fourth circuit, reroute the task response of the access task originally from the target master device corresponding to the faulty UCIE interface to the fourth circuit corresponding to the target master device by reusing the normal UCIE interface, so as to ensure that the task response can be correctly returned to the source master device.
[0025] Thirdly, embodiments of this application also provide a chip, including: n master devices, n uCIE interfaces, and a multiplexing device as provided in any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment, or a multiplexing device as provided in the second aspect embodiment, where n is an integer greater than or equal to 2; the multiplexing device is connected to the n master devices and the n uCIE interfaces respectively.
[0026] In the above embodiments, by adding a multi-path multiplexing device between n master devices and n uCIE interfaces, when some uCIE interfaces fail due to lane failure, the multi-path multiplexing device can reroute the access tasks originally transmitted through the failed uCIE interface to the normal uCIE interface by multiplexing (or partially multiplexing) the normal uCIE interface, thereby completing the access to the IO Die connected to the uCIE interface. This can improve the memory access obstacle caused by the inability to use the corresponding uCIE interface due to lane failure when lane redundancy repair is not supported.
[0027] In one possible implementation of the third aspect embodiment, the chip includes 4 groups of I / O interfaces, each group of I / O interfaces includes 16 UCIIE interfaces, and when n=4, every 4 UCIIE interfaces are connected to one of the multiplexing devices.
[0028] In the above embodiments, a multi-path multiplexing device can be connected (shared) for every 4 UCIIE interfaces. By managing the 4 UCIIE interfaces in a group, it is possible to allow normal use even if up to 3 UCIIE interfaces are damaged. Compared with a fully interconnected multiplexing structure with more UCIIE interfaces, its design complexity and timing convergence difficulty are lower, which can improve the reliability of chip access.
[0029] Fourthly, embodiments of this application also provide an electronic device, including: a chip and a memory as provided in the third aspect embodiments and / or a possible implementation in conjunction with the third aspect embodiments, wherein the chip is connected to the memory via a UCI-E interface.
[0030] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.
[0032] Figure 1a This illustration shows a schematic diagram of the connection between the transmitting module and the host device and the ucie interface in a multi-path multiplexing device provided in an embodiment of this application.
[0033] Figure 1b This illustration shows a schematic diagram of the connection between the transmitting module and the master device and the ucie interface in another multi-path multiplexing device provided in this application embodiment.
[0034] Figure 2a for Figure 1a A possible structural diagram.
[0035] Figure 2b for Figure 1b A possible structural diagram.
[0036] Figure 3This illustration shows a schematic diagram of the connection between the receiving module and the host device and the ucie interface in a multi-path multiplexing device provided in an embodiment of this application.
[0037] Figure 4 for Figure 3 A possible structural diagram.
[0038] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation
[0039] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.
[0040] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0041] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.
[0042] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.
[0043] In view of the current problem of IO Die access obstacles caused by lane failures rendering corresponding UCIIE interfaces unusable, this application provides a multi-path multiplexing device. By connecting multiple UCIIE interfaces, when some UCIIE interfaces fail due to lane failures, the device reroutes access tasks originally transmitted through the failed UCIIE interfaces to the normal UCIIE interfaces by reusing (or partially reusing) the normal UCIIE interfaces, thereby completing the IO Die access. Alternatively, the device reroutes the task response of the access task originally from the target master device corresponding to the failed UCIIE interface to the target master device by reusing (or partially reusing) the normal UCIIE interface, ensuring that the task response can be correctly returned to the source master device.
[0044] To mitigate the problem of corresponding UCI-IE interfaces becoming unusable due to lane failures, a backup lane design (such as an x16+1 lane redundancy scheme) has been introduced in the new generation of UCI-IE interfaces. When a lane fails, the faulty lane can be dynamically switched to a backup lane via a built-in switching circuit, thereby restoring the link. While introducing a backup lane design into the UCI-IE interface can solve the problem of the entire UCI-IE interface failing due to a single lane failure, it increases chip area and power consumption, as well as chip packaging costs. The multi-path multiplexing device provided in this application, however, allows multiple UCI-IE interfaces to share a single device and eliminates the need for a backup lane design within the UCI-IE interface. This eliminates the need for a switching circuit within the UCI-IE interface (for the x16+1 lane redundancy scheme, typically 18 switching circuits are required). Compared to the approach of introducing a backup lane design into the UCI-IE interface, this application also reduces chip area and power consumption, as well as the increased chip packaging costs associated with the backup lane design.
[0045] The multi-path multiplexing device provided in this application is used to connect n master devices and n UCIE interfaces, where n is an integer greater than or equal to 2. In some possible implementations, n is an integer greater than or equal to 2 and less than or equal to 16. The UCIE interfaces in this application include, but are not limited to, x16 UCIE interfaces. For example, in some possible implementations, the UCIE interface can be a UCIE interface that supports lane number degradation, such as an x8 UCIE interface.
[0046] When managing multiple UCIIE interfaces, 16 (or 16) UCIIE interfaces corresponding to each I / O Die can be managed. For example, the 16 UCIIE interfaces can be divided into 4 groups, with each group containing 4 UCIIE interfaces, in which case n=4. A multiplexing device is used to connect the 4 UCIIE interfaces, enabling task transmission to be completed by reusing the normal UCIIE interfaces when some of these 4 UCIIE interfaces fail.
[0047] The master device can refer to any functional module in the chip to which the uCIE interface belongs that needs to read and write data. For example, it can be a computing unit, processor core, graphics processing unit, DMA (Direct Memory Access) controller, etc.
[0048] The following describes the multipath multiplexing device provided in the embodiments of this application. This multipath multiplexing device may include a transmitting module, through which the master device can send access tasks to a memory (such as the IO Die mentioned above) connected to the UCI-IE interface. Alternatively, the multipath multiplexing device may include a receiving module, through which the master device can receive task responses sent by the memory (such as the IO Die mentioned above) connected to the UCI-IE interface. In some possible implementations, the multipath multiplexing device may also include both a receiving module and a transmitting module.
[0049] like Figure 1a , Figure 1b As shown, the transmitting module includes: a first control circuit, n first circuits, and n second circuits. The n first circuits are used to connect to n master devices, with one first circuit connected to one master device. The n second circuits are used to connect to n UCIE interfaces, with one second circuit connected to one UCIE interface. The first control circuit is connected to the n first circuits and the n second circuits respectively. Figure 1a , Figure 1b The left side of the first circuit is used to connect the master device, and the right side of the second circuit is used to connect the ucie interface. Figure 1a , Figure 1b In the multiplexing device, P0, P1, P2, and P3 represent the entry points of the transmitting module. These can be AXI (Advanced eXtensible Interface) data ports used to connect different master devices. uh_P0, uh_P1, uh_P2, and uh_P3 represent the exit points of the transmitting module. These can be AXI data ports accessed by ucie and used to connect different ucie interfaces.
[0050] In this configuration, each of the n first circuits corresponds one-to-one with one of the n master devices, each of the n first circuits corresponds one-to-one with one of the n second circuits, and each of the n second circuits corresponds one-to-one with one of the n UCIE interfaces. In other words, each of the n master devices also corresponds one-to-one with one of the n UCIE interfaces.
[0051] Figure 1a , Figure 1b Only the case of n=4 is shown, but n can take any value from [2, 16]. Considering that implementing full interconnection and multiplexing of 16 (n=16) UCI-IE interfaces would lead to high design complexity and timing convergence difficulty, in some implementations, n can take any value from [3, 8]. In this case, the probability of all n UCI-IE interfaces failing is reduced, and the design complexity and timing convergence difficulty are lower, which can improve the reliability of chip access. For example, when n=4, by managing 4 UCI-IE interfaces in a group, a maximum of 3 UCI-IE interfaces can still be used normally even if they fail. As another example, when n=5, by managing 5 UCI-IE interfaces in a group, a maximum of 4 UCI-IE interfaces can still be used normally even if they fail. And as yet another example, when n=8, by managing 8 UCI-IE interfaces in a group, a maximum of 7 UCI-IE interfaces can still be used normally even if they fail.
[0052] It is understandable that when n takes other values, such as n=6, the corresponding... Figure 1a Based on this, two first circuits and two second circuits need to be added. Simultaneously, slv0_remap[4], slv0_remap[5], and the slv0_remap_sel[3:0] signal needs to be changed to the slv0_remap_sel[5:0] signal. Similarly, it is necessary to... Figure 1b Based on this, two first circuits and two second circuits are added. At the same time, slv0_remap[4], slv0_remap[5], _remap_sel[4], and remap_sel[5] need to be added. Other cases will not be exemplified.
[0053] Each first circuit is configured to send an access task from the master device to either the first control circuit or the second circuit. The output direction of the corresponding first circuit can be controlled by the slv0_remap[0] signal, slv0_remap[1] signal, slv0_remap[2] signal, and slv0_remap[3] signal. For example, when slv0_remap[0]=1, the first circuit is configured to send an access task from the master device to the first control circuit, and when slv0_remap[0]=0, the first circuit is configured to send an access task from the master device to the second circuit. Of course, it can also be controlled in reverse.
[0054] The aforementioned slv0_remap signal is a bit map signal, where each bit represents an independent enable or flag. The values of the slv0_remap[0], slv0_remap[1], slv0_remap[2], and slv0_remap[3] signals can come from a 4-bit register (e.g., represented by the slv0_remap register). The access task of the first circuit can be determined by modifying the value of this 4-bit register, and whether the normal ucie interface needs to be reused through the first control circuit. For example, when the ucie interface is normal, slv0_remap=4'b0000. When the ucie interface is known to be partially abnormal, the software needs to modify the register value in the static configuration. Assuming that the ucie interface connected to the uh_P2 and uh_P3 outlets is faulty, if the ucie interface connected to the uh_P1 outlet is reused, the value of the slv0_remap signal can be modified to: slv0_remap=4'b1110.
[0055] When all n UCIE interfaces are functioning normally, each first circuit is configured to send the received access task to the second circuit (commonly known as data pass-through). In some possible implementations, the received access task can be sent to the first control circuit when the UCIE interface corresponding to the first circuit fails. For example, if some of the n UCIE interfaces fail, the target first circuit among the n first circuits is configured to send the received access task to the first control circuit. The target first circuit can be the first circuit corresponding to the failed UCIE interface. Furthermore, the target first circuit can also be the first circuit corresponding to a multiplexed UCIE interface. For example, assuming the UCIE interfaces connected to UH_P2 and UH_P3 are faulty, if the UCIE interface connected to UH_P1 is reused, then the first circuits connected to P2, P3, and P1 can all send the received access task to the first control circuit. In this case, the first circuits connected to P2, P3, and P1 are all target first circuits.
[0056] In the above implementation, when some paths fail, only the faulty path and the multiplexed path are allowed to pass through the first control circuit to reduce bandwidth loss, while data from the remaining non-faulty paths is passed directly, and the bandwidth of the remaining non-faulty paths is unaffected. That is, when a certain UCI-IE interface fails, for normal and unmultiplexed UCI-IE interfaces, the first circuit directly sends the received access task to the second circuit (commonly known as data pass-through), without needing to go through the control of the first control circuit. This method of partial multiplexing and partial pass-through can effectively improve the efficiency of data transmission compared to full multiplexing.
[0057] In some possible implementations, the structures of the various first circuits can be identical; for example, each first circuit can be a demultiplexer (DEMUX). The demultiplexer is the inverse process of a multiplexer (MUX). It has one input, multiple outputs, and a selection control signal. Its function is to distribute a unique input data to one of the multiple outputs based on the value of the selection signal.
[0058] The first control circuit is configured to, when some of the n UCIE interfaces fail, reroute access tasks originally transmitted through the failed UCIE interfaces to the second circuit corresponding to the normal UCIE interfaces by reusing the normal UCIE interfaces. For example, assuming the UCIE interfaces connected to uh_P2 and uh_P3 are faulty, the first control circuit can route access tasks sent by the master device connected to P2 and P3 to the UCIE interfaces connected to uh_P1 or uh_P0. Since the UCIE interfaces corresponding to the master devices connected to P2 and P3 are faulty (i.e., the UCIE interfaces connected to uh_P2 and uh_P3 are faulty), the first circuit connected to P2 and P3 will send the received access tasks to the first control circuit instead of the second circuit.
[0059] Assuming the UCIE interfaces connected to uh_P2 and uh_P3 fail, the UCIE interface connected to uh_P1 is reused. To facilitate subsequent differentiation of which master device a access task sent from uh_P1 originates from, the first control circuit is specifically configured to add the identity identifier of the corresponding master device to the received access task. For example, after receiving an access task sent by the first circuit connected to P3, the first control circuit will add the identity identifier of the master device connected to P3; similarly, after receiving an access task sent by the first circuit connected to P2, the first control circuit will add the identity identifier of the master device connected to P2; and similarly, after receiving an access task sent by the first circuit connected to P1, the first control circuit will add the identity identifier of the master device connected to P1. It is understood that the identity identifiers of different master devices are different; the identity identifiers of the master devices connected to P0, P1, P2, and P3 are different. For example, assuming the identity identifier is 2 bits, the identity identifier of the master device connected to the P0 entry can be 00, the identity identifier of the master device connected to the P1 entry can be 01, the identity identifier of the master device connected to the P2 entry can be 10, and the identity identifier of the master device connected to the P3 entry can be 11.
[0060] In one possible implementation, the access task before adding the identity identifier can have a bit width of 12 bits, while the access task after adding the identity identifier has a bit width of 14 bits. When adding the identity identifier, it can be added to the highest bit of the original 12 bits, the lowest bit, or other agreed-upon bits.
[0061] After adding an identity identifier, in one possible implementation, the first control circuit can send the access task with the added identity identifier to the second circuit corresponding to the normal UCIIE interface. When sending the access task with the added identity identifier to the second circuit corresponding to the normal UCIIE interface, the first control circuit can send the access task with the added identity identifier to the second circuit corresponding to only one normal UCIIE interface (that is, the UCIIE interface that is being reused). For example, assuming that the UCIIE interfaces connected to the UH_P2 and UH_P3 exits are faulty, if the first control circuit only sends the access task with the added identity identifier to the UCIIE interface connected to the UH_P1 exit, then the UCIIE interface connected to the UH_P1 exit is the reused UCIIE interface.
[0062] After adding an identifier, in some possible implementations, the first control circuit can send the access task with the added identifier to all second circuits. The specific second circuit that outputs the access task sent by the first control circuit is controlled by the remap_sel signal.
[0063] exist Figure 1a In the example shown, the first control circuit outputs a task to only one second circuit. The specific second circuit to which the first control circuit outputs the access task can be controlled via the slv0_remap_sel[3:0] signal. Figure 1b In the example shown, the first control circuit sends access tasks to all the second circuits. The access task from the first control circuit can be output by one of the n second circuits through the remap_sel[0], remap_sel[1], remap_sel[2], and remap_sel[3] signals. For example, when the remap_sel signal is 0, the access task from the first circuit is selected by default; when the remap_sel signal is 1, the access task from the first control circuit is selected by default. Of course, it can also be controlled in reverse.
[0064] The value of the slv0_remap_sel[3:0] signal comes from another 4-bit register (e.g., represented by the slv0_remap_sel register), and the slv0_remap_sel signal is one-hot. A specific UCIE data path can be selected for multiplexing by modifying the value of this 4-bit register. By default, slv0_remap_sel = 4'b0000. When a UCIE interface is known to be faulty and a specific UCIE data path needs to be multiplexed, the value of the corresponding path can be modified. For example, if the UCIE interface connected to the uh_P1 outlet needs to be multiplexed, the value of the slv0_remap_sel signal can be modified to: slv0_remap_sel = 4'b0010.
[0065] The remap_sel signal is a bit map signal, where each bit represents an independent enable or flag. The values of remap_sel[0], remap_sel[1], remap_sel[2], and remap_sel[3] can come from another 4-bit register (e.g., represented by the remap_sel register). The value of this 4-bit register can be modified to determine whether the second circuit selects the access task output from the first circuit or the first arbiter. For example, when the ucie interface is normal, remap_sel = 4'b0000 by default. When the ucie interface is known to be faulty, the software needs to modify the register value in the static configuration. Assuming that the ucie interface connected to the uh_P2 and uh_P3 outlets is faulty, if the ucie interface connected to the uh_P1 outlet is reused, the value of the remap_sel signal can be modified to: remap_sel = 4'b0010.
[0066] exist Figure 1a In the example shown, the first control circuit may include a first arbiter (ARB) and a first selection circuit. The first arbiter is connected to n first circuits and n first selection circuits, respectively, and the first selection circuits are connected to n second circuits.
[0067] The first arbitrator is configured to add the identity of the corresponding master device to the received access task and send the access task with the added identity to the first selection circuit. In addition to adding the identity of the corresponding master device to the received access task, the first arbitrator also arbitrates access tasks from different first circuits. Arbitration can be based on a PQ (Priority Queuing) + RR (Round-Robin) arbitration strategy. For access tasks with different priorities, the PQ arbitration strategy is used; for access tasks with the same priority, the RR arbitration strategy is used.
[0068] The first selection circuit is configured to send the received access task to the second circuit corresponding to a normal UCIE interface (which is the multiplexed UCIE interface). The specific second circuit to which the first control circuit outputs the access task can be controlled via the slv0_remap_sel[3:0] signal. In some possible implementations, the first selection circuit is a resetter.
[0069] exist Figure 1b In the example shown, the first control circuit may consist of only a first arbitrator. The first arbitrator is connected to n first circuits and n second circuits, respectively. The first arbitrator is configured to add the corresponding master device's identity to received access tasks and send the identified access tasks to each second circuit. In addition to adding the corresponding master device's identity to received access tasks, the first arbitrator also arbitrates access tasks from different first circuits, and the arbitration can be based on a PQ+RR arbitration strategy.
[0070] The second circuit is configured to output access tasks from the first circuit or the first control circuit. Figure 1a The second circuit shown is Figure 1b The second circuit shown can be different.
[0071] exist Figure 1a In the example shown, the second circuit connected to a faulty UCIE interface will not receive access tasks. For a second circuit connected to a normal UCIE interface, it will only receive access tasks from the first circuit or the first control circuit. Simultaneously, the first control circuit will only send access tasks to one of the second circuits connected to a normal UCIE interface. Therefore, the second circuit only needs to output the received access tasks. For example, if the UCIE interfaces connected to UH_P2 and UH_P3 are faulty, the first circuit connected to the P0 input can directly send access tasks to the second circuit connected to the UH_P0 output, while the second circuit connected to the UH_P1 output will only receive access tasks from the first control circuit.
[0072] exist Figure 1a In the example shown, the second circuit can be a logic gate transmission circuit, such as an OR gate. In some possible implementations, the second circuit can be a multiplexer (MUX) without a selection signal, i.e., the remap_sel control mentioned above. In this case, the multiplexer can be considered a special type of multiplexer (without a selection signal). Typically, a multiplexer is a combinational logic circuit with multiple inputs, one output, and a set of selection control signals. Its function is to select one of the multiple input data based on the value of the selection signal and transmit it to the unique output.
[0073] exist Figure 1b In the example shown, since the first control circuit sends access tasks to all second circuits, each second circuit cannot simply output the received access tasks; otherwise, duplicate access tasks would be output. In this case, the second circuits can be switching circuits. Each switching circuit is configured to select the access task output from the first circuit or the first arbitrator based on the `remap_sel` signal. Specifically, the target switching circuit is configured to select the access task output from the first arbitrator, and the remaining switching circuits select the access task output from the first circuit. The target switching circuit is the second circuit corresponding to the multiplexed ucie interface. In some possible implementations, the second circuit can be a multiplexer (MUX) and requires control by the `remap_sel` signal.
[0074] In some possible implementations, Figure 1a One possible specific structure of the circuit shown can be as follows: Figure 2a As shown, at this time, the first circuit is DEMUX, the second circuit is MUX, and the first control circuit includes ARB and DEMUX. Taking the failure of a lane in the ucie interface corresponding to uh_P2 and uh_P3 as an example, the uh_P1 path is reused, and the slv0_remap register is configured as 4'b1110, that is, P0 is pass-through. The data paths of P3, P2 and P1 are combined through the ARB arbiter (the bandwidth is reduced). At the same time, the slv0_remap_sel register is configured as 4'b0010, and the uh_P1 path is selected for reuse. The P0 inlet traffic is not affected.
[0075] In some possible implementations, Figure 1b One possible specific structure of the circuit shown can be as follows: Figure 2bAs shown. At this point, the first circuit is DEMUX, the second circuit is MUX, and the first control circuit is ARB. Taking the failure of a lane in the ucie interface corresponding to uh_P2 and uh_P3 outlets as an example, the uh_P1 path is reused, and the slv0_remap register is configured as 4'b1110, meaning P0 is pass-through. The data paths of P3, P2, and P1 are sent to each MUX after passing through the ARB arbitrator. Simultaneously, remap_sel is configured as register 4'b0010. The second circuit connected to uh_P1 outlet will select data output from the ARB arbitrator, and the second circuits connected to uh_P2, uh_P3, and uh_P0 outlets will select data output from the first circuit. Since the first circuits corresponding to uh_P2 and uh_P3 outlets do not output data to the corresponding second circuits, the second circuits corresponding to uh_P2 and uh_P3 outlets will not output data.
[0076] This application does not need to focus on how to detect a UCIE interface failure. Instead, when a UCIE interface failure is known, it can control the first circuit and the first control circuit, or control the first circuit and the second circuit, by modifying the value of the register. This enables the rerouting of access tasks originally transmitted through the faulty UCIE interface to the normal UCIE interface when some of the n UCIE interfaces are faulty, by reusing the normal UCIE interface.
[0077] In some possible implementations, the multiplexing device may include a receiving module; in some implementations, the multiplexing device may include both a transmitting module and a receiving module.
[0078] Among them, such as Figure 3 As shown, the receiving module includes: a second control circuit, n third circuits, and n fourth circuits. The n third circuits are used to connect to n UCIE interfaces, with one third circuit connected to one UCIE interface; the n fourth circuits are used to connect to n master devices, with one fourth circuit connected to one master device. The second control circuit is connected to each of the n third circuits and the n fourth circuits. In this embodiment, Figure 3 In the multiplexing device, P0, P1, P2, and P3 represent the outputs of the receiving module, used to connect to different master devices. uh_P0, uh_P1, uh_P2, and uh_P3 represent the inputs of the receiving module, used to connect to different UCIE interfaces.
[0079] in, Figure 3 The receiving module shown is multiplexed. Figure 1a or Figure 2aThe slv0_remap_sel[3:0] signal and the slv0_remap signal (such as slv0_remap[0] signal, slv0_remap[1] signal, slv0_remap[2] signal, slv0_remap[3] signal) are used, thus eliminating the need for additional configuration and reducing the number of registers used. Furthermore, when the transmitting module is... Figure 1b or Figure 2b When the structure shown is used, Figure 3 The receiving module shown can also be reused. Figure 1b or Figure 2b The slv0_remap signal shown is used to reduce the configuration of registers.
[0080] Each third circuit is configured to send a task response from the UCIIE interface to either the second or fourth control circuit. In one possible implementation, when some of the n UCIIE interfaces fail, the target circuit among the n third circuits is configured to send the task response from the multiplexed UCIIE interface to the second control circuit, where the target third circuit is the third circuit corresponding to the multiplexed UCIIE interface. When all n UCIIE interfaces are functioning normally, each third circuit is configured to send the received task response to the corresponding fourth circuit.
[0081] In some possible implementations, the structures of the various third circuits can be identical; for example, each third circuit can be a demultiplexer. The control signals of the third circuits are the same as those of the aforementioned first circuit.
[0082] The second control circuit is configured to, when some of the n UCIE interfaces fail, reroute the task responses of access tasks originally originating from the target master device corresponding to the failed UCIE interface to the fourth circuit corresponding to the target master device by reusing the normal UCIE interfaces. For example, if the UCIE interfaces connected to uh_P2 and uh_P3 fail, and the UCIE interface connected to uh_P1 is reused, the second control circuit can send the task responses from access tasks received by the UCIE interface connected to uh_P1 from the master devices connected to P2 and P3 to the fourth circuit corresponding to the master devices connected to P2 and P3.
[0083] In some possible implementations, the second control circuit is specifically configured to send the task response to the fourth circuit corresponding to the master device to which the identity carries in the received task response, to ensure that the task response is correctly returned to the target master device that sent the access task corresponding to the task response. The second control circuit can be controlled via the slv0_remap_sel[3:0] signal to only receive task responses from the third circuit corresponding to the multiplexed ucie interface.
[0084] In some possible implementations, the second control circuit includes a second arbitrator (which may be represented as an ARB) and a second selection circuit. The second arbitrator is connected to n fourth circuits and the second selection circuit, respectively, and the second selection circuit is connected to the n third circuits. In some possible implementations, the second arbitrator may also be replaced by other devices that perform the same function, such as a controller.
[0085] The second selection circuit is configured to select the task response received by the third circuit corresponding to the multiplexed ucie interface. The specific task response output of the second selection circuit (the third circuit corresponding to the multiplexed ucie interface) can be controlled by the slv0_remap_sel[3:0] signal. In some possible implementations, the second selection circuit is a multiplexer.
[0086] The second arbitrator is configured to forward the task response to the fourth circuit corresponding to the master device to which the identity belongs, based on the identity carried in the received task response. Furthermore, the second arbitrator can also arbitrate the transmission order of the received task responses. Arbitration can be based on a PQ+RR arbitration strategy.
[0087] In some possible implementations, Figure 3 One possible specific structure of the circuit shown can be as follows: Figure 4 As shown. At this time, the third circuit is DEMUX, the fourth circuit is MUX, and the second control circuit includes ARB and MUX. Taking the failure of a lane in the ucie interface corresponding to uh_P2 and uh_P3 as an example, the uh_P1 path is reused, the slv0_remap register is configured as 4'b1110, that is, uh_P0 is pass-through, and the data flow of uh_P3, uh_P2 and uh_P1 is directed to the MUX in the second control circuit. At the same time, the slv0_remap_sel register is configured as 4'b0010, and the uh_P1 path is selected for reuse. The second arbitrator sends the task response to the fourth circuit corresponding to the master device to which the identity belongs, according to the identity identifier carried in the received task response.
[0088] In some possible implementations, the second arbitrator in the receiving module and the first arbitrator in the transmitting module can be the same arbitrator. By reusing the arbitrator, chip area and cost can be reduced.
[0089] This application also provides a chip comprising n master devices, n uCIE interfaces, and the aforementioned multiplexing device, where n is an integer greater than or equal to 2; the multiplexing device is connected to the n master devices and the n uCIE interfaces respectively.
[0090] In some possible implementations, the chip includes four sets of I / O interfaces, each set containing 16 UCIIE interfaces. When n=4, every four UCIIE interfaces connect to one multiplexing device. It is understood that the value of n is not limited to 4. In some possible implementations, n is an integer greater than or equal to 2 and less than or equal to 16, such as n=3, n=5, n=6, n=7, etc., which will not be listed here.
[0091] In some possible implementations, the chip provided in this application may be a single chip, such as a processor, including but not limited to a central processing unit (CPU), network processor (NP), graphics processing unit (GPU), accelerated processing unit (accelerated processing unit), multimedia application processor (MAP), microprocessor, etc.; it may also be a digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component.
[0092] In some possible implementations, the chip provided in this embodiment may be a SOC (System On a Chip) chip, which may be a chip that integrates a core processing unit (such as including one or more CPU cores, GPU cores, etc.), peripheral interfaces (such as integrating a memory controller, storage controller, USB controller, display controller, audio codec, etc.), dedicated hardware accelerators, etc.
[0093] The multi-path multiplexing device provided in the chip embodiment has the same implementation principle and technical effect as the aforementioned multi-path multiplexing device embodiment. For the sake of brevity, any parts not mentioned in the chip embodiment can be referred to the corresponding content in the aforementioned multi-path multiplexing device embodiment. This application also provides an electronic device, which includes the chip and memory described above, with the chip connected to the memory via a UCI-E interface.
[0094] In some possible implementations, when the chip is a processor, the structure of the electronic device can be as follows: Figure 5As shown, the electronic device includes a transceiver, a memory, a communication bus, and a processor. In some possible implementations, the communication bus may be an AXI bus. The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores data such as computer programs, where the computer program includes at least one software functional module that can be stored in the memory as software or firmware or embedded in the operating system (OS) of the electronic device. The processor executes the software functional module or computer program stored in the memory. The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.
[0095] A processor may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), Network Processor (NP), Graphics Processing Unit (GPU), Accelerated Processing Unit (ACCU), Multimedia Application Processor (MAP), microprocessor, etc.; it can also be a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. Alternatively, the processor can be any conventional processor.
[0096] The aforementioned electronic devices include, but are not limited to, mobile phones, tablets, laptops, desktop computers, servers, etc.
[0097] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0098] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A multi-path multiplexing device, characterized in that, The multiplexing device, used to connect n master devices and n uCIE interfaces, where n is an integer greater than or equal to 2, includes a transmitting module: The transmitting module includes: a first control circuit, n first circuits, and n second circuits; The n first circuits are used to connect the n master devices, and one first circuit is connected to one master device; each first circuit is configured to send an access task from the master device to the first control circuit or the second circuit. The n second circuits are used to connect the n ucie interfaces, and one second circuit is connected to one ucie interface; the second circuits are configured to output access tasks from the first circuit or the first control circuit. The first control circuit is connected to the n first circuits and the n second circuits respectively; the first control circuit is configured to, when some of the n ucie interfaces are faulty, reroute the access tasks originally transmitted through the faulty ucie interfaces to the second circuit corresponding to the normal ucie interfaces by reusing the normal ucie interfaces.
2. The multi-path multiplexing device according to claim 1, characterized in that, When some of the n UCIE interfaces are faulty, the target first circuit among the n first circuits is configured to send the received access task to the first control circuit, wherein the target first circuit is the first circuit corresponding to the faulty UCIE interface and the first circuit corresponding to the reused UCIE interface. The first control circuit is specifically configured to add the identity identifier of the corresponding master device to the received access task, and send the access task with the added identity identifier to the second circuit corresponding to the multiplexed ucie interface.
3. The multi-path multiplexing device according to claim 1, characterized in that, When all n ucie interfaces are functioning normally, each of the first circuits is configured to send the received access task to the second circuit.
4. The multi-path multiplexing device according to claim 1, characterized in that, The second circuit is a switching circuit; The first control circuit includes: A first arbitrator is connected to the n first circuits and the n second circuits respectively; the first arbitrator is configured to add the identity identifier of the corresponding master device to the received access task and send the access task with the added identity identifier to each second circuit; The target switching circuit among the n second circuits is configured to select the access task output from the first arbitrator, and the target switching circuit is the second circuit corresponding to the multiplexed ucie interface.
5. The multi-path multiplexing device according to claim 1, characterized in that, The first control circuit includes: a first arbitrator and a first selection circuit; the first arbitrator is connected to the n first circuits and the first selection circuit respectively, and the first selection circuit is connected to the n second circuits; The first arbiter is configured to add the identity identifier of the corresponding master device to the received access task and send the access task with the added identity identifier to the first selection circuit; The first selection circuit is configured to send the received access task to a second circuit corresponding to a normal ucie interface.
6. The multi-path multiplexing device according to claim 1, characterized in that, The multi-path multiplexing device also includes a receiving module; The receiving module includes: a second control circuit, n third circuits, and n fourth circuits; The n third circuits are used to connect the n ucie interfaces, and one third circuit is connected to one ucie interface; each third circuit is configured to send a task response from the ucie interface to the second control circuit or the fourth circuit; The n fourth circuits are used to connect the n master devices, and one fourth circuit is connected to one master device; the fourth circuit is configured to output a task response from the third circuit or the second control circuit; The second control circuit is connected to the n third circuits and the n fourth circuits respectively; the second control circuit is configured to, when some of the n ucie interfaces are faulty, reroute the task response of the access task originally from the target master device corresponding to the faulty ucie interface to the fourth circuit corresponding to the target master device by reusing the normal ucie interface.
7. The multi-path multiplexing device according to claim 6, characterized in that, When some of the n UCIE interfaces are faulty, the target third circuit among the n third circuits is configured to send the task response from the multiplexed UCIE interface to the second control circuit, wherein the target third circuit is the third circuit corresponding to the multiplexed UCIE interface. The second control circuit is specifically configured to send the task response to the fourth circuit corresponding to the master device to which the identity identifier belongs, based on the identity identifier carried in the received task response.
8. The multi-path multiplexing device according to claim 6, characterized in that, When all n ucie interfaces are functioning normally, each of the third circuits is configured to send the received task response to the corresponding fourth circuit.
9. The multi-path multiplexing device according to claim 6, characterized in that, The second control circuit includes: a second arbitrator and a second selection circuit; the second arbitrator is connected to the n fourth circuits and the second selection circuit respectively, and the second selection circuit is connected to the n third circuits; The second selection circuit is configured to select the task response received by the third circuit corresponding to the multiplexed ucie interface; The second arbitrator is configured to send the task response to the fourth circuit corresponding to the master device to which the identity is to be represented, based on the identity carried in the received task response.
10. A multi-path multiplexing device, characterized in that, The multiplexing device is used to connect n master devices and n uCIE interfaces, where n is an integer greater than or equal to 2. The multiplexing device includes a receiving module. The receiving module includes: a second control circuit, n third circuits, and n fourth circuits; The n third circuits are used to connect the n ucie interfaces, and one third circuit is connected to one ucie interface; each third circuit is configured to send a task response from the ucie interface to the second control circuit or the fourth circuit; The n fourth circuits are used to connect the n master devices, and one fourth circuit is connected to one master device; the fourth circuit is configured to output a task response from the third circuit or the second control circuit; The second control circuit is connected to the n third circuits and the n fourth circuits respectively; the second control circuit is configured to, when some of the n ucie interfaces are faulty, reroute the task response of the access task originally from the target master device corresponding to the faulty ucie interface to the fourth circuit corresponding to the target master device by reusing the normal ucie interface.
11. A chip, characterized in that, include: n master devices, n uCIE interfaces, and a multiplexing device as described in any one of claims 1-10, where n is an integer greater than or equal to 2; The multiplexing device is connected to the n master devices and the n uCIE interfaces respectively.
12. The chip according to claim 11, characterized in that, The chip includes 4 sets of I / O interfaces, each set of I / O interfaces includes 16 UCIIE interfaces. When n=4, every 4 UCIIE interfaces are connected to one of the multiplexing devices.
13. An electronic device, characterized in that, include: The chip and memory as described in claim 11 or 12, wherein the chip is connected to the memory via a UCI-E interface.