Data prefetching method and electronic equipment

Abstract

The invention provides a data prefetching method and electronic equipment, and the method comprises the steps that when a main thread executes a first program to a first prefetching position, the main thread sends a first message to an auxiliary thread, the first prefetching position is determined according to first information, and the first information comprises first data and the position of the first data; the first data are data which are determined before the main thread executes the first program and need to be acquired from the memory; the auxiliary thread obtains second information according to the first message, the second information comprises second data and the position of the second data, and the second data is data which is determined by the main thread based on the first program and needs to be obtained from the memory; and the auxiliary thread prefetches the data of the first program according to the first information and the second information. According to the method and the device, the data needing to be prefetched and the position of the data can be dynamically adjusted in real time, so that the auxiliary thread can prefetch the required data every time, the prefetching effect is relatively good, and the time delay of executing the program by the main thread is reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data prefetching method and electronic device. Background Technology

[0002] Currently, when a Central Processing Unit (CPU) runs a program, it can use software prefetching technology to prefetch instructions and / or data that may fail to cache, thus filling the data segments in the CPU pipeline where cache errors occur. This method uses fixed prefetch instructions to perform data prefetching. These fixed prefetch instructions are determined before program execution (e.g., during the compilation phase), and the data to be prefetched and the location of that data are fixed and unchanging. However, during actual program execution, the instructions and data actually executed may change, and the originally fixed prefetch instructions may fail to prefetch the required data, resulting in poor prefetching performance and thus causing significant latency in program execution. Summary of the Invention

[0003] This application discloses a data prefetching method and an electronic device that can dynamically adjust the data to be prefetched and the position of the data in real time, so that the auxiliary thread can prefetch the required data each time, resulting in a better prefetching effect and reducing the latency of the main thread executing the program.

[0004] In a first aspect, embodiments of this application provide a data prefetching method, the method comprising: when a main thread executes a first program to a first prefetching position, the main thread sends a first message to an auxiliary thread, the first prefetching position being determined based on first information, the first information including first data and the position of the first data, the first data being data that the main thread determines needs to retrieve from memory before executing the first program, and the position of the first data being the execution position of the first data in the main thread; the auxiliary thread obtaining second information based on the first message, the second information including second data and the position of the second data, the second data being data that the main thread determines needs to retrieve from memory based on the first program, and the position of the second data being the execution position of the second data in the main thread; and the auxiliary thread prefetching data of the first program based on the first information and the second information.

[0005] In the above method, when the main thread reaches the first prefetch position, it can send a first message to the auxiliary thread to wake it up. The auxiliary thread can then obtain second information, which may include instructions and / or data that will be cache-invalidated (i.e., the aforementioned second data) determined during the execution of the first program, as well as the location of the second data. The first information may include instructions and / or data that will be cache-invalidated (i.e., the aforementioned first data) determined before the first program's execution (e.g., during the compilation / development phase of the first program), as well as the location of the first data. The auxiliary thread can prefetch data from the first program based on the first and second information. In this way, the auxiliary thread can dynamically adjust the information on instructions and / or data that will be cache-invalidated in real time, i.e., dynamically adjust the data that needs to be prefetched in the first program and its location, ensuring that the auxiliary thread can prefetch the required data each time, thus reducing the latency of the main thread's program execution.

[0006] In one possible implementation, the auxiliary thread prefetches data of the first program based on the first information and the second information, including: when the first data and the second data are the same and the positions of the first data and the second data are the same, the auxiliary thread prefetches data of the first program based on the first information; when the first data and the second data are different and / or the positions of the first data and the second data are different, the auxiliary thread updates the first information based on the second information and prefetches data of the first program based on the updated first information.

[0007] In one possible implementation, the first message further includes a first prefetch address, the first prefetch location being the prefetch location of third data in the first information, the third data being any one of the first data, the third data corresponding to the first prefetch address, and the auxiliary thread prefetching data of the first program according to the first message and the first information, including: the auxiliary thread obtaining the third data from the memory according to the first prefetch address and loading the third data into the cache.

[0008] In the above method, when the first information and the second information are consistent (i.e., the first data and the second data are the same, and the positions of the first data and the second data are the same), the auxiliary thread can determine the third data that needs to be prefetched based on the first prefetch position, then determine the first prefetch address in the first message corresponding to the third data, and then retrieve the third data corresponding to the first prefetch address from memory and load it into the cache. In this approach, the data that needs to be prefetched in the first program remains unchanged, so the auxiliary thread can directly perform data prefetching based on the first information, reducing CPU overhead.

[0009] In one possible implementation, the auxiliary thread updates the first information according to the second information, and prefetches data of the first program according to the updated first information, including: the auxiliary thread updates the first information to the second information to obtain the updated first information, the updated first information including the second data, the position of the second data, the prefetch position of the second data, and the prefetch address of the second data; if the updated first information includes the first prefetch position, the auxiliary thread retrieves fourth data from the memory according to the second prefetch address, and loads the fourth data into the cache, wherein the first prefetch position is the prefetch position of the fourth data in the updated first information, the fourth data is any one of the second data, and the fourth data corresponds to the second prefetch address.

[0010] In one possible implementation, the method further includes: if the updated first information does not include the first prefetch position, the auxiliary thread executes a first instruction, the first instruction being used to switch the auxiliary thread to a low-power mode.

[0011] In the above method, when the first information and the second information are inconsistent (i.e., the first data and the second data are different, and / or the positions of the first data and the second data are different), the auxiliary thread can update the first information to the second information and obtain the updated first information. If the updated first information includes the first prefetch position, the auxiliary thread can determine the fourth data that needs to be prefetched based on the first prefetch position, and determine the second prefetch address in the second information corresponding to the fourth data. Then, it retrieves the fourth data corresponding to the second prefetch address from memory and loads it into the cache. If the updated first information does not include the first prefetch position, the auxiliary thread does not perform data prefetching this time and runs the first instruction to put the auxiliary thread in a low-power mode. In this way, when the data that needs to be prefetched in the first program changes, the auxiliary thread can perform data prefetching based on the second information (the information recorded in the PMU register). Since the PMU register can be used to store information about the current execution of the first program, the auxiliary thread can dynamically adjust the data that needs to be prefetched and the position of the data in the first program in real time based on the second information, so that the auxiliary thread can prefetch the required data every time, reducing the latency of the main thread executing the first program.

[0012] In one possible implementation, before the main thread sends the first message to the auxiliary thread, the auxiliary thread is in a low-power mode. The first message includes a second instruction, which is used for the auxiliary thread to switch from the low-power mode to the working mode. After the auxiliary thread prefetches data of the first program based on the first information and the second information, the method further includes: the auxiliary thread running the first instruction, which is used for the auxiliary thread to switch from the working mode to the low-power mode.

[0013] In the above method, when data prefetching is required, the main thread can run a second instruction to wake up the auxiliary thread, enable it, and perform data prefetching. When data prefetching is not required, the auxiliary thread can run a first instruction to enter a low-power mode. The first and second instructions can switch the running state of the auxiliary thread (e.g., working state or sleeping state) in a timely manner, reducing the latency of inter-thread interaction, reducing the load on the auxiliary thread, and thus reducing the CPU's computing power overhead.

[0014] In one possible implementation, after the auxiliary thread updates the first information based on the second information and prefetches the data of the first program based on the updated first information, the method further includes: the auxiliary thread running a first instruction, the first instruction being used for the auxiliary thread to switch to a low-power mode; when the main thread executes the first program to a second prefetch position, the main thread sends a second message to the auxiliary thread, the second prefetch position being determined based on the updated first information, the second message including a second instruction, the second instruction being used for the auxiliary thread to switch from the low-power mode to a working mode; the auxiliary thread obtaining third information based on the second message, the third information including third data and the position of the third data, the third data being data that the main thread needs to retrieve from the memory based on the first program, the position of the third data being the execution position of the third data in the main thread; and the auxiliary thread prefetching the data of the first program based on the third information and the updated first information.

[0015] In the above method, after the first program is executed once, it can be executed again. Subsequent auxiliary threads can continue to prefetch data from the first program based on the instructions and / or data that will be cached invalidated (i.e., the third data mentioned above) and the updated first information, and choose whether to update the updated first information according to the actual scenario. This enables real-time dynamic adjustment of the information of instructions and / or data that will be cached invalidated, that is, real-time dynamic adjustment of the data that needs to be prefetched in the first program and the position of the data, so that the auxiliary thread can prefetch the required data each time, reducing the latency of the main thread executing the program.

[0016] In one possible implementation, the process of the main thread executing the first program is the Nth time the main thread executes the first program, where N is a positive integer, and N is greater than or equal to 2. The first data is the data that needs to be retrieved from the memory before the main thread executes the first program for the first time, and the second data is the data that needs to be retrieved from the memory when the main thread executes the first program for the Nth time.

[0017] In one possible implementation, the auxiliary thread is created when the main thread starts executing the first program, and during the execution of the first program by the main thread, the auxiliary thread and the main thread are on the same physical core in the synchronous multithreaded SMT mode.

[0018] In the above method, the auxiliary thread can be bound to the same physical core as the main thread in SMT mode in real time, which can increase the size of the shared cache area and further improve prefetching efficiency.

[0019] In a second aspect, this application provides an electronic device, including a transceiver, a processor, and a memory, wherein the memory is used to store a computer program, and the processor invokes the computer program to execute the data prefetching method in any possible implementation of the first aspect.

[0020] Thirdly, this application provides an electronic device including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program code, including computer instructions, which, when executed by the one or more processors, cause the electronic device to perform the data prefetching method in any possible implementation of the first aspect described above.

[0021] Fourthly, this application provides a computer storage medium storing a computer program that, when executed by a processor, implements the data prefetching method in any of the possible implementations of any of the above aspects.

[0022] Fifthly, this application provides a computer program product that, when run on an electronic device, causes the electronic device to execute the data prefetching method in any possible implementation of the first aspect described above.

[0023] Sixthly, this application provides an electronic device including the method or apparatus described in any implementation of the first aspect of this application. The electronic device is, for example, a chip. Attached Figure Description

[0024] The following describes the accompanying drawings used in this application.

[0025] Figure 1 This is a schematic diagram of a software prefetching technology provided in this application;

[0026] Figure 2 This is a schematic diagram of the hardware architecture of an electronic device 100 provided in this application;

[0027] Figure 3 This is a schematic diagram of a data prefetching method provided in this application;

[0028] Figure 4 This is a flowchart illustrating a data prefetching method provided in this application;

[0029] Figure 5 This is a flowchart illustrating another data prefetching method provided in this application. Detailed Implementation

[0030] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; the word "and / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0031] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0032] In this embodiment, the main thread can be a thread created by the operating system for the program when it starts / begins to run. The main thread can be used to handle user interface-related logic, and includes, but is not limited to, application main threads, rendering main threads, web threads, compositing threads, etc. When the Central Processing Unit (CPU) runs the program, the main thread can execute multiple instructions and data within the program. The execution order / position of these instructions and data is related to the program itself, such as the code contained in the program. Auxiliary threads can be threads created after the main thread starts. Auxiliary threads can be used to perform background tasks, such as accessing memory, data processing, and business monitoring.

[0033] When a CPU runs a program, it can retrieve the required instructions and data from memory or cache. Specifically, the CPU can first determine whether the data requested by the CPU during program execution (referred to as requested data, such as instructions and / or data) exists in the cache. If the requested data exists in the cache (in this embodiment, "hit" is used to represent the existence of requested data in the cache), the CPU can directly retrieve the requested data from the cache without accessing memory again. If the requested data does not exist in the cache (referred to as a cache miss), the requested data in memory needs to be loaded into the cache first, and then the CPU retrieves the requested data from the cache. However, this method will cause a significant delay for the CPU, affecting its processing efficiency. The aforementioned cache may include register memory (referred to as registers) and CPU cache, such as L1 cache, L2 cache, and L3 cache. Both the memory and the cache can be integrated inside the CPU. In some examples, the CPU's internal memory may include multiple memory structures, which, from closest to furthest from the CPU core, are: registers, L1 cache, L2 cache, L3 cache, and main memory. Understandably, the next level down from registers is L1 cache, the next level down from L1 cache is L2 cache, the next level down from L2 cache is L3 cache, and the next level down from L3 cache is main memory. Furthermore, the CPU's access speed to these memory structures, from fastest to slowest, is: registers, L1 cache, L2 cache, L3 cache, and main memory. Table 1 exemplifies the time required for the CPU to access different memory structures.

[0034] Table 1

[0035] event Delay Read register 1 clock cycle L1 cache hit 3 cycles L1 cache miss, L2 cache hit 10 cycles L2 cache miss, L3 cache hit 30 cycles Read memory 150 cycles or more

[0036] Table 1 shows that the CPU needs 1 cycle to read the requested data from the register; when the requested data is not in the register, the CPU needs 3 cycles to read the requested data from the L1 cache; when the requested data is not in the L1 cache, the CPU needs 10 cycles to read the requested data from the L2 cache; when the requested data is not in the L2 cache, the CPU needs 30 cycles to read the requested data from the L3 cache; and when the requested data is not in the L3 cache, the CPU needs more than 150 cycles to read the requested data from memory. In other words, when a cache miss occurs, the CPU will experience a significant latency (e.g., more than 150 cycles), which will severely impact CPU performance and lead to low processing efficiency.

[0037] Currently, CPUs can use software prefetching technology to prefetch instructions and / or data (which can be called cache miss data / data segments) that may fail to cache, thus filling the cache miss data segments in the CPU pipeline and significantly reducing or eliminating the latency caused by cache misses. Prefetching is the process of retrieving a data segment from memory and storing it in the cache before the CPU processes it. Figure 1 An exemplary schematic diagram of a software prefetching technique is shown, such as Figure 1 As shown, without prefetching, after processing data s1, the processor needs to process data r1, but r1 is not in the cache. The CPU needs to fetch r1 from memory, incurring a 5ms delay. Next, after processing data s2, the CPU needs to process data r2, which is not in the cache. The CPU fetches r2 from memory, incurring a 5ms delay. Then, after processing data s3, the CPU needs to process data r3, which is not in the cache. The CPU fetches r3 from memory, incurring a 5ms delay. Finally, the CPU processes data s4. The processor without prefetching takes 40ms to process the data, of which 15ms is spent fetching the required data from memory.

[0038] like Figure 1 As shown, a processor using prefetching technology prefetches cache-missed data r1 during the processing of data s1 (i.e., fetches data segment r1 from memory and stores it in the cache). Therefore, after the CPU finishes processing data s1, it can directly process the prefetched data r1, reducing the CPU latency (e.g., 5ms) while waiting to retrieve data r1 from memory. Next, during the processing of data s2, the CPU prefetches cache-missed data r2, further reducing the CPU latency while waiting to retrieve data r2 from memory. Similarly, this also reduces the CPU latency while waiting to retrieve data r3 from memory. It can be seen that the processing time of a processor using prefetching technology (e.g., 28ms) is less than the time (40ms) of a processor without prefetching technology, significantly reducing the latency caused by cache misses. However, this method uses fixed prefetch instructions to implement data prefetching. The data to be prefetched and the location of the prefetched data are fixed and unchanging. For example... Figure 1In this CPU, only data r1, r2, and r3 are prefetched, and the positions of these prefetched data r1, r2, and r3 are fixed. Therefore, in different scenarios, such as when the CPU executes different instructions in response to different user operations, the fixed prefetch instructions may not be suitable for different scenario requirements. For example, scenario 1 requires prefetching data r1, r2, and r3, but scenario 2 requires prefetching data r4. In this case, the aforementioned fixed prefetch instructions can only satisfy scenario 1, but not scenario 2, thus affecting the prefetching effect. Furthermore, when the program (program code) is updated, the corresponding executed instructions and data will change, and the original fixed prefetch instructions may become invalid and no longer applicable to the new program. In addition, when the CPU prefetches data, it is difficult to determine the amount of data to prefetch and the timing of prefetching, making it impossible to achieve optimal prefetching results. Moreover, this prefetching method is executed by a single thread in the CPU (such as the main thread). This thread needs to prefetch data while processing data, which can cause excessive load on the thread, thus affecting its performance.

[0039] To address the issue of excessive load on a single thread, the CPU can run an auxiliary thread on an idle physical core. The main thread executes instructions and data, while the auxiliary thread accesses memory for data prefetching. For example, the CPU can adjust the prefetch distance on the auxiliary thread based on the ratio between the main thread's computational load and memory access volume. Synchronized processing by the main and auxiliary threads effectively reduces latency in fetching data from memory, thereby improving the main thread's performance. However, the auxiliary and main threads may not reside on the same physical core in Simultaneous Multi-Threading (SMT) mode, resulting in a smaller shared cache area, limited cache capacity, and low prefetch efficiency. Furthermore, the overhead of synchronized processing between the auxiliary and main threads is significant, leading to excessive load on the auxiliary thread.

[0040] To address the issue of excessive load on auxiliary threads, a prefetch instruction can be inserted during the program's compilation phase at the location where a cache miss occurs in the main thread. When the main thread executes this prefetch instruction, it wakes up the auxiliary thread to prefetch data. Once prefetching is complete, the auxiliary thread can terminate and release all resources to the main thread. However, this method uses fixed prefetch instructions determined during compilation. During program execution, the actual instructions and data executed may differ from those compiled during compilation. Therefore, the fixed prefetch instructions determined at compile time are not entirely applicable to actual program execution. Furthermore, because the cache size is fixed, after data is prefetched from memory and loaded into the cache, the data originally stored in the cache may be lost (e.g., popped from the stack). This popped data may become the new cache miss data, meaning the cache miss data has changed. In this case, the auxiliary thread using the fixed prefetch instructions cannot prefetch the new cache miss data, resulting in poor prefetching performance. For example, the cache stores four data / instructions (e.g., A, B, C, D). A fixed prefetch instruction indicates that the data / instruction to be prefetched is, for example, E. When the auxiliary thread prefetches E into the cache, since the cache can only store four data / instructions, A is popped from the stack, and the data / instructions in the cache become B, C, D, and E. If the main thread needs to execute A later, A becomes the new cache miss data, and the fixed prefetch instruction cannot prefetch A at this time.

[0041] Furthermore, the main thread needs to wait for the auxiliary thread to fetch new cache miss data from memory before it can continue execution, resulting in significant latency for the main thread. Additionally, when the auxiliary thread uses a fixed prefetch instruction to prefetch old cache miss data, even if the old cache miss data is not the data the CPU is currently executing, the CPU will still execute the old cache miss data, causing redundant operations and increasing CPU overhead, further increasing latency.

[0042] This application proposes a data prefetching method for electronic devices. The main thread can create an auxiliary thread, and both the main thread and the auxiliary thread are bound to the same physical core in SMT mode. During the program compilation phase, the electronic device can use the compiler to determine the data in the main thread that will experience a cache miss and its location (referred to as the first cache miss information), and record / store this information in the compiler. This location can be the execution position of the cache-missed data in the main thread. During the program training phase, when the program runs for the first time, the main thread can determine the prefetching position based on the first cache miss information. This prefetching position can be the position where the cache-missed data is prefetched in the main thread. During the program optimization phase, when the main thread reaches the prefetching position, it can wake up the auxiliary thread. The auxiliary thread can obtain the second cache miss information from the current performance monitor unit (PMU) event register (referred to as the PMU register). This second cache miss information can include the data that experienced a cache miss during program execution, its location, and the prefetching position. If the second cache miss information matches the first cache miss information, the auxiliary thread prefetches the cache-missed data. If the second cache miss information does not match the first cache miss information, the auxiliary thread updates the first cache miss information in the compiler based on the second cache miss information (e.g., updating the first cache miss information to the second cache miss information) and prefetches data based on the updated cache miss information. Subsequently, the auxiliary thread can continue to prefetch data based on the cache miss information in the PMU register and the updated cache miss information in the compiler, and choose whether to update the cache miss information in the compiler according to the actual scenario. This achieves real-time dynamic adjustment of the cache miss information, that is, real-time dynamic adjustment of the data to be prefetched and the location of the data, so that the auxiliary thread can prefetch the required data every time, reducing the latency of the main thread executing the program. Furthermore, the main thread does not need to prefetch erroneous data according to fixed prefetch instructions, avoiding redundant operations by the main thread, thereby reducing CPU overhead and achieving good prefetching performance in different scenarios. Furthermore, binding the main thread and auxiliary threads to the same physical core can increase the size of the shared cache area, further improving prefetching efficiency.

[0043] In this application, the electronic device may be, but is not limited to, a mobile phone, tablet computer, handheld computer, desktop computer, laptop computer, ultra-mobile personal computer (UMPC), netbook, cellular phone, personal digital assistant (PDA), as well as smart home devices such as smart TVs and smart cameras, wearable devices such as smart bracelets, smartwatches, and smart glasses, extended reality (XR) devices such as augmented reality (AR), virtual reality (VR), and mixed reality (MR), in-vehicle devices, or smart city devices. The embodiments of this application do not impose any special restrictions on the specific type of electronic device.

[0044] The structure of the exemplary electronic device provided in the embodiments of this application will be described below.

[0045] Figure 2 An exemplary schematic diagram of the hardware structure of an electronic device 100 is shown.

[0046] like Figure 2 As shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0047] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0048] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0049] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0050] The processor 110 may also include a memory for storing instructions and data. In one embodiment, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can directly retrieve it from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0051] The charging management module 140 receives charging input from the charger. The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and supplies power to the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160, etc. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In another embodiment, the power management module 141 can also be located in the processor 110. In another embodiment, the power management module 141 and the charging management module 140 can also be located in the same device.

[0052] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0053] Antennas 1 and 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In another embodiment, the antenna can be used in conjunction with a tuning switch.

[0054] The mobile communication module 150 can provide wireless communication solutions for applications on the electronic device 100, including second-generation (2G), third-generation (3G), fourth-generation (4G), fifth-generation (5G), and sixth-generation (6G) mobile communication technologies. The mobile communication module 150 may include at least one filter, switch, power amplifier, low-noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 1. In one embodiment, at least some functional modules of the mobile communication module 150 may be housed in the processor 110. In another embodiment, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 may be housed in the same device.

[0055] The modem processor may include a modulator and a demodulator. The modulator modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs sound signals through audio devices (not limited to speaker 170A, receiver 170B, etc.) or displays images or videos through the display screen 194. In one embodiment, the modem processor may be a separate device. In another embodiment, the modem processor may be independent of the processor 110 and housed within the same device as the mobile communication module 150 or other functional modules.

[0056] The wireless communication module 160 can provide solutions for wireless communication applications on the electronic device 100, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0057] In one embodiment, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, enabling electronic device 100 to communicate with networks and other devices via wireless communication technology. The wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies, etc. The GNSS may include the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Navigation Satellite System (BDS), the Quasi-Zenith Satellite System (QZSS), and / or satellite-based augmentation systems (SBAS).

[0058] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0059] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In one embodiment, the electronic device 100 may include one or N display screens 194, where N is a positive integer greater than 1.

[0060] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0061] The ISP (Image Signal Processor) is used to process data fed back from the camera 193. For example, when taking a picture, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, and the camera's photosensitive element transmits the electrical signal to the ISP for processing, transforming it into an image visible to the naked eye. The ISP can also perform algorithmic optimization on image noise, brightness, and color. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In one implementation, the ISP can be integrated into the camera 193.

[0062] Camera 193 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In one embodiment, electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0063] The external storage interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0064] Internal memory 121 can be used to store computer executable program code, which includes instructions and data. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc. The data storage area may store data created during the use of electronic device 100 (such as audio data, phone book, etc.). In addition, internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. Processor 110 executes various functional applications and data processing of electronic device 100 by running instructions stored in internal memory 121 and / or instructions stored in memory disposed in the processor.

[0065] Electronic device 100 can implement audio functions through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0066] Audio module 170 is used to convert digital audio information into analog audio signal output, and also to convert analog audio input into digital audio signal. Audio module 170 can also be used for encoding and decoding audio signals.

[0067] The loudspeaker 170A, also known as a "loudspeaker", is used to convert audio electrical signals into sound signals.

[0068] The receiver 170B, also known as the "earpiece", is used to convert audio electrical signals into sound signals.

[0069] The microphone 170C, also known as a "microphone" or "voice transducer," is used to convert sound signals into electrical signals.

[0070] The 170D headphone jack is used to connect wired headphones.

[0071] Pressure sensor 180A is used to sense pressure signals and can convert the pressure signals into electrical signals. In one embodiment, pressure sensor 180A can be disposed on display screen 194. There are many types of pressure sensors 180A, such as resistive pressure sensors, inductive pressure sensors, and capacitive pressure sensors. A capacitive pressure sensor may include at least two parallel plates with conductive material. When force is applied to pressure sensor 180A, the capacitance between the electrodes changes. Electronic device 100 determines the pressure intensity based on the change in capacitance. When a touch operation is applied to display screen 194, electronic device 100 detects the intensity of the touch operation based on pressure sensor 180A. Electronic device 100 can also calculate the touch position based on the detection signal from pressure sensor 180A. In one embodiment, touch operations applied to the same touch position but with different touch operation intensities can correspond to different operation commands.

[0072] The gyroscope sensor 180B can be used to determine the motion attitude of the electronic device 100. In one embodiment, the angular velocity of the electronic device 100 about three axes (i.e., the x, y, and z axes) can be determined by the gyroscope sensor 180B.

[0073] The 180C barometric pressure sensor is used to measure barometric pressure.

[0074] The magnetic sensor 180D includes a Hall sensor. The electronic device 100 can use the magnetic sensor 180D to detect the opening and closing of the flip cover.

[0075] The accelerometer 180E can detect the magnitude of acceleration of electronic device 100 in various directions (generally three axes).

[0076] A distance sensor 180F is used to measure distance. Electronic device 100 can measure distance via infrared or laser. In one embodiment, when shooting a scene, electronic device 100 can utilize the distance sensor 180F to measure distance for rapid focusing.

[0077] The proximity sensor 180G may include, for example, a light-emitting diode (LED) and a light detector, such as a photodiode. The LED may be an infrared LED. The electronic device 100 emits infrared light outward through the LED. The electronic device 100 uses the photodiode to detect infrared reflected light from a nearby object. When sufficient reflected light is detected, it can be determined that an object is near the electronic device 100. When insufficient reflected light is detected, the electronic device 100 can determine that no object is near the electronic device 100.

[0078] The 180L ambient light sensor is used to detect ambient light intensity.

[0079] The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can utilize the characteristics of the collected fingerprints to achieve fingerprint unlocking, accessing application locks, taking photos with fingerprints, answering calls with fingerprints, etc.

[0080] The 180J temperature sensor is used to detect temperature.

[0081] Touch sensor 180K, also known as a "touch device," can be located on display screen 194. The touch sensor 180K and display screen 194 together form a touchscreen, also known as a "touchscreen." Touch sensor 180K detects touch operations applied to or near it. The touch sensor can transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through display screen 194. In other embodiments, touch sensor 180K may also be located on the surface of electronic device 100, in a different position than display screen 194.

[0082] The bone conduction sensor 180M can acquire vibration signals.

[0083] Buttons 190 include a power button, volume buttons, etc. Buttons 190 can be mechanical buttons or touch-sensitive buttons. Electronic device 100 can receive button input and generate key signal inputs related to user settings and function control of electronic device 100.

[0084] Motor 191 can generate vibration alerts. Indicator 192 can be an indicator light, used to indicate charging status, battery level changes, messages, missed calls, notifications, etc. SIM card interface 195 is used to connect a SIM card.

[0085] Figure 3 An exemplary schematic diagram of data prefetching is shown.

[0086] like Figure 3 As shown, during the compilation phase of a program, the compiler in an electronic device can determine the data in the main thread that will experience a cache miss and its location based on historical data, and record / store it in the compiler. The cache-missed data can include one or more items; for example, the cache-missed data may include data 1 and data 2. The location of each data item can be its execution position in the main thread. For ease of explanation, the right edge of the data is used as an example; for instance, the location of data 1 is the right edge of data 1 during the compilation phase, and the location of data 2 is the right edge of data 2 during the compilation phase. However, this is not limited to this; the location of the data can also be the left edge, the middle position, etc., and this application does not impose any limitations on this.

[0087] During the program's training phase, which can be understood as the program's first run / trial run, the main thread determines the prefetch location for each piece of data based on the cache miss data and its location recorded during the compilation phase. This prefetch location can be the position where the data is prefetched in the main thread. For example, the main thread can determine prefetch location 1 for data 1 based on data 1 (e.g., the size of data 1) and its location, and determine prefetch location 2 for data 2 based on data 2 (e.g., the size of data 2) and its location. Prefetch location 1 is located before the location of data 1, and prefetch location 2 is located before the location of data 2.

[0088] During the optimization phase of the program, which can be understood as the main thread notifying the auxiliary thread to prefetch data when it reaches prefetch position 1 during the actual program execution, the main thread can send an SEV instruction to the auxiliary thread to wake it up and enable it. The auxiliary thread can then obtain the cache miss data and its location recorded in the PMU register and determine whether the cache miss data and its location in the PMU register are consistent with the cache miss data and its location recorded by the compiler. In some examples, when they are consistent, see the example in the optimization phase (case 1). In this case, the cache miss data and its location recorded by the compiler remain unchanged, and the auxiliary thread can prefetch data 1 corresponding to prefetch position 1. After prefetching data 1 into the cache, the auxiliary thread can run the WFE instruction to terminate execution and switch to low-power mode. When the main thread reaches the location of data 1 (e.g., the right edge of data 1 in the compilation phase), data 1 has already been prefetched (e.g., data 1 was prefetched before the location of data 1), and the main thread can directly retrieve data 1 from the cache and execute it.

[0089] In other examples, when the two are inconsistent, the auxiliary thread can update the cache miss data and its location recorded by the compiler. For example, it can update the cache miss data and its location recorded by the compiler to the cache miss data and its location recorded by the PMU register. See the example in the optimization phase (case 2), such as updating data 1, data 2, the location of data 1, and the location of data 2 recorded by the compiler to data 1, data 3, the location of data 1, and the location of data 3 recorded by the PMU register. The auxiliary thread can perform data prefetching based on the updated cache miss data and its location (i.e., the locations of data 1, data 3, data 1, and data 3 mentioned above). For example, if the updated cache miss data still includes data 1, then data 1 corresponding to prefetch location 1 is prefetched. After the auxiliary thread prefetches data 1 into the cache, it can run the WFE instruction to terminate execution and switch to low-power mode. When the main thread executes to the location of data 1, data 1 has already been prefetched, and the main thread can directly retrieve data 1 from the cache and execute it.

[0090] In one implementation, after executing data 1 during the optimization phase (case 1), when the main thread executes to prefetch position 2, it can notify the auxiliary thread to perform data prefetching. For example, the main thread can send an SEV instruction to the auxiliary thread to wake up and enable the auxiliary thread. The auxiliary thread can then obtain the cache miss data and its position recorded in the current PMU register, and then determine whether the cache miss data and its position in the PMU register are consistent with the cache miss data and its position recorded by the compiler. For details, please refer to the description of prefetching data 1 above, which will not be repeated here.

[0091] In another implementation, after executing data 1 in the optimization phase (case 2), when the main thread executes to the prefetch position 3, it can notify the auxiliary thread to perform data prefetching. For details, please refer to the above description of prefetching data 1, which will not be repeated here.

[0092] The data prefetching method provided in the embodiments of this application will be introduced next.

[0093] Please see Figure 4 , Figure 4 This is a schematic flowchart of a data prefetching method provided in an embodiment of this application. This method can be applied to... Figure 2 The illustrated electronic device 100. This method can be applied to... Figure 3 The data prefetching shown. This method may include, but is not limited to, the following steps:

[0094] S101: The compiler determines the first data and its location (first information).

[0095] In one implementation, the first information (i.e. the first cache miss information mentioned above) may include first data and the location of the first data. The first data may be instructions and / or data that are predicted to be cache-invalidated when the main thread runs the first program before the first program runs for the first time. The first data may include one or more cache miss data, wherein the location of each data may be the execution location of the data in the main thread, and one cache miss data may correspond to one execution location.

[0096] In one implementation, during the compilation / development phase of the first program, the compiler can determine, based on historical data, the data that will be cached and miss when the main thread runs the first program (i.e., the first data), and the location of this data (i.e., the location of the first data), and record / store it (i.e., the first information) in the compiler.

[0097] S102: The main thread creates an auxiliary thread.

[0098] In one implementation, when the first program starts / begins to run, the main thread can create an auxiliary thread. The auxiliary thread can run a first instruction to put the auxiliary thread into a low-power mode, which can be understood as the auxiliary thread entering a sleep state. The first instruction is, for example, a Wait for Event (WFE) instruction.

[0099] In one implementation, the main thread can bind the main thread and the auxiliary thread to the same physical core in SMT mode. When the main thread moves from one physical core to another to execute instructions, the auxiliary thread also moves to another physical core. During the execution of the first program, the main thread and the auxiliary thread are always kept on the same physical core in SMT mode.

[0100] S103: The main thread determines the prefetch position of the first data based on the first information.

[0101] In one implementation, the prefetch location of the first data may include at least one prefetch location. A prefetch location may be the location in the main thread where a cache-missed data is prefetched. A cache-missed data may correspond to a prefetch location, and the prefetch location of each data is located before the location of that data.

[0102] In one implementation, during the training phase of the first program, which can be understood as the first time / trial run of the first program, the main thread can determine the prefetch position of the first data based on the first data determined during the compilation phase and the position of the first data. For example, based on the size of each cache miss data and the position of the data, the optimal position for prefetching each data is evaluated, and the optimal position is the prefetch position of the data.

[0103] S104: When the main thread reaches the first prefetch position, the main thread sends the first message to the auxiliary thread.

[0104] In one implementation, the first prefetch location can be the prefetch location of third data in the first information, where the third data is any one of at least one cache-missed data (i.e., the first data) in the first information. In another implementation, the first prefetch location can be any one of the aforementioned at least one prefetch location (i.e., the prefetch location of the first data).

[0105] In one implementation, the first message may include a prefetch address of the first data, which is the memory storage address corresponding to the first data in the first message. The prefetch address of the first data may include at least one prefetch address, wherein the first prefetch address may correspond to the aforementioned third data, and the first prefetch address may be any one of the prefetch addresses of the first data.

[0106] In one implementation, the first message may further include a second instruction, which can be used to wake up the auxiliary thread enable so that the auxiliary thread is in working mode. The second instruction is, for example, a Send Event instruction (SEV instruction).

[0107] In one implementation, during the optimization phase of the first program, which can be understood as the first program running (e.g., the first program running for the Nth time, where N is a positive integer greater than or equal to 2), when the main thread reaches the first prefetch position, it can send a first message to the auxiliary thread to wake up the auxiliary thread and enable data prefetching.

[0108] S105: The auxiliary thread obtains the second information based on the first message.

[0109] In one implementation, after receiving the first message, the auxiliary thread can obtain the second information (i.e. the aforementioned second cache miss information) in the register of the current PMU event (which may be called the PMU register). The PMU register can be used to store information about the current execution of the first program.

[0110] In one implementation, the second information may include second data and the location of the second data. The second data may be data that would cause a cache miss when the main thread runs the first program, as determined during the execution of the first program (e.g., the Nth execution of the first program). The second data may include one or more cache-missed data, wherein the location of each data may be the execution location of that data in the main thread, and one cache-missed data may correspond to one execution location. Optionally, the second information may further include the prefetch location and the prefetch address of the second data, wherein one cache-missed data in the second data may correspond to one prefetch location and one cache-missed data may correspond to one prefetch address.

[0111] S106: The auxiliary thread performs data prefetching based on the first and second information.

[0112] In one implementation, the auxiliary thread can determine whether the positions of the first data and the first data in the first information are consistent with the positions of the second data and the second data in the second information. If they are consistent, the auxiliary thread performs data prefetching based on the first message and the first information; if they are inconsistent, the auxiliary thread updates the first information recorded by the compiler and performs data prefetching based on the updated first information. For details, please refer to [link to relevant documentation]. Figure 5 The steps will not be detailed here.

[0113] In one implementation, after S106, the auxiliary thread can run a first instruction to put the auxiliary thread into a low-power mode, which can be understood as the auxiliary thread entering a sleep state.

[0114] In one implementation, after S106, the main thread can continue to execute the instructions and data corresponding to the first program. When it reaches the second prefetch position, the main thread can wake up the auxiliary thread again to enable data prefetching. The auxiliary thread can obtain the cache miss information in the current PMU register (e.g., including the cache miss data and the data location), and perform data prefetching based on the cache miss information in the PMU register and the updated cache miss information in the compiler (i.e., the updated first information). It can also choose whether to update the cache miss information in the compiler according to the actual scenario, so as to dynamically adjust the cache miss information in the compiler.

[0115] In one implementation, Figure 4Following the implementation shown, when the first program completes its Nth execution, it can execute for the (N+1)th time. At this point, steps similar to S104-S106 can be repeated. The difference is that the cache miss information recorded in the compiler may have been updated during the Nth execution (e.g., becoming updated cache miss information). The auxiliary thread can obtain the data and its location that will cause a cache miss (i.e., the cache miss information recorded in the current PMU register) determined during the (N+1)th execution of the first program, and perform data prefetching based on the current PMU register's cache miss information and the updated cache miss information to adjust the cache miss information in the compiler in real time. It can be understood that with each execution of the first program after the Nth time, the cache miss information in the compiler is continuously updated iteratively.

[0116] exist Figure 4 In the method shown, when the main thread reaches the prefetch location, it can wake up and enable the auxiliary thread. The auxiliary thread can prefetch data based on the cache miss information in the PMU register and the cache miss information in the compiler, and choose whether to update the cache miss information in the compiler according to the actual scenario. This achieves real-time dynamic adjustment of the cache miss information in the compiler, that is, real-time dynamic adjustment of the data to be prefetched and its location, ensuring that the auxiliary thread can prefetch the required data every time, reducing the latency of the main thread executing the first program. Furthermore, the main thread does not need to prefetch incorrect data according to fixed prefetch instructions, avoiding redundant operations and reducing CPU overhead, thus achieving good prefetching performance in different scenarios. Furthermore, the auxiliary thread can be bound to the same physical core as the main thread in SMT mode in real time, which can increase the size of the shared cache area and further improve prefetching efficiency. When data prefetching is required, the main thread can run a second instruction to wake up the auxiliary thread to enable and perform data prefetching. When data prefetching is not required, the auxiliary thread can run a first instruction to enter low-power mode. The first and second instructions can switch the running state of the auxiliary thread (e.g., working state or sleeping state) in a timely manner, reducing the latency of inter-thread interaction, reducing the load of the auxiliary thread, and thus reducing the CPU's computing power overhead.

[0117] Please see Figure 5 , Figure 5 This is a flowchart illustrating another data prefetching method provided in an embodiment of this application. This method can be applied to... Figure 2 The illustrated electronic device 100. This method can be applied to... Figure 3 The data prefetching shown. This method may include, but is not limited to, the following steps:

[0118] S201: The auxiliary thread determines whether the position of the first data in the first information is consistent with the position of the second data in the second information.

[0119] In one implementation, the auxiliary thread can determine whether the first data and the position of the first data in the first information are consistent with the positions of the second data and the second data in the second information. Specifically, it can determine whether the first data recorded by the compiler in the first information and the second data recorded by the PMU register in the second information are consistent with the positions of the first data in the first information and the second data in the second information. If they are consistent (i.e., the first data and the second data are the same, and the positions of the first data and the second data are the same), the auxiliary thread can execute S202. If they are inconsistent (i.e., the first data and the second data are different, and / or the positions of the first data and the second data are not the same), the auxiliary thread can execute S203-S204.

[0120] S202: The auxiliary thread performs data prefetching based on the first message and the first information.

[0121] In one implementation, when the first data and the second data are the same, and the positions of the first data and the second data are the same, the auxiliary thread can prefetch the third data corresponding to the first prefetch address based on the first prefetch address in the first message and the third data in the first message. For example, the auxiliary thread can determine the third data that needs to be prefetched based on the first prefetch position, then determine the first prefetch address in the first message corresponding to the third data, and then retrieve the third data corresponding to the first prefetch address from memory and load it into the cache. For example... Figure 3 The optimization stage shown (case 1) involves the prefetching of data 1 corresponding to prefetch position 1.

[0122] In one implementation, after S202, the auxiliary thread can run a first instruction to put the auxiliary thread into a low-power mode, which can be understood as the auxiliary thread entering a sleep state.

[0123] S203: The auxiliary thread updates the first information based on the second information and obtains the updated first information.

[0124] In one implementation, when the first data and the second data are different, and / or the positions of the first data and the second data are different, the auxiliary thread can update the first information recorded by the compiler based on the second information recorded in the PMU register, for example, updating the first information to the second information, and obtaining the updated first information, for example. Figure 3In the optimization phase shown (case 2), the updated first information may include the second data, the location of the second data, the prefetch location of the second data, and the prefetch address of the second data.

[0125] S204: The auxiliary thread performs data prefetching based on the updated first information.

[0126] In one implementation, S204 is an optional step.

[0127] In one implementation, the auxiliary thread can perform data prefetching based on the updated first information. In some examples, if the updated first information includes a first prefetch position, the auxiliary thread can determine the fourth data that needs to be prefetched based on the first prefetch position, and determine the second prefetch address in the second information corresponding to the fourth data. Then, it retrieves the fourth data corresponding to the second prefetch address from memory based on the second prefetch address and loads it into the cache. For example... Figure 3 The optimization phase shown (case 2) involves prefetching data 1 corresponding to prefetch position 1. In other examples, if the updated first information does not include the first prefetch position, the auxiliary thread does not perform data prefetching this time.

[0128] The order of S203 and S204 is not limited. The auxiliary thread can first prefetch data based on the second information, and then update the first information to obtain the updated first information.

[0129] In one implementation, after S204, the auxiliary thread can run a first instruction to put the auxiliary thread into a low-power mode, which can be understood as the auxiliary thread entering a sleep state.

[0130] exist Figure 5 In the method shown, the auxiliary thread can prefetch data based on the second information in the PMU register and the first information in the compiler, and choose whether to update the cache miss information in the compiler according to the actual scenario. This enables real-time dynamic adjustment of the cache miss information in the compiler, that is, real-time dynamic adjustment of the data to be prefetched and the location of the data, so that the auxiliary thread can prefetch the required data each time, reducing the latency of the main thread executing the first program.

[0131] The methods provided in the embodiments of this application can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DWD), or a semiconductor medium (e.g., solid-state drive). (disk, SSD, etc.). The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data prefetching method, characterized in that, Applied to electronic devices, the method includes: When the main thread executes the first program to the first prefetch position, the main thread sends a first message to the auxiliary thread. The first prefetch position is determined based on first information, which includes first data and the position of the first data. The first data is the data that the main thread needs to retrieve from memory before executing the first program, and the position of the first data is the execution position of the first data in the main thread. The auxiliary thread obtains second information based on the first message. The second information includes second data and the location of the second data. The second data is the data that the main thread needs to retrieve from the memory based on the first program. The location of the second data is the execution location of the second data in the main thread. The auxiliary thread prefetches data from the first program based on the first information and the second information.

2. The method as described in claim 1, characterized in that, The auxiliary thread prefetches data from the first program based on the first information and the second information, including: When the first data and the second data are the same, and the positions of the first data and the second data are the same, the auxiliary thread prefetches the data of the first program according to the first message and the first information; When the first data and the second data are different, and / or the positions of the first data and the second data are different, the auxiliary thread updates the first information according to the second information, and prefetches the data of the first program according to the updated first information.

3. The method as described in claim 2, characterized in that, The first message also includes a first prefetch address, the first prefetch location being the prefetch location of the third data in the first information, the third data being any one of the first data, the third data corresponding to the first prefetch address, and the auxiliary thread prefetching data of the first program according to the first message and the first information, including: The auxiliary thread retrieves the third data from the memory based on the first prefetch address and loads the third data into the cache.

4. The method as described in claim 2, characterized in that, The auxiliary thread updates the first information based on the second information, and prefetches data from the first program based on the updated first information, including: The auxiliary thread updates the first information to the second information to obtain the updated first information, which includes the second data, the position of the second data, the prefetch position of the second data, and the prefetch address of the second data. If the updated first information includes the first prefetch position, the auxiliary thread retrieves the fourth data from the memory according to the second prefetch address and loads the fourth data into the cache. The first prefetch position is the prefetch position of the fourth data in the updated first information, the fourth data is any one of the second data, and the fourth data corresponds to the second prefetch address.

5. The method as described in claim 4, characterized in that, The method further includes: If the updated first information does not include the first prefetch position, the auxiliary thread executes a first instruction, which is used to switch the auxiliary thread to a low-power mode.

6. The method according to any one of claims 1-5, characterized in that, Before the main thread sends the first message to the auxiliary thread, the auxiliary thread is in a low-power mode. The first message includes a second instruction, which is used for the auxiliary thread to switch from the low-power mode to the working mode. After the auxiliary thread prefetches data from the first program based on the first information and the second information, the method further includes: The auxiliary thread executes a first instruction, which is used to switch the auxiliary thread from the working mode to the low-power mode.

7. The method as described in claim 2 or 4, characterized in that, The auxiliary thread updates the first information based on the second information, and after prefetching the data of the first program based on the updated first information, the method further includes: The auxiliary thread executes a first instruction, which is used to switch the auxiliary thread to a low-power mode. When the main thread executes the first program to the second prefetch position, the main thread sends a second message to the auxiliary thread. The second prefetch position is determined based on the updated first information. The second message includes a second instruction, which is used for the auxiliary thread to switch from the low-power mode to the working mode. The auxiliary thread obtains third information based on the second message. The third information includes third data and the location of the third data. The third data is the data that the main thread needs to obtain from the memory based on the first program. The location of the third data is the execution location of the third data in the main thread. The auxiliary thread prefetches data from the first program based on the third information and the updated first information.

8. The method according to any one of claims 1-7, characterized in that, The auxiliary thread is created when the main thread starts executing the first program. During the execution of the first program by the main thread, the auxiliary thread and the main thread are on the same physical core in the synchronous multithreaded SMT mode.

9. An electronic device, characterized in that, It includes a transceiver, a processor, and a memory, the memory being used to store a computer program, and the processor calling the computer program to perform the method as described in any one of claims 1-8.

10. A computer storage medium, characterized in that, The computer storage medium stores a computer program, which, when executed by a processor, implements the method as described in any one of claims 1-8.

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