Quantum error mitigation method, fitting parameter determination method and related device

Abstract

The embodiment of the invention discloses a quantum error mitigation method, a fitting parameter determination method and a related device, and relates to the technical field of quantum computing. A conjugate circuit corresponding to an original quantum circuit is determined, and the overlap ratio of the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2; the conjugate circuit is easier to simulate on a classic computer, so that the simulation result of conjugation on the classic computer can be efficiently determined, and the fitting parameters of the conjugate circuit can be determined based on the simulation result of the conjugate circuit on the classic computer and the operation result of the conjugate circuit on the quantum chip. As the overlap ratio of the conjugate circuit and the original quantum circuit is high, the fitting parameter can also be used for correcting the operation result of the original quantum circuit.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum error mitigation method, a fitting parameter determination method, and related apparatus. Background Technology

[0002] Quantum error mitigation is a post-processing method that can be understood as using software to compensate for noise generated during computation. It verifies quantum computation results with a small number of qubits through classical simulation, or obtains theoretical values ​​using classically easily simulated circuits, mitigating errors in larger or more difficult-to-simulate systems with a certain degree of confidence. Quantum error mitigation is another method for achieving precise quantum computation. Because it does not require a large number of qubits, it is suitable for the current era of noisy intermediate-scale quantum (NISQ). Quantum algorithms, represented by variational quantum solvers, choose quantum error mitigation techniques to suppress errors rather than correct them. This technique allows for acceptable computational accuracy with only moderate additional resources and has made some progress in both theory and experiment. Summary of the Invention

[0003] This application provides a quantum error mitigation method, a fitting parameter determination method, and related apparatus. By designing a conjugate structural framework and then filling in conjugate angle gates based on this framework, the operating results of the original quantum circuit can be corrected using the fitting parameters of the conjugate circuit. This approach reduces simulation difficulty and facilitates more efficient determination of fitting parameters, thereby enabling more efficient quantum error mitigation.

[0004] The first aspect of this application provides a method for determining fitting parameters for quantum error mitigation, including:

[0005] Determine the conjugate circuit corresponding to the original quantum circuit; wherein the degree of overlap between the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2;

[0006] Based on the simulation results of the above conjugate circuit on a classical computer and the operation results of the above conjugate circuit on a quantum chip, the fitting parameters of the above conjugate circuit are determined; wherein, the above fitting parameters are used to correct the operation results of the above original quantum circuit.

[0007] Optionally, the above-described conjugate circuit corresponding to the original quantum circuit includes:

[0008] Based on the timing of operation, the original quantum circuit can be divided into a front circuit and a back circuit, wherein the difference in the number of logic gates between the front circuit and the back circuit is less than a preset threshold.

[0009] The conjugate circuit is obtained by updating the logic gates in the first part of the circuit or updating the logic gates in the second part of the circuit.

[0010] Optionally, the logic gates in the circuit before or after the update are used to obtain the conjugate circuit, including:

[0011] Determine the first proportion of logic gates in the aforementioned first part of the circuit that belong to the preset type of logic gates, and determine the second proportion of logic gates in the aforementioned second part of the circuit that belong to the preset type of logic gates.

[0012] Based on the first proportion and the second proportion mentioned above, the logic gates in the circuit before the update or the logic gates in the circuit after the update are determined.

[0013] Optionally, the aforementioned preset type logic gates include at least Clifford gates, and the determination of updating the logic gates in the preceding part of the circuit or updating the logic gates in the following part of the circuit based on the first proportion and the second proportion includes:

[0014] In response to the detection that the first proportion is greater than the second proportion, the logic gates in the updated part of the circuit are determined, and the conjugate circuit is obtained.

[0015] In response to detecting that the first proportion is less than or equal to the second proportion, the logic gates in the previous part of the circuit are determined to be updated, and the conjugate circuit is obtained.

[0016] Optionally, the original quantum circuit includes the QAOA quantum circuit.

[0017] A second aspect of this application provides a quantum error mitigation method, including: obtaining the original quantum circuit;

[0018] Initial results were obtained by running the original quantum circuit described above using a quantum chip.

[0019] The initial result is corrected using the fitting parameters obtained by any of the methods described in the first aspect above, to obtain the target result.

[0020] A third aspect of this application provides a fitting parameter determination apparatus for quantum error mitigation, comprising:

[0021] A determining unit is used to determine the conjugate circuit corresponding to the original quantum circuit; wherein the degree of overlap between the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2;

[0022] The parameter fitting unit is used to determine the fitting parameters of the conjugate circuit based on the simulation results of the conjugate circuit on a classical computer and the operation results of the conjugate circuit on a quantum chip; wherein the fitting parameters are used to correct the operation results of the original quantum circuit.

[0023] A fourth aspect of this application provides a quantum error mitigation device, comprising:

[0024] Acquisition unit, used to acquire the original quantum circuit;

[0025] The execution unit is used to run the original quantum circuit described above using the quantum chip to obtain initial results;

[0026] The correction unit is used to correct the initial result using the fitting parameters obtained by any of the methods described in the first aspect above, so as to obtain the target result.

[0027] A fifth aspect of this application provides an electronic device, including: a processor and a memory;

[0028] The processor is connected to a memory, wherein the memory is used to store computer programs, and the processor is used to invoke the computer programs to execute the methods as described in the first aspect of the embodiments of this application, or to execute the methods as described in the second aspect of the embodiments of this application.

[0029] A sixth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the first aspect of this application, or perform the method as described in the second aspect of this application.

[0030] This application embodiment determines a conjugate circuit corresponding to the original quantum circuit. The conjugate circuit and the original quantum circuit have an overlap of greater than or equal to 1 / 2. Since the conjugate circuit is easier to simulate on a classical computer, the simulation results of the conjugate circuit on the classical computer can be determined efficiently. Based on the simulation results of the conjugate circuit on the classical computer and the operation results of the conjugate circuit on the quantum chip, the fitting parameters of the conjugate circuit can be determined. Since the conjugate circuit and the original quantum circuit have a high overlap, the fitting parameters can also be used to correct the operation results of the original quantum circuit.

[0031] This approach not only efficiently determines the fitting parameters but is also applicable to most variable quantum circuits, thus improving the applicability of the fitting parameter determination method. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 An example system block diagram of a fitting parameter determination method for quantum error mitigation provided in one embodiment of this application is shown;

[0034] Figure 2 A flowchart illustrating a fitting parameter determination method for quantum error mitigation provided in one embodiment of this application is shown.

[0035] Figure 3 A schematic diagram of a conjugate circuit operating on four qubits is shown in one embodiment of this application;

[0036] Figure 4A A schematic diagram of a non-conjugate circuit provided in one embodiment of this application is shown. Figure 4B A schematic diagram illustrating the conversion of a non-conjugate circuit to a conjugate circuit according to an embodiment of this application is shown;

[0037] Figure 5 A schematic diagram of a quantum circuit for a possible conjugate circuit provided in one embodiment of this application is shown;

[0038] Figure 6 A flowchart illustrating a quantum error mitigation method provided in one embodiment of this application is shown;

[0039] Figure 7 This invention provides a schematic diagram of the structure of a fitting parameter determination device for quantum error mitigation according to an embodiment of the present application.

[0040] Figure 8 A schematic diagram of the structure of a quantum error mitigation device provided in one embodiment of this application is shown;

[0041] Figure 9 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0043] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, then there are 2... n Possible classical states, and represent one state at a time.

[0044] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A single qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, then 2^n qubits can represent n bits of data. n A quantum state can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement, where the state of one qubit (whether 1, 0, or both) depends on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0045] Please refer to Figure 1 This illustrates an example system block diagram of a fitting parameter determination method for quantum error mitigation provided in one embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1 In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0046] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1In the illustrated example embodiment, the quantum system 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. The quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0047] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface having interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical computer 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0048] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0049] The classical computer 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide the quantum system 110 with various control signals, instructions, and data encoded in classical bits. Further, quantum states measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, the classical computer 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing the preparation module 121 to perform quantum computation using data stored in the data storage module 122 as part of the construction and computation. The data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as an application programming interface (API) function call, or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and can be instantiated by components of interface 112 to execute, enabling quantum operations of quantum gates to be performed on quantum chip 113.

[0050] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0051] As can be seen from the above background information, quantum computers often fail to produce theoretically optimal solutions due to noise, decoherence, and other factors. Error mitigation schemes can effectively reduce the impact of these problems. Currently, the VQA (Variational Quantum Algorithms) algorithm is considered to be an effective algorithm implemented on quantum computers in the near future. The purpose of quantum error mitigation is to optimize the expectation of the Hamiltonian in the algorithm and find its accurate value (i.e., as close as possible to the theoretical value in the noise-free case).

[0052] Based on this, this disclosure provides a method for determining fitting parameters for quantum error mitigation. After obtaining the original quantum circuit, a local update can be performed on the original quantum circuit to obtain a conjugate circuit while retaining at least half of the original structure. Since the conjugate circuit can be easily simulated on a classical computer, the fitting parameters of the conjugate circuit can be determined relatively efficiently. Furthermore, because the conjugate circuit has a high degree of overlap with the original quantum circuit, the fitting parameters of the conjugate circuit can be used to correct the operating results of the original quantum circuit. Therefore, the method disclosed in this disclosure can more efficiently determine the fitting parameters for the original quantum circuit, and this method of determining fitting parameters has a wide range of applications, applicable to most variable quantum circuits.

[0053] Please refer to Figure 2 This illustration shows a flowchart of a method for determining fitting parameters for quantum error mitigation according to an embodiment of this application. The method can be applied to computer devices, which refer to electronic devices with data computing and processing capabilities. The method may include the following steps:

[0054] Step 201: Determine the conjugate circuit corresponding to the original quantum circuit.

[0055] Here, the overlap between the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2.

[0056] As an example, a conjugate circuit can be obtained by updating the original quantum circuit. For instance, a portion of the original quantum circuit can be updated to obtain the conjugate circuit. During the update process, at least half of the original quantum circuit's structure must be retained to ensure that the overlap between the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2.

[0057] As an example, a conjugate circuit can consist of two parts; for instance, if part of the quantum circuit U is a unitary gate, then the other quantum circuit... This can be the inverse operation of the quantum circuit U; that is, the conjugate circuit can usually be formed by U and... Composition, and can satisfy (Identity operation).

[0058] Therefore, when simulating this circuit using a classical computer, it is only necessary to store the matrix representation of U. This can be quickly obtained through the conjugate transpose without independent computation. Therefore, this method helps classical computers to perform efficient simulations of quantum circuits.

[0059] As an example, a quantum circuit includes logic gates and the timing relationship of the logic gates. That is, the overlap between the original circuit and the conjugate circuit is greater than or equal to 1 / 2, which can be understood as: at least half of the conjugate circuit is the same as the original quantum circuit. The sameness here can include the same logic gates and the same timing of the logic gates.

[0060] Step 202: Based on the simulation results of the conjugate circuit on a classical computer and the operation results of the conjugate circuit on a quantum chip, determine the fitting parameters of the conjugate circuit.

[0061] Here, the fitting parameters can be used to correct the results of the original quantum circuit's operation.

[0062] It should be understood that in practical applications, there are many ways to determine the fitting parameters based on the differences between simulation results and actual operating results. For the sake of brevity, these methods will not be elaborated here; simply select the appropriate method based on the actual situation. For example, the least squares method or gradient descent method can be used to determine the fitting parameters.

[0063] As an example, both simulation results and running results can indicate Hamilton's expectation. That is, simulation results can be used to indicate the theoretical value of Hamilton's expectation, while running results can be used to indicate the actual value of Hamilton's expectation. Fitting parameters can be used to indicate how to correct the actual value to a reasonable range from the theoretical value.

[0064] It should be understood that since the fitting parameters are determined by the conjugate circuit, and the conjugate circuit and the original quantum circuit have a high degree of overlap, the fitting parameters of the conjugate circuit and the original quantum circuit will be quite close. Therefore, the fitting parameters corresponding to the conjugate circuit can be used to correct the operating results of the original quantum circuit. Furthermore, since the conjugate circuit is easier to simulate on a classical computer than the original quantum circuit, this approach also helps to more efficiently determine the fitting parameters of the original quantum circuit, thereby enabling more efficient quantum error mitigation.

[0065] As can be seen, in this disclosure, by determining the conjugate circuit corresponding to the original quantum circuit, and the degree of overlap between the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2, and the conjugate circuit is easier to simulate on a classical computer, the simulation results of the conjugate circuit on the classical computer can be determined efficiently. Based on the simulation results of the conjugate circuit on the classical computer and the running results of the conjugate circuit on the quantum chip, the fitting parameters of the conjugate circuit can be determined. Since the degree of overlap between the conjugate circuit and the original quantum circuit is high, the fitting parameters can also be used to correct the running results of the original quantum circuit.

[0066] This approach not only efficiently determines the fitting parameters but is also applicable to most variable quantum circuits, thus improving the applicability of the fitting parameter determination method.

[0067] It should be understood that the original quantum circuit can be a variable quantum circuit, and the variable quantum circuit is a generalized quantum circuit framework. Ansatz (parameterized quantum circuit) can indicate the specific structural design of the variable quantum circuit. That is, Ansatz can be understood as the carrier of the variable quantum circuit. Therefore, updating the original quantum circuit can be understood as changing the parameters in Ansatz.

[0068] In some embodiments, step 201, "determining the conjugate circuit corresponding to the original quantum circuit," may specifically include:

[0069] The original quantum circuit is divided into a front part and a back part based on the timing of operation; the logic gates in the front part or the logic gates in the back part are updated to obtain the above-mentioned conjugate circuit.

[0070] Here, the difference in the number of logic gates between the front-end circuit and the back-end circuit is less than a preset threshold.

[0071] As an example, the first and second halves can be determined based on the original quantum circuit. Since the conjugate circuit is obtained by updating the original quantum circuit, the original quantum circuit can be divided into two parts. One part can be updated while the other part is retained. This allows for adjustments to only a local part of the original quantum circuit to obtain the conjugate circuit. The conjugate circuit obtained in this way retains at least half of the structure of the original quantum circuit, thus ensuring that the overlap with the original quantum circuit is greater than or equal to 1 / 2.

[0072] It should be understood that "update" here can be interpreted as operations such as adding, deleting, or replacing logic gates.

[0073] As an example, the original quantum circuit is divided into a front part and a back part based on the timing of action. This makes it possible to construct a conjugate circuit by updating only the front part or only the back part.

[0074] As an example, the logic gates in the first part of the circuit and the logic gates in the second part of the circuit may be different. Therefore, the logic gates in the first part of the circuit and the logic gates in the second part of the circuit may be different. For example, if the first part of the circuit needs to add a new RY gate, the second part of the circuit needs to add an RZ gate and an H gate.

[0075] Based on this, the aforementioned "updating the logic gates in the previous part of the circuit or updating the logic gates in the subsequent part of the circuit to obtain a conjugate circuit" can specifically include:

[0076] Determine the first proportion of logic gates in the first part of the circuit that belong to the preset type of logic gates, and determine the second proportion of logic gates in the second part of the circuit that belong to the preset type of logic gates;

[0077] Based on the first proportion and the second proportion, determine the logic gates in the circuit before the update or the logic gates in the circuit after the update.

[0078] As an example, since the main types of logic gates in the front part of the circuit are different from those in the back part of the circuit, and different types of logic gates have different simulation difficulties on classical computers, for example, the combination of multiple single-qubit rotating gates or multi-qubit gates are difficult to simulate on classical computers, while Clifford gates are easy to simulate on classical computers.

[0079] Based on this, the preset type logic gate is used to indicate the type of quantum logic gate that is easy to simulate on a classical computer.

[0080] As an example, the first percentage of logic gates in the front part of the circuit that belong to a preset type of logic gate can reflect the ease or difficulty of simulating the front part of the circuit on a classic computer, and correspondingly, the second percentage can reflect the ease or difficulty of simulating the rear part of the circuit on a classic computer.

[0081] In this disclosure, the logic gates in the circuit before or after the update are determined based on the first and second proportions. This helps to enable the obtained conjugate circuit to be simulated more efficiently on a classical computer and helps to reduce the hardware resources required during the simulation process.

[0082] In some embodiments, the preset type logic gate may include at least Clifford gates, and, based on a first proportion and a second proportion, the logic gates in the pre-updated portion of the circuit or the post-updated portion of the circuit may be determined, specifically including:

[0083] In response to the detection that the first proportion is greater than the second proportion, the logic gates in the updated part of the circuit are determined, and the conjugate circuit is obtained.

[0084] In response to detecting that the first proportion is less than or equal to the second proportion, the logic gates in the previous part of the circuit are determined to be updated, and the above conjugate circuit is obtained.

[0085] As an example, when the first proportion is greater than the second proportion, it can be characterized that most of the front part of the circuit is easily simulated by a classical computer. Therefore, the logic gates in the back part of the circuit can be updated to obtain a conjugate circuit. Conversely, when the first proportion is less than or equal to the second proportion, it can be characterized that the back part of the circuit is easily simulated by a classical computer. Therefore, the logic gates in the front part of the circuit can be updated to obtain a conjugate circuit.

[0086] Of course, the logic gates of the preset type can be reasonably adjusted according to the actual situation. For example, the preset type of logic gate can also include single-qubit rotation gates.

[0087] As can be seen, in this disclosure, the method of updating the original quantum circuit to obtain the conjugate circuit can be flexibly selected so that the updated conjugate circuit can be simulated by a classical computer more accurately and efficiently.

[0088] In some embodiments, the original quantum circuit may include a QAOA quantum circuit.

[0089] As an example, the QAOA quantum circuit, also known as the quantum approximation optimization algorithm quantum circuit, has a low-depth and symmetric evolution structure. Therefore, the QAOA quantum circuit can be easily converted into a conjugate circuit, thus giving the QAOA quantum circuit a more significant advantage when using the method disclosed herein.

[0090] To better understand the ideas in this disclosure, one can combine them with... Figure 3 and Figure 4A and 4B To explain, Figure 3 This can be understood as a schematic diagram of a conjugate circuit operating on 4 qubits. When {θ, θ′} are randomly generated, this circuit is a normal Ansatz circuit. However, when θ + θ′ = 0, the theoretical result of this circuit is |0> n State. If we want to learn the expectation of a certain Hamiltonian H and the path is based on random angles. Then the following circuit can be constructed:

[0091] First, run on a real chip The corresponding angle, then simulated. Angle, where angle α = {α1, α2, ..., α n The first n angles of the quantum circuit (0, ..., 0) are randomly generated. Theoretically, this circuit is equivalent to executing a single-gate operation, which is easily simulated on a classical computer. On a real chip, it executes the same circuit and gates as the original ansatz. Compared to the actual angles that need to be calculated, at least the first n angles are completely identical to the quantum circuit structure; similarly, it can be simulated and run. The angle, which is equivalent to executing a single gate at the end of the quantum circuit, and all subsequent angles are the same as the target value, thus realizing a circuit that is easily simulated classically. In this way, the target angle can be approximated by the angles around the target value.

[0092] For example, suppose our target ansatz can be divided into two parts U1(θ1) and U2(θ2), where θ1 and θ2 represent the set of midpoint angles of the two line segments. First, we transform it into... Here, V(α) represents a single-angle gate, allowing for classical simulation while ensuring consistency between the quantum circuit and the original circuit. Similarly, it can be modified to... And other easily simulated scenarios. By obtaining the actual chip's circuit results and theoretical results, and by fitting the interval between the actual and theoretical solutions, the theoretical values ​​of U1(θ1) and U2(θ2) on the actual chip can be fitted using the same curve.

[0093] Further integration Figure 4A and Figure 4B To explain, Figure 4A A schematic diagram of a non-conjugate line is disclosed. This can be converted into a conjugate line, and then error mitigation can be performed as described above. Figure 4A As can be seen, the only obstacle preventing it from becoming a conjugate circuit is the blue section; more precisely, it's the double gate within the red dashed box that makes it difficult to become a conjugate gate. However, an additional layer of circuitry can be added to convert it into a conjugate circuit. This can be achieved by replacing the CZ double gate with two CZ gates, sandwiching an angle gate in between. Structurally, this is similar to the target circuit and allows for the cancellation of conjugate circuitry by controlling the angle, thus achieving the theoretical solution. For example... Figure 4B This can be understood as a possible schematic diagram of an updated circuit structure, derived from... Figure 4B It is evident that after the local update, the overall circuit structure conforms to the target structure, that is, it is conjugate.

[0094] Further reading Figure 5 , Figure 5 This can be understood as a schematic diagram of a possible conjugated quantum circuit, derived from... Figure 5 As can be seen, the method disclosed herein can generally be directly applied to QAOA quantum circuits because QAOA quantum circuits are also symmetrical layered circuit structures, and therefore, they can be highly compatible with the method disclosed herein.

[0095] In other words, the concept of this disclosure lies in designing a conjugate structural framework and then filling in conjugate angle gates based on this framework. This results in the learning circuit and the target circuit having the same framework, and the simulation cost of the learning circuit is extremely low. Furthermore, to further approximate the target circuit, half of the conjugate gates used in the learning circuit are the same as those in the target circuit. This results in half of the angle gates being identical to those in the target circuit, and the overall circuit framework being completely identical to the target circuit. This allows the fitting parameters corresponding to the conjugate circuit to be applied to the original quantum circuit.

[0096] Please refer to Figure 6 This illustration shows a flowchart of a quantum error mitigation method provided in one embodiment of this application. The method can be applied to computer devices, which refer to electronic devices capable of data computation and processing. The method may include the following steps:

[0097] Step 601: Obtain the original quantum circuit;

[0098] Step 602: Use the quantum chip to run the original quantum circuit to obtain initial results;

[0099] Step 603: Use the fitting parameters obtained by the above fitting parameter determination method to correct the initial result and obtain the target result.

[0100] As an example, the objective result of this disclosure can indicate the effect of the quantum chip on the original quantum circuit in the absence of noise.

[0101] As can be seen, the method disclosed herein obtains the fitting parameters of the conjugate circuit corresponding to the original quantum circuit and corrects the operating results of the original quantum circuit, which has a wider range of applications.

[0102] Figure 7 A schematic diagram of a fitting parameter determination device for quantum error mitigation according to an embodiment of this application is shown. The device includes:

[0103] The determining unit 701 is used to determine the conjugate circuit corresponding to the original quantum circuit; wherein the overlap between the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2.

[0104] The parameter fitting unit 702 is used to determine the fitting parameters of the conjugate circuit based on the simulation results of the conjugate circuit on a classical computer and the operation results of the conjugate circuit on a quantum chip; wherein the fitting parameters are used to correct the operation results of the original quantum circuit.

[0105] In some embodiments, the determining unit 701 is further configured to:

[0106] Based on the timing of operation, the original quantum circuit can be divided into a front circuit and a back circuit, wherein the difference in the number of logic gates between the front circuit and the back circuit is less than a preset threshold.

[0107] The conjugate circuit is obtained by updating the logic gates in the first part of the circuit or updating the logic gates in the second part of the circuit.

[0108] In some embodiments, the determining unit 701 is further configured to:

[0109] Determine the first proportion of logic gates in the aforementioned first part of the circuit that belong to the preset type of logic gates, and determine the second proportion of logic gates in the aforementioned second part of the circuit that belong to the preset type of logic gates.

[0110] Based on the first proportion and the second proportion mentioned above, the logic gates in the circuit before the update or the logic gates in the circuit after the update are determined.

[0111] In some embodiments, the aforementioned preset type logic gate includes at least a Clifford gate, and the aforementioned determining unit 701 is further configured to:

[0112] In response to the detection that the first proportion is greater than the second proportion, the logic gates in the updated part of the circuit are determined, and the conjugate circuit is obtained.

[0113] In response to detecting that the first proportion is less than or equal to the second proportion, the logic gates in the previous part of the circuit are determined to be updated, and the conjugate circuit is obtained.

[0114] In some embodiments, the original quantum circuit includes a QAOA quantum circuit.

[0115] Figure 8 A schematic diagram of a quantum error mitigation device according to an embodiment of this application is shown. The device includes:

[0116] Acquisition unit 801 is used to acquire the original quantum circuit;

[0117] The operation unit 802 is used to run the original quantum circuit described above using a quantum chip to obtain initial results;

[0118] The correction unit 803 is used to correct the initial result using the fitting parameters obtained by the fitting parameter determination method described above, so as to obtain the target result.

[0119] Figure 9 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the functions of the computer system for determining fitting parameters or a method for determining fitting parameters for quantum error mitigation in any of the above embodiments.

[0120] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system for determining fitting parameters or a method for determining fitting parameters for quantum error mitigation in any of the above embodiments.

[0121] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system for determining fitting parameters or fitting parameter determination methods for quantum error mitigation in any of the above embodiments.

[0122] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0123] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0124] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0125] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0126] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0127] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0128] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0129] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0131] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0132] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0133] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for determining fitting parameters for quantum error mitigation, characterized in that, include: Determine the conjugate circuit corresponding to the original quantum circuit; wherein the degree of overlap between the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2; Based on the simulation results of the conjugate circuit on a classical computer and the operation results of the conjugate circuit on a quantum chip, the fitting parameters of the conjugate circuit are determined; wherein, the fitting parameters are used to correct the operation results of the original quantum circuit.

2. The method according to claim 1, characterized in that, The determination of the conjugate circuit corresponding to the original quantum circuit includes: The original quantum circuit can be divided into a front part circuit and a back part circuit according to the timing of operation, wherein the difference in the number of logic gates between the front part circuit and the back part circuit is less than a preset threshold number. The conjugate circuit is obtained by updating the logic gates in the first part of the circuit or updating the logic gates in the second part of the circuit.

3. The method according to claim 2, characterized in that, The logic gates in the pre-update portion of the circuit or the logic gates in the post-update portion of the circuit are used to obtain the conjugate circuit, including: Determine a first percentage of logic gates in the front part of the circuit that belong to a preset type of logic gate, and determine a second percentage of logic gates in the rear part of the circuit that belong to the preset type of logic gate; Based on the first proportion and the second proportion, the logic gates in the circuit before the update or the logic gates in the circuit after the update are determined.

4. The method according to claim 3, characterized in that, The preset type of logic gate includes at least Clifford gates, and the step of determining whether to update the logic gates in the front part of the circuit or update the logic gates in the rear part of the circuit based on the first proportion and the second proportion includes: In response to detecting that the first proportion is greater than the second proportion, the logic gates in the updated portion of the circuit are determined, and the conjugate circuit is obtained; In response to detecting that the first proportion is less than or equal to the second proportion, the logic gates in the preceding part of the circuit are determined to be updated, and the conjugate circuit is obtained.

5. The method according to claim 1, characterized in that, Primitive quantum circuits include QAOA quantum circuits.

6. A quantum error mitigation method, characterized in that, include: Obtain the original quantum circuit; Initial results were obtained by running the original quantum circuit using a quantum chip. The initial result is corrected using the fitting parameters obtained by any one of the methods described in claims 1-5 to obtain the target result.

7. A fitting parameter determination device for quantum error mitigation, characterized in that, include: A determining unit is used to determine a conjugate circuit corresponding to the original quantum circuit; wherein the degree of overlap between the conjugate circuit and the original quantum circuit is greater than or equal to 1 / 2; A parameter fitting unit is used to determine the fitting parameters of the conjugate circuit based on the simulation results of the conjugate circuit on a classical computer and the operation results of the conjugate circuit on a quantum chip; wherein the fitting parameters are used to correct the operation results of the original quantum circuit.

8. A quantum error mitigation device, characterized in that, include: Acquisition unit, used to acquire the original quantum circuit; The operation unit is used to run the original quantum circuit using the quantum chip to obtain initial results; The correction unit is used to correct the initial result using the fitting parameters obtained by any one of the methods described in claims 1-5, so as to obtain the target result.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-5, or to perform the method as described in claim 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-5, or perform the method as described in claim 6.

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