Quantum line compiling method based on neutral atom hardware topology and related device

Abstract

The invention discloses a quantum circuit compiling method based on neutral atom hardware topology and a related device, and belongs to the technical field of quantum computing, and the method comprises the following steps: obtaining characteristic parameters of a quantum circuit to be compiled; forming a feature vector by the obtained feature parameters of the quantum circuit, and inputting the feature vector into a pre-trained classical neural network to determine a neutral atom hardware topological structure to be subjected to mapping operation; wherein the pre-trained classical neural network is used for determining a neutral atom hardware topological structure of the quantum circuit to be compiled based on the characteristic parameters of the quantum circuit; executing mapping operation on the quantum circuit based on the neutral atom hardware topological structure; according to the quantum circuit compiling method of the neutral atom hardware topological structure, the diversified requirements of different application fields are met, the new method can provide more technical adaptation routes for a future multi-back-end quantum computing framework, and the robustness and flexibility of a quantum computing system are improved.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a quantum circuit compilation method and related apparatus based on neutral atom hardware topology. Background Technology

[0002] In the field of quantum computing, different types of quantum chips each have their unique advantages, such as superconducting quantum chips, neutral atom quantum chips, and topological qubits. Currently, mainstream superconducting quantum chips perform well in terms of scalability and control precision, but relying on a single technology carries certain risks. If a particular technology encounters an insurmountable technical bottleneck, the development of the entire quantum computing system may be hindered. By combining the advantages of different technologies, more powerful quantum computing capabilities can be achieved.

[0003] Therefore, a quantum circuit compilation method based on neutral atom hardware topology is proposed to meet the diverse needs of different application fields. The new method can provide more technical adaptation routes for future multi-backend quantum computing frameworks, thereby improving the robustness and flexibility of quantum computing systems. Summary of the Invention

[0004] The purpose of this invention is to provide a quantum circuit compilation method and related device based on neutral atom hardware topology, which aims to meet the diverse needs of different application fields and provide more technical adaptation routes for future multi-backend quantum computing frameworks, so as to improve the robustness and flexibility of quantum computing systems.

[0005] One embodiment of the present invention provides a quantum circuit compilation method based on neutral atom hardware topology, the method comprising:

[0006] Obtain the characteristic parameters of the quantum circuit to be compiled;

[0007] The obtained feature parameters of the quantum circuit are used to form a feature vector, and the feature vector is input into a pre-trained classical neural network to determine the neutral atom hardware topology of the quantum circuit to be mapped; wherein, the pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the feature parameters of the quantum circuit.

[0008] The quantum circuit is mapped based on the neutral atom hardware topology.

[0009] Optionally, obtaining the characteristic parameters of the quantum circuit to be compiled includes:

[0010] The quantum circuit is obtained by feature extraction. The feature parameters of the quantum circuit include the number of qubits, quantum circuit depth, quantum logic gate density, program communication, quantum circuit critical depth, quantum circuit entanglement ratio, qubit ranking value, quantum logic gate ratio, and total number of operations of the quantum circuit. The program communication is used to characterize the connection characteristics of qubit pairs. The qubit ranking value is a numerical value of the weight of the qubit connection relationship in the quantum circuit.

[0011] Optionally, obtaining the qubit ranking value is a numerical value of the qubit connection weight in the quantum circuit, including:

[0012] A topological connection table of qubits in the quantum circuit is obtained. The connection weight of each qubit is initialized with the same score value. Taking any qubit as the target bit, the connection weight of the target bit is updated by the associated bits that are connected to the target bit, so as to obtain the updated connection weight of each qubit. The topological connection table of qubits is used to characterize the connection relationship between qubits in the quantum circuit.

[0013] Optionally, the step of taking any qubit as the target qubit and updating the connection weight of the target qubit through associated qubits that are connected to the target qubit includes:

[0014] The numerical value of the connection relationship weight of each quantum bit is obtained based on the page ranking formula. The specific calculation method is as follows:

[0015]

[0016] Where d is the damping coefficient, N is the number of qubits, and q i For the target qubit, M(q) i ) is related to the target quantum bit q i A set of associated bits that have connection relationships, q j To be related to the target quantum bit q i Associated bits with connection relationships, L(q) j ) for quantum bits q j The number of associated bits that are connected in a quantum circuit.

[0017] Optionally, the neutral atom hardware topology includes a square topology, an S-triangle topology, and a T-triangle topology.

[0018] Optionally, training the pre-trained classical neural network includes:

[0019] Generate a feature vector containing the characteristic parameters of the quantum circuit; the quantum circuit contains a topology label with the fewest pulses determined based on hardware topology test results;

[0020] One part of the feature vector is used as the training dataset, and the other part is used as the test dataset;

[0021] A classic neural network model containing an input layer, hidden layers, and an output layer is constructed. The training dataset is input into the classic neural network model, and the predicted values ​​are calculated through forward propagation and the parameters are updated through backpropagation. The iteration continues until the loss function converges, and the classic neural network model is trained. The test dataset is then input into the classic neural network model to obtain the error between the test results and the true topological structure labels.

[0022] Optionally, performing the mapping operation on the quantum circuit based on the neutral atom hardware topology includes:

[0023] Determine the neutral atom hardware topology for which the quantum circuit performs mapping operations;

[0024] In response to the initial mapping of the quantum circuit not satisfying the neutral atom hardware topology, and the existence of two-bit quantum logic gates of the quantum circuit that are physically topologically unconnected to the target physical bits of the neutral atom hardware topology, a SWAP gate is inserted to make the physical topology of the target physical bits connected.

[0025] Optionally, inserting a SWAP gate to make the physical topology of the target physical bits physically connected includes:

[0026] The first and second qubits of a two-qubit quantum logic gate are determined. Within the effective interaction radius of the first qubit, a target qubit is selected to insert into the SWAP gate to perform a swap operation. The current target qubit is used as the first qubit to perform the next swap operation. The steps of selecting the target qubit within the effective interaction radius of the first qubit to insert into the SWAP gate to perform a swap operation are continued, and the swap relationship is recorded until the first and second qubits of the two-qubit quantum logic gate are physically topologically connected. The swap operation path is the shortest path from the first qubit to the second qubit.

[0027] Another embodiment of the present invention provides a quantum circuit compilation device based on neutral atom hardware topology, the device comprising:

[0028] The acquisition unit is used to acquire the characteristic parameters of the quantum circuit to be compiled;

[0029] A determining unit is configured to construct a feature vector from the obtained feature parameters of the quantum circuit, and input the feature vector into a pre-trained classical neural network to determine the neutral atom hardware topology of the mapping operation to be performed; wherein, the pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the feature parameters of the quantum circuit.

[0030] An execution unit is used to perform mapping operations on the quantum circuit based on the neutral atom hardware topology.

[0031] Another embodiment of the present invention provides an electronic device, wherein the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, perform the methods described in any of the above embodiments.

[0032] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, perform the methods described in any of the above embodiments.

[0033] Another embodiment of the present invention provides a quantum computer operating system, which implements quantum circuit compilation based on neutral atom hardware topology according to the method described in any of the above embodiments.

[0034] Compared with existing technologies, this invention provides a quantum circuit compilation method based on neutral atom hardware topology. First, the characteristic parameters of the quantum circuit to be compiled are obtained. Then, the obtained characteristic parameters of the quantum circuit are used to construct a feature vector, which is input into a pre-trained classical neural network to determine the neutral atom hardware topology for which a mapping operation is to be performed. The pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the characteristic parameters of the quantum circuit. Finally, a mapping operation is performed on the quantum circuit based on the neutral atom hardware topology.

[0035] This invention first obtains the characteristic parameters of the quantum circuit to be compiled; by extracting and quantizing key characteristic parameters of the quantum circuit, such as the number of qubits, quantum circuit depth, and quantum logic gate density, the unique properties of each quantum circuit can be described more accurately, providing a solid foundation for the subsequent application of classical neural networks; then, the obtained characteristic parameters of the quantum circuit are used to construct a feature vector, and the feature vector is input into a pre-trained classical neural network to determine the neutral atom hardware topology of the quantum circuit to be mapped; wherein, the pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the characteristic parameters of the quantum circuit; through the pre-trained classical neural network... By processing feature vectors, the most suitable neutral atom hardware topology can be predicted quickly and accurately. An intelligent selection mechanism based on feature parameters can choose the most suitable neutral atom hardware topology from a variety of possible topologies, making the quantum circuit compilation process more intelligent and flexible to adapt to ever-changing application requirements and technological advancements. Finally, a mapping operation is performed on the quantum circuit based on the neutral atom hardware topology. Performing the mapping operation according to the selected optimal hardware topology maximizes hardware performance, reduces the error rate and latency of the compiled quantum circuit, improves overall execution efficiency, ensures a perfect match between the quantum circuit to be compiled and the target hardware, and enhances the stability and reliability of the system. Attached Figure Description

[0036] Figure 1 This is a network block diagram of a quantum circuit compilation system based on neutral atom hardware topology, provided for an embodiment of the present invention.

[0037] Figure 2 A flowchart illustrating a quantum circuit compilation method based on neutral atom hardware topology, provided for embodiments of the present invention.

[0038] Figure 3 This is a flowchart of a classic neural network training method provided in an embodiment of the present invention.

[0039] Figure 4 This is a flowchart of a quantum circuit execution mapping method provided in an embodiment of the present invention.

[0040] Figure 5 A flowchart illustrating a method for topologically connecting target physical bits according to an embodiment of the present invention.

[0041] Figure 6 This is a structural diagram of a quantum circuit compilation device based on neutral atom hardware topology, provided as an embodiment of the present invention.

[0042] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0043] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0044] Figure 1 This is a network block diagram of a quantum circuit compilation system based on a neutral atom hardware topology provided in an embodiment of the present invention. The quantum circuit compilation system based on a neutral atom hardware topology may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices (not shown).

[0045] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum circuit compilation system based on neutral atom hardware topology, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof, and the connection method can be wired, wireless communication links or fiber optic cables, etc.

[0046] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0047] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled by the quantum circuit compilation method based on neutral atom hardware topology provided in the embodiments of the present invention.

[0048] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0049] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0050] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0051] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0052] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0053] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0054] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0055] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0056] In the field of quantum computing, different types of quantum chips each have their unique advantages, such as superconducting quantum chips, neutral atom quantum chips, and topological qubits. Currently, mainstream superconducting quantum chips perform well in terms of scalability and control precision, but relying on a single technology carries certain risks. If a particular technology encounters an insurmountable technical bottleneck, the development of the entire quantum computing system may be hindered. By combining the advantages of different technologies, more powerful quantum computing capabilities can be achieved.

[0057] Therefore, a quantum circuit compilation method based on neutral atom hardware topology is proposed to meet the diverse needs of different application fields. The new method can provide more technical adaptation routes for future multi-backend quantum computing frameworks, thereby improving the robustness and flexibility of quantum computing systems.

[0058] See Figure 2 , Figure 2A quantum circuit compilation method based on neutral atom hardware topology, provided for embodiments of the present invention, includes the following steps:

[0059] Step S201: Obtain the characteristic parameters of the quantum circuit to be compiled.

[0060] Specifically, the process begins by obtaining multiple characteristic parameters of the quantum circuit to be compiled.

[0061] Step S202: The obtained feature parameters of the quantum circuit are used to form a feature vector, and the feature vector is input into a pre-trained classical neural network to determine the neutral atom hardware topology of the mapping operation to be performed; wherein, the pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the feature parameters of the quantum circuit.

[0062] Specifically, a feature vector is constructed from multiple feature parameters of the quantum circuit through feature extraction. The feature vector is then input into a pre-trained classical neural network to determine the type of neutral atom hardware topology for which the mapping operation is to be performed. The pre-trained classical neural network is mainly used to determine the neutral atom hardware topology to be executed by the quantum circuit to be compiled based on the feature parameters of the quantum circuit.

[0063] For example, by extracting multiple quantum circuit feature parameters such as the number of qubits, quantum circuit depth, quantum logic gate density, program communication, quantum circuit critical depth, quantum circuit entanglement ratio, qubit ranking value, quantum logic gate ratio, and total number of quantum circuit operations, and by combining these multiple feature parameters into a feature vector, and inputting the resulting feature vector into a classical neural network, the specific type of neutral atom hardware topology structure to be mapped can be obtained.

[0064] Step S203: Perform a mapping operation on the quantum circuit based on the neutral atom hardware topology.

[0065] Specifically, mapping operations are performed on quantum circuits based on a defined type of neutral atom hardware topology.

[0066] In summary, this invention first obtains the characteristic parameters of the quantum circuit to be compiled; by extracting and quantizing the key characteristic parameters of the quantum circuit, such as the number of qubits, quantum circuit depth, and quantum logic gate density, the unique properties of each quantum circuit can be described more accurately, providing a solid foundation for the subsequent application of classical neural networks; then, the obtained characteristic parameters of the quantum circuit are used to construct a feature vector, and the feature vector is input into a pre-trained classical neural network to determine the neutral atom hardware topology of the quantum circuit to be mapped; wherein, the pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the characteristic parameters of the quantum circuit; through the pre-trained classical neural network... The network processes the feature vectors to quickly and accurately predict the most suitable neutral atom hardware topology. Based on the intelligent selection mechanism of feature parameters, it can select the most suitable neutral atom hardware topology from a variety of possible hardware topologies, making the compilation process of quantum circuits more intelligent and flexible to adapt to ever-changing application requirements and technological advancements. Finally, a mapping operation is performed on the quantum circuit based on the neutral atom hardware topology. Performing the mapping operation according to the selected optimal hardware topology can maximize hardware performance, reduce the error rate and latency of the compiled quantum circuit, improve overall execution efficiency, ensure a perfect match between the quantum circuit to be compiled and the target hardware, and enhance the stability and reliability of the system.

[0067] In one embodiment of this application, obtaining the characteristic parameters of the quantum circuit to be compiled includes:

[0068] The quantum circuit is obtained by feature extraction. The feature parameters of the quantum circuit include the number of qubits, quantum circuit depth, quantum logic gate density, program communication, quantum circuit critical depth, quantum circuit entanglement ratio, qubit ranking value, quantum logic gate ratio, and total number of operations of the quantum circuit. The program communication is used to characterize the connection characteristics of qubit pairs. The qubit ranking value is a numerical value of the weight of the qubit connection relationship in the quantum circuit.

[0069] Among them, quantum circuit depth refers to the maximum number of quantum logic gates that can be executed in parallel in a quantum circuit; quantum logic gate density refers to the occupancy level of quantum logic gates in a quantum circuit; program communication refers to the connectivity between pairs of qubits in a quantum circuit; quantum circuit critical depth refers to the shortest time required for a quantum circuit to complete, measured in terms of two-qubit quantum logic gates; quantum circuit entanglement ratio refers to the proportion of two-qubit quantum logic gates to all quantum logic gates in the entire quantum circuit; qubit ranking value refers to the importance value of each qubit obtained based on the page ranking algorithm; quantum logic gate percentage refers to the proportion of single-qubit, two-qubit, and three-qubit quantum logic gates to all quantum logic gates; and the total number of quantum circuit operations refers to the sum of the number of all quantum logic gate operations in the quantum circuit.

[0070] Specifically, assuming a quantum circuit has 4 qubits, then W = 4; where the maximum number of parallel execution quantum logic gates in the quantum circuit includes 3 quantum logic gate operations (such as H gate, CNOT gate, X gate), then the quantum circuit depth is D = 3; assuming the quantum circuit has 5 single-qubit quantum logic gates, 3 two-qubit quantum logic gates, and 1 three-qubit quantum logic gate, then the gate density ρ = G / W*D = [5 + 2*3 + 3*1] / [4*3] = 1.17; assuming the quantum circuit has... Given four qubits q1, q2, q3, and q4, with a degree d(q1) = 2 (q1 is connected to two other qubits), d(q2) = 3, d(q3) = 1, and d(q4) = 2, the program communication PC = [d(q1) + d(q2) + d(q3) + d(q4)] / W * (W - 1) = 8 / 12 = 0.67. Assuming there are two two-qubit quantum logic gates on the critical path of the quantum circuit, and five two-qubit quantum logic gates in the entire quantum circuit, the critical depth of the quantum circuit is... The degree CD = 2 / 5 = 0.4; if the quantum circuit has 5 two-qubit quantum logic gates and 10 total quantum logic gates (including single quantum logic gates, multiple quantum logic gates, etc.), then the quantum circuit entanglement ratio is ER = 5 / 10 = 0.5; calculate the PageRank value of each qubit based on the page ranking algorithm. Assuming there are 4 qubits, assume the obtained PageRank values ​​are 0.4, 0.5, 0.45, and 0.65, then calculate the standard deviation, maximum value, and average value of these values ​​respectively; if A quantum circuit has 10 quantum logic gates, of which 5 are single quantum logic gates, so the proportion of single quantum logic gates is P1 = 5 / 10 = 0.5; 5 are two-qubit quantum logic gates, so the proportion of two-qubit quantum logic gates is P2 = 5 / 10 = 0.5; and 1 is a three-qubit quantum logic gate, so the proportion of three-qubit quantum logic gates is P3 = 1 / 10 = 0.1. If the quantum circuit has 5 single quantum logic gates, 5 two-qubit quantum logic gates, and 1 three-qubit quantum logic gate, then the total number of operations of the quantum circuit is N = 5 + 5 + 1 = 11.

[0071] In one embodiment of this application, obtaining the qubit ranking value is a numerical value of the qubit connection relationship weight in the quantum circuit, including:

[0072] A topological connection table of qubits in the quantum circuit is obtained. The connection weight of each qubit is initialized with the same score value. Taking any qubit as the target bit, the connection weight of the target bit is updated by the associated bits that are connected to the target bit, so as to obtain the updated connection weight of each qubit. The topological connection table of qubits is used to characterize the connection relationship between qubits in the quantum circuit.

[0073] Specifically, firstly, the topological connection table of qubits in the quantum circuit is obtained. Then, the connection weight of each qubit is initialized with the same score. Any qubit is selected as the target bit. The connection weight of the target bit is updated by the associated qubits that are connected to the target bit, so as to obtain the updated connection weight value of each qubit.

[0074] For example, suppose there is a simple quantum circuit containing 3 qubits (q0, q1, q2). First, obtain the topology connection table. Assume that q0 and q1 are topologically connected, q1 is connected to q0 and q2 respectively, and q2 is connected to q1. Then the topology connection table is {0:[1],1:[0,2],2:[1]}. Assign the connection weight of each qubit with the same score value. Then select any qubit as the target qubit. Update the connection weight value of the target qubit by the qubits that are connected to the target qubit. So as to obtain the updated connection weight value of each qubit.

[0075] In one embodiment of this application, updating the connection weight of the target bit by using any qubit as the target bit and the associated bits connected to the target bit includes:

[0076] The numerical value of the connection relationship weight of each quantum bit is obtained based on the page ranking formula. The specific calculation method is as follows:

[0077]

[0078] Where d is the damping coefficient, N is the number of qubits, and q i For the target qubit, M(q) i ) is related to the target quantum bit q i A set of associated bits that have connection relationships, q j To be related to the target quantum bit q i Associated bits with connection relationships, L(q) j ) for quantum bits q j The number of associated bits that are connected in a quantum circuit.

[0079] Specifically, taking any one qubit as the target qubit, the connection weight of the target qubit is updated through the associated qubits connected to it. The connection weight of each qubit is mainly obtained through the page ranking formula, as shown in the formula above, where d is the damping coefficient (a constant), N is the number of qubits, and q... i For the target qubit, M(q) i ) for the target quantum bit q iA set of associated bits that have connection relationships, q j To be related to the target quantum bit q i Associated bits with connection relationships, L(q) j ) for quantum bits q j The number of associated bits that are connected in a quantum circuit.

[0080] For example, suppose there are three qubits (numbered 0, 1, and 2) and the following connections exist between them: qubit q0 is connected to qubit q1, qubit q1 is connected to qubits q0 and q2, and qubit q2 is connected to qubit q1. Therefore, the qubit topology connection table is obtained as {0:[1], 1:[0,2], 2:[1]}. First, each qubit is assigned the same connection weight value: PR(0) = 1 / 3, PR(1) = 1 / 3, PR(2) = 1 / 3. During the first iteration, the connection weight value of each qubit is updated according to the page ranking formula, as shown in the formula above. d is the damping factor, which is set to 0.85 here. N is the number of qubits, N = 3. M(q i ) for the target quantum bit q i The set of associated bits with connection relationships exists, where the set of connection relationships for the target qubit q1 is {0, 2}, L(q j ) for quantum bits q j The number of associated bits with connection relationships in a quantum circuit, such as the number of associated bits with connection relationships in quantum bit q0 being 1; then further calculate PR(0)=(1-0.85) / 3+0.85*[PR(1 / 2)]; PR(1)=(1-0.85) / 3+0.85*[PR(0) / 1+PR(2) / 1]; PR(2)=(1-0.85) / 3+0.85*[PR(1) / 2]; substituting the initial values ​​PR(0)=1 / 3, PR(1)=1 / 3, PR(2)=1 / 3, we can get PR(0)=0.1667, PR(1)=0.6111, PR(2)=0.1667.

[0081] In one embodiment of this application, the neutral atom hardware topology includes a square topology, an S-triangle topology, and a T-triangle topology.

[0082] Specifically, the variability of the topology of neutral atom hardware generally includes square topology, S-triangle topology, and T-triangle topology.

[0083] See Figure 3 , Figure 3 A flowchart of a classic neural network training method provided in this embodiment of the invention includes the following steps:

[0084] Step S301: Generate a feature vector containing the feature parameters of the quantum circuit; the quantum circuit contains a topology label with the fewest pulses determined based on the hardware topology test results.

[0085] Among them, the topology tags are those with square topology tags, S-triangle topology tags, and T-triangle topology tags.

[0086] Specifically, feature vectors containing the feature parameters of quantum circuits are first generated through feature extraction. These quantum circuits have been tested in hardware, and the test results determine the most suitable topology type for each quantum circuit. The most suitable topology type is the one that generates the fewest pulses during the test.

[0087] Step S302: Use a portion of the feature vector as the training dataset and the other portion as the test dataset.

[0088] Specifically, a portion of the generated feature vectors is used as the training dataset, and the other portion is used as the test dataset.

[0089] Step S303: Construct a classic neural network model containing an input layer, a hidden layer, and an output layer. Input the training dataset into the classic neural network model, calculate the predicted value through forward propagation and update the parameters through backpropagation, and continue iterating until the loss function converges. The classic neural network model is then trained. Finally, input the test dataset into the classic neural network model to obtain the error between the test result and the real topological structure label.

[0090] Specifically, firstly, a classic neural network model containing an input layer, hidden layers, and an output layer is constructed. Then, the training dataset is input into the classic neural network model, and the predicted values ​​are calculated through forward propagation and the model parameters are updated through back propagation. The process continues iterating until the loss function converges, at which point the classic neural network model training is complete. Another part of the test dataset is input into the classic neural network model to obtain the error value between the test results and the true topological label, in order to calculate the generalization ability of the classic neural network model.

[0091] In summary, by converting data containing quantum circuit characteristic parameters into feature vectors, complex quantum circuit information can be simplified into a form easily processed by classical computers. This allows classical neural networks to learn the mapping relationship between different quantum circuits and the hardware topologies best suited to them. Dividing the generated feature vectors into training and testing datasets ensures that the model not only performs well on known data but also makes accurate predictions on unseen data. This approach helps avoid overfitting, i.e., the problem where the model performs well on training data but fails to generalize to new data. By constructing a classical neural network with input, hidden, and output layers and training it using the training dataset, this method allows for the transformation of machine learning computations... Patterns are discovered in the model to determine the optimal neutral atom hardware topology for executing the quantum circuit to be compiled. Forward propagation is used to calculate the predicted values, while backpropagation is used to optimize the network weights. As the number of iterations increases, the loss function gradually converges, indicating that the model's learning process tends to stabilize. Finally, a model that can accurately predict the hardware topology required for quantum circuits is obtained. The trained classical neural network model is evaluated using a test dataset. By calculating the error between the predicted results and the actual topology labels, the performance of the model can be quantitatively evaluated. If the error is small enough, it indicates that the model has good generalization ability and can be used in practical applications to guide the mapping operation of quantum circuits to specific neutral atom hardware topologies.

[0092] See Figure 4 , Figure 4 A flowchart of a quantum circuit mapping method provided in this embodiment of the invention includes the following steps:

[0093] Step S401: Determine the neutral atom hardware topology for which the quantum circuit performs the mapping operation.

[0094] Specifically, the first step is to determine the neutral atom hardware topology of the quantum circuit to be compiled.

[0095] Step S402: In response to the initial mapping of the quantum circuit not satisfying the neutral atom hardware topology, and the existence of two-bit quantum logic gates of the quantum circuit that are physically topologically unconnected to the target physical bits of the neutral atom hardware topology, a SWAP gate is inserted to make the physical topology of the target physical bits connected.

[0096] Specifically, assuming that the initial mapping relationship of the quantum circuit does not satisfy the neutral atom hardware topology, and that the two-bit quantum logic gates of the quantum circuit are not physically connected to the target physical bits of the neutral atom hardware topology, then a SWAP gate needs to be inserted to make the physical topology of the target physical bits connected.

[0097] In summary, by determining the neutral atom hardware topology for the quantum circuit to perform mapping operations, we ensure that the quantum circuit can be correctly executed on a specific hardware platform. During the mapping process, we specifically consider the connection relationship between the two-qubit quantum logic gates (such as CNOT gates) of the quantum circuit and the target physical bits of the neutral atom hardware topology. If the initial mapping does not satisfy the hardware topology, that is, if the target physical bits mapped by two-qubit quantum logic gates are not physically connected, a SWAP gate is inserted to adjust the layout of the physical bits so that they can be connected. This dynamic adjustment ensures that the quantum logic gates can be correctly executed on the hardware to adapt to different quantum computing tasks.

[0098] See Figure 5 , Figure 5 A flowchart of a target physical bit topology interconnection method provided by an embodiment of the present invention includes the following steps:

[0099] Step S501: Determine the first and second qubits of the two-qubit quantum logic gate; select a target qubit within the effective interaction radius of the first qubit to insert into the SWAP gate and perform a swap operation; use the current target qubit as the first qubit for the next swap operation; continue the step of selecting the target qubit within the effective interaction radius of the first qubit to insert into the SWAP gate and perform a swap operation; and record the swap relationship until the physical topology of the first and second qubits of the two-qubit quantum logic gate is connected; the swap operation path is the shortest path from the first qubit to the second qubit.

[0100] Specifically, firstly, the first and second qubits of the two-qubit quantum logic gate to be mapped are determined. Within the effective interaction radius of the first qubit, a target qubit is selected to insert into the SWAP gate to perform a swap operation. The current target qubit is used as the first qubit to perform the next swap operation. The process of selecting a target qubit within the effective interaction radius of the first qubit to insert into the SWAP gate to perform a swap operation continues, and the swap relationship is recorded until the physical topology of the first and second qubits of the two-qubit quantum logic gate is connected. The path for performing the swap operation is the shortest path from the first qubit to the second qubit.

[0101] For example, suppose we have a quantum computer whose qubits are arranged on a two-dimensional grid. Each qubit can only interact directly with its neighboring (e.g., above, below, left, and right) qubits. We need to implement a two-qubit CNOT gate in this physical layout, where the control bit and the target bit are not physically adjacent. Assume the control bit (called Q1) is located at the top-left corner of the grid with coordinates (1,1), and the target bit (called Q2) is located at the bottom-right corner with coordinates (N,N), where N is the size of the grid. We use a graph search algorithm (such as breadth-first search or A* algorithm) to find the shortest swap path from Q1 to Q2, which contains only qubits that can interact directly. Assume the shortest... The path passes through qubits Q3, Q4, ..., QK in sequence, where QK is adjacent to Q2. First, within the effective interaction radius of Q1 (i.e., among the qubits directly adjacent to Q1), the second qubit (let's say Q3) on the closest shortest path is selected and a SWAP operation is performed, swapping the positions of Q1 and this intermediate qubit. The swap relationship is recorded. Then, the current qubit (originally Q1, now adjacent to Q3) is used as the new starting point, and the next target qubit is selected within the effective interaction radius for SWAP operation until the adjacent position of Q2 is reached. During each step, the executed SWAP operation and its swap relationship are recorded until Q1 (after a series of SWAP operations) and Q2 are physically adjacent.

[0102] In summary, the correct execution of a two-qubit quantum logic gate (such as a CNOT gate) in a quantum circuit depends on the physical connection between the two qubits it operates on. By inserting a SWAP gate, target qubits that were originally physically disconnected can be connected, thus ensuring the correct execution of the quantum logic gate. This is an indispensable step in the quantum circuit compilation process and the foundation for realizing quantum algorithm functions. Although inserting a SWAP gate increases the number of operations in the quantum circuit, it improves the efficiency and feasibility of quantum computing by selecting the shortest path for the swap operation and recording the swap relationship. In quantum computing, different quantum circuits may require different hardware topologies and mapping strategies. By intelligently inserting SWAP gates to adjust the layout of qubits, the quantum circuit can flexibly adapt to different hardware topologies. This flexibility contributes to the widespread application and expansion of quantum circuit compilation methods, improving the practicality and scalability of quantum computing.

[0103] See Figure 6 , Figure 6 A quantum circuit compilation device based on neutral atom hardware topology provided in this embodiment of the invention includes: an acquisition unit 601, a determination unit 602, and an execution unit 603.

[0104] Acquisition unit 601 is used to acquire the characteristic parameters of the quantum circuit to be compiled.

[0105] Specifically, feature parameters of the quantum circuit are obtained by feature extraction. These parameters include the number of qubits, quantum circuit depth, quantum logic gate density, program communication, quantum circuit critical depth, quantum circuit entanglement ratio, qubit ranking value, quantum logic gate ratio, and the total number of operations of the quantum circuit. The program communication is used to characterize the connection characteristics of qubit pairs. The qubit ranking value is a numerical value representing the weight of the qubit connection relationship in the quantum circuit.

[0106] The determining unit 602 is used to construct a feature vector from the obtained feature parameters of the quantum circuit, and input the feature vector into a pre-trained classical neural network to determine the neutral atom hardware topology of the mapping operation to be performed; wherein, the pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the feature parameters of the quantum circuit.

[0107] Specifically, obtaining the qubit ranking value is a numerical value representing the weight of the qubit connection relationship in the quantum circuit, including:

[0108] A topological connection table of qubits in the quantum circuit is obtained. The connection weight of each qubit is initialized with the same score value. Taking any qubit as the target bit, the connection weight of the target bit is updated by the associated bits that are connected to the target bit, so as to obtain the updated connection weight of each qubit. The topological connection table of qubits is used to characterize the connection relationship between qubits in the quantum circuit.

[0109] Specifically, the step of taking any qubit as the target qubit and updating the connection weight of the target qubit through associated qubits that are connected to the target qubit includes:

[0110] The numerical value of the connection relationship weight of each quantum bit is obtained based on the page ranking formula. The specific calculation method is as follows:

[0111]

[0112] Where d is the damping coefficient, N is the number of qubits, and q i For the target qubit, M(q) i ) is related to the target quantum bit q i A set of associated bits that have connection relationships, q j To be related to the target quantum bit q i Associated bits with connection relationships, L9qj ) for quantum bits q j The number of associated bits that are connected in a quantum circuit.

[0113] Specifically, the neutral atom hardware topology includes a square topology, an S-triangle topology, and a T-triangle topology.

[0114] Specifically, training the pre-trained classical neural network includes:

[0115] Generate a feature vector containing the characteristic parameters of the quantum circuit; the quantum circuit contains a topology label with the fewest pulses determined based on hardware topology test results;

[0116] One part of the feature vector is used as the training dataset, and the other part is used as the test dataset;

[0117] A classic neural network model containing an input layer, hidden layers, and an output layer is constructed. The training dataset is input into the classic neural network model, and the predicted values ​​are calculated through forward propagation and the parameters are updated through backpropagation. The iteration continues until the loss function converges, and the classic neural network model is trained. The test dataset is then input into the classic neural network model to obtain the error between the test results and the true topological structure labels.

[0118] The execution unit 603 is used to perform a mapping operation on the quantum circuit based on the neutral atom hardware topology.

[0119] Specifically, the mapping operation on the quantum circuit based on the neutral atom hardware topology includes:

[0120] Determine the neutral atom hardware topology for which the quantum circuit performs mapping operations;

[0121] Specifically, in response to the initial mapping of the quantum circuit not satisfying the neutral atom hardware topology, and the existence of two-bit quantum logic gates of the quantum circuit that are physically topologically unconnected to the target physical bits of the neutral atom hardware topology, a SWAP gate is inserted to make the physical topology of the target physical bits connected.

[0122] Specifically, inserting a SWAP gate to make the physical topology of the target physical bits physically connected includes:

[0123] The first and second qubits of a two-qubit quantum logic gate are determined. Within the effective interaction radius of the first qubit, a target qubit is selected to insert into the SWAP gate to perform a swap operation. The current target qubit is used as the first qubit to perform the next swap operation. The steps of selecting the target qubit within the effective interaction radius of the first qubit to insert into the SWAP gate to perform a swap operation are continued, and the swap relationship is recorded until the first and second qubits of the two-qubit quantum logic gate are physically topologically connected. The swap operation path is the shortest path from the first qubit to the second qubit.

[0124] The specific functions and effects of the quantum circuit compilation device based on neutral atom hardware topology described above can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the quantum circuit compilation device based on neutral atom hardware topology can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in hardware or independently of the processor in a computer device, or it can be stored in software in the memory of a computer device, so that the processor can call and execute the operations corresponding to each module.

[0125] Please see Figure 7 This specification also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum circuit compilation method based on neutral atom hardware topology in any of the above embodiments. Please refer to [link to documentation]. Figure 7 The electronic device can be a classical computer or a quantum computer.

[0126] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum circuit compilation method based on neutral atom hardware topology in any of the above embodiments.

[0127] This invention also provides a quantum computer operating system, which implements a quantum circuit compilation method based on neutral atom hardware topology according to any of the above-described method embodiments provided in this invention.

[0128] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0129] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0130] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0131] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0132] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0133] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0134] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0135] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0136] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0138] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0139] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0140] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A quantum circuit compilation method based on neutral atom hardware topology, characterized in that, The method includes: Obtain the characteristic parameters of the quantum circuit to be compiled; The obtained feature parameters of the quantum circuit are used to form a feature vector, and the feature vector is input into a pre-trained classical neural network to determine the neutral atom hardware topology of the quantum circuit to be mapped; wherein, the pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the feature parameters of the quantum circuit. The quantum circuit is mapped based on the neutral atom hardware topology.

2. The method according to claim 1, characterized in that, The process of obtaining the characteristic parameters of the quantum circuit to be compiled includes: The quantum circuit is obtained by feature extraction. The feature parameters of the quantum circuit include the number of qubits, quantum circuit depth, quantum logic gate density, program communication, quantum circuit critical depth, quantum circuit entanglement ratio, qubit ranking value, quantum logic gate ratio, and total number of operations of the quantum circuit. The program communication is used to characterize the connection characteristics of qubit pairs. The qubit ranking value is a numerical value of the weight of the qubit connection relationship in the quantum circuit.

3. The method according to claim 1, characterized in that, The process of obtaining the qubit ranking value is a numerical value representing the weight of the qubit connection relationship in the quantum circuit, including: A topological connection table of qubits in the quantum circuit is obtained. The connection weight of each qubit is initialized with the same score value. Taking any qubit as the target bit, the connection weight of the target bit is updated by the associated bits that are connected to the target bit, so as to obtain the updated connection weight of each qubit. The topological connection table of qubits is used to characterize the connection relationship between qubits in the quantum circuit.

4. The method according to claim 3, characterized in that, The step of taking any qubit as the target qubit and updating the connection weight of the target qubit through associated qubits that are connected to the target qubit includes: The numerical value of the connection relationship weight of each quantum bit is obtained based on the page ranking formula. The specific calculation method is as follows: Where d is the damping coefficient, N is the number of qubits, and q i For the target qubit, M(q) i ) is related to the target quantum bit q i A set of associated bits that have connection relationships, q j To be related to the target quantum bit q i Associated bits with connection relationships, L9q j ) for quantum bits q j The number of associated bits that are connected in a quantum circuit.

5. The method according to claim 1, characterized in that, The neutral atom hardware topology includes square topology, S-triangle topology, and T-triangle topology.

6. The method according to claim 1, characterized in that, The training of the pre-trained classical neural network includes: Generate a feature vector containing the characteristic parameters of the quantum circuit; the quantum circuit contains a topology label with the fewest pulses determined based on hardware topology test results; One part of the feature vector is used as the training dataset, and the other part is used as the test dataset; A classic neural network model containing an input layer, hidden layers, and an output layer is constructed. The training dataset is input into the classic neural network model, and the predicted values ​​are calculated through forward propagation and the parameters are updated through backpropagation. The iteration continues until the loss function converges, and the classic neural network model is trained. The test dataset is then input into the classic neural network model to obtain the error between the test results and the true topological structure labels.

7. The method according to claim 1, characterized in that, The mapping operation performed on the quantum circuit based on the neutral atom hardware topology includes: Determine the neutral atom hardware topology for which the quantum circuit performs mapping operations; In response to the initial mapping of the quantum circuit not satisfying the neutral atom hardware topology, and the existence of two-bit quantum logic gates of the quantum circuit that are physically topologically unconnected to the target physical bits of the neutral atom hardware topology, a SWAP gate is inserted to make the physical topology of the target physical bits connected.

8. The method according to claim 7, characterized in that, The insertion of the SWAP gate to make the physical topology of the target physical bits physically connected includes: The first and second qubits of a two-qubit quantum logic gate are determined. Within the effective interaction radius of the first qubit, a target qubit is selected to insert into the SWAP gate to perform a swap operation. The current target qubit is used as the first qubit to perform the next swap operation. The steps of selecting the target qubit within the effective interaction radius of the first qubit to insert into the SWAP gate to perform a swap operation are continued, and the swap relationship is recorded until the first and second qubits of the two-qubit quantum logic gate are physically topologically connected. The swap operation path is the shortest path from the first qubit to the second qubit.

9. A quantum circuit compilation device based on neutral atom hardware topology, characterized in that, The device includes: The acquisition unit is used to acquire the characteristic parameters of the quantum circuit to be compiled; A determining unit is configured to construct a feature vector from the obtained feature parameters of the quantum circuit, and input the feature vector into a pre-trained classical neural network to determine the neutral atom hardware topology of the mapping operation to be performed; wherein, the pre-trained classical neural network is used to determine the neutral atom hardware topology of the quantum circuit to be compiled based on the feature parameters of the quantum circuit. An execution unit is used to perform mapping operations on the quantum circuit based on the neutral atom hardware topology.

10. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claims 1-8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claims 1-8.

12. A quantum computer operating system, characterized in that, The quantum computer operating system implements quantum circuit compilation based on neutral atom hardware topology according to any one of claims 1-8.

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