Display method, display circuit and electronic equipment

Abstract

The embodiment of the invention discloses a display method, a display circuit and electronic equipment, belongs to the technical field of image display, and is used for reducing the power consumption of a display interface processor so as to reduce the power consumption of the electronic equipment. The display method is applied to a display circuit and comprises the following steps: entering a signal sending state under the condition that a low power consumption quit instruction is received firstly and then a first instruction is received; under the condition that the low-power-consumption quit instruction is received but the first instruction is not received, not entering a signal sending state; and if entering the signal sending state, sending the to-be-displayed data.

Description

Technical Field

[0001] This application relates to the field of image display technology, and more particularly to a display method, display circuit, and electronic device. Background Technology

[0002] With the rapid development of mobile internet, electronic devices with displays that use non-traditional power supply methods (such as smartwatches, smart bands, and mobile phones) are emerging in large numbers. These electronic devices have extremely high requirements for performance and power consumption; the goal is to ensure display quality and user experience while reducing power consumption and extending standby time.

[0003] The graphics display system of electronic devices accounts for a significant portion of their power consumption. Among this, the display interface processor (MIPI) consumes a substantial amount of power. This MIPI processor can be, for example, a processor compliant with the Mobile Industry Processor Interface (MIPI) standard.

[0004] In related technologies, the power consumption of the display interface processor is reduced through automated ultra-low power states (AUTOULPS), thereby reducing the power consumption of the entire system. However, current solutions for reducing the power consumption of the display interface processor based on AUTOULPS technology still suffer from some unnecessary power waste in the display interface processor. Summary of the Invention

[0005] This application provides a display method, display circuit, and electronic device that can precisely control the timing of the display interface processor exiting the low-power state in real time, thereby reducing the power consumption of the display interface processor and thus reducing the power consumption of the electronic device.

[0006] In a first aspect, a display method is provided, which is applied to a display circuit. The method includes: entering a signal transmission state when a low-power exit instruction is received first, followed by a first instruction; not entering the signal transmission state when a low-power exit instruction is received but the first instruction is not received; and if the signal transmission state is entered, transmitting data to be displayed.

[0007] As can be seen from the above, after the display interface processor in the display circuit receives the exit low-power command, the display circuit will only respond to the exit low-power command and enter the signal transmission state if it then receives the first command; otherwise, it will not enter the signal transmission state. This differs from related technologies that respond immediately upon receiving the exit low-power command and enter the signal transmission state. Therefore, the timing of entering the signal transmission state can be controlled in real time, extending the time the display interface processor remains in the low-power state, reducing the power consumption of the display interface processor, and thus reducing the power consumption of the display circuit.

[0008] In one possible implementation, the first instruction includes the rising edge or falling edge of the first pulse.

[0009] As can be seen from the above, when the first instruction includes the rising edge or falling edge of the first pulse, it can periodically control the display interface processor. When it receives the exit low power instruction, it responds to the exit low power instruction and enters the signal transmission state, thereby improving the stability and autonomy of the display circuit in entering the signal transmission state.

[0010] In one possible implementation, an exit low-power instruction sent by the graphics processor is received; a first instruction sent by the signal generator is also received.

[0011] In one possible implementation, the data to be displayed is acquired, and upon receiving a second instruction, the data to be displayed is sent through the display interface processor.

[0012] As shown above, after acquiring the data to be displayed, if a second instruction is received, the display controller sends the data to be displayed to the display driver chip through the display interface processor. This allows for precise control of the timing of data transmission, shortening the waiting time of the display circuit in the signal transmission state and further reducing the power consumption of the display circuit.

[0013] In one possible implementation, the second instruction includes the rising edge or falling edge of the second pulse.

[0014] As can be seen from the above, when the second instruction includes the rising edge or falling edge of the second pulse, it can periodically control the display controller to determine whether to send the data to be displayed, thereby improving the stability and autonomy of the data to be displayed transmission.

[0015] In one possible implementation, a second instruction sent by a signal generator is received.

[0016] In one possible implementation, the rising edge of the second pulse signal is delayed compared to the rising edge of the first pulse signal.

[0017] As can be seen from the above, by controlling the rising edge of the second pulse signal to be delayed compared to the rising edge of the first pulse signal, the display circuit can first enter the signal transmission state and then transmit the data to be displayed, ensuring that the data to be displayed can be successfully transmitted.

[0018] In one possible implementation, the rising edge of the second pulse signal is delayed by a preset time interval equal to the rising edge of the first pulse signal, controlled by a signal controller.

[0019] As can be seen from the above, by controlling the rising edge of the second pulse signal to be delayed by a preset time interval equal to the rising edge of the first pulse signal by the signal controller, the display interface processor can immediately send the data to be displayed when it is in the signal sending state, thereby shortening the time for the display interface processor to enter the signal generation state, which means extending the time for the display interface processor to be in the low power state, thereby reducing the power consumption of the display interface processor.

[0020] Secondly, a display circuit is provided, which is applied in an electronic device. The display circuit includes a display controller and a display interface processor. The display interface processor is configured to enter a signal transmission state when it first receives an exit low-power instruction and then receives a first instruction; and not enter the signal transmission state when it receives an exit low-power instruction but does not receive the first instruction. The display controller is configured to transmit the data to be displayed if it enters the signal transmission state.

[0021] As can be seen from the above, after the display interface processor in the display circuit receives the exit low-power command, the display circuit will only respond to the exit low-power command and enter the signal transmission state if it then receives the first command; otherwise, it will not enter the signal transmission state. This differs from related technologies that respond immediately upon receiving the exit low-power command and enter the signal transmission state. Therefore, the timing of entering the signal transmission state can be controlled in real time, extending the time the display interface processor remains in the low-power state, reducing the power consumption of the display interface processor, and thus reducing the power consumption of the display circuit.

[0022] In one possible implementation, the first instruction includes the rising edge or falling edge of the first pulse.

[0023] As can be seen from the above, when the first instruction includes the rising edge or falling edge of the first pulse, it can periodically control the display interface processor. When it receives the exit low power instruction, it responds to the exit low power instruction and enters the signal transmission state, thereby improving the stability and autonomy of the display circuit in entering the signal transmission state.

[0024] In one possible implementation, the display circuitry further includes a signal generator connected to a display interface processor: the display interface processor is also configured to receive an exit low-power instruction sent by the graphics processor; the display interface processor is also configured to receive a first instruction sent by the signal generator.

[0025] In one possible implementation, the display controller is also configured to acquire data to be displayed, and upon receiving a second instruction, send the data to be displayed through the display interface processor.

[0026] As shown above, after acquiring the data to be displayed, if a second instruction is received, the display controller sends the data to be displayed to the display driver chip through the display interface processor. This allows for precise control of the timing of data transmission, shortening the waiting time of the display circuit in the signal transmission state and further reducing the power consumption of the display circuit.

[0027] In one possible implementation, the second instruction includes the rising edge or falling edge of the second pulse.

[0028] As can be seen from the above, when the second instruction includes the rising edge or falling edge of the second pulse, it can periodically detect whether the display controller needs to send the data to be displayed, thereby improving the stability and autonomy of the data to be displayed transmission.

[0029] In one possible implementation, the display circuitry also includes a signal generator connected to the display controller: the display controller is also used to receive a second instruction sent by the signal generator.

[0030] In one possible implementation, the rising edge of the second pulse signal is delayed compared to the rising edge of the first pulse signal.

[0031] As can be seen from the above, by controlling the rising edge of the second pulse signal to be delayed compared to the rising edge of the first pulse signal, the display circuit can first enter the signal transmission state and then transmit the data to be displayed, ensuring that the data to be displayed can be successfully transmitted.

[0032] In one possible implementation, the display circuit further includes a signal controller connected to the signal generator: the signal controller controls the rising edge of the second pulse signal to be delayed by a preset time interval equal to the delay of the display interface processor.

[0033] As can be seen from the above, by controlling the rising edge of the second pulse signal to be delayed by a preset time interval equal to the rising edge of the first pulse signal by the signal controller, the display interface processor can immediately send the data to be displayed when it is in the signal sending state, thereby shortening the time for the display interface processor to enter the signal generation state, which means extending the time for the display interface processor to be in the low power state, thereby reducing the power consumption of the display interface processor.

[0034] In one possible implementation, the display interface processor includes a Mobile Industry Interface (MIPI) processor or a High Definition Multimedia Interface (HDMI) processor.

[0035] Thirdly, embodiments of this application provide an electronic device including the aforementioned display circuit and display screen. The display screen is used to receive and display data to be displayed. The electronic device also includes a processor and a memory for storing processor-executable instructions; the processor is configured to execute instructions, causing the computing device to perform the display method provided in the first aspect.

[0036] Fourthly, embodiments of this application provide a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor to implement the display method provided in the first aspect above.

[0037] Fifthly, embodiments of this application provide a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computing node reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing node to perform the display methods in the various optional implementations provided in the first aspect.

[0038] For a detailed description of the third to fifth aspects and their various implementations in the embodiments of this application, please refer to the detailed descriptions in the first aspect, the second aspect and their various implementations; and for a detailed description of the beneficial effects of the third to fifth aspects and their various implementations, please refer to the beneficial effect analysis in the various implementations of the first aspect, which will not be repeated here.

[0039] These or other aspects of the embodiments of this application will become more apparent in the following description. Attached Figure Description

[0040] Figure 1 A timing diagram illustrating data transmission is shown in the related art;

[0041] Figure 2 This paper shows a schematic diagram of the structure of an electronic device 200 provided in an embodiment of this application;

[0042] Figure 3 This illustration shows a schematic diagram of a display circuit 300 provided in an embodiment of this application;

[0043] Figure 4 This illustration shows a schematic flowchart of a display method provided in an embodiment of this application;

[0044] Figure 5 A timing diagram of a response to an exit low-power instruction provided in an embodiment of this application is shown;

[0045] Figure 6 This illustration shows a schematic diagram of a pulse signal provided in an embodiment of this application;

[0046] Figure 7 This illustration shows a timing diagram of data transmission to be displayed, provided in an embodiment of this application. Detailed Implementation

[0047] The terms “first,” “second,” “third,” and “fourth,” etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to define a specific order.

[0048] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0049] First, the application scenarios of the embodiments of this application will be introduced by way of example.

[0050] With the development and popularization of mobile internet, users' demand for longer battery life in electronic devices with displays that use non-traditional power supply methods (such as smartwatches, fitness trackers, and mobile phones) continues to increase. Therefore, reducing the power consumption of these electronic devices has become an important research direction.

[0051] The graphics display system of the aforementioned electronic devices accounts for a significant portion of their power consumption. Taking the Mobile Industry Processor Interface (MIPI) processor as an example, its power consumption constitutes a large proportion of the overall system power consumption. The MIPI processor is a processor compliant with the MIPI transmission interface standard, comprising both MIPI software and hardware modules.

[0052] In related technologies, when the system is in a relatively idle or low-load state, a detection and judgment mechanism is used to determine whether the conditions for entering the Low Power State (ULPS) are met. Once met, relevant control signals and circuits are triggered, putting the MIPI processor into the ULPS state. In the ULPS state, the MIPI processor reduces its clock frequency, decreases signal transmission activity, and shuts down unnecessary circuit modules, thereby reducing power consumption.

[0053] However, in the aforementioned related technologies, when new data to be displayed is generated in the electronic device, the graphics processor sends an exit ULPS command to the display interface processor (MIPI). The MIPI processor then responds to this command and exits the ULPS state. Simultaneously, after a forced wait of a certain time (e.g., 1ms), the display controller sends the data to be displayed to the display driver chip via the MIPI processor. Figure 1 A timing diagram 100 for displaying data transmission is shown in the related art. For example... Figure 1 As shown, the timing diagram 100 for display data transmission includes the rendering timing of the graphics processor and the display sending timing of the display controller. The rendering timing indicates the time points at which the graphics processor in the electronic device processes graphics display tasks; the display sending timing indicates the time points at which the display controller in the electronic device sends display data to the display device. At this time, since the MIPI processor is in a low-power state (ULPS), if the rendering thread receives a display sending command at time T1, the graphics processor will send an exit ULPS command to the MIPI processor. Upon receiving the exit ULPS command, the MIPI processor immediately executes the exit command and exits the ULPS state of the MIPI processor. Subsequently, the graphics processor typically waits for 1ms before sending a transmission command to the display controller, allowing the display controller to begin the display sending task. Because the display controller's display sending timing is based on a fixed period for sending display data, that is, at time T2 after the rising edge of the pulse, the display controller sends the data to be displayed to the display driver chip through the MIPI processor. However, the MIPI processor has already exited ULPS at time T1, increasing the power consumption of the MIPI processor within (K+1)ms, thus resulting in high power consumption of the electronic device. At the same time, forcing the graphics processor to wait 1ms for an operation will also increase the load on the graphics processor, causing display data to be unable to be sent to the display device in a timely manner, thus resulting in a decrease in frame rate.

[0054] In view of this, embodiments of this application provide a display method and a display circuit. The display method is applied to a display circuit. The method includes: entering a signal transmission state when a low-power exit instruction is received first, followed by a first instruction; not entering the signal transmission state when a low-power exit instruction is received but the first instruction is not received; and if the signal transmission state is entered, sending data to be displayed to the display driver chip through a display interface processor. Specifically, when the display interface processor in the display circuit receives a low-power exit instruction, if it also receives a first instruction, the display interface processor responds to the low-power exit instruction and enters the signal transmission state. If only the low-power exit instruction is received and the first instruction is not received, the processor does not respond to the low-power exit instruction and does not enter the signal transmission state.

[0055] In the above process, after receiving the exit low-power command, the display interface processor, upon receiving the first command, enters the signal transmission state. At this time, the display controller sends the data to be displayed to the display driver chip through the display interface processor. Unlike related technologies, the display interface processor does not immediately respond and enter the signal transmission state upon receiving the exit low-power command; instead, it responds and enters the signal transmission state upon receiving the first command. This timing of controlling the display circuit to enter the signal transmission state extends the time the display interface processor remains in the low-power state, reducing the power consumption of the display interface processor and thus reducing the power consumption of the electronic device.

[0056] Secondly, the system architecture of the embodiments of this application will be described by way of example.

[0057] For example, Figure 2 A schematic diagram of the structure of an electronic device 200 provided in an embodiment of this application is shown, with a smartwatch as an example for illustration. Figure 2 As shown, the electronic device 200 includes a processor 210, a memory 220, a multimedia component 230, and a sensor component 240.

[0058] The memory 220 includes internal memory and external memory. The internal memory may be RAM and integrated with the processor 210. The memory 220 stores data, software programs, and various software modules, primarily including a program storage area and a data storage area. The program storage area can store the operating system and at least one application program required to implement functional modules; the data storage area can store various data created according to the usage status of the electronic device 200, such as audio data, display data, or spreadsheet data. The memory 220 may also include high-speed random access memory or non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0059] Processor 210 is the control center of electronic device 200. It connects various parts of the device via different interfaces and lines, and implements various functions of electronic device 200 by running or executing applications stored in memory 220 and accessing various data in memory 220. Processor 210 typically includes one or more processing units. In this embodiment, processor 210 may include a central processing unit (CPU) and a graphics processing unit (GPU). Optionally, processor 210 may also include an application processor (AP), a modem processor, an image signal processor (ISP), a controller, a video playback codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU), etc.

[0060] Multimedia component 230 includes a display screen and audio / video components. The display screen may be a touch panel, including one or more touch sensors for receiving user input signals, such as swiping, touching, or clicking on the display screen. The display screen also receives and displays data to be displayed. Furthermore, when the electronic device is in video playback mode, the audio / video components can support video playback.

[0061] Sensor assembly 240 includes one or more sensors, such as power consumption sensors and application sensors, for providing status assessments of various aspects of the electronic device. Sensor assembly 240 can detect the electronic device's power consumption, orientation, on / off state, relative positioning of components, or temperature changes. Sensor assembly 240 may also include gyroscope sensors, magnetic sensors, pressure sensors, or temperature sensors. Furthermore, sensor assembly 240 may include scene sensors for detecting the application scenario of the electronic device, such as a 2D watch face, time display, fitness tracking, information display, mobile payment, mobile calling, video playback, music playback, or a 3D watch face.

[0062] Power supply 250 is used to provide power to the various components of the electronic device. Power supply 250 may include a power management system, one or more power supplies, or other components associated with the generation, management, and distribution of power by the electronic device.

[0063] The above Figure 2The illustrated electronic device also includes a display circuit 300. The display circuit 300 is responsible for display-related functions and can reduce the power consumption of the display interface processor, thereby reducing the power consumption of the electronic device 200.

[0064] For example, Figure 3 A schematic diagram of a display circuit 300 provided in an embodiment of this application is shown. Figure 3 As shown, the display circuit 300 includes a display controller 310, a display interface processor 320, and a display driver chip 330.

[0065] The display controller 310 can be a display subsystem (DSS). The DSS includes hardware components for managing and controlling the display system, as well as corresponding software drivers, comprising a video output processor (VOP) and encoders. The VOP reads image data from the video memory and can also process the image, such as color transformation, GAMA transformation, and image rotation. The encoder converts the data processed by the VOP into an output signal. The DSS is a crucial part of the electronic device responsible for processing and managing display-related functions. In this embodiment, the display controller 310 acquires data to be displayed. This data is the data that the display circuit 300 needs to transmit to the display screen for display.

[0066] In this embodiment, the display circuit 300 further includes a graphics processor 340; the graphics processor 340 may be a GPU, which can obtain the data to be displayed through rendering processing. In this embodiment, the display controller 310 can acquire the data to be displayed sent by the graphics processor 340.

[0067] The display interface processor 320 is a processor that conforms to transmission standards and protocols, specifically a MIPI processor or a high-definition multimedia interface (HDMI) processor. Taking the MIPI processor as an example, when the electronic device does not need to update display data or needs to enter a sleep state, it receives instructions from the power management system or external trigger instructions, such as entering power-saving mode or the display being turned off. At this time, the MIPI processor will enter a low-power state. When the MIPI processor is in a low-power state, it will reduce the clock frequency, reduce signal transmission activity, and shut down unnecessary circuit modules to reduce power consumption. Once the electronic device needs to update display data, and the MIPI processor is in a low-power state, it will receive an exit low-power instruction sent by the GPU. After receiving the exit low-power instruction, the MIPI processor will then receive the first instruction and, in response to the exit low-power instruction, enter the signal transmission state.

[0068] As can be seen from the above, when the MIPI processor receives the exit low-power instruction, it does not respond to the exit low-power instruction immediately. Instead, it responds and exits the low-power state after receiving the first instruction. Therefore, during the time period between receiving the exit low-power instruction and receiving the first instruction, the MIPI processor remains in the low-power state, which prolongs the time that the MIPI processor is in the low-power state and further reduces the power consumption of the MIPI processor.

[0069] If MIPI enters the signal transmission state, the display controller 310 acquires the data to be displayed and then receives a second instruction. The display controller 310 then sends the data to be displayed to the display driver chip 330 through the display interface processor 320.

[0070] Optionally, the display circuit 300 also includes a graphics processor 340, a signal generator 350, and a signal controller 360. The signal generator 350 generates a first pulse signal and a second pulse signal. For example, the signal generator 350 sends the first pulse signal to the display interface processor 320; the first pulse signal controls the display interface processor to respond to an exit low-power instruction, that is, the first instruction includes the rising edge or falling edge of the first pulse signal. The second pulse signal is sent to the display controller 310; the second pulse signal controls the display controller 310 to send data to be displayed, that is, the second instruction includes the rising edge or falling edge of the second pulse signal.

[0071] For example, when the display interface processor 320 is in a low-power state, it receives an exit low-power instruction sent by the GPU; the display interface processor 320 does not execute the exit instruction immediately. When the display interface processor 320 receives the first instruction, that is, when it detects the rising or falling edge of the first pulse signal, the display interface processor 320 responds to the exit low-power instruction and enters the signal sending state.

[0072] When the display interface processor 320 exits the low-power state, when the display controller 310 receives the second instruction, it sends the data to be displayed to the display driver chip 330 through the display interface processor 320; wherein, the second instruction includes the rising edge or falling edge of the second pulse signal.

[0073] Optionally, the display circuit 300 also includes a signal controller 360. The signal controller 360 is used to control the rising edge of the second pulse signal to be delayed compared to the rising edge of the first pulse signal.

[0074] For example, the signal controller 360 controls the rising edge of the second pulse signal to be delayed by a preset time interval equal to the rising edge of the first pulse signal, which is equal to the delay of the display interface processor 320. When the display interface processor 320 detects the rising edge of the first pulse signal, it responds by exiting the low-power instruction and entering the signal transmission state. Since the time interval between the rising edge of the second pulse signal and the rising edge of the first pulse signal is equal to the delay of the display interface processor 320, the display controller 320 can immediately send the data to be displayed through the display interface processor 320 when it starts to run smoothly. That is, when the display controller 310 receives the rising edge of the second pulse, the display controller 310 can send the data to be displayed through the display interface processor 320.

[0075] As shown above, the timing of the display interface processor exiting the low-power state is controlled by the first pulse signal, and it will not immediately execute the exit low-power command upon receiving it. Simultaneously, the time interval between the rising edge of the second pulse signal and the rising edge of the first pulse signal can be set via the GPU according to the hardware characteristics of the display controller. The preset time interval between the rising edge of the second pulse signal and the rising edge of the first pulse signal is equal to the latency of the display interface processor. Therefore, the CPU does not need to force the display interface processor to wait 1ms after exiting the low-power state before starting the display controller to send data, and it is not affected by CPU load. This not only extends the low-power state time of the MIPI processor and reduces the power consumption of the display interface processor, but also improves the display frame rate.

[0076] The display driver chip 330 can specifically be a display driver IC (DDIC), an integrated circuit chip specifically used to control and drive a display panel. Its main function is to convert the data to be displayed into electrical signals, ensuring that the image indicated by the data is clearly and accurately presented on the display screen. For example, the display controller sends the data to be displayed to the display driver chip 330 through the display interface processor at a second moment, enabling the data to be displayed.

[0077] Optionally, the display circuit 300 also includes a display screen connected to the display driver chip 330. The display screen is used to receive and display data to be displayed.

[0078] It should be noted that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0079] For ease of understanding, the display method provided in this application is described below with reference to the accompanying drawings. This display method is applicable to... Figure 3 The display circuit shown.

[0080] Figure 4 A schematic flowchart of a display method according to an embodiment of this application is shown. This display method can be applied to a display circuit and includes the following steps:

[0081] S101, upon receiving the exit low-power instruction first and then the first instruction, the display interface processor enters the signal sending state.

[0082] In this embodiment, the display controller acquires the data to be displayed before the display interface processor receives the exit low-power instruction. The display controller can acquire the data to be displayed when it receives an external trigger or when data needs to be displayed.

[0083] For example, the display controller can obtain the data to be displayed from the GPU. The data to be displayed includes data that the display circuitry needs to display on the display screen.

[0084] In one possible implementation, the display circuitry receives an exit low-power command from the graphics processor via the display interface processor; the display circuitry also receives a first command from the signal generator via the display interface processor.

[0085] For example, when the display interface processor is in a low-power state, it receives an exit low-power instruction sent by the graphics processor; and after receiving the exit low-power instruction, it receives a first instruction sent by the signal generator. In response to the exit low-power instruction, the display interface processor exits the low-power state and enters the signal transmission state.

[0086] In one possible implementation, the first instruction includes the rising edge or falling edge of the first pulse.

[0087] As can be seen from the above, when the first instruction includes either the rising edge or falling edge of the first pulse, it can periodically control the display interface processor. Upon receiving an exit low-power instruction, it responds to the exit low-power instruction and enters the signal transmission state. This improves the stability and autonomy of the display circuit entering the signal transmission state.

[0088] In one possible implementation, the display interface processor does not enter the transmit signal state if it receives an exit low-power instruction but does not receive the first instruction.

[0089] In other words, if the display interface processor receives an exit low-power instruction but has not received the first instruction, it will not respond to the exit low-power instruction and enter the signal transmission state. Therefore, it ensures that the display interface processor remains in a low-power state during the time between receiving the exit low-power instruction and receiving the first instruction, thus extending the time the display interface processor is in a low-power state and reducing the power consumption of the display interface processor.

[0090] As can be seen from the above, taking the MIPI processor as an example, which is the display interface processor. Figure 5 A timing diagram illustrating a response to an exit low-power instruction, as provided in an embodiment of this application, is shown. Figure 5 As shown, the first pulse signal is created by a signal generator and is used to control when the MIPI processor responds to the exit low-power instruction. If the MIPI processor receives the exit instruction sent by the GPU at time T0, the MIPI processor saves the exit instruction and does not execute it yet. When the MIPI processor reaches the first instruction, which is the rising edge of the first pulse signal, the MIPI executes the saved exit low-power instruction and enters the send signal state.

[0091] S102, if entering the signal transmission state, send the data to be displayed.

[0092] In one possible implementation, the display circuit acquires the data to be displayed through the display controller, and upon receiving a second instruction, the display controller sends the data to be displayed through the display interface processor.

[0093] When the display controller receives an external trigger or needs to display data, it can acquire the data to be displayed.

[0094] For example, after the display interface processor enters the signal transmission state, when the display controller receives the second instruction, the display controller sends the data to be displayed to the display driver chip through the display interface processor.

[0095] In one possible implementation, the display circuitry receives a second instruction from the signal generator via a display controller.

[0096] Optionally, the second instruction may include the rising edge or falling edge of the second pulse.

[0097] As can be seen from the above, when the second instruction includes the rising edge or falling edge of the second pulse, it can periodically detect whether the display controller needs to send the data to be displayed, thereby improving the stability and autonomy of the data to be displayed transmission.

[0098] In one possible implementation, the rising edge of the second pulse signal is delayed compared to the rising edge of the first pulse signal.

[0099] For example, the display circuit controls the rising edge of the second pulse signal to be delayed by a preset time interval equal to the rising edge of the first pulse signal, through a signal controller.

[0100] For example, the signal controller controls the rising edge of the second pulse signal to be delayed by a preset time interval of 0.8ms from the rising edge of the first pulse signal, while the display interface processor's latency is also 0.8ms. If the display interface processor receives an exit low-power command before receiving the rising edge of the first pulse signal, it will respond to the exit low-power command upon receiving the rising edge of the first pulse signal. At this point, due to hardware latency, the display interface processor needs to enter the signal transmission state 0.8ms after exiting the low-power state. Since the time between the rising edge of the second pulse signal and the rising edge of the first pulse signal is equal to the display interface processor's latency, meaning that the display controller starts running smoothly 0.8ms later, it receives the rising edge of the second pulse and can then send the data to be displayed through the display interface processor.

[0101] As shown above, the timing of the display interface processor exiting the low-power state is controlled by the first pulse signal, and it will not immediately execute the exit low-power command upon receiving it. Simultaneously, the time interval between the rising edge of the second pulse signal and the rising edge of the first pulse signal can be set via the GPU according to the hardware characteristics of the display controller. The preset time interval between the rising edge of the second pulse signal and the rising edge of the first pulse signal is equal to the latency of the display interface processor. Therefore, the CPU does not need to force the display interface processor to wait 1ms after exiting the low-power state before starting the display controller to send data, and it is not affected by CPU load. This not only extends the time the display interface processor is in the low-power state and reduces its power consumption, but also improves the display frame rate.

[0102] In another possible implementation, the signal generator produces a third pulse signal and sends the third pulse signal to the graphics processor.

[0103] The third pulse is used to control the GPU to process the data to be displayed.

[0104] For example, the GPU can send a periodic instruction to a signal generator, causing the signal generator to create a first pulse, a second pulse, and a third pulse of a specified period.

[0105] for example, Figure 6 This illustration shows a pulse signal provided in an embodiment of this application, such as... Figure 6 As shown, the pulse generator creates three different pulse signals: the first pulse signal, the second pulse signal, and the third pulse signal.

[0106] In one possible implementation, the pulse controller controls the rising edge of the second pulse signal to be synchronized with or later than the rising edge of the first pulse signal. For example, the time interval between the rising edges of the second and first pulse signals can be set by the GPU. During this time interval, the display controller can begin smooth operation, satisfying the operational state for sending data to be displayed.

[0107] In another possible implementation, the pulse controller synchronizes the rising edge of the third pulse signal with the rising edge of the first pulse signal.

[0108] In one possible implementation, the display interface processor includes a Mobile Industry Interface (MIPI) processor or a High Definition Multimedia Interface (HDMI) processor.

[0109] Figure 7 This illustration shows a timing diagram of data transmission to be displayed, provided in an embodiment of this application. For example... Figure 7As shown, the timing diagram for transmitting the data to be displayed includes a first pulse signal, a second pulse signal, and a third pulse signal. These three pulse signals are created by a signal generator. The first pulse signal controls when the display interface processor responds to an exit low-power instruction; that is, the first instruction includes the rising edge of the first pulse signal. The second pulse signal controls when the display controller sends the data to be displayed; that is, the second instruction includes the rising edge of the second pulse signal. The third pulse signal controls the GPU to process the data to be displayed.

[0110] The time interval P between the rising edge of the second pulse signal and the rising edge of the first pulse signal can be set by the GPU; the signal controller keeps the time interval P between the rising edge of the second pulse signal and the rising edge of the first pulse signal constant. The signal controller also controls the rising edge of the third pulse signal to arrive synchronously with the rising edge of the first pulse signal.

[0111] Taking a display interface processor (MIPI processor), a display controller (DSS), and a display driver chip (DDIC) as an example: At time T0, the GPU receives the display data processing task, and the DSS can obtain the data to be displayed from the GPU. At this time, the MIPI processor is in a low-power state. At time T0, the MIPI processor receives an exit low-power instruction sent by the GPU, but the MIPI processor does not execute the exit instruction. Upon receiving the first instruction, i.e., the rising edge of the first pulse signal, the MIPI processor responds to the exit low-power instruction and exits the low-power state. When the DSS receives the second signal, i.e., the rising edge of the second pulse signal, the DSS sends the data to be displayed to the DDIC.

[0112] In the above method, the timing of the MIPI processor's low-power state is controlled by the first pulse signal, and it will not immediately execute the exit low-power instruction at time T0 upon receiving the exit instruction. Simultaneously, the time interval P between the rising edge of the second pulse signal and the rising edge of the first pulse signal can be set by the GPU according to the hardware characteristics of the DSS. Therefore, the CPU does not need to force the MIPI processor to wait 1ms after exiting the low-power state before starting DSS display, and it is not affected by CPU load. Thus, maintaining the low-power state during the time period from time T0 to the moment the first instruction is received extends the low-power state time of the MIPI processor, not only reducing the MIPI processor's power consumption but also improving the display frame rate.

[0113] S103, the display screen receives and displays the data to be displayed.

[0114] In this embodiment of the application, the display circuit also includes a display screen connected to the display driver chip.

[0115] For example, the display driver chip receives the data to be displayed sent by the display controller, the display driver chip sends the data to be displayed to the display screen, the display screen receives the data to be displayed and displays the data to be displayed, thus completing the display of the data to be displayed.

[0116] In summary, this application provides a display method applied in a display circuit. The method includes: entering a signal transmission state when a low-power exit instruction is received first, followed by a first instruction; not entering the signal transmission state when a low-power exit instruction is received but the first instruction is not received; and if the signal transmission state is entered, sending data to be displayed to the display driver chip via a display interface processor. Specifically, when the display interface processor in the display circuit receives a low-power exit instruction, if it then receives the first instruction, the display interface processor responds to the low-power exit instruction and enters the signal transmission state. If the first instruction is not received, it does not respond to the low-power exit instruction and does not enter the signal transmission state. As can be seen, when the display interface processor receives a low-power exit instruction, it does not immediately respond and enter the signal transmission state; instead, it responds and enters the signal transmission state only after receiving the first instruction, thus controlling the timing of the display circuit entering the signal transmission state. This extends the time the display interface processor is in a low-power state, reduces the power consumption of the display interface processor, and consequently reduces the power consumption of the electronic device.

[0117] This application also provides an electronic device, which includes... Figure 2 The diagram shows a display circuit and a display screen. The display screen is used to display data to be displayed. The electronic device also includes a memory and one or more processors; the memory is coupled to the processors; wherein the memory stores computer program code, which includes computer instructions, and when the computer instructions are executed by the processor, the electronic device performs the relevant method steps in the above method embodiments.

[0118] This application also provides a computer-readable storage medium storing computer program code. When the processor executes the computer program code, the electronic device executes the relevant method steps in the above method embodiments.

[0119] This application also provides a computer program product that, when run on a computer, causes the computer to execute the relevant method steps described in the above method embodiments.

[0120] This application also provides a chip system, including: a processor coupled to a memory, the memory being used to store programs or instructions, and when the program or instructions are executed by the processor, the chip system enables the methods in any of the above method embodiments.

[0121] Optionally, the chip system may contain one or more processors. These processors can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor, implemented by reading software code stored in memory.

[0122] Optionally, the chip system may contain one or more memories. The memory may be integrated with the processor or disposed separately from it; this application embodiment does not limit this. For example, the memory may be a non-transient processor, such as a read-only memory (ROM), which may be integrated with the processor on the same chip or disposed separately on different chips. This application embodiment does not specifically limit the type of memory or the arrangement of the memory and processor.

[0123] For example, the chip system can be a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0124] The electronic devices, computer storage media, or computer program products provided in this application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0125] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0127] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units, located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0128] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0129] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the contributing parts, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0130] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display method, characterized in that, The display method is applied to a display circuit, and the method includes: If the low-power exit command is received first, and then the first command is received, the signal transmission state is entered. If the exit low-power instruction is received, but the first instruction is not received, the system will not enter the signal transmission state. If the signal transmission state is entered, the data to be displayed will be sent.

2. The display method according to claim 1, characterized in that, The first instruction includes the rising edge or falling edge of the first pulse.

3. The display method according to claim 1 or 2, characterized in that, The method further includes: Receive the exit low-power instruction sent by the graphics processor; Receive the first instruction sent by the signal generator.

4. The display method according to any one of claims 1-3, characterized in that, If the signal transmission state is entered, the data to be displayed is transmitted, including: Upon acquiring the data to be displayed and receiving the second instruction, the data to be displayed is sent through the display interface processor.

5. The display method according to claim 4, characterized in that, The second instruction includes the rising edge or falling edge of the second pulse.

6. The display method according to claim 4 or 5, characterized in that, The method further includes: Receive the second instruction sent by the signal generator.

7. The display method according to claim 5, characterized in that, The rising edge of the second pulse signal is delayed compared to the rising edge of the first pulse signal.

8. The display method according to claim 7, characterized in that, The rising edge of the second pulse signal is delayed compared to the rising edge of the first pulse signal, including: The signal controller controls the rising edge of the second pulse signal to be delayed by a preset time interval equal to the rising edge of the first pulse signal, which is equal to the delay of the display interface processor.

9. A display circuit, characterized in that, The display circuit is used in electronic devices, and the display circuit includes a display controller and a display interface processor; The display interface processor is configured to enter a signal transmission state when it first receives an exit low-power instruction and then receives a first instruction; and not enter a signal transmission state when it receives the exit low-power instruction but does not receive the first instruction. The display controller is used to send data to be displayed if it enters the signal sending state.

10. The display circuit according to claim 9, characterized in that, The first instruction includes the rising edge or falling edge of the first pulse.

11. The display circuit according to claim 9 or 10, characterized in that, The display circuit also includes a signal generator, which is connected to the display interface processor. The display interface processor is also configured to receive the exit low-power instruction sent by the graphics processor; The display interface processor is also configured to receive the first instruction sent by the signal generator.

12. The display circuit according to any one of claims 9-11, characterized in that, The display controller is configured to send data to be displayed if it enters a signal transmission state, including: The display controller is used to acquire the data to be displayed, and after receiving the second instruction, to send the data to be displayed through the display interface processor.

13. The display circuit according to claim 12, characterized in that, The second instruction includes the rising edge or falling edge of the second pulse.

14. The display circuit according to claim 12 or 13, characterized in that, The display circuit also includes a signal generator, which is connected to the display controller. The display controller is also configured to receive the second instruction sent by the signal generator.

15. The display circuit according to claim 13, characterized in that, The rising edge of the second pulse signal is delayed compared to the rising edge of the first pulse signal.

16. The display circuit according to claim 15, characterized in that, The display circuit also includes a signal controller, which is connected to the signal generator. The signal controller is configured to control the rising edge of the second pulse signal to be delayed by a preset time interval equal to the rising edge of the first pulse signal, which is equal to the delay of the display interface processor.

17. The display circuit according to any one of claims 9-16, characterized in that, The display interface processor includes a Mobile Industry Interface (MIPI) processor or a High Definition Multimedia Interface (HDMI) processor.

18. An electronic device, characterized in that, The electronic device includes a display circuit and a display screen, the display screen being used to receive and display the data to be displayed; the display circuit includes the display circuit as described in any one of claims 9-17.

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