Display device and electronic device including the same

Abstract

A display device and an electronic apparatus including the same are disclosed. The display device includes: a display panel including pixels; a scan driver configured to provide a first scan signal and a second scan signal to the pixels; and a controller configured to provide a first scan control signal for generating the first scan signal and a second scan control signal for generating the second scan signal to the scan driver, the second scan signal includes an active pulse in an active period having a constant time length and at least one dummy pulse in a vertical blanking period having a variable time length, and wherein the second scan signal includes an active pulse in an active period having a constant time length, an interval between the effective pulse of the second scan signal and the first dummy pulse is different from an interval between the first dummy pulse and the second dummy pulse of the second scan signal.

Description

Technical Field

[0001] Some aspects of embodiments of this disclosure relate to display devices and electronic devices including the display devices. Background Technology

[0002] The display device may include a display panel, a scan driver, and a controller. The display panel may include pixels for displaying images. The scan driver may provide scan signals to the pixels. The controller may provide scan control signals to the scan driver for generating scan signals.

[0003] The display device can be driven in Variable Refresh Rate (VRR) mode, in which the driving frequency of the display panel can be changed. When the display device displays moving images, the driving frequency of the display panel can be increased to relatively improve the image quality of the display device. When the display device displays still images, the driving frequency of the display panel can be decreased to reduce the power consumption of the display device.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0005] Some aspects of embodiments of this disclosure relate to display devices and electronic devices including the display devices. For example, some aspects of embodiments of this disclosure relate to display devices driven by variable refresh rates and electronic devices including the display devices.

[0006] Some embodiments include a display device having relatively improved display quality and an electronic device including the display device.

[0007] A display device according to some embodiments includes: a display panel including pixels; a scan driver providing a first scan signal and a second scan signal to the pixels; and a controller providing the scan driver with a first scan control signal for generating the first scan signal and a second scan control signal for generating the second scan signal. According to some embodiments, the second scan signal includes a valid pulse located in an effective time period having a constant duration and at least one dummy pulse located in a vertical blanking time period having a variable duration. According to some embodiments, the interval between the valid pulse and the first dummy pulse of the second scan signal is different from the interval between the first dummy pulse and the second dummy pulse of the second scan signal.

[0008] According to some embodiments, the interval between the first dummy pulse and the second dummy pulse of the second scan signal can be equal to the interval between the second dummy pulse and the third dummy pulse of the second scan signal.

[0009] According to some embodiments, the interval between the effective pulse of the second scan signal and the first dummy pulse can be greater than the interval between the first dummy pulse and the second dummy pulse of the second scan signal.

[0010] According to some embodiments, the interval between the first dummy pulse and the second dummy pulse of the second scan signal may be different from the interval between the second dummy pulse and the third dummy pulse of the second scan signal.

[0011] According to some embodiments, the interval between the effective pulse of the second scan signal and the first dummy pulse can be greater than the interval between the first dummy pulse and the second dummy pulse of the second scan signal.

[0012] According to some embodiments, the interval between the first dummy pulse and the second dummy pulse of the second scan signal can be greater than the interval between the second dummy pulse and the third dummy pulse of the second scan signal.

[0013] According to some embodiments, a pixel may include: a first transistor including a gate connected to a first node, a first terminal receiving a first power voltage, and a second terminal connected to a second node; a second transistor including a gate receiving a first scan signal, a first terminal receiving a data voltage, and a second terminal connected to the first node; a third transistor including a gate receiving a second scan signal, a first terminal receiving a reference voltage, and a second terminal connected to the second node; a capacitor including a first terminal connected to the first node and a second terminal connected to the second node; and a light-emitting diode including a first terminal connected to the second node and a second terminal receiving a second power voltage.

[0014] According to some embodiments, the capacitor can store the difference between the data voltage and the reference voltage in response to pulses of the first scan signal and effective pulses of the second scan signal during the effective period. During the vertical blanking period, the reference voltage can be applied to the second node in response to at least one dummy pulse of the second scan signal.

[0015] According to some embodiments, the voltage level of the reference voltage can be lower than the voltage level of the threshold voltage of the light-emitting diode.

[0016] According to some embodiments, the first scan signal may include a pulse located in the effective time period and has a deactivation level in the vertical blanking time period.

[0017] A display device according to some embodiments includes: a display panel including pixels; a scan driver providing a first scan signal and a second scan signal to the pixels; and a controller providing the scan driver with a first scan control signal for generating the first scan signal and a second scan control signal for generating the second scan signal. According to some embodiments, the second scan control signal includes a valid pulse group comprising a plurality of continuous pulses located in an effective time period having a constant duration and at least one dummy pulse group comprising a plurality of continuous pulses located in a vertical blanking time period having a variable duration. According to some embodiments, the interval between the valid pulse group and the first dummy pulse group of the second scan control signal is different from the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal.

[0018] According to some embodiments, the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal can be equal to the interval between the second dummy pulse group and the third dummy pulse group of the second scan control signal.

[0019] According to some embodiments, the interval between the effective pulse group and the first dummy pulse group of the second scan control signal can be greater than the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal.

[0020] According to some embodiments, the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal may be different from the interval between the second dummy pulse group and the third dummy pulse group of the second scan control signal.

[0021] According to some embodiments, the interval between the effective pulse group and the first dummy pulse group of the second scan control signal can be greater than the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal.

[0022] According to some embodiments, the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal can be greater than the interval between the second dummy pulse group and the third dummy pulse group of the second scan control signal.

[0023] According to some embodiments, a pixel may include: a first transistor including a gate connected to a first node, a first terminal receiving a first power voltage, and a second terminal connected to a second node; a second transistor including a gate receiving a first scan signal, a first terminal receiving a data voltage, and a second terminal connected to the first node; a third transistor including a gate receiving a second scan signal, a first terminal receiving a reference voltage, and a second terminal connected to the second node; a capacitor including a first terminal connected to the first node and a second terminal connected to the second node; and a light-emitting diode including a first terminal connected to the second node and a second terminal receiving a second power voltage.

[0024] According to some embodiments, the first scan control signal may include a pulse group comprising a plurality of consecutive pulses located in the effective time period, and has a deactivation level in the vertical blanking time period.

[0025] An electronic device according to some embodiments includes: the display device described above; and a processor that provides a controller with control signals for generating a first scan control signal and a second scan control signal.

[0026] In display devices and electronic devices according to some embodiments, the interval between the effective pulse of the second scan signal and the first dummy pulse is greater than the interval between the first dummy pulse and the second dummy pulse of the second scan signal, so that the maximum brightness deviation between frequencies can be reduced, and correspondingly, the image quality of the display device can be relatively improved. Attached Figure Description

[0027] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating a display device according to some embodiments.

[0029] Figure 2 It is shown Figure 1 The circuit diagram of the pixels.

[0030] Figure 3 It is used to describe Figure 1 A diagram showing the variable refresh rate mode of the display device.

[0031] Figure 4 It is a timing diagram used to describe the operation of pixels at the first and second frequencies according to the comparison example.

[0032] Figure 5 This is a timing diagram showing the brightness of a display device at a first frequency and a second frequency according to a comparative example.

[0033] Figure 6 It is a timing diagram used to describe the operation of the pixels in the comparison example at the second frequency.

[0034] Figure 7 This is a timing diagram showing the brightness of a display device at a second frequency according to a comparative example.

[0035] Figure 8 This is a schematic diagram illustrating the relationship between frequency and brightness of a display device according to a comparative example.

[0036] Figure 9This is a timing diagram illustrating a first scan control signal, a second scan control signal, a first scan signal, and a second scan signal according to some embodiments.

[0037] Figure 10 This is a schematic diagram illustrating the relationship between the frequency and brightness of a display device according to some embodiments.

[0038] Figure 11 This is a timing diagram illustrating a first scan control signal, a second scan control signal, a first scan signal, and a second scan signal according to some embodiments.

[0039] Figure 12 This is a block diagram illustrating an electronic device according to some embodiments.

[0040] Figure 13 It is shown Figure 12 The diagram shows an example of an electronic device implemented as a computer monitor. Detailed Implementation

[0041] In the following, display devices and electronic devices according to some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals will be used for the same elements in the drawings.

[0042] Figure 1 This is a block diagram illustrating a display device 100 according to some embodiments.

[0043] refer to Figure 1 The display device 100 may include a display panel 110, a data driver 120, a scan driver 130, and a controller 140.

[0044] The display panel 110 may include multiple data lines, multiple first scan lines, multiple second scan lines, and multiple pixels (PX). Although Figure 1 The illustration shows a single pixel PX, but as those skilled in the art will understand, the display device 100 may include any suitable number of pixels PX depending on its design and size. A data line may provide a data voltage DV to the pixel PX. A first scan line may provide a first scan signal S1 to the pixel PX. A second scan line may provide a second scan signal S2 to the pixel PX. The pixel PX may emit light in response to the data voltage DV, the first scan signal S1, and the second scan signal S2.

[0045] The display panel 110 may further include multiple reference voltage lines. These reference voltage lines can provide a reference voltage to the pixel PX. According to some embodiments, the reference voltage lines can be used as sensing lines for sensing characteristics of the pixel PX.

[0046] Data driver 120 can provide a data voltage DV to pixel PX via a data line. Data driver 120 can generate the data voltage DV based on a data control signal DCTRL and output image data ODAT. According to some embodiments, the data control signal DCTRL may include an output data enable signal, a level start signal, and a load signal. According to some embodiments, data driver 120 can receive output image data ODAT at a drive frequency DF that is variable within a range (e.g., a set or predetermined range).

[0047] According to some embodiments, the data driver 120 and the controller 140 can be implemented as a single integrated circuit, and such integrated circuit can be referred to as a timing controller embedded data driver (TED). According to some embodiments, the data driver 120 and the controller 140 can be implemented as separate integrated circuits.

[0048] The scan driver 130 can sequentially provide a first scan signal S1 to pixel PX via a first scan line in pixel rows, and can also sequentially provide a second scan signal S2 to pixel PX via a second scan line in pixel rows. The scan driver 130 can generate the first scan signal S1 based on a first scan control signal SCTRL1, and can generate the second scan signal S2 based on a second scan control signal SCTRL2.

[0049] According to some embodiments, the scan driver 130 may be formed or mounted in the peripheral area of ​​the display panel 110. According to some embodiments, the scan driver 130 may be implemented as at least one integrated circuit.

[0050] Controller 140 can control the operation (or drive) of data driver 120 and scan driver 130. Controller 140 can provide output image data ODAT and data control signal DCTRL to data driver 120, and can provide a first scan control signal SCTRL1 and a second scan control signal SCTRL2 to scan driver 130. Controller 140 can generate output image data ODAT, data control signal DCTRL, first scan control signal SCTRL1, and second scan control signal SCTRL2 based on input image data IDAT and control signal CTRL. According to some embodiments, input image data IDAT may include red image data, green image data, and blue image data. According to some embodiments, control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a master clock signal. Controller 140 can receive input image data IDAT and control signal CTRL from an external host processor.

[0051] The host processor can change the length of the vertical blanking period for each frame segment to provide input image data IDAT to the controller 140 at a variable input frame rate (VIFF) that varies within a range (e.g., a set or predetermined range). The controller 140 can control the data driver 120 and the scan driver 130 to drive the display panel 110 at a drive frequency DF corresponding to the variable input frame rate (VIFF). In other words, the drive frequency DF of the display panel 110 can be determined as the variable input frame rate (VIFF). According to some embodiments, the mode in which the display device 100 drives the display panel 110 with the variable input frame rate (VIFF) can be referred to as a variable refresh rate (VRR) mode. The variable refresh rate mode can be a free sync mode, a G-sync mode, etc., but is not limited to these.

[0052] Figure 2 This illustrates some embodiments. Figure 1 The circuit diagram of the pixel PX aspect. Although Figure 2 The figures illustrate various components in a pixel PX according to some embodiments, but the embodiments of this disclosure are not limited thereto, and the pixel PX may include additional or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0053] refer to Figure 1 and Figure 2 Pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a capacitor CST, and a light-emitting diode (LED). Pixel PX may receive a first scan signal S1, a second scan signal S2, a data voltage DV, a reference voltage VREF, a first power voltage ELVDD, and a second power voltage ELVSS. According to some embodiments, the voltage level of the first power voltage ELVDD may be higher than the voltage level of the second power voltage ELVSS. According to some embodiments, the voltage level of the reference voltage VREF may be lower than the threshold voltage level of the LED.

[0054] The first transistor T1 can generate a drive current corresponding to the voltage difference between the first node NG and the second node NS. The first transistor T1 may include a gate connected to the first node NG, a first terminal (e.g., drain) receiving a first power voltage ELVDD, and a second terminal (e.g., source) connected to the second node NS.

[0055] The second transistor T2 can transmit the data voltage DV to the first node NG in response to the first scan signal S1. The second transistor T2 may include a gate for receiving the first scan signal S1, a first terminal (e.g., drain) connected to the data line DL for transmitting the data voltage DV, and a second terminal (e.g., source) connected to the first node NG.

[0056] The third transistor T3 can transmit a reference voltage VREF to the second node NS in response to the second scan signal S2. The third transistor T3 may include a gate receiving the second scan signal S2, a first terminal (e.g., drain) connected to the reference voltage line VREFL through which the reference voltage VREF is transmitted, and a second terminal (e.g., source) connected to the second node NS. According to some embodiments, the third transistor T3 can transmit a voltage at the second node NS that reflects the characteristics of the first transistor T1 or the light-emitting diode (LED) to the reference voltage line VREFL in response to the second scan signal S2.

[0057] According to some embodiments, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be an NMOS transistor. According to some embodiments, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be a PMOS transistor.

[0058] A capacitor CST can be connected between a first node NG and a second node NS. The capacitor CST may include a first terminal connected to the first node NG and a second terminal connected to the second node NS.

[0059] The light-emitting diode (LED) may include a first terminal (e.g., anode) connected to the second node NS and a second terminal (e.g., cathode) receiving a second power voltage ELVSS. The LED may emit light with a brightness corresponding to the drive current generated by the first transistor T1.

[0060] Figure 3 It is used to describe Figure 1 A diagram of the variable refresh rate mode of the display device 100.

[0061] refer to Figure 1 and Figure 3 The time periods or frequencies of the host processor's rendering 210 and rendering 220 may not be constant, and the host processor can provide input image data IDAT (i.e., frame data FD1 and FD2) to the display device 100 in a variable refresh rate mode in sync with the non-constant time periods or frequencies of rendering 210 and rendering 220. In the variable refresh rate mode, each frame time period FP1 and FP2 may have valid time periods AP1 and AP2 containing constant durations, and the host processor can provide frame data FD1 and FD2 to the display device 100 at a variable input frame frequency VIFF by changing the durations of the vertical blanking time periods VBP1 and VBP2 of each frame time period FP1 and FP2.

[0062] like Figure 3As illustrated, during the first frame period FP1, when the second frame data FD2 is rendered at the first frequency FRQ1 (i.e., rendering 210), the host processor can provide the first frame data FD1 to the display device 100 at a variable input frame rate (VIFF) of the first frequency FRQ1. Furthermore, the host processor can output the second frame data FD2 during the effective period AP2 of the second frame period FP2, and can continue the vertical blanking period VBP2 of the second frame period FP2 until the rendering of the third frame data FD3 is completed (220). Correspondingly, during the second frame period FP2, when the third frame data FD3 is rendered at a second frequency FRQ2 (i.e., rendering 220) lower than the first frequency FRQ1, the host processor can increase the duration of the vertical blanking period VBP2 of the second frame period FP2 to provide the second frame data FD2 to the display device 100 at a variable input frame rate (VIFF) of the second frequency FRQ2.

[0063] In variable refresh rate mode, each frame period FP1 and FP2 may include effective periods AP1 and AP2 with constant durations independent of the variable input frame rate VIFF, and vertical blanking periods VBP1 and VBP2 with variable durations corresponding to the variable input frame rate VIFF. For example, in variable refresh rate mode, as the variable input frame rate VIFF decreases, the durations of the vertical blanking periods VBP1 and VBP2 may increase. In variable refresh rate mode, controller 140 may output input image data IDAT received at the variable input frame rate VIFF as output image data ODAT to data driver 120 at a drive frequency DF substantially equal to the variable input frame rate VIFF. Accordingly, the display device 100 supporting variable refresh rate mode can display images synchronously with the variable input frame rate VIFF to prevent or reduce tearing caused by frame rate mismatch.

[0064] Figure 4 It is a timing diagram used to describe the operation of pixel PX according to the comparison example at the first frequency FRQ1 and the second frequency FRQ2.

[0065] refer to Figure 2 and Figure 4Pixel PX can simultaneously receive pulses of the first scan signal S1 and the second scan signal S2 during each effective time period AP1 and AP2. When the pulses of the first scan signal S1 and the second scan signal S2 are applied to pixel PX, the data voltage DV can be applied to the first node NG (i.e., the first terminal of capacitor CST), and the reference voltage VREF can be applied to the second node NS (i.e., the second terminal of capacitor CST). Accordingly, when the pulses of the first scan signal S1 and the second scan signal S2 are applied to pixel PX, capacitor CST can store the difference between the data voltage DV and the reference voltage VREF. When the pulses of the first scan signal S1 and the second scan signal S2 are applied to pixel PX, the light-emitting diode LED can not emit light because the second node NS connected to the first terminal of the light-emitting diode LED has the reference voltage VREF.

[0066] like Figure 4 As illustrated, the pulses of the first scan signals S1_1, ..., S1_N and the pulses of the second scan signals S2_1, ..., S2_N can be sequentially provided to pixel PX on a pixel-row basis during each effective time period AP1 and AP2. Accordingly, when the pulses of the first scan signals S1_1, ..., S1_N and the pulses of the second scan signals S2_1, ..., S2_N are applied to pixel PX during each effective time period AP1 and AP2, the third transistor T3 of pixel PX can apply a reference voltage VREF to the second node NS, and the voltages V_NS_1, ..., V_NS_N of the second node NS can change from the first power supply voltage ELVDD to the reference voltage VREF. Because the voltages V_NS_1, ..., V_NS_N of the second node NS have the reference voltage VREF, the light-emitting diode (LED) of pixel PX may not emit light. Accordingly, when the pulses of the first scan signal S1_1, ..., S1_N and the pulses of the second scan signal S2_1, ..., S2_N are applied to pixel PX in each effective time period AP1 and AP2, the light-emitting diode (LED) may not emit light.

[0067] The durations of the vertical blanking periods VBP1 and VBP2 can be varied according to the driving frequency DF of the display panel 110. When the display panel 110 is driven at a first frequency FRQ1, the duration of the vertical blanking period VBP1 can differ from the duration of the vertical blanking period VBP2 when the display panel 110 is driven at a second frequency FRQ2, which is different from the first frequency FRQ1. Within the same duration, the number of times pulses of the first scan signal S1 and the second scan signal S2 are applied to pixel PX (i.e., the number of times the light-emitting diode (LED) is turned off) when the display panel 110 is driven at the first frequency FRQ1 can differ from the number of times pulses of the first scan signal S1 and the second scan signal S2 are applied to pixel PX when the display panel 110 is driven at the second frequency FRQ2. Accordingly, even if the display device according to the comparative example displays an image with the same grayscale, the brightness of the display panel 110 may change when the driving frequency DF of the display panel 110 changes, and flickering may occur.

[0068] Figure 5 This is a timing diagram showing the brightness of a display device according to a comparative example at a first frequency FRQ1 and a second frequency FRQ2.

[0069] refer to Figure 5 In the display device according to the comparative example, within the same time length, the light-emitting diodes (LEDs) of the display panel 110 driven at a first frequency FRQ1 (e.g., about 240 Hz) can be turned off approximately four times, and the LEDs of the display panel 110 driven at a second frequency FRQ2 (e.g., about 60 Hz) can be turned off approximately once. Accordingly, the average brightness AVGLUM2 of the display panel 110 driven at the second frequency FRQ2 (e.g., 2.1 nits) can be higher than the average brightness AVGLUM1 of the display panel 110 driven at the first frequency FRQ1 (e.g., 1.6 nits).

[0070] Figure 6 This is a diagram used to describe the operation of pixel PX at the second frequency FRQ2 according to the comparison example.

[0071] refer to Figure 2 and Figure 6 To prevent or reduce the increase in brightness of the display panel 110 at low frequencies, in the display device according to the comparative example, a first scan signal S1 can be provided to the pixel PX at a driving frequency DF, and a second scan signal S2 can be provided to the pixel PX at a maximum driving frequency (e.g., a first frequency FRQ1). According to some embodiments, the driving of providing the second scan signal S2 to the pixel PX at the maximum driving frequency can be referred to as a dummy shutdown drive.

[0072] like Figure 6As illustrated, when the display panel 110 is driven at a second frequency FRQ2, which is lower than the first frequency FRQ1 (the maximum driving frequency), the pulses of the first scan signals S1_1, ..., S1_N and the effective pulse PS_A of the second scan signals S2_1, ..., S2_N can be sequentially provided to pixel PX in pixel rows during the effective period AP2. The pulses of the first scan signals S1_1, ..., S1_N may not be provided to pixel PX during the vertical blanking period VBP2, and the dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N can be sequentially provided to pixel PX at least once in pixel rows during the vertical blanking period VBP2. For example, as... Figure 6 As illustrated, when the display panel 110 is driven at the second frequency FRQ2, the dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N can be provided to pixel PX three times during the vertical blanking period VBP2. Correspondingly, when the pulses of the first scan signals S1_1, ..., S1_N are not applied to pixel PX during the vertical blanking period VBP2, but the dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N are applied to pixel PX, the third transistor T3 of pixel PX can apply the reference voltage VREF to the second node NS, and the voltages V_NS_1, ..., V_NS_N of the second node NS can change from the first power voltage ELVDD to the reference voltage VREF. Since the voltages V_NS_1, ..., V_NS_N of the second node NS have the reference voltage VREF, the light-emitting diode (LED) of pixel PX can remain off. Accordingly, when the pulses of the first scan signals S1_1, ..., S1_N and the effective pulse PS_A of the second scan signals S2_1, ..., S2_N are applied to the pixel PX during the effective time period AP2, the LED may not emit light. Furthermore, when only the dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N are applied to the pixel PX, the LED may not emit light.

[0073] Figure 7 This is a timing diagram showing the brightness of a display device according to a comparative example at the second frequency FRQ2.

[0074] refer to Figure 5 and Figure 7When the display panel 110 is driven at a first frequency FRQ1, the number of times the LED of pixel PX is turned off can be substantially the same as the number of times the LED of pixel PX is turned off when the display panel 110 is driven at a second frequency FRQ2. Accordingly, in the display device according to the comparative example, even if the driving frequency DF of the display panel 110 changes, the brightness of the display panel 110 can remain substantially unchanged, and flickering can be avoided. Figure 5 and Figure 7 As illustrated in the diagram, in the display device according to the comparative example, within the same time length, the LEDs of the display panel 110 driven at the first frequency FRQ1 can be turned off approximately four times, and the LEDs of the display panel 110 driven at the second frequency FRQ2 can also be turned off approximately four times. Accordingly, the average brightness AVGLUM2' (e.g., 1.6 nits) of the display panel 110 driven at the second frequency FRQ2 can be substantially equal to the average brightness AVGLUM1 (e.g., 1.6 nits) of the display panel 110 driven at the first frequency FRQ1.

[0075] Figure 8 This is a schematic diagram illustrating the relationship between frequency and brightness of a display device according to a comparative example.

[0076] refer to Figure 8 When the display device does not use the dummy shutdown driver, the brightness of the display device may increase as the frequency of the display device decreases (e.g., due to...). Figure 8 (As indicated by the dashed line representing the dummy shutdown (X) in the diagram). Accordingly, when the display device does not use the dummy shutdown drive, the brightness of the display device may increase at low frequencies. When the display device uses the dummy shutdown drive (as indicated by... Figure 8 The dummy off (O) indicator (shown by the solid line) prevents the display device's brightness from increasing at low frequencies. However, when the display device uses dummy off drive, the brightness may repeatedly decrease and increase periodically as the display device's frequency decreases, and the maximum brightness deviation (MLD) between frequencies may actually increase. For example, when the display device's frequency decreases from the maximum drive frequency (e.g., 360 Hz) to a specific frequency (e.g., approximately 300 Hz), the brightness of the display device may decrease, and because the length of the first decrease segment is relatively large, the minimum brightness (LU_MN) may be relatively low. Accordingly, the maximum brightness deviation (MLD) between frequencies may increase, and the image quality of the display device may deteriorate.

[0077] Figure 9 This is a timing diagram showing the first scan control signal SCTRL1, the second scan control signal SCTRL2, the first scan signals S1_1, ..., S1_N, and the second scan signals S2_1, ..., S2_N according to some embodiments.

[0078] refer to Figure 9 To reduce the maximum brightness deviation between frequencies, in the display device 100 according to some embodiments, the interval WS1 between the effective pulse PS_A and the first dummy pulse PS_D1 of each of the second scan signals S2_1, ..., S2_N may be different from the interval WS2 between the first dummy pulse PS_D1 and the second dummy pulse PS_D2 of each of the second scan signals S2_1, ..., S2_N. Each of the second scan signals S2_1, ..., S2_N may include an effective pulse PS_A located in the effective time period AP and at least one dummy pulse PS_D1, PS_D2, and PS_D3 located in the vertical blanking time period VBP. Figure 9 The illustration shows an aspect of the embodiment, wherein each of the second scan signals S2_1, ..., S2_N includes three dummy pulses PS_D1, PS_D2 and PS_D3 located in the vertical blanking period VBP, but the present disclosure is not limited thereto.

[0079] According to some embodiments, the interval WS1 between the effective pulse PS_A and the first dummy pulse PS_D1 of each of the second scan signals S2_1, ..., S2_N can be greater than the interval WS2 between the first dummy pulse PS_D1 and the second dummy pulse PS_D2 of each of the second scan signals S2_1, ..., S2_N. The interval WS2 between the first dummy pulse PS_D1 and the second dummy pulse PS_D2 of each of the second scan signals S2_1, ..., S2_N can be equal to the interval WS3 between the second dummy pulse PS_D2 and the third dummy pulse PS_D3 of each of the second scan signals S2_1, ..., S2_N. In other words, the interval between the m-th (m is a natural number greater than 0) dummy pulse and the (m+1)-th dummy pulse of each of the second scan signals S2_1, ..., S2_N can be equal to the interval between the (m+1)-th dummy pulse and the (m+2)-th dummy pulse of each of the second scan signals S2_1, ..., S2_N, and the interval WS1 between the effective pulse PS_A and the first dummy pulse PS_D1 of each of the second scan signals S2_1, ..., S2_N can be greater than the interval between the m-th dummy pulse and the (m+1)-th dummy pulse of each of the second scan signals S2_1, ..., S2_N.

[0080] Each of the first scan signals S1_1, ..., S1_N may include a pulse located in the active time period AP, and may have a deactivation level in the vertical blanking time period VBP.

[0081] The second scan control signal SCTRL2 may include a valid pulse group SET_PS_A containing multiple continuous pulses in the valid time period AP, and at least one dummy pulse group SET_PS_D1, SET_PS_D2 and SET_PS_D3 containing multiple continuous pulses in the vertical blanking time period VBP. Figure 9 The figure illustrates an aspect of an embodiment in which the second scan control signal SCTRL2 includes three dummy pulse groups SET_PS_D1, SET_PS_D2, and SET_PS_D3 located in the vertical blanking period VBP, but this disclosure is not limited thereto.

[0082] The effective pulses PS_A of the second scan signals S2_1, ..., S2_N can be generated sequentially in response to the continuous pulses of the effective pulse group SET_PS_A of the second scan control signal SCTRL2. For example, the effective pulses PS_A of the first and second scan signals S2_1 can be generated in response to the first pulse of the effective pulse group SET_PS_A of the second scan control signal SCTRL2, and the effective pulses PS_A of the Nth and Nth second scan signals S2_N can be generated in response to the Nth (last) pulse of the effective pulse group SET_PS_A of the second scan control signal SCTRL2.

[0083] The dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N can be generated sequentially in response to the continuous pulses of the dummy pulse group SET_PS_D1, SET_PS_D2, and SET_PS_D3 of the second scan control signal SCTRL2. For example, the first dummy pulse PS_D1 of the first second scan signal S2_1 can be generated in response to the first pulse of the first dummy pulse group SET_PS_D1 of the second scan control signal SCTRL2, and the first dummy pulse PS_D1 of the Nth second scan signal S2_N can be generated in response to the Nth (last) pulse of the first dummy pulse group SET_PS_D1 of the second scan control signal SCTRL2.

[0084] The interval WSC1 between the effective pulse group SET_PS_A and the first dummy pulse group SET_PS_D1 of the second scan control signal SCTRL2 may be different from the interval WSC2 between the first dummy pulse group SET_PS_D1 and the second dummy pulse group SET_PS_D2 of the second scan control signal SCTRL2.

[0085] According to some embodiments, the interval WSC1 between the effective pulse group SET_PS_A and the first dummy pulse group SET_PS_D1 of the second scan control signal SCTRL2 can be greater than the interval WSC2 between the first dummy pulse group SET_PS_D1 and the second dummy pulse group SET_PS_D2 of the second scan control signal SCTRL2. The interval WSC2 between the first dummy pulse group SET_PS_D1 and the second dummy pulse group SET_PS_D2 of the second scan control signal SCTRL2 can be equal to the interval WSC3 between the second dummy pulse group SET_PS_D2 and the third dummy pulse group SET_PS_D3 of the second scan control signal SCTRL2. In other words, the interval between the m-th dummy pulse group and the (m+1)-th dummy pulse group of the second scan control signal SCTRL2 can be equal to the interval between the (m+1)-th dummy pulse group and the (m+2)-th dummy pulse group of the second scan control signal SCTRL2, and the interval WSC1 between the effective pulse group SET_PS_A and the first dummy pulse group SET_PS_D1 of the second scan control signal SCTRL2 can be greater than the interval between the m-th dummy pulse group and the (m+1)-th dummy pulse group of the second scan control signal SCTRL2.

[0086] The first scan control signal SCTRL1 may include a pulse group containing multiple consecutive pulses located in the active time period AP, and may have a deactivation level in the vertical blanking time period VBP.

[0087] The pulses of the first scan signals S1_1, ..., S1_N can be generated sequentially in response to the continuous pulses of the pulse group of the first scan control signal SCTRL1. For example, the pulse of the first scan signal S1_1 can be generated in response to the first pulse of the pulse group of the first scan control signal SCTRL1, and the pulse of the Nth scan signal S1_N can be generated in response to the Nth (last) pulse of the pulse group of the first scan control signal SCTRL1.

[0088] Figure 10 This is a schematic diagram illustrating the relationship between the frequency and brightness of a display device 100 according to some embodiments.

[0089] refer to Figures 8 to 10In the display device 100 according to some embodiments, the interval WS1 between the effective pulse PS_A and the first dummy pulse PS_D1 of each of the second scan signals S2_1, ..., S2_N can be greater than the interval WS2 between the first dummy pulse PS_D1 and the second dummy pulse PS_D2 of each of the second scan signals S2_1, ..., S2_N (the interval WSC1 between the effective pulse group SET_PS_A and the first dummy pulse group SET_PS_D1 of the second scan control signal SCTRL2 can be greater than the interval WSC2 between the first dummy pulse group SET_PS_D1 and the second dummy pulse group SET_PS_D2 of the second scan control signal SCTRL2), and correspondingly, the maximum brightness deviation MLD' between frequencies when using the dummy off drive according to some embodiments can be less than the maximum brightness deviation MLD between frequencies when using the dummy off drive according to the comparative example. For example, when the frequency of the display device decreases from the maximum driving frequency (e.g., 360 Hz) to a specific frequency (e.g., approximately 240 Hz), the brightness of the display device can increase, and because the length of the first reduction segment is relatively small, the minimum brightness LU_MN' can be relatively high. Accordingly, the maximum brightness deviation MLD' between frequencies can be reduced, and the image quality of the display device 100 can be relatively improved.

[0090] Figure 11 This is a timing diagram showing the first scan control signal SCTRL1, the second scan control signal SCTRL2, the first scan signals S1_1, ..., S1_N, and the second scan signals S2_1, ..., S2_N according to some embodiments.

[0091] Reference omitted Figure 9 The descriptions of the first scan control signal SCTRL1, the second scan control signal SCTRL2, the first scan signals S1_1, ..., S1_N, and the second scan signals S2_1, ..., S2_N are repeated from the previous descriptions. Figure 11 The description of the first scan control signal SCTRL1, the second scan control signal SCTRL2, the first scan signal S1_1, ..., S1_N, and the second scan signal S2_1, ..., S2_N.

[0092] refer to Figure 11 The interval WS2 between the first dummy pulse PS_D1 and the second dummy pulse PS_D2 of each of the second scan signals S2_1, ..., S2_N may be different from the interval WS3 between the second dummy pulse PS_D2 and the third dummy pulse PS_D3 of each of the second scan signals S2_1, ..., S2_N.

[0093] According to some embodiments, the interval WS1 between the effective pulse PS_A and the first dummy pulse PS_D1 of each of the second scan signals S2_1, ..., S2_N can be greater than the interval WS2 between the first dummy pulse PS_D1 and the second dummy pulse PS_D2 of each of the second scan signals S2_1, ..., S2_N, and the interval WS2 between the first dummy pulse PS_D1 and the second dummy pulse PS_D2 of each of the second scan signals S2_1, ..., S2_N can be greater than the interval WS3 between the second dummy pulse PS_D2 and the third dummy pulse PS_D3 of each of the second scan signals S2_1, ..., S2_N.

[0094] The valid pulse PS_A of the second scan signals S2_1, ..., S2_N can be generated sequentially in response to the continuous pulses of the valid pulse group SET_PS_A of the second scan control signal SCTRL2. The dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N can be generated sequentially in response to the continuous pulses of the dummy pulse group SET_PS_D1, SET_PS_D2, and SET_PS_D3 of the second scan control signal SCTRL2.

[0095] The interval WSC2 between the first dummy pulse group SET_PS_D1 and the second dummy pulse group SET_PS_D2 of the second scan control signal SCTRL2 may be different from the interval WSC3 between the second dummy pulse group SET_PS_D2 and the third dummy pulse group SET_PS_D3 of the second scan control signal SCTRL2.

[0096] According to some embodiments, the interval WSC1 between the effective pulse group SET_PS_A and the first dummy pulse group SET_PS_D1 of the second scan control signal SCTRL2 can be greater than the interval WSC2 between the first dummy pulse group SET_PS_D1 and the second dummy pulse group SET_PS_D2 of the second scan control signal SCTRL2, and the interval WSC2 between the first dummy pulse group SET_PS_D1 and the second dummy pulse group SET_PS_D2 of the second scan control signal SCTRL2 can be greater than the interval WSC3 between the second dummy pulse group SET_PS_D2 and the third dummy pulse group SET_PS_D3 of the second scan control signal SCTRL2.

[0097] Figure 12 This is a block diagram illustrating an electronic device 1000 according to some embodiments. Figure 13 It is shown Figure 12 The diagram shows an example of an electronic device 1000 implemented as a computer monitor.

[0098] refer to Figure 12 and Figure 13 The electronic device 1000 can output various information through the display module 1040 within the operating system. When the processor 1010 executes an application stored in the memory 1020, the display module 1040 can provide application information to the user through the display panel 1041. According to some embodiments, the processor 1010 can provide information to the display module 1040. Figure 1 Input image data IDAT and Figure 1 The control signal CTRL.

[0099] Processor 1010 can obtain external input through input module 1030 or sensor module 1061 and can execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 1041, processor 1010 can obtain user input through input sensor 1061-2 and activate camera module 1071. Processor 1010 can send image data corresponding to the captured image acquired by camera module 1071 to display module 1040. Display module 1040 can display the image corresponding to the captured image through display panel 1041. Some components of electronic device 1000 can be integrated and provided as a single component, or a single component can be provided as two or more separate components.

[0100] Electronic device 1000 can communicate with external electronic device 1002 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to some embodiments, electronic device 1000 may include a processor 1010, a memory 1020, an input module 1030, a display module 1040, a power module 1050, an internal module 1060, and an external module 1070. According to some embodiments, electronic device 1000 may omit at least one of the components described above, or one or more other components may be added. According to some embodiments, some of the components described above (e.g., sensor module 1061, antenna module 1062, or audio output module 1063) may be integrated into another component (e.g., display module 1040).

[0101] The processor 1010 can execute software to control at least one other component (e.g., hardware or software component) of the electronic device 1000 connected to the processor 1010, and can perform various data processing or calculations. According to some embodiments, as at least part of the data processing or calculation, the processor 1010 can store commands or data received from another component (e.g., input module 1030, sensor module 1061, or communication module 1073) in volatile memory 1021, can process the commands or data stored in volatile memory 1021, and can store the result data in non-volatile memory 1022.

[0102] Processor 1010 may include a main processor 1011 and a coprocessor 1012. Main processor 1011 may include one or more of a central processing unit (CPU) 1011-1 and an application processor (AP). Main processor 1011 may further include one or more of a graphics processing unit (GPU) 1011-2, a communication processor (CP), and an image signal processor (ISP). At least two of the processing units and processors described above may be implemented as integrated components (e.g., a single chip), or each may be implemented as a separate component (e.g., multiple chips).

[0103] The coprocessor 1012 may include a controller 1012-1. The controller 1012-1 may include interface conversion circuitry and timing control circuitry. The controller 1012-1 can receive image signals from the main processor 1011, convert the data format of the image signals to adapt to the interface specifications of the display module 1040, and output image data. The controller 1012-1 can output various control signals required to drive the display module 1040.

[0104] The coprocessor 1012 may further include a data conversion circuit 1012-2, a gamma correction circuit (or gamma compensation circuit) 1012-3, a rendering circuit 1012-4, etc. The data conversion circuit 1012-2 can receive image data from the controller 1012-1 and can compensate the image data according to the characteristics of the electronic device 1000 or user settings to display the image with the desired brightness, or can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit 1012-3 can convert the image data or gamma reference voltage so that the image displayed on the electronic device 1000 has the desired gamma characteristics. The rendering circuit 1012-4 can receive image data from the controller 1012-1 and can render the image data by taking into account the pixel arrangement of the display panel 1041 applied to the electronic device 1000. At least one of the data conversion circuit 1012-2, the gamma correction circuit 1012-3, and the rendering circuit 1012-4 can be integrated into another component (e.g., the main processor 1011 or the controller 1012-1). At least one of the data conversion circuit 1012-2, the gamma correction circuit 1012-3, and the rendering circuit 1012-4 can be integrated into the data driver 1043, which is described below.

[0105] The memory 1020 may store various data used by at least one component of the electronic device 1000 (e.g., processor 1010 or sensor module 1061) and input or output data of commands associated therewith. The memory 1020 may include at least one of volatile memory 1021 and non-volatile memory 1022.

[0106] The input module 1030 can receive commands or data from outside the electronic device 1000 (e.g., from a user or external electronic device 1002) to be used in components of the electronic device 1000 (e.g., processor 1010, sensor module 1061, or sound output module 1063).

[0107] Input module 1030 may include a first input module 1031 through which commands or data are input from a user, and a second input module 1032 through which commands or data are input from an external electronic device 1002. The first input module 1031 may include a microphone, mouse, keyboard, buttons (e.g., keypads), or pen (e.g., passive or active pen). The second input module 1032 may support a specified protocol that can be connected to the external electronic device 1002 via wired or wireless connection. According to some embodiments, the second input module 1032 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface. The second input module 1032 may include a connector that can be physically connected to the external electronic device 1002, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0108] Display module 1040 can provide visual information to a user. Display module 1040 may include display panel 1041, gate driver 1042, and data driver 1043. Display module 1040 may further include a window, chassis, and bracket to protect display panel 1041. Display module 1040 may correspond to... Figure 1 The display device 100. The display panel 1041, the gate driver 1042, and the data driver 1043 can respectively correspond to Figure 1 The display panel 110, scan driver 130 and data driver 120.

[0109] Power module 1050 can supply power to components of electronic device 1000. Power module 1050 may include a battery that can be charged with a power voltage. The battery may include a non-rechargeable primary battery cell, a rechargeable secondary battery cell, or a fuel cell cell. Power module 1050 may include power management circuitry 1051. Power management circuitry 1051 can supply optimized power to each of the modules described above and below. Power module 1050 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple coil-shaped antenna radiators.

[0110] The electronic device 1000 may further include an internal module 1060 and an external module 1070. The internal module 1060 may include a sensor module 1061, an antenna module 1062, and a sound output module 1063. The external module 1070 may include a camera module 1071, an optical module 1072, and a communication module 1073.

[0111] Sensor module 1061 can detect input from the user's body or from the pen in the first input module 1031, and can generate an electrical signal or data value corresponding to the input. Sensor module 1061 may include at least one of fingerprint sensor 1061-1, input sensor 1061-2, and digitizer 1061-3.

[0112] The processor 1010 can output commands or data to the display module 1040, the sound output module 1063, the camera module 1071, or the optical module 1072 based on input data received from the input module 1030. For example, the processor 1010 can generate image data in response to input data applied via a mouse or stylus and output the image data to the display module 1040, or it can generate command data in response to input data and output the command data to the camera module 1071 or the optical module 1072. When no input data is received from the input module 1030 for a specific period of time, the processor 1010 can switch the operating mode of the electronic device 1000 to a low-power mode or a sleep mode to reduce the power consumption of the electronic device 1000.

[0113] The processor 1010 can output commands or data to the display module 1040, the sound output module 1063, the camera module 1071, or the optical module 1072 based on the sensing data received from the sensor module 1061. For example, the processor 1010 can compare the authentication data authorized by the fingerprint sensor 1061-1 with the authentication data stored in the memory 1020, and then execute an application based on the comparison result. The processor 1010 can execute commands or output corresponding image data to the display module 1040 based on the sensing data detected by the input sensor 1061-2 or the digitizer 1061-3. When the sensor module 1061 includes a temperature sensor, the processor 1010 can receive temperature data measured from the sensor module 1061, and can further perform brightness correction, etc., on the image data based on the temperature data.

[0114] According to some embodiments, such as Figure 13 As illustrated, the electronic device 1000 can be implemented as a computer monitor. However, this disclosure is not limited thereto, and according to some embodiments, the electronic device 1000 can be implemented as a television, mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation system, laptop computer, head-mounted display device, augmented reality (AR) device, etc.

[0115] The display device according to the embodiments can be applied to display devices included in computers (such as laptops and smart tablets), mobile phones, smartphones, smartwatches, PMPs, PDAs, or MP3 players.

[0116] Although the display device and electronic device according to embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the appended claims and their equivalents.

Claims

1. A display device, comprising: Display panel, including pixels; A scan driver is configured to provide a first scan signal and a second scan signal to the pixel; as well as The controller is configured to provide the scan driver with a first scan control signal for generating the first scan signal and a second scan control signal for generating the second scan signal. The second scan signal includes a valid pulse in an effective time period with a constant duration and at least one dummy pulse in a vertical blanking time period with a variable duration. The interval between the effective pulse and the first dummy pulse of the second scan signal is different from the interval between the first dummy pulse and the second dummy pulse of the second scan signal.

2. The display device according to claim 1, wherein, The interval between the first dummy pulse and the second dummy pulse of the second scan signal is equal to the interval between the second dummy pulse and the third dummy pulse of the second scan signal.

3. The display device according to claim 2, wherein, The interval between the valid pulse of the second scan signal and the first dummy pulse is greater than the interval between the first dummy pulse and the second dummy pulse of the second scan signal.

4. The display device according to claim 1, wherein, The interval between the first dummy pulse and the second dummy pulse of the second scan signal is different from the interval between the second dummy pulse and the third dummy pulse of the second scan signal.

5. The display device according to claim 4, wherein, The interval between the valid pulse of the second scan signal and the first dummy pulse is greater than the interval between the first dummy pulse and the second dummy pulse of the second scan signal.

6. The display device according to claim 5, wherein, The interval between the first dummy pulse and the second dummy pulse of the second scan signal is greater than the interval between the second dummy pulse and the third dummy pulse of the second scan signal.

7. The display device according to claim 1, wherein, The pixels include: The first transistor includes a gate connected to a first node, a first terminal configured to receive a first electrical voltage, and a second terminal connected to a second node; The second transistor includes a gate configured to receive the first scan signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node. The third transistor includes a gate configured to receive the second scan signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the second node; The capacitor includes a first terminal connected to the first node and a second terminal connected to the second node; and The light-emitting diode includes a first terminal connected to the second node and a second terminal configured to receive a second electrical voltage.

8. The display device according to claim 7, wherein, The capacitor is configured to store the difference between the data voltage and the reference voltage in response to pulses of the first scan signal and the second scan signal during the effective time period. During the vertical blanking period, the reference voltage is applied to the second node in response to at least one dummy pulse of the second scan signal.

9. The display device according to claim 8, wherein, The reference voltage level is lower than the threshold voltage level of the light-emitting diode.

10. The display device according to claim 1, wherein, The first scan signal includes pulses during the effective time period and has a deactivation level during the vertical blanking time period.

11. A display device, comprising: Display panel, including pixels; A scan driver is configured to provide a first scan signal and a second scan signal to the pixel; as well as The controller is configured to provide the scan driver with a first scan control signal for generating the first scan signal and a second scan control signal for generating the second scan signal. The second scan control signal includes an effective pulse group comprising multiple continuous pulses within an effective time period of constant length and at least one dummy pulse group comprising multiple continuous pulses within a vertical blanking time period of variable length. The interval between the effective pulse group and the first dummy pulse group of the second scan control signal is different from the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal.

12. The display device according to claim 11, wherein, The interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal is equal to the interval between the second dummy pulse group and the third dummy pulse group of the second scan control signal.

13. The display device according to claim 12, wherein, The interval between the effective pulse group and the first dummy pulse group of the second scan control signal is greater than the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal.

14. The display device according to claim 11, wherein, The interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal is different from the interval between the second dummy pulse group and the third dummy pulse group of the second scan control signal.

15. The display device according to claim 14, wherein, The interval between the effective pulse group and the first dummy pulse group of the second scan control signal is greater than the interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal.

16. The display device according to claim 15, wherein, The interval between the first dummy pulse group and the second dummy pulse group of the second scan control signal is greater than the interval between the second dummy pulse group and the third dummy pulse group of the second scan control signal.

17. The display device according to claim 11, wherein, The pixels include: The first transistor includes a gate connected to a first node, a first terminal configured to receive a first electrical voltage, and a second terminal connected to a second node; The second transistor includes a gate configured to receive the first scan signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node. The third transistor includes a gate configured to receive the second scan signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the second node; The capacitor includes a first terminal connected to the first node and a second terminal connected to the second node; and The light-emitting diode includes a first terminal connected to the second node and a second terminal configured to receive a second electrical voltage.

18. The display device according to claim 11, wherein, The first scan control signal includes a pulse group comprising multiple consecutive pulses contained in the effective time period, and has a deactivation level in the vertical blanking time period.

19. An electronic device comprising: The display device according to any one of claims 1 to 18; as well as The processor is configured to provide the controller with control signals for generating the first scan control signal and the second scan control signal.

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