Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a plurality of pixel units arranged in an array, a plurality of power signal lines and a plurality of data signal lines, each pixel unit comprises a plurality of sub-pixels with different light emitting colors; each sub-pixel comprises a pixel circuit and a light-emitting element which are electrically connected; two adjacent columns of pixel circuits are electrically connected with the same data signal line; the power signal lines are arranged in the row direction of the pixel units and extend in the column direction of the pixel units; the distance between two adjacent power supply signal lines is L1; wherein L1 is larger than or equal to Lp, and Lp is the size of one pixel unit in the row direction. According to the technical scheme, the screen flash problem can be solved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, the requirements for display panel resolution and size are getting higher and higher, making high resolution, large size and high refresh rate the important development trend of display panels.

[0003] Currently, display panels with high display resolution typically have a large number of sub-pixels and a large number of signal lines. For example, the display panel has a large number of data signal lines and a large number of power signal lines. The data signal lines and power signals are electrically connected to the corresponding sub-pixels to provide data signals and power signals to the sub-pixels respectively, driving the sub-pixels to display and emit light.

[0004] However, a larger number of data signal lines and power signals increases the number of bezel wiring and driver chips required for the display panel, hindering narrow bezels and low cost. Furthermore, at the start of a frame's display time, a large instantaneous current flows through the power signal lines. This current causes voltage fluctuations in the transmitted power signal, which can couple to the sub-pixels, resulting in abnormal light emission and screen flicker, thus affecting the display's performance. Summary of the Invention

[0005] The present invention provides a display panel and a display device that can improve the screen flicker problem and enhance the display effect of the display panel.

[0006] In a first aspect, the present invention provides a display panel, comprising: a plurality of pixel units arranged in an array, a plurality of power signal lines, and a plurality of data signal lines;

[0007] The pixel unit includes multiple sub-pixels with different light-emitting colors; each sub-pixel includes an electrically connected pixel circuit and a light-emitting element.

[0008] The pixel circuits in two adjacent columns are electrically connected to the same data signal line;

[0009] The power signal lines are arranged along the row direction of the pixel unit and extend along the column direction of the pixel unit; the spacing between two adjacent power signal lines is Ll; where Ll ≥ Lp, and Lp is the size of a pixel unit in the row direction.

[0010] Optionally, the spacing between two adjacent power signal lines is 2n×Lp; 1≤n≤5, and n is a positive integer.

[0011] Optionally, the power signal line is electrically connected to the pixel circuit of one of the 2n pixel units arranged along the row direction; n is a positive integer.

[0012] Optionally, n adjacent pixel units arranged along the row direction constitute a pixel unit group;

[0013] The power signal lines are electrically connected to the pixel circuits in the two pixel unit groups on their opposite sides.

[0014] Optionally, the power signal line is located in the gap between two adjacent pixel unit groups arranged along the row direction.

[0015] Optionally, the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along the row direction; the pixel circuit of the first sub-pixel is a first pixel circuit, the pixel circuit of the second sub-pixel is a second pixel circuit, and the pixel circuit of the third sub-pixel is a third pixel circuit.

[0016] The emission wavelength of the first sub-pixel is greater than that of the second sub-pixel, and the emission wavelength of the second sub-pixel is greater than that of the third sub-pixel;

[0017] Two adjacent pixel circuits arranged along the row direction constitute a sub-display group; the sub-display group includes a first sub-display group, and the two pixel circuits in the first sub-display group are the first pixel circuit and the third pixel circuit, respectively;

[0018] The plurality of power signal lines include a first power signal line located in the gap between two adjacent pixel circuits in the first sub-display group.

[0019] Optionally, the sub-display group further includes a second sub-display group and a third sub-display group;

[0020] The two pixel circuits in the second sub-display group are the first pixel circuit and the second pixel circuit, respectively; the two pixel circuits in the third sub-display group are the second pixel circuit and the third pixel circuit, respectively;

[0021] The plurality of power signal lines include a second power signal line located in the gap between two adjacent pixel circuits in the second sub-display group, and a third power signal line located in the gap between two adjacent pixel circuits in the third sub-display group.

[0022] Optionally, among the plurality of power signal lines, the number of the first power signal lines is greater than the number of the second power signal lines, and the number of the first power signal lines is greater than the number of the third power signal lines.

[0023] Optionally, among the multiple power signal lines, the number of the first power signal lines is k1, the number of the second power signal lines is k2, and the number of the third power signal lines is k3.

[0024] Where k1:k2:k3 = 2:1:1.

[0025] Optionally, along the row direction, the four adjacent power signal lines are, in sequence, the first power signal line, the second power signal line, the first power signal line, and the third power signal line.

[0026] Optionally, the spacing between adjacent first power signal lines and second power signal lines is Ll1; the spacing between adjacent first power signal lines and third power signal lines is Ll3; wherein, Ll1=Ll3.

[0027] Optionally, m adjacent pixel units arranged along the row direction constitute a display unit group; m is a positive integer greater than or equal to 2;

[0028] The p adjacent display unit groups include a first display unit groups, b second display unit groups, and c third display unit groups; p = a + b + c, where p, a, b, and c are all positive integers;

[0029] The first display unit group includes a first sub-display group with the first power signal line provided, the second display unit group includes a second sub-display group with the second power signal line provided, and the third display unit group includes a third sub-display group with the third power signal line provided.

[0030] Optional, a:b:c = 2:1:1.

[0031] Optionally, the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged along the row direction; the pixel circuit of the first sub-pixel is a first pixel circuit, the pixel circuit of the second sub-pixel is a second pixel circuit, the pixel circuit of the third sub-pixel is a third pixel circuit, and the pixel circuit of the fourth sub-pixel is a fourth pixel circuit.

[0032] The emission wavelength of the first sub-pixel is greater than that of the second sub-pixel, the emission wavelength of the second sub-pixel is greater than that of the third sub-pixel, and the display emission color of the fourth sub-pixel includes at least the combined emission colors of the first sub-pixel and the second sub-pixel;

[0033] In the row direction, the distance between the power signal line and the fourth pixel circuit is at least d1; where d1>d0, and d0 is the size of the pixel circuit in the row direction.

[0034] Optionally, in the same pixel unit, the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are arranged sequentially along the row direction; the plurality of power signal lines include a second power signal line located in the gap between adjacent first pixel circuits and second pixel circuits, and / or a third power signal line located in the gap between adjacent second pixel circuits and third pixel circuits.

[0035] Optionally, the first pixel circuit and the third pixel circuit are adjacent in the same pixel unit, or the first pixel circuit and the third pixel circuit are adjacent in two adjacent pixel units; the plurality of power signal lines include a first power signal line located in the gap between adjacent first pixel circuits and third pixel circuits.

[0036] Optionally, m adjacent pixel units form a display unit group; the power signal line is electrically connected to the pixel circuit in the same display unit group; m is a positive integer;

[0037] The p adjacent display unit groups include a first display unit groups, b second display unit groups, and c third display unit groups; p = a + b + c, where p, a, b, and c are all positive integers;

[0038] The first display unit group includes adjacent first pixel circuits and third pixel circuits, and the power signal line electrically connected to the pixel circuits in the first display unit group is located in the gap between the adjacent first pixel circuits and third pixel circuits.

[0039] The second display unit group includes adjacent first pixel circuits and second pixel circuits, and the power signal line electrically connected to the pixel circuits in the second display unit group is located in the gap between adjacent first pixel circuits and second pixel circuits;

[0040] The third display unit group includes adjacent second pixel circuits and third pixel circuits, and the power signal line electrically connected to the pixel circuits in the third display unit group is located in the gap between adjacent second pixel circuits and third pixel circuits.

[0041] Optional, a:b:c = 2:1:1.

[0042] Optionally, the display panel further includes: a plurality of power connection lines extending along the row direction; the power signal lines are electrically connected to the pixel circuit through the power connection lines.

[0043] Optionally, the power connection line has a line width of W3 in the column direction, and the power signal line has a line width of W1 in the row direction; wherein, W1>W3.

[0044] Optionally, among the interconnected power signal lines and power connection lines, the distance between the power signal line and the pixel circuit closest to the power signal line in the row direction is a1, and the distance between the power connection line and the pixel circuit closest to the power connection line in the column direction is a2; wherein, a2>a1.

[0045] Optionally, the display panel further includes: a plurality of first signal lines extending along the row direction and arranged along the column direction; at least a portion of the pixel circuits located in the same row are electrically connected to the same first gate signal line;

[0046] At least one first signal line is provided between the power connection line and the pixel circuit.

[0047] Optionally, the display panel further includes: a display area and a non-display area surrounding the display area; the non-display area includes a fan-out area located on one side of the display area; the fan-out area is provided with multiple fan-out traces;

[0048] The pixel unit, the power signal line, and the data signal line are all located in the display area;

[0049] The multiple fan-out traces include multiple first fan-out traces corresponding to the multiple power signal lines, and multiple second fan-out traces corresponding to the multiple data signal lines. The first fan-out traces are electrically connected to the corresponding power signal lines; the second fan-out traces are electrically connected to the corresponding data signal lines.

[0050] The display panel further includes at least one conductive layer; the first fan-out trace is located in the same conductive layer.

[0051] Optionally, the conductive layer includes a first conductive layer and a second conductive layer with an insulating gap; two adjacent second fan-out traces are located in the first conductive layer and the second conductive layer, respectively.

[0052] Optionally, the display panel further includes: a display area and a non-display area surrounding the display area; the non-display area includes a fan-out area located on one side of the display area; the fan-out area is provided with multiple fan-out traces;

[0053] The pixel unit, the power signal line, and the data signal line are all located in the display area;

[0054] The multiple fan-out traces include multiple first fan-out traces corresponding to the multiple power signal lines, and multiple second fan-out traces corresponding to the multiple data signal lines. The first fan-out traces are electrically connected to the corresponding power signal lines; the second fan-out traces are electrically connected to the corresponding data signal lines.

[0055] The display panel includes a first conductive layer and a second conductive layer that are insulated from each other; the two adjacent fan-out traces are located on the first conductive layer and the second conductive layer, respectively.

[0056] Optionally, the data signal line is located in the gap between two pixel circuits that are electrically connected to it and arranged along the row direction.

[0057] Optionally, the pixel circuits of two adjacent sub-pixels electrically connected to the same data signal line are centrally symmetrical about the data signal line.

[0058] Optionally, the gap between two adjacent pixel circuits arranged along the row direction is the pixel gap;

[0059] The power signal line and the data signal line are respectively located in different pixel gaps.

[0060] Optionally, in the row direction, the line width of the power signal line is W1, and the line width of the data signal line is W2; wherein, 2×W2≤W1≤6×W2.

[0061] Optionally, the display panel may also include: multiple first gate signal lines;

[0062] The pixel circuit includes at least a driving module and a data writing module; the data writing module is electrically connected to the data signal line, the first gate signal line, and the driving module, respectively.

[0063] The data writing modules of the two pixel circuits located in the same row and electrically connected to the same data signal line are respectively electrically connected to different first gate signal lines.

[0064] In a second aspect, the present invention provides a display device, comprising: the display panel described in the first aspect.

[0065] The technical solution of this invention reduces the number of data signal lines in the display panel by electrically connecting the same data signal line to two adjacent columns of sub-pixels. This reduces the number of bezel wirings and driver chips in the display panel, thus contributing to a narrower bezel and lower driving costs. Simultaneously, by electrically connecting power signal lines to at least the sub-pixels of pixel units in the same column, and setting the spacing between two adjacent power signal lines to be greater than the size of a pixel unit in the row direction, the number of power signal lines in the display panel is reduced compared to having only one power signal line between two adjacent columns of sub-pixels. This also reduces bezel wiring, further contributing to a narrower bezel. Furthermore, reducing the number of power signal lines in the display panel reduces the number of sub-pixels adjacent to the power signal lines, decreasing the number of sub-pixels coupled to them. This reduces the number of sub-pixels that emit abnormal light, thus improving the screen flicker problem that occurs at the beginning of a frame display and enhancing the display effect. Attached Figure Description

[0066] Figure 1 This is a schematic diagram of the structure of a display panel provided by related technologies;

[0067] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0068] Figure 3 This is a schematic diagram of a sub-pixel structure provided in an embodiment of the present invention;

[0069] Figure 4 This is a schematic diagram of the driving timing of a sub-pixel provided in an embodiment of the present invention;

[0070] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0071] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0072] Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0073] Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0074] Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0075] Figure 10This is a partial top view of a display panel provided in an embodiment of the present invention;

[0076] Figure 11 This is a partial top view of another display panel structure provided in an embodiment of the present invention;

[0077] Figure 12 This is a partial top view of the structure of another display panel provided in an embodiment of the present invention;

[0078] Figure 13 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of the present invention;

[0079] Figure 14 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0080] Figure 15 This is a schematic diagram of the relationship between visual perceived intensity and light wavelength provided in an embodiment of the present invention;

[0081] Figure 16 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to an embodiment of the present invention;

[0082] Figure 17 This is a schematic diagram of the structure of a row of sub-pixels in a display panel provided in another embodiment of the present invention;

[0083] Figure 18 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0084] Figure 19 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0085] Figure 20 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0086] Figure 21 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0087] Figure 22 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0088] Figure 23 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0089] Figure 24 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0090] Figure 25 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0091] Figure 26 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0092] Figure 27 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0093] Figure 28 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0094] Figure 29 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0095] Figure 30 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0096] Figure 31 This is a schematic diagram of the structure of a row of sub-pixels in a display panel according to another embodiment of the present invention;

[0097] Figure 32 This is a partial top view of the structure of another display panel provided in an embodiment of the present invention;

[0098] Figure 33 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0099] Figure 34 This is a schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention;

[0100] Figure 35 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention;

[0101] Figure 36 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention;

[0102] Figure 37 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0103] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0104] Self-emissive display panels, such as organic light-emitting diode (OLED) display panels, micro OLED display panels, and mini OLED display panels, are favored by various display devices because they do not require a backlight, have vivid and realistic colors, a wide color gamut, can be made thin and light, and support flexible forms such as folding and rolling, offering a high degree of design freedom. Figure 1 This is a structural diagram of a display panel provided by related technologies, such as... Figure 1 As shown, the display panel 001 includes multiple sub-pixels 01 arranged in an array and multiple signal lines. Each sub-pixel 01 may include a pixel circuit OP and a light-emitting element OD electrically connected to each other. The pixel circuit OP can drive the light-emitting element OD to emit light for display. The signal lines may include at least data signal lines 02 and power signal lines 03. The pixel circuit OP is electrically connected to the data signal lines 02 and the power signal lines 03 respectively to receive data signals provided by the data signal lines 02 and power signals transmitted by the power signal lines 03. Based on the power signals and data signals, the pixel circuit OP provides corresponding driving signals to the light-emitting element OD to drive the light-emitting element OD to emit light for display.

[0105] Currently, in high-resolution, large-size display panels 001, data signal lines 02 and power signal lines 03 are alternately distributed between pixel circuits 0P of two adjacent columns of sub-pixels 01. At the same time, by electrically connecting the same data signal line 02 to the pixel circuits 0P of two adjacent columns of sub-pixels 01, and by having the pixel circuits 0P electrically connected to the same data signal line 02 receive different gate signals respectively, that is, two pixel circuits 0P located in the same row and electrically connected to the same data signal line 02 receive different gate signals respectively, the Dual Gate Line Driving (DGLD) technology is realized, so that the pixel circuits 0P electrically connected to the same data signal line 02 can be scanned in a time-division manner, so that the data signal line 02 provides data signals to the pixel circuits 0P electrically connected to it in a time-division manner. Meanwhile, a power signal line 03 is electrically connected to the pixel circuit 0P of one or two columns of sub-pixels 01, and the devices in the pixel circuit 0P electrically connected to the same power signal line 03 are turned on by time-division control, so that the power signal transmitted by the power signal line 03 can be written into the pixel circuit 01 electrically connected to it in time-division.

[0106] However, when data signal line 02 and power signal line 03 are alternately distributed between the pixel circuits OP of two adjacent columns of sub-pixels 01, there is no longer a data signal line 02 between the power signal line 03 and the pixel circuit OP, nor is there a power signal line 03 between the data signal line 02 and the pixel circuit OP. The data signal line 02 can be directly adjacent to the pixel circuits OP located on its opposite sides, and the power signal line 03 can be directly adjacent to the pixel circuits OP located on its opposite sides. This results in a parasitic capacitance between the data signal line 02 and the pixel circuits OP on its opposite sides, and a parasitic capacitance between the power signal line 03 and the pixel circuits OP located on its opposite sides and directly adjacent.

[0107] Furthermore, the data signal transmitted by data signal line 02 typically changes with the brightness of the sub-pixel 01, allowing the data signal line 02 to be designed according to actual needs. The power signal transmitted by power signal line 03 is typically a fixed signal. At the beginning of a frame's display time, when the device electrically connected to power signal line 03 in pixel circuit OP is turned on, the power signal transmitted by power signal line 03 rapidly charges the corresponding node in pixel circuit OP, generating a large instantaneous current on power signal line 03. This causes instantaneous voltage fluctuations in the power signal transmitted by power signal line 03. Because parasitic capacitance exists between power signal line 03 and the pixel circuits OP on its opposite sides, the power signal with its large instantaneous current and voltage fluctuations on power signal line 03 couples to the pixel circuits OP on its opposite sides. The pixel circuits OP, due to the presence of this coupling signal, drive the light-emitting element OD electrically connected to it to emit light, causing sub-pixel 01 to emit light abnormally. Therefore, during the development of DGLD technology, the applicant discovered that the pixel circuit OP of the factor pixel 01 is directly adjacent to the power signal line 03. This causes the sub-pixels 01 in the display panel 001 to emit abnormal light at the beginning of a frame display time, resulting in a momentary brighter image on the display panel 001. This causes screen flickering on the display panel 001 and affects the display effect of the display panel 001.

[0108] To address the aforementioned problems, embodiments of the present invention provide a display panel comprising: a plurality of pixel units arranged in an array, a plurality of power signal lines, and a plurality of data signal lines; each pixel unit includes a plurality of sub-pixels with different emission colors; each sub-pixel includes an electrically connected pixel circuit and a light-emitting element; adjacent columns of pixel circuits are electrically connected to the same data signal line; the power signal lines are arranged along the row direction of the pixel units and extend along the column direction of the pixel units; the spacing between two adjacent power signal lines is Ll; wherein, Ll ≥ Lp, and Lp is the dimension of a pixel unit in the row direction.

[0109] By adopting the above technical solution, and electrically connecting the same data signal line to two adjacent columns of sub-pixels, the number of data signal lines in the display panel can be reduced, thereby reducing the number of bezel wirings and driver chips in the display panel. This contributes to a narrower bezel and lowers the driving cost of the display panel. Simultaneously, by electrically connecting the power signal line to at least the sub-pixels of the pixel unit located in the same column, and setting the spacing between two adjacent power signal lines to be greater than the size of a pixel unit in the row direction, compared to setting one power signal line between two adjacent columns of sub-pixels, the number of power signal lines in the display panel is reduced, which also reduces the bezel wiring, thus contributing to a narrower bezel. Furthermore, reducing the number of power signal lines in the display panel reduces the number of sub-pixels adjacent to the power signal lines, reducing the number of sub-pixels coupled to the power signal lines. This reduces the number of sub-pixels that emit light abnormally, thus improving the screen flicker problem that occurs at the beginning of a frame display time and enhancing the display effect of the display panel.

[0110] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0111] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, such as... Figure 2 As shown, the display panel includes: multiple pixel units 1 arranged in an array, multiple power signal lines 3, and multiple data signal lines 2. Pixel unit 1 includes multiple sub-pixels 10 with different emitting colors. Sub-pixels 10 include a pixel circuit P and a light-emitting element D that are electrically connected. Two adjacent columns of pixel circuits P are electrically connected to the same data signal line 2. The power signal lines 3 are arranged along the row direction X of pixel unit 1 and extend along the column direction Y of pixel unit 1. The spacing between two adjacent power signal lines 3 is Ll; where Ll ≥ Lp, and Lp is the size of a pixel unit 1 in the row direction X.

[0112] It is understood that pixel unit 1 can be the smallest repeating unit in the display panel, or the basic visual unit when the display panel displays an image. Pixel unit 1 can include multiple sub-pixels 10 with different emitting colors. The number of sub-pixels 10 arranged along the row direction X in pixel unit 1 can be greater than or equal to 3, and can be designed according to actual needs. This embodiment of the invention does not specifically limit this. In an exemplary embodiment, pixel unit 1 can include a first sub-pixel 11 with a first emitting color of a first color, a second sub-pixel 12 with a second emitting color of a second color, and a third sub-pixel 13 with a third emitting color of a third color, arranged along the row direction. The first color, second color, and third color can be red, green, and blue, respectively. It is understood that in some embodiments, some sub-pixels 10 in pixel unit 1 can also be the same color. For example, pixel unit 1 can include one first sub-pixel 11, one third sub-pixel 13, and two second sub-pixels 12. This invention does not limit this. In sub-pixel 10, pixel circuit P is electrically connected to light-emitting element D and data signal line 2, enabling pixel circuit P to receive data signals transmitted by data signal line 2 and provide corresponding driving signals to light-emitting element D according to the received data signals, so as to drive light-emitting element D to display light emission. Furthermore, the display light emission of light-emitting element D in sub-pixels of different colors is combined with each other, which can make display panel 100 display a rich color display screen.

[0113] The light-emitting element D may include current-driven elements such as organic light-emitting diodes (OLEDs), micro-LEDs, or miniature LEDs. The pixel circuit P may consist of active and / or passive devices to convert the voltage signal of the data signal transmitted on the data signal line 2 into a current signal, thereby driving the electrically connected light-emitting element D to emit light accurately. The active devices may include, but are not limited to, transistors, and the passive devices may include at least one of capacitors, resistors, and inductors. It should be noted that, provided that the pixel circuit P can drive the light-emitting element D to emit light accurately, the specific structure of the pixel circuit P is not limited in this embodiment of the invention.

[0114] In an optional embodiment, Figure 3 This is a schematic diagram of a sub-pixel structure provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 2 and Figure 3 The pixel circuit P includes at least a driving module 101 and a data writing module 102. The data writing module 102 is electrically connected to the data signal line 2 and the driving module 101 respectively. The data writing module 102 can control the provision of the data signal Vdata transmitted by the data signal line 2 to the driving module 101. The driving module 101 can selectively provide driving current to the light-emitting element D according to the written data signal Vdata to drive the light-emitting element D to display light emission.

[0115] In addition, the display panel 100 should also include multiple first gate signal lines 4. The data writing module 102 in the pixel circuit P is also electrically connected to the first gate signal line 4 to receive the first gate signal S2 transmitted by the first gate signal line 4. When the first gate signal S2 is at an effective level, the data signal Vdata transmitted by the control data signal line 2 is provided to the driving module 102 to realize the writing of the data signal Vdata.

[0116] It is understandable that two adjacent columns of pixel circuits P are electrically connected to the same data signal line 2. That is, one data signal line 2 can be electrically connected to the data writing modules 102 of two adjacent columns of pixel circuits P, so that one data signal line 2 can provide data signal Vdata to the data writing modules 102 of two adjacent pixel circuits P in a row. Therefore, it is not necessary to set up data signal lines 2 separately for pixel circuits P in the same row. This helps to reduce the number of data signal lines 2 in the display panel 100, reduce the space occupied by data signal lines 2, and relatively increase the setting space of pixel circuits P, which helps to improve the resolution of the display panel 100. At the same time, the data signal is usually provided by the driver chip, which is usually located in the bezel area of ​​the display panel 100. Reducing the number of data signal lines 2 helps to reduce the signal traces set in the bezel area to connect the data signal lines 2 and the driver chip, and also reduces the number of driver chips set in the bezel area. This helps to achieve a narrow bezel of the display panel 100 and reduce the driving cost of the display panel 100.

[0117] Correspondingly, when data signal line 2 is electrically connected to two adjacent columns of pixel circuits P, in order to ensure that each pixel circuit P accurately receives the data signal Vdata, data signal line 2 needs to transmit the data signal Vdata of the pixel circuit P electrically connected to it in a time-division manner, and write the data signal Vdata into the pixel circuit P electrically connected to it in a time-division manner. At this time, the data writing module 102 of the pixel circuit P electrically connected to the same data signal line 2 should be electrically connected to different first gate signal lines 4 respectively. That is, the data writing modules 102 of the two pixel circuits P located in the same row and electrically connected to the same data signal line 2 are electrically connected to different first gate signal lines 4 respectively.

[0118] Multiple first gate signal lines 4 can transmit the effective level of the first gate signal S2 in a time-division manner, thereby controlling the pixel circuits P electrically connected to different first gate signal lines 4 to write data signals in a time-division manner. Since the data writing modules 102 of two pixel circuits P located in the same row and electrically connected to the same data signal line 2 are electrically connected to different first gate signal lines 4, the data signals Vdata of the two pixel circuits P located in the same row and electrically connected to the same data signal line 2 can be written in a time-division manner. For example, in the first sub-pixel 11 and the second sub-pixel 12 located in the same row and adjacent to each other, the data writing module 101 of the pixel circuit P is electrically connected to the same data signal line 2. At this time, the data writing module 101 of the pixel circuit P in the first sub-pixel 11 can be electrically connected to the first first gate signal line 41, and the data writing module 101 of the pixel circuit P in the second sub-pixel 12 can be electrically connected to the second first gate signal line 42. The effective level time t22 of the first gate signal S22 transmitted by the second first gate signal line 42 can be located after the effective level time t21 of the first gate signal S21 transmitted by the first first gate signal line 41 (e.g., ...). Figure 4 As shown), when the first gate signal line 41 transmits the effective level of the first gate signal S21 and the second gate signal line 42 transmits the effective level of the first gate signal S22, the data writing module 102 of the first sub-pixel 11 can write the data signal Vdata transmitted by the data signal line 2 into the first sub-pixel 11; after the first sub-pixel 11 completes the writing of the data signal Vdata, the first gate signal S21 transmitted by the first gate signal line 41 becomes ineffective, and the second gate signal line 42 transmits the effective level of the first gate signal S22. The data writing module 102 of the second sub-pixel 12 can write the data signal Vdata transmitted by the data signal line 2 into the second sub-pixel 12, thereby enabling the two sub-pixels 10 that are electrically connected to the same data signal line 2 and located in the same row to perform time-division multiplexing of data signal writing.

[0119] It is understandable that, since two sub-pixels 10 that are electrically connected to the same data signal line 2 and located in the same row are electrically connected to different first gate signal lines 4, a row of sub-pixels needs to be connected to two first gate signal lines, so that the display panel 100 realizes the dual gate line driving (DGLD) technology.

[0120] Continue to refer to Figure 2 and Figure 3The driving module 101 can also be coupled to the power signal line 3, allowing the power signal transmitted by the power signal line 3 to be selectively provided to the driving module 101. When the power signal transmitted by the power signal line 3 is provided to the driving module 101, the driving module 101 can provide the driving current generated according to the data signal Vdata to the light-emitting element D, enabling the light-emitting element D to emit light. The power signal transmitted by the power signal line 3 can be a positive power signal PVDD or a negative power signal PVEE, and can be designed according to actual needs. This embodiment of the invention does not impose specific limitations on this. For ease of description, unless otherwise specified, this embodiment of the invention uses the positive power signal PVDD transmitted by the power signal line 3 as an example to illustrate the technical solution of this embodiment.

[0121] Correspondingly, the pixel circuit P can also include a light-emitting control module 105, so that the driving module 101 is electrically connected to the power signal line 3 and the anode of the light-emitting element D through the light-emitting control module 105, and the cathode of the light-emitting element D can receive the negative power signal PVEE. Thus, when the light-emitting control module 105 is turned on, a current path is formed between the positive power signal PVDD transmitted by the power signal line 3 and the negative power signal PVEE received by the cathode of the light-emitting element D, so that the driving module 101 can provide the driving current generated according to the data signal Vdata to the light-emitting element D, driving the light-emitting element D to emit light for display.

[0122] Since the positive power signal PVDD transmitted by the power signal line 3 is usually a fixed voltage signal, and the extension direction of the power signal line 3 is consistent with the extension direction of the data signal line 2, that is, the extension directions of the power signal line 3 and the data signal line 2 are both the column direction Y of the pixel unit 1, the power signal line 3 can be electrically connected to the light emission control module 105 in one or more column pixel circuits P to provide the positive power signal PVDD to the light emission control module 105 of one or more column pixel circuits P.

[0123] Understandably, when developing DGLD technology, the applicant used an alternating arrangement of power signal lines and data signal lines between pixel circuits to ensure uniform signal line routing in the display panel. However, this arrangement creates parasitic capacitance between the pixel circuits and the power signal lines. At the start of a frame's display time, when the light-emitting control module in the pixel circuit is turned on, the positive power signal transmitted by the power signal line rapidly charges the node electrically connected to the drive module and the light-emitting control module, resulting in a large instantaneous current on the power signal line. The voltage of the positive power signal on the power signal line fluctuates. This positive power signal with its large instantaneous current and fluctuating voltage is coupled to the pixel circuit through the parasitic capacitance, causing the pixel circuit to generate a driving current to drive the light-emitting element to emit light. Compared to the pixel circuit controlling the light-emitting element to emit light based on the received data signal, the light emission generated by the coupling of the positive power signal on the power signal line is an abnormal emission from the sub-pixels. During the research process, it was found that the instantaneous abnormal emission of sub-pixels at the start of a frame's display time causes screen flickering problems in the display panel. To improve the screen flicker problem, the applicant proposed a solution to increase the spacing between power signal lines and reduce the pixel circuits that form parasitic capacitance with the power signal lines.

[0124] Continue to refer to Figure 2 As shown, in this embodiment, the spacing L1 between two adjacent power signal lines 3 is greater than or equal to the size of a pixel unit 1 in the row direction X. That is, at least one pixel circuit P of a pixel unit 1 is provided between two adjacent power signal lines 3, so that at least some pixel circuit P in a pixel unit 1 has other pixel circuit P and / or data signal lines 2 between it and the power signal line 3. The power signal line 3 cannot directly form a parasitic capacitance with this part of the pixel circuit P, so that at the beginning of the display time of a frame, the positive power signal of the instantaneous large current and fluctuating voltage transmitted on the power signal line 3 cannot couple to this part of the pixel circuit P. The pixel circuit P will not drive the light-emitting element D connected to it to emit light due to the coupling of the positive power signal PVDD transmitted by the power signal line 3. At the beginning of the display time of a frame, the number of sub-pixels 1 that emit light abnormally due to the coupling of the positive power signal PVDD transmitted by the power signal line 3 can be relatively reduced, thereby reducing the brightness of abnormal light emission of the display panel 100. This makes it less likely for the human eye to detect the abnormal light emission of the display panel 100, thereby improving the screen flicker problem of the display panel 100 at the beginning of the display time of a frame, and thus improving the display effect of the display panel 100.

[0125] It is understood that a pixel unit includes a pixel circuit and a light-emitting element. The pixel circuit contains corresponding devices and their connecting lines. In the thickness direction of the display panel, the light-emitting element overlaps with the pixel circuit. Therefore, the dimension of the pixel unit along the row direction can be the width of the area where the light-emitting element and pixel circuit are located in the pixel unit in the row direction. This can be the overall width of the pixel unit or the sum of the widths of the sub-pixels in the pixel unit. The specific design can be tailored to actual needs, and this embodiment of the invention does not impose any specific limitations on this.

[0126] It should be noted that, Figure 2 The example shown only illustrates the case where the spacing Ll between two adjacent power signal lines is greater than Lp and less than 2×Lp. In this embodiment of the invention, the spacing Ll between two adjacent power signal lines can also be equal to Lp, or greater than or equal to 2×Lp. The specific design can be tailored to actual needs. This embodiment of the invention does not impose specific limitations on this, provided that the number of pixel circuits directly adjacent to the power signal lines can be reduced. Furthermore, the spacing Ll between two adjacent power signal lines can be a fixed value or a non-fixed value, and can also be designed according to actual needs. This embodiment of the invention does not impose specific limitations on this either.

[0127] In an optional embodiment, the spacing between two adjacent power signal lines is 2n×Lp; 1≤n≤5, and n is a positive integer.

[0128] In one exemplary embodiment, such as Figure 5 As shown, when n equals 1, Ll equals 2×Lp. If a pixel unit 1 includes m sub-pixels 10 arranged along the row direction, then the number of sub-pixels 10 arranged along the row direction X and located between two adjacent power signal lines 3 is 2m. This ensures that the number of sub-pixels 10 in two adjacent pixel units 1 that are not directly adjacent to the power signal line 3 is 2m-2. At the beginning of a frame display time, the instantaneous large current and fluctuating voltage on the power signal line 3 cannot couple to the 2m-2 sub-pixels 10 that are not directly adjacent to the power signal line 3. This prevents at least 2m-2 sub-pixels 10 in two adjacent pixel units 1 from producing abnormal display light emission, thereby helping to improve the screen flicker problem of the display panel 100 and improve the display effect of the display panel 100. At the same time, the spacing Ll between two adjacent power signal lines 3 is 2×Lp, which allows the power signal lines 3 to be evenly distributed in the display panel 100, which helps to simplify the wiring method of the display panel 100 and improve the display uniformity of the display panel 100.

[0129] In another exemplary embodiment, such as Figure 6As shown, when n equals 2, Ll equals 4×Lp. If a pixel unit 1 includes m sub-pixels 10 arranged along the row direction, then in four adjacent pixel units 1, the number of sub-pixels 10 not directly adjacent to the power signal line 3 is 4m-2. This ensures that at the beginning of a frame display time, at least 4m-2 sub-pixels 10 in two adjacent pixel units 1 can be prevented from generating abnormal display light emission, thereby helping to improve the screen flicker problem of the display panel 100 and improve the display effect of the display panel 100. At the same time, the spacing Ll between two adjacent power signal lines 3 is 4×Lp, which allows the power signal lines 3 to be evenly distributed in the display panel 100, which helps to simplify the wiring method of the display panel 100 and improve the display uniformity of the display panel 100.

[0130] In summary, the larger the value of n, the more sub-pixels 10 are located between two adjacent power signal lines 3, and the more sub-pixels 10 are not directly adjacent to the power signal lines 3. This results in fewer sub-pixels 10 emitting light abnormally at the beginning of a frame display time. However, the pixel circuit P of the sub-pixel 10 needs to be electrically connected to the power signal line 3. That is, the pixel circuit P located between two adjacent power signal lines 3 needs to be electrically connected to one of the two power signal lines 3. Furthermore, the positive power signal PVDD will experience a voltage drop during transmission due to transmission loss, and the longer the transmission path, the greater the voltage drop. This means that the greater the connection distance between the pixel circuit P and the power signal line 3, the lower the voltage value of the positive power signal PVDD received by the pixel circuit P. Thus, there is a difference between the positive power signal PVDD received by the pixel circuit P with a shorter connection distance and the positive power signal PVDD received by the pixel circuit P with a longer connection distance. When this difference is large, it will affect the display light emission consistency of the sub-pixels 10 to which the pixel circuit P belongs, thereby affecting the display uniformity of the display panel 100. Based on this, n is set to a positive integer greater than or equal to 1 and less than or equal to 5, so that while reducing the number of abnormal display light-emitting sub-pixels 10, the positive power supply signal PVDD received by each pixel circuit P has a small difference, which is beneficial to improving the display uniformity of the display panel 100.

[0131] Furthermore, since the pixel circuits P of two adjacent columns of sub-pixels 10 are electrically connected to the same data signal line 2, the spacing Ld between two adjacent data signal lines 2 can be the width of two adjacent sub-pixels 10 arranged along the row direction X in the row direction X. That is, along the row direction X, a data signal line 2 is set every two sub-pixels 10. If the number of sub-pixels 10 in pixel unit 1 is odd, there will be sub-pixels 10 located in the same row and electrically connected to the same data signal line 2 that belong to different pixel units 1. Therefore, by making the spacing Ll between two adjacent power signal lines 3 2n×Lp, it can be ensured that the number of sub-pixels 10 between the two adjacent power signal lines 3 is even, so that the data signal lines 2 located between the two adjacent power signal lines 3 can be electrically connected to the pixel circuits P of the sub-pixels 10 located between the two adjacent power signal lines 3. This helps to simplify the wiring of the power signal lines 3 and the data signal lines 2, thereby simplifying the design of the display panel 100 and reducing the cost of the display panel 100.

[0132] It is understood that 1≤n≤5, and n is a positive integer, that is, the value of n can be 1, 2, 3, 4 or 5. The specific value of n can be designed according to actual needs. In order to facilitate description and simplify the accompanying drawings, unless otherwise specified, the embodiments of the present invention all take n equal to 1 as an example to illustrate the technical solution of the embodiments of the present invention.

[0133] It is also understood that, since the positive power signal PVDD transmitted by power signal line 3 is a fixed voltage signal, the light-emitting control modules in pixel circuits P located in the same row can be turned on simultaneously to write the positive power signal PVDD into pixel circuit P at the same time. In this case, the number of pixel circuits P connected to power signal line 3 can be a fixed value or a non-fixed value. That is, there may be two adjacent power signal lines 3 that connect to pixel circuits P with the same data, or there may be two adjacent power signal lines 3 that connect to pixel circuits P with different numbers of data. The specific design can be tailored to actual needs, and this embodiment of the invention does not impose any specific limitations on this.

[0134] In an alternative embodiment, such as Figure 7 As shown, the power signal line 3 is electrically connected to the pixel circuit P in the 2n pixel units 1 arranged along the row direction X; n is a positive integer.

[0135] In this configuration, the pixel circuits P of the 2n pixel units 1 arranged along the row direction X share a single power signal line 3. This eliminates the need for a separate power signal line 3 for each pixel unit 1, reducing the number of power signal lines, minimizing the space occupied by the power signal lines 3, and relatively increasing the space available for the pixel circuits P. Consequently, this improves the resolution of the display panel 100. Furthermore, the power signal line 3 is electrically connected to the pixel circuits P in the 2n pixel units 1 arranged along the row direction X. When the number of pixel circuits P in each pixel unit 1 is fixed, the number of pixel circuits P electrically connected to the power signal line 3 can be fixed, ensuring a consistent number of connected pixel circuits P. This, in turn, ensures a consistent load on the power signal line 3, maintaining a consistent positive power signal PVDD supplied by the power signal line 3 to the pixel circuits P. This further enhances the display uniformity of the display panel 100.

[0136] Furthermore, the number of pixel circuits P in the 2n pixel units 1 arranged along the row direction X, i.e., the number of pixel circuits P located in the same row and electrically connected to the same power signal line 3, is even. Since the pixel circuits P of two adjacent sub-pixels 10 arranged along the row direction X are electrically connected to the same data signal line 2, each pair of pixel circuits P located in the same row and electrically connected to the same power signal line 3 can be electrically connected to one data signal line 2. This allows the pixel circuits P electrically connected to the same data signal line 2 to be electrically connected to the same power signal line 3 simultaneously. This helps to improve the consistency of the positive power signal PVDD and data signal Vdata received by each pixel circuit P, thereby improving the display uniformity of the display panel 100.

[0137] It is understood that the pixel circuit P of the 2n pixel units 1 arranged along the row direction X is electrically connected to the same power signal line 3. The 2n pixel units arranged along the row direction X can be located on the same side or opposite sides of the power signal line 3. The specific design can be made according to actual needs. This embodiment of the invention does not make specific limitations in this regard.

[0138] In an alternative embodiment, such as Figure 8 As shown, n adjacent pixel units 1 arranged along the row direction X form a pixel unit group 1A; the power signal line 3 is electrically connected to the pixel circuit P in the two pixel unit groups 1A (1A1 and 1A2) on its opposite sides.

[0139] The power signal line 3 can be electrically connected to two pixel unit groups 1A, which are located on opposite sides of the power signal line 3. For example, the power signal line 3 can be electrically connected to the pixel unit group 1A1 on its left and the pixel unit group 1A2 on its right, so that the transmission path of the positive power signal PVDD received by the pixel circuit P in the two pixel unit groups 1A located on opposite sides of the power signal line 3 and electrically connected to the power signal line 3 is consistent, thereby improving the consistency of the positive power signal PVDD received by the pixel circuit P, which in turn helps to improve the display uniformity of the display panel 100.

[0140] It is understood that the power signal line 3 is electrically connected to the pixel unit group 1A on both sides opposite to it. That is, the pixel unit group 1A electrically connected to the power signal line 3 can be a pixel unit group 1A that is adjacent to or not adjacent to the power signal line 3. The specific design can be made according to actual needs. This embodiment of the invention does not make specific limitations in this regard.

[0141] In an alternative embodiment, reference continues. Figure 8 The power signal line 3 is located in the gap between two adjacent pixel unit groups 1A arranged along the row direction X. That is, the power signal line 3 can be located in the gap between two pixel unit groups 1A that are electrically connected to it, so that the pixel unit group 1A can be adjacent to its electrically connected power signal line 3. This ensures that the transmission path of the power signal line 3 to provide positive power signal PVDD to the pixel circuit P in the pixel unit group 1A is shorter, which is beneficial to improving the accuracy of the positive power signal PVDD received by the pixel circuit P. In turn, it is beneficial to improve the display light emission accuracy of the light-emitting element electrically connected to the pixel circuit P and improve the display effect of the display panel 100.

[0142] Furthermore, by placing the power signal line 3 in the gap between two adjacent pixel unit groups 1A arranged along the row direction X, the two adjacent power signal lines 3 can be evenly routed in the display panel 100, simplifying the routing method of the display panel 100, reducing the design cost of the display panel 100, and contributing to the low cost of the display panel 100.

[0143] It should be noted that the above description only illustrates the connection method between the power signal line 3 and the pixel circuit P in the pixel unit 1. However, provided that the core inventive points of this embodiment are achieved, the connection method between the power signal line 3 and the pixel circuit P can be designed according to actual needs, and this embodiment does not impose specific limitations on this. For ease of description and simplification of the accompanying drawings, unless otherwise specified, this embodiment uses the example of the power signal line 3 being located at the gap between two pixel unit groups 1A that are electrically connected to it and located in the same row to illustrate at least some of the technical solutions of this embodiment.

[0144] Based on the above embodiments, alternatively, refer to the following: Figure 8 The display panel 100 may also include multiple power connection lines 5 extending along the row direction X; the power signal line 3 is electrically connected to the pixel circuit P through the power connection lines 5.

[0145] In this configuration, at least some pixel circuits P are electrically connected by the power signal line 3. At least one other pixel circuit P is spaced between each pixel circuit P and the power signal line 3. To achieve the connection between the pixel circuit P and the power signal line 3, a corresponding power connection line 5 is required to connect the power signal line 3 and the pixel circuit P. The power connection line 5 can extend along the row direction X, allowing multiple pixel circuits P located adjacent in the row direction X to be electrically connected to the power signal line 3 through the same power connection line 5, thus simplifying the wiring of the power connection line 5.

[0146] In other alternative embodiments, such as Figure 9 As shown, the pixel circuits P arranged along the row direction X can also be electrically connected to the same power signal line 3 through different power connection lines 5. In this case, the pixel circuits P arranged along the row direction X can receive the positive power signal PVDD transmitted by the power signal line 3 through different power connection lines 5, so that the power connection line 5 has a smaller load, which is beneficial to improve the transmission accuracy of the positive power signal PVDD on the power connection line 5, improve the accuracy of the positive power signal PVDD received by the pixel circuit P, thereby improving the display light emission accuracy of the light-emitting element driven by the pixel circuit P, and thus improving the display effect of the display panel 100.

[0147] It should be noted that the specific connection relationship between the power connection line 5 and the pixel circuit P can be designed according to actual needs, and the embodiments of the present invention do not impose specific limitations on this. For ease of description, unless otherwise specified, the embodiments of the present invention use the example of multiple pixel circuits P located adjacent in the row direction X being electrically connected to the power signal line 3 through the same power connection line 5 to illustrate the technical solution of the embodiments of the present invention.

[0148] In an optional embodiment, Figure 10 This is a partially enlarged structural schematic diagram of a display panel provided in an embodiment of the present invention, as shown below. Figure 10 As shown, the line width of the power connection line 5 in the column direction Y is W3, and the line width of the power signal line 3 in the row direction X is W1; where W1>W3.

[0149] In this configuration, power connection line 5 extends along the row direction X to electrically connect to the pixel circuits P arranged in the row direction X, and power signal line 3 extends along the column direction Y to electrically connect to both the pixel circuits P arranged in the column direction Y and power connection line 5. This allows the same power signal line 3 to be electrically connected to multiple columns of pixel circuits P, making power signal line 3 the main transmission line for the positive power signal PVDD, and power connection line 5 a branch transmission line for the positive power signal PVDD. By setting the line width W1 of power signal line 3 in the row direction X to be greater than the line width of power connection line 5 in the column direction Y, the power signal line 3 per unit length has a smaller impedance, thereby ensuring the accuracy of the transmission of the positive power signal PVDD in the main transmission line. Simultaneously, because power connection line 5 extends along the row direction X, in the column direction Y, power connection line 5 and each pixel circuit P it is electrically connected to overlap, and when power connection line 5 and each pixel circuit P it is electrically connected to are directly adjacent, parasitic capacitance is formed between power connection line 5 and the directly adjacent pixel circuit P. However, due to the small width of the power connection line 5, the parasitic capacitance formed between the power connection line 5 and the pixel circuit P is small, resulting in a small amount of signal coupled from the power connection line 5 to the pixel circuit P. This ensures that the positive power signal PVDD of the instantaneous large current and fluctuating voltage on the power connection line 5 will not affect the pixel circuit P's driving of the light-emitting element to display light emission, thus guaranteeing the display light emission effect of the display panel 100.

[0150] Furthermore, when the power connection line 5 is positioned in the gap between two adjacent rows of pixel circuits P, by setting the power connection line 5 to have a smaller line width W3 in the column direction Y, the power connection line 5 occupies less space in the column direction Y, thereby relatively increasing the gap size between the power connection line 5 and the pixel circuit P. This can correspondingly reduce the parasitic capacitance formed by the power connection line 5 and the pixel circuit P, thereby reducing the amount of signal coupling from the positive power signal PVDD of the instantaneous large current and fluctuating voltage on the power connection line 5 to the pixel circuit P. This ensures that the pixel circuit P drives the light-emitting element electrically connected to it to emit light accurately, improving the display effect of the display panel 100.

[0151] Optional, continue to refer to Figure 10 In the interconnected power signal line 3 and power connection line 5, the distance between the power signal line 3 and its nearest pixel circuit P in the row direction X is a1, and the distance between the power connection line 5 and its nearest pixel circuit P in the column direction Y is a2; where a2>a1.

[0152] By setting a2>a1, a larger distance is maintained between the power connection line 5 and the pixel circuit P closest to the power connection line 5. This relatively reduces the parasitic capacitance formed by the power connection line 5 and the pixel circuit P closest to the power connection line 5. Consequently, the amount of signal coupling from the positive power signal PVDD of the instantaneous large current and fluctuating voltage on the power connection line 5 to the pixel circuit P is reduced. This ensures that the pixel circuit P drives the light-emitting element electrically connected to it to emit light accurately, thereby improving the display effect of the display panel 100.

[0153] Furthermore, by setting a small gap between the power signal line 3 and the pixel circuit P closest to the power signal line 3, the gap size between the power signal line 3 and the pixel circuit P can be reduced, thereby relatively increasing the space occupied by the power signal line 3. This ensures that the power signal line 3 has a larger line width, reduces the transmission impedance of the positive power signal PVDD transmitted on the power signal line 3, and helps to improve the accuracy of the positive power signal PVDD received by the pixel circuit P. This, in turn, improves the light emission accuracy of the light-emitting element driven by the pixel circuit P, and thus improves the display effect of the display panel 100.

[0154] It should be noted that the above only exemplifies the case where the power connection line 5 is adjacent to the pixel circuit P, resulting in a parasitic capacitance between them. In this embodiment of the invention, other structures can be provided between the power connection line 5 and the pixel circuit P to prevent a direct parasitic capacitance from forming between them. These other structures between the power connection line 5 and the pixel circuit P can be shielding structures separately provided in the display panel 100, or existing structures in the display panel 100 can be reused. The specific design can be tailored to actual needs, and this embodiment of the invention does not impose specific limitations on this.

[0155] Optional, such as Figure 11 As shown, the display panel 100 may further include a plurality of first signal lines 6 extending along the row direction X and arranged along the column direction Y; at least a portion of the pixel circuits P located in the same row are electrically connected to the same first signal line 6; at least one first signal line 6 is provided between the power connection line 5 and the pixel circuit P.

[0156] The first signal line 6 can be used to transmit fixed voltage signals or alternating voltage signals. The specific design can be tailored to actual needs. The signal transmitted by the first signal line 6 is the signal required for the normal operation of the pixel circuit P.

[0157] It is understandable that at the beginning of a frame display time, the signal transmitted on the first signal line 6 will not generate a large instantaneous current, so that the signal transmitted on the first signal line 6 will not be coupled into the pixel circuit P, or the amount of signal transmitted on the first signal line 6 coupled into the pixel circuit P is small, so as to ensure that the parasitic capacitance formed between the first signal line 6 and the pixel circuit P will not affect the magnitude of the driving current provided by the pixel circuit P to the light-emitting element, thereby ensuring the display light emission accuracy of the light-emitting element driven by the pixel circuit P.

[0158] Meanwhile, since the power connection line 5 is used to electrically connect the pixel circuit P and the power signal line 3, the signal transmitted on the power connection line 5 is consistent with the signal transmitted on the power signal line 3. That is, the signal transmitted on the power connection line 5 will change with the signal transmitted on the power signal line 3. Specifically, when the positive power signal PVDD transmitted on the power signal line 3 has a large instantaneous current and fluctuating voltage, the positive power signal PVDD transmitted on the power connection line 5 will also have a large instantaneous current and fluctuating voltage. By setting a first signal line 6 between the power connection line 5 and the pixel circuit P, the first signal line 6 can act as an isolation structure between the power connection line 5 and the pixel circuit P, preventing the power connection line 5 from directly forming a parasitic capacitance with the pixel circuit P. This prevents the positive power signal PVDD on the power connection line 5 from coupling into the pixel circuit P, thus avoiding the situation where the pixel circuit P drives the light-emitting element to display the accuracy of light emission. Thus, by setting a first signal line 6 between the power connection line 5 and the pixel circuit P, the abnormal display and light emission of the light-emitting element caused by the instantaneous large current and fluctuating voltage of the positive power signal PVDD can be improved, thereby improving the display effect of the display panel 100.

[0159] The first signal line 6 being located between the power connection line 5 and the pixel circuit P can be understood as follows: in a direction parallel to the plane of the display panel 100, the power connection line 5 is located on the side of the first signal line 6 furthest from the pixel circuit P (e.g., Figure 11 (As shown), or, in the thickness direction of the display panel 100, the film layer where the power connection line 5 is located is located on the side of the film layer where the first signal line 6 is located that is far away from the film layer where the pixel circuit P is located (e.g.) Figure 12 and Figure 13 Provided that the first signal line 6 can be used to isolate the power supply connection line 5 from the pixel circuit P, the embodiments of the present invention do not impose specific limitations on this.

[0160] In one exemplary embodiment, reference is made to... Figure 12 and Figure 13Taking a pixel circuit P represented by a transistor as an example, the display panel 100 includes a substrate cl1, a circuit setting layer cl2 located on one side of the substrate cl1, a first signal line layer cl3 located on the side of the circuit setting layer cl2 facing away from the substrate cl1, and a second signal line layer cl4 located on the side of the first signal line layer cl3 facing away from the substrate cl1. The circuit setting layer cl2 is provided with the pixel circuit P, the first signal line layer cl3 is provided with a first signal line 6, and the second signal line layer cl4 is provided with a power connection line 5. The power connection line 5 overlaps with the first signal line 6 in a direction perpendicular to the plane of the substrate cl1. Simultaneously, both the power connection line 5 and the first signal line 6 can extend along the row direction X, meaning the extension directions of the power connection line 5 and the first signal line 6 are the same. The line width W4 of the first signal line 6 in the column direction Y can be greater than the line width W3 of the power connection line 5 in the column direction Y, so that the first signal line 6 can completely isolate the power connection line 5 extending along the row direction X from the pixel circuit P. Thus, the first signal line layer cl3 is located between the circuit setting layer cl2 and the second signal line layer cl4, so that the first signal line 6 of the first signal line layer cl3 can isolate the pixel circuit P of the circuit setting layer cl2 and the power connection line 5 of the second signal line layer cl4, preventing the positive power signal PVDD transmitted by the power connection line 5 from coupling to the pixel circuit P, thereby ensuring the display light emission accuracy of the light-emitting element driven by the pixel P, and making the display panel 100 have high display quality.

[0161] It should be noted that the above description is merely an example of the film layer structure of the display panel. In the embodiments of the present invention, the film layer structure of the display panel is not limited to this and can be designed according to actual needs. The embodiments of the present invention do not impose specific limitations on this.

[0162] It is understood that the first signal line is electrically connected to the pixel circuit, and the first signal line can transmit the signals required by the pixel circuit. In an exemplary embodiment, refer to... Figure 11 or Figure 12 When the display panel 100 includes a first gate signal line 4 electrically connected to the data writing module in the pixel circuit P, the first signal line 6 can be the first gate signal line 4, thereby enabling the first gate signal line to isolate the pixel circuit P from the power connection line. In other exemplary embodiments, the first signal line can also be other signal lines electrically connected to the pixel circuit P, which can be specifically designed according to the structure of the pixel circuit P and the required signals.

[0163] In one exemplary embodiment, reference is made to... Figure 3The pixel circuit P includes a driving module 101, a data writing module 102, a reset module 103, a threshold compensation module 104, a light emission control module 105, an initialization module 106, and a storage capacitor Cst. The driving module 101 may include a driving transistor M1; the data writing module 102 may include a data writing transistor M2, the first terminal of which can receive the data signal Vdata transmitted by the data signal line, the second terminal of which can be electrically connected to the first terminal of the driving transistor M1, and the gate of which can receive a first gate signal S2, allowing the first gate signal S2 to control the data writing transistor M2 to be turned on or off; the threshold compensation module 104 may include a threshold compensation transistor M4, the first terminal of which can be electrically connected to the second terminal of the driving transistor M1, and the threshold compensation module M4 can receive a first gate signal S2, allowing the first gate signal S2 to control the data writing transistor M2 to be turned on or off; the threshold compensation module 104 may include a threshold compensation transistor M4, the first terminal of which can be electrically connected to the second terminal of the driving transistor M1, and the threshold compensation module M4 can receive the data signal Vdata transmitted by the data signal line, the second terminal of which can be electrically connected to the first ... The second terminal of the compensation transistor M4 can be electrically connected to the gate of the driving transistor M1. The gate of the threshold compensation transistor M4 can receive a first gate signal S2, so that the first gate signal S2 can control the threshold compensation transistor M4 to be turned on or off. The reset module 103 can include a reset transistor M3. The first terminal of the reset transistor M3 can receive a reset signal Vref1. The second terminal of the reset transistor M3 can be electrically connected to the gate of the driving transistor M1. The gate of the reset transistor M3 can receive a second gate signal S1, so that the second gate signal S3 can control the reset transistor M3 to be turned on or off. The light emission control module 105 can include a first gate signal S3. A first light-emitting control transistor M5 and a second light-emitting control transistor M6 are configured. The first terminal of the first light-emitting control transistor M5 receives a positive power signal PVDD transmitted from the power signal line. The second terminal of the first light-emitting control transistor M5 is electrically connected to the first terminal of the driving transistor M1. The second terminal of the driving transistor M1 is electrically connected to the second light-emitting control transistor M6. The second terminal of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting element D. The cathode of the light-emitting element D can receive a negative power signal PVEE. The gates of both the first light-emitting control transistor M5 and the second light-emitting control transistor M6 receive a light-emitting control signal EM, so that the light-emitting control signal EM can... The first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on or off. The initialization module 106 includes an initialization transistor M7. The first terminal of the initialization transistor M7 can receive an initialization signal Vref2. The second terminal of the initialization transistor M7 can be electrically connected to the anode of the light-emitting element D. The gate of the initialization transistor M7 can receive a third gate signal S3, so that the third gate signal S3 can control the initialization transistor M7 to turn on or off. The first plate of the storage capacitor Cst can receive a positive power signal PVDD transmitted by the power signal line. The second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M1.

[0164] Specifically, when the second gate signal S1 controls the reset transistor M3 to turn on, the reset transistor M3 can transmit the reset signal Vref2 to the gate of the driving transistor M1 to reset the gate of the driving transistor M1 and the storage capacitor Cst; when the first gate signal S2 controls the data writing transistor M2 and the threshold compensation transistor M4 to turn on, the data signal Vdata transmitted by the data signal line and the threshold voltage of the driving transistor M1 are both written to the gate of the driving transistor M1 and stored in the storage capacitor Cst; when the third gate signal S3 controls the initialization transistor M7 to turn on, the initialization transistor M7 can provide the initialization signal Vref2 to the anode of the light-emitting element D to initialize the light-emitting element D; when the light-emitting control signal EM controls the first light-emitting control transistor M5 and the second light-emitting control transistor M6 to turn on, a conducting current path is formed between the positive power supply signal PVEE and the negative power supply signal PVEE, so that the driving transistor M1 provides the driving current generated by its gate signal to the light-emitting element D, driving the light-emitting element D to display light emission.

[0165] Correspondingly, the display panel 100 may also include a reset signal line, an initialization signal line, a first gate signal line, a second gate signal line, a third gate signal line, and an emissive control line. The reset signal line is used to transmit a reset signal Vref1, the initialization signal line is used to transmit an initialization signal Vref2, the first gate signal line is used to transmit a first gate signal S2, the second gate signal line is used to transmit a second gate signal S2, the third gate signal line is used to transmit a third gate signal S3, and the emissive control line is used to transmit an emissive control signal EM. In this case, the first signal line can be at least one of the reset signal line, the initialization signal line, the first gate signal line, the second gate signal line, the third gate signal line, and the emissive control line. This eliminates the need for additional isolation power supply connection lines to the pixel circuit P, simplifying the display panel structure and reducing its cost.

[0166] It should be noted that the above description only illustrates the structure of the pixel circuit in the display panel of this invention, and the structure of the pixel circuit in this invention is not limited to this. It can be designed according to actual needs. For ease of description, unless otherwise specified, the embodiments of this invention all use the following... Figure 3 Taking the structure of the pixel circuit as an example, the technical solution of the embodiment of the present invention will be described by way of example.

[0167] It is understandable that a pixel unit in a display panel comprises multiple sub-pixels of different colors, and the light-emitting elements within these sub-pixels emit different colors of light. Because the human eye has varying sensitivities to different colors of light, the brightness of the light emitted from sub-pixels of different colors varies in visual sensitivity. Therefore, during abnormal display illumination caused by the instantaneous high current and fluctuating voltage of a positive power signal at the start of a frame's display time, the color of the light emitted is the one with low visual sensitivity to the human eye, making it less likely to be perceived. Therefore, when configuring the power signal line, it is advisable to place the power signal line as close as possible to the sub-pixels emitting light of colors with low visual sensitivity to the human eye, and as far away as possible from the sub-pixels emitting light of colors with high visual sensitivity to the human eye.

[0168] In an alternative embodiment, such as Figure 14 As shown, pixel unit 1 includes a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13 arranged along the row direction X; the pixel circuit of the first sub-pixel 11 is a first pixel circuit P1, the pixel circuit of the second sub-pixel 12 is a second pixel circuit P2, and the pixel circuit of the third sub-pixel 13 is a third pixel circuit P3; the emission wavelength of the first sub-pixel 11 is greater than the emission wavelength of the second sub-pixel 12, and the emission wavelength of the second sub-pixel 12 is greater than the emission wavelength of the third sub-pixel 13; two adjacent pixel circuits P arranged along the row direction X constitute a sub-display group Pa; the sub-display group Pa includes a first sub-display group Pa1, and the two pixel circuits P in the first sub-display group Pa are the first pixel circuit P1 and the third pixel circuit P3, respectively; the multiple power signal lines 3 include a first power signal line 31 located in the gap between two adjacent pixel circuits P in the first sub-display group Pa.

[0169] In this display panel 100, the emission wavelength of the first sub-pixel 11 is greater than that of the second sub-pixel 12, and the emission wavelength of the second sub-pixel 12 is greater than that of the third sub-pixel 13. This allows the emission color of the first sub-pixel 11 to be red, the emission color of the second sub-pixel 12 to be green, and the emission color of the third sub-pixel 13 to be blue. When only the first sub-pixel 11 and the second sub-pixel 12 are emitted, the displayed image of the display panel 100 tends to be yellow; when only the second sub-pixel 12 and the third sub-pixel 13 are emitted, the displayed image of the display panel 100 tends to be cyan; and when only the first sub-pixel 11 and the third sub-pixel 13 are emitted, the displayed image of the display panel 100 tends to be purple.

[0170] It is understandable that, under photopic and scotopic vision, the human eye is more sensitive to different colors of light, such as... Figure 15 As shown, the horizontal axis represents the wavelength of light, and the vertical axis represents the normalized visually perceived brightness. Figure 15It is known that under photopic vision, the human eye's perceived brightness V(λ) reaches its peak when the light wavelength is 550nm, and under scotopic vision, the human eye's perceived brightness V´(λ) reaches its peak when the light wavelength is 510nm. Since the wavelength of yellow light is 580nm, the wavelength of violet light is 460nm, and the wavelength of cyan light is 490nm, the human eye has a lower visual sensitivity to violet light, while it has a higher visual sensitivity to yellow light and erotic light.

[0171] Continue to refer to Figure 14 In the first sub-display group Pa1, the two pixel circuits P are a first pixel circuit P1 and a third pixel circuit P3. The sub-pixel of the first pixel circuit P1 is a first sub-pixel 11 with a red emission color, and the sub-pixel of the third pixel circuit P3 is a third sub-pixel 13 with a blue emission color. By setting the first power signal line 31 in the gap between two adjacent pixel circuits P (P1 and P3) in the first sub-display group Pa1, at the beginning of a frame display time, the positive power signal PVDD transmitted on the first power signal line 31, which has a large instantaneous current and fluctuating voltage, will be coupled to the first pixel circuit P1 and the third pixel circuit P3 adjacent to the first power signal line 31, so that the first sub-pixel 11 of the first pixel circuit P1 and the third sub-pixel 13 of the third pixel circuit P3 will simultaneously display and emit light. When only the first power signal line 31 is provided in the display panel 100, the display light emitted by the positive power signal PVDD caused by the coupling effect of the instantaneous large current and fluctuating voltage will make the display screen of the display panel 100 tend to be purple. That is, the color of the display screen presented by the display panel 100 is closer to the color with lower visual sensitivity of the human eye, making the instantaneous display screen of the display panel 100 less likely to be perceived by the human eye. This helps to improve the screen flicker problem of the display panel 100 and improve the display effect of the display panel 100.

[0172] It is understandable that when pixel unit 1 includes sub-pixels 10 arranged along the row direction, including first sub-pixel 11, second sub-pixel 12, and third sub-pixel 13, two pixel circuits P in the same sub-display group Pa can belong to the same pixel unit 1 or to different pixel units 1. For example, in the same pixel unit 1, when the first sub-pixel 11, second sub-pixel 12, and third sub-pixel 13 are arranged sequentially along the row direction, the two pixel circuits P in the first sub-display group Pa1 belong to two adjacent pixel units 1. Correspondingly, sub-display group Pa can also include a second sub-display group Pa2 and a third sub-display group Pa3. In the second sub-display group Pa2, the two pixel circuits P arranged along the row direction X are the first pixel circuit P1 and the second pixel circuit P2, respectively. In the third sub-display area Pa3, the two pixel circuits P arranged along the row direction X are the second pixel circuit P2 and the third pixel circuit P3, respectively. The two pixel circuits P in the second sub-display group Pa2 can belong to the same pixel unit 1, and the two pixel circuits P in the third sub-display area Pa3 can also belong to the same pixel unit 1. Thus, any two adjacent pixel circuits P can form a sub-display group Pa, such that the second pixel circuit P2 in the second sub-display group Pa2 is also the second pixel circuit P2 in the third sub-display group Pa3, the third pixel circuit P3 in the third sub-display group Pa3 is also the third pixel circuit P3 in the first sub-display group Pa1, and the first pixel circuit P1 in the first sub-display area Pa1 is also the first pixel circuit P1 in the second sub-display area Pa2.

[0173] It should be noted that the above description describes the case where the power signal line is only set in the gap between two adjacent pixel circuits in the first sub-display group. However, in the embodiments of the present invention, the setting method of the power signal line is not limited to this. That is, the power signal line can also be set in the gap between two adjacent pixel circuits in the second sub-display group and / or the third sub-display group. The specific design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0174] In an optional embodiment, when the sub-display group Pa includes a first sub-display group Pa1, a second sub-display group Pa2, and a third sub-display group Pa3, and the two pixel circuits P in the first sub-display group Pa are the first pixel circuit P1 and the third pixel circuit P3 respectively, the two pixel circuits P in the second sub-display group Pa2 are the first pixel circuit P1 and the second pixel circuit P2 respectively, and the two pixel circuits P in the third sub-display group Pa are the second pixel circuit P2 and the third pixel circuit P3 respectively, the multiple power signal lines 3 may include not only the first power signal line 31 located in the gap between two adjacent pixel circuits P (P1 and P3) in the first sub-display group Pa1, but also the second power signal line 32 located in the gap between two adjacent pixel circuits P (P1 and P2) in the second sub-display group Pa2, and the third power signal line 33 located in the gap between two adjacent pixel circuits P (P2 and P3) in the third sub-display group Pa3.

[0175] At the beginning of a frame display, a positive power signal PVDD with a large instantaneous current and fluctuating voltage transmitted on the first power signal line 31 is coupled to the first pixel circuit P1 and the third pixel circuit P3 adjacent to the first power signal line 31, causing the first sub-pixel 11 of the first pixel circuit P1 and the third sub-pixel 13 of the third pixel circuit P3 to simultaneously illuminate; a positive power signal PVDD with a large instantaneous current and fluctuating voltage transmitted on the second power signal line 32 is coupled to the first pixel circuit P1 and the second pixel circuit P2 adjacent to the first power signal line 32, causing the first sub-pixel 11 of the first pixel circuit P1 and the second sub-pixel 12 of the second pixel circuit P2 to simultaneously illuminate; a positive power signal PVDD with a large instantaneous current and fluctuating voltage transmitted on the third power signal line 33 is coupled to the second pixel circuit P2 and the third pixel circuit P3 adjacent to the third power signal line 33, causing the second sub-pixel 11 of the first pixel circuit P1 and the second sub-pixel 12 of the second pixel circuit P2 to simultaneously illuminate; and a positive power signal PVDD with a large instantaneous current and fluctuating voltage transmitted on the third power signal line 33 is coupled to the second pixel circuit P2 and the third pixel circuit P3 adjacent to the third power signal line 33, causing the second sub-pixel 11 of the first pixel circuit P1 and the third sub-pixel 12 of the second pixel circuit P2 to simultaneously illuminate; and a positive power signal PVDD with a large instantaneous current and fluctuating voltage transmitted on the third power signal line 33 is coupled to the second pixel circuit P2 and the third pixel circuit P3 to simultaneously illuminate. The second sub-pixel 12 belonging to pixel circuit P2 and the third sub-pixel 13 belonging to third pixel circuit P3 simultaneously emit light. Thus, when the first power signal line 31, the second power signal line 32, and the third power signal line 33 are simultaneously provided in the display panel 100, the light emission caused by the coupling effect of the positive power signal PVDD with instantaneous large current and fluctuating voltage will result in the presence of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 emitting light in the display panel 100. When the brightness of the light emission of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 is consistent, the combination of the light emission colors of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 can make the overall display color of the display panel 100 tend to be white, which is beneficial to improving the overall color deviation of the display panel 100. Therefore, in bright environments, the instantaneous light emission of the display panel 100 is less likely to be perceived by the human eye, which in turn helps to improve the screen flicker problem of the display panel 100 and improve the display effect of the display panel 100.

[0176] It is understandable that, since the spacing Ll between two adjacent power signal lines 3 is greater than Lp, when the power signal line 3 includes the first power signal line 31, the second power signal line 32 and the third power signal line 33, it can still ensure that there are a small number of abnormally illuminated sub-pixels in the display panel 100, which helps to improve the screen flicker problem of the display panel 100 and improve the display effect of the display panel 100.

[0177] Furthermore, when the power signal line 3 includes a first power signal line 31, a second power signal line 32, and a third power signal line 33, the number of the first power signal line 31, the second power signal line 32, and the third power signal line 33 may be the same or different. The specific design can be made according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0178] In an alternative embodiment, reference continues. Figure 16 Among the multiple power signal lines 3, the number of first power signal lines 31 is greater than the number of second power signal lines 32, and the number of first power signal lines 31 is greater than the number of third power signal lines 33.

[0179] The fact that the number of first power signal lines 31 is greater than the number of second power signal lines 32 and the number of third power signal lines 33 can be understood as the total number of first power signal lines 31 in the display panel 100 being greater than the total number of second power signal lines 32 and the total number of third power signal lines 33. In an optional embodiment, the display panel 100 may have at least one first display area, in which the arrangement density of the first power signal lines 31 is greater than the arrangement density of the second power signal lines 32 and the arrangement density of the third power signal lines 33. For example, the first display area may have k11 first power signal lines 31, k21 second power signal lines 32, and k31 third power signal lines 33, where k11>k21 and k11>k31, and k11, k21, and k31 are all natural numbers. In other optional embodiments, the display panel 100 may also have at least one second display area. The number of first display areas may be greater than the number of second display areas. In the second display area, the density of the first power signal lines 31 may be less than or equal to the density of the second power signal lines 32 and / or the density of the third power signal lines 33. For example, the second display area may have k12 first power signal lines 31, k22 second power signal lines 32, and k32 third power signal lines 33, where k12 ≤ k22 and k12 ≤ k32, and k12, k22, and k32 are all natural numbers. Provided that the number of first power signal lines 31 is simultaneously greater than the number of second power signal lines 32 and the number of third power signal lines 33, the specific arrangement of the first power signal lines 31, second power signal lines 32, and third power signal lines 33 is not limited in this embodiment.

[0180] Correspondingly, by setting the number of first power signal lines 31 to be greater than the number of second power signal lines 32 and the number of third power signal lines 33, the number of first sub-display groups Pa1 with first power signal lines 31 is larger, while the number of second sub-display groups Pa2 with second power signal lines 32 and the number of third sub-display areas Pa3 with third power signal lines 33 are smaller. As a result, at the beginning of a frame display time, in the abnormal display light emitted due to the instantaneous large current and fluctuating voltage of the positive power signal PVDD, the amount of purple light is larger, while the amount of yellow light and cyan light is smaller.

[0181] Meanwhile, because the first sub-pixel 11 of the first pixel circuit P1 in the first sub-display group Pa1 and the third sub-pixel 13 of the third pixel circuit P3 emit light simultaneously, the emitted light color is purple; the first sub-pixel 11 of the first pixel circuit P1 in the second sub-display group Pa2 and the second sub-pixel 12 of the second pixel circuit P2 emit light simultaneously, the emitted light color is yellow; and the second sub-pixel 12 of the second pixel circuit P2 and the third sub-pixel 13 of the third pixel circuit P3 in the third sub-display group Pa3 emit light simultaneously, the emitted light color is cyan. And when the amount of purple light, yellow light and cyan light emitted from the sub-pixels in the display panel 100 is the same, the display screen of the display panel 100 seen by the human eye will be more cyan-yellow due to the human eye's visual sensitivity to purple light. Thus, at the beginning of a frame display, by increasing the amount of violet light (which has lower visual sensitivity to the human eye) and decreasing the amount of yellow and cyan light (which have higher visual sensitivity), the brightness of the violet light perceived by the human eye is kept consistent with the brightness of the yellow and cyan light. As a result, after the human eye mixes the violet, yellow, and cyan light, a display image that tends to be white can be seen, thereby balancing the color of the light received by the human eye and improving the color deviation of the display panel 100.

[0182] It is understood that when the number of the first power signal lines 31 is greater than the number of the second power signal lines 32 and the number of the third power signal lines 33, the number of the second power signal lines 32 may be the same as or different from the number of the third power signal lines 33. The specific design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0183] In an alternative embodiment, reference continues. Figure 16 Among the multiple power signal lines 3, the number of first power signal lines 31 is k1, the number of second power signal lines 32 is k2, and the number of third power signal lines 33 is k3; where k1:k2:k3=2:1:1.

[0184] Wherein, k1:k2:k3=2:1:1 can be understood as the display panel 100 having at least one first display area, in which the ratio of the number of first power signal lines 31, the number of second power signal lines 32, and the number of third power signal lines 33 is 2:1:1. The display panel 100 may also have at least one second display area, in which the ratio of the number of first power signal lines 31, the number of second power signal lines 32, and the number of third power signal lines 33 may not be equal to 2:1:1. Provided that the overall ratio of the total number of first power signal lines 31, the total number of second power signal lines 32, and the total number of third power signal lines 33 in the display panel 100 is 2:1:1, this embodiment of the invention does not specifically limit this ratio.

[0185] In this embodiment, by setting k1:k2:k3=2:1:1, the number of the first power signal line 31 is the sum of the number of the second power signal line 32 and the third power signal line 33, and the number of the second power signal line 32 can be equal to the number of the third power signal line 33, so as to ensure the overall wiring uniformity at the gap between the sub-pixels of the corresponding colors while improving the display color deviation.

[0186] In an alternative embodiment, such as Figure 17 As shown, m adjacent pixel units 1 arranged along the row direction X constitute a display unit group 1B; m is a positive integer greater than or equal to 2; among the p adjacent display unit groups 1B, there are a first display unit groups 1B1, b second display unit groups 1B2, and c third display unit groups 1B3; p = a + b + c, where p, a, b, and c are all positive integers; the sub-display group Pa of the first display unit group 1B1 includes a first sub-display group Pa1 with a first power signal line 31, the sub-display group Pa of the second display unit group 1B2 includes a second sub-display group Pa2 with a second power signal line 32, and the sub-display group Pa of the third display unit group 1B3 includes a third sub-display group Pa3 with a third power signal line 33.

[0187] Where p = a + b + c, and p, a, b, and c are all positive integers, such that p is a positive integer greater than or equal to 3. The specific value of p can be designed according to actual needs, and the embodiments of the present invention do not impose specific limitations on it. m is a positive integer greater than or equal to 2, that is, m can be equal to 2, or m can be other integers greater than 2. For the sake of simplicity in description and drawings, unless otherwise specified, the embodiments of the present invention use m equal to 2 as an example for illustrative explanation.

[0188] Specifically, since the first power signal line 31 is located between the first pixel circuit P1 and the third pixel circuit P3 in the first sub-display group Pa1, the second power signal line 32 is located between the first pixel circuit P1 and the second pixel circuit P2 in the second sub-display group Pa2, and the third power signal line 33 is located between the second pixel circuit P2 and the third pixel circuit P3 in the third sub-display group Pa3, by setting adjacent p display unit groups 1B to include a first display unit group 1B1, b second display unit groups 1B2, and c third display unit groups 1B3, adjacent p display unit groups 1B can be used as a power signal line 3 setting cycle, which is beneficial for the uniform wiring of power signal lines 3 in the display panel 100; at the beginning of the display time of one frame, because In the abnormal display luminescence sub-pixels caused by the instantaneous large current and fluctuating voltage of the positive power signal PVDD, the adjacent P display unit groups 1B may include a+b first sub-pixels 11, b+c second sub-pixels 12, and a+c third sub-pixels 13. This allows the abnormally luminous first sub-pixels 11, second sub-pixels 12, and third sub-pixels 13 to be arranged periodically. This avoids the bright display image in a certain area being captured by the human eye due to a large number of abnormally luminous sub-pixels in that area. As a result, the overall display uniformity of the display panel 100 can be improved, so that at the beginning of the display time of a frame, each area of ​​the display panel 100 has a low display luminescence brightness, improving the screen flicker problem and enhancing the display effect of the display panel 100.

[0189] It is understood that p power signal lines 3 can be provided in the area where p adjacent display unit groups 1B are located. The number a of the first power signal lines 31, the number b of the second power signal lines 32, and the number c of the third power signal lines 33 in the p power signal lines 3 can be designed according to actual needs. This embodiment of the invention does not make specific limitations on this.

[0190] In an optional embodiment, the number of first power signal lines 31 (a), the number of second power signal lines 32 (b), and the number of third power signal lines 33 (c) among adjacent p power signal lines 3 can satisfy the following ratio: a:b:c = 2:1:1. This arrangement ensures that the number of first power signal lines 31 (a) is the sum of the number of second power signal lines 32 (b) and the number of third power signal lines 33 (c). This improves the uniformity of signal line routing in the display panel 100 while balancing the colors of the displayed image as perceived by the human eye, thereby helping to improve color distortion.

[0191] It should be noted that, Figure 17The example only shows that in the adjacent p power signal lines 3, the first power signal line 31 is located between the second power signal line 32 and the third power signal line 33. However, in the embodiments of the present invention, the specific arrangement of the first power signal line 31, the second power signal line 32 and the third power signal line 33 can be designed according to actual needs. The embodiments of the present invention do not impose specific limitations on this.

[0192] In an alternative embodiment, such as Figure 18 As shown, along the row direction X, the four adjacent power signal lines 3 are sequentially named: first power signal line 31, second power signal line 32, first power signal line 31, and third power signal line 32. The second power signal line 32 and the third power signal line 33 can be separated by the first power signal line 31, such that the number of first power signal lines 31 is the sum of the number of second power signal lines 32 and third power signal lines 33. This allows the first sub-pixel 11 and the third sub-pixel 12 to emit abnormal light due to the positive power signal PVDD coupling on the first power signal line 31. The emitted light rays can be combined with the light rays emitted by the first sub-pixel 11 and the second sub-pixel 13 that are coupled with the positive power signal PVDD on the second power signal line 32 to produce abnormal display light emission, and the light rays emitted by the second sub-pixel 12 and the third sub-pixel 13 that are coupled with the positive power signal PVDD on the third power signal line 33 to produce abnormal display light emission, so as to ensure that the display light emission color of the display image at each position in the display panel 100 seen by the human eye is consistent, and to ensure that each position in the display panel 100 has a low display light emission brightness.

[0193] Meanwhile, by setting four adjacent power signal lines 3 as first power signal line 31, second power signal line 32, and third power signal line 32 in sequence, the first power signal line 31, second power signal line 32, and third power signal line 32 can be evenly distributed in the display panel 100. For example, every four power signal lines 3 constitute one power signal line setting cycle. This prevents abnormal display and illumination of a single color that is more easily captured by the human eye from occurring in a certain area due to the large number of power signal lines 3 of a certain type in that area. This helps to improve the overall display uniformity of the display panel and alleviate the screen flicker problem of the display panel.

[0194] It is understood that when the four adjacent power signal lines 3 are, in sequence, the spacing between the adjacent first power signal line 31 and the second power signal line 32, and the spacing between the adjacent first power signal line 31 and the second power signal line 32, and the spacing between the adjacent first power signal line 31 and the third power signal line 33, can be the same or different. The specific design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0195] In an optional embodiment, when the first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 in the pixel unit 1 are arranged sequentially along the row direction X, the spacing between the first power signal line 31 and the second power signal line 32, and the spacing between adjacent first power signal lines 31 and third power signal lines 33 are different spacings.

[0196] In another optional embodiment, the spacing between adjacent first power signal lines 31 and second power signal lines 32 is Ll1; the spacing between adjacent first power signal lines 31 and third power signal lines 33 is Ll2; wherein Ll1=Ll2. This configuration ensures that the spacing between two adjacent power signal lines 3 is a fixed value, allowing the power signal lines 3 to be evenly distributed in the display panel 100. This simplifies the wiring of the display panel 100 and improves the display uniformity of the display panel 100.

[0197] As a feasible embodiment, when the four adjacent power signal lines 3 are sequentially the first power signal line 311, the second power signal line 32, the second power signal line 312, and the third power signal line 33, and Ll1=Ll2, the four adjacent display unit groups 1B can be the first display unit group 1B11, the second display unit group 1B2, the second display unit group 1B12, and the third display unit group 1B3, respectively. In the same pixel unit 1 of the first display unit group 1B11, the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 are arranged sequentially along the row direction X. At this time, the first power signal line 311 can be located at the gap between the pixel circuits of two adjacent pixel units 1 in the first display unit group 1B11; in the same pixel unit 1 of the second display unit group 1B2, the first sub-pixel 11, the third sub-pixel 13, and the second sub-pixel 12 are arranged sequentially along the row direction X. At this time, the second power signal line 32 can be located at the gap between the pixel circuits of two adjacent pixel units 1 in the second display unit group 1B2. In the second first display unit group 1B12, the third sub-pixel 13, the second sub-pixel 12, and the first sub-pixel 11 in the same pixel unit 1 are arranged sequentially along the row direction X. In this case, the second first power signal line 312 can be located at the gap between the pixel circuits of two adjacent pixel units 1 in the second first display unit group 1B12. Similarly, in the third display unit group 1B3, the third sub-pixel 13, the first sub-pixel 11, and the second sub-pixel 12 in the same pixel unit 1 are arranged sequentially along the row direction X. In this case, the third power signal line 33 can be located at the gap between the pixel circuits of two adjacent pixel units 1 in the third display unit group 1B3. This configuration allows the power signal line 3 to be located at the gap between the pixel circuits of two adjacent pixel units 1. When the power signal line 3 is electrically connected to the pixel circuits in the pixel units 1 on its opposite sides, it ensures the consistency of the connection between the power signal line 3 and the pixel circuits in the pixel units 1 on its opposite sides. This ensures that the positive power signal PVDD provided by the power signal line 3 to the pixel circuits in the pixel units 1 on its opposite sides remains consistent, thereby improving the display uniformity of the display panel 100.

[0198] In other alternative embodiments, such as Figure 20As shown, the four adjacent power signal lines 3 can also be the second power signal line 32, the first power signal line 311, the third power signal line 33, and the second power signal line 312 in sequence. When Ll1=Ll2, the four adjacent display unit groups 1B can be the second display unit group 1B2, the first display unit group 1B11, the third display unit group 1B3, and the second display unit group 1B12, respectively. In the same pixel unit 1 of the second display unit group 1B2, the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 are arranged sequentially along the row direction X. At this time, the second power signal line 32 can be located at the gap between adjacent first pixel circuit P1 and second pixel circuit P2 in one of the pixel units 1 of the second display unit group 1B2. Similarly, in the same pixel unit 1 of the first display unit group 1B11, the first sub-pixel 11, the third sub-pixel 13, and the second sub-pixel 12 are arranged sequentially along the row direction X. At this time, the first power signal line 311 can be located at the gap between adjacent first pixel circuit P1 and third pixel circuit P3 in one of the pixel units 1 of the first display unit group 1B11. In the third display unit group 1B3, the third sub-pixel 13, the second sub-pixel 12, and the first sub-pixel 11 in the same pixel unit 1 are arranged sequentially along the row direction X. In this case, the third power signal line 33 can be located at the gap between adjacent third pixel circuits P3 and P2 in one of the pixel units 1 of the third display unit group 1B3. Similarly, in the second first display unit group 1B12, the first sub-pixel 11, the third sub-pixel 13, and the second sub-pixel 12 in the same pixel unit 1 are arranged sequentially along the row direction X. In this case, the second first power signal line 312 can be located at the gap between adjacent third pixel circuits P3 and P1 in one of the pixel units 1 of the second first display unit group 1B12. This arrangement ensures that the power signal line 3 is located at the gap between adjacent pixel circuits in the same pixel unit 1, thereby improving the display uniformity of the display panel 100.

[0199] It is understood that the specific arrangement of the first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 of the same pixel unit 1 in the display panel 100 can be designed according to actual needs. Under the premise that the spacing between two adjacent power signal lines 3 can be ensured to be a fixed value, the embodiments of the present invention do not make specific limitations on this.

[0200] It should be noted that the above is only an exemplary description of the distribution of power signal lines when the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In the embodiments of the present invention, the pixel unit may also include other sub-pixels. When the pixel unit includes other sub-pixels, the distribution of power signal lines needs to be adjusted according to actual needs. Specifically, it can be designed according to actual needs. The embodiments of the present invention do not make specific limitations in this regard.

[0201] In an alternative embodiment, such as Figures 21 to 23 As shown, pixel unit 1 includes a first sub-pixel 11, a second sub-pixel 12, a third sub-pixel 13, and a fourth sub-pixel 14 arranged along the row direction X; the pixel circuit of the first sub-pixel 11 is the first pixel circuit P1, the pixel circuit of the second sub-pixel 12 is the second pixel circuit P2, the pixel circuit of the third sub-pixel 13 is the third pixel circuit P3, and the pixel circuit of the fourth sub-pixel 14 is the fourth pixel circuit P4; the emission wavelength of the first sub-pixel 11 is greater than the emission wavelength of the second sub-pixel 12, the emission wavelength of the second sub-pixel 12 is greater than the emission wavelength of the third sub-pixel 13, and the display emission color of the fourth sub-pixel 14 includes at least the combined emission colors of the first sub-pixel 11 and the second sub-pixel 12; the distance between the power signal line 3 and the fourth pixel circuit P4 in the row direction X is d1; where d1>d0, and d0 is the size of the pixel circuit in the row direction X.

[0202] Specifically, when the emission wavelength of the first sub-pixel 11 is greater than that of the second sub-pixel 12, and the emission wavelength of the second sub-pixel 12 is greater than that of the third sub-pixel 13, the display emission color of the first sub-pixel 11 can be red, the display emission color of the second sub-pixel 12 can be green, and the display emission color of the third sub-pixel 13 can be blue. When the display emission color of the fourth sub-pixel 14 includes a combination of the emission colors of the first sub-pixel 11 and the second sub-pixel 12, the display emission color of the fourth sub-pixel 14 can be yellow. Alternatively, the display emission color of the fourth sub-pixel 14 can also include a combination of the emission colors of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13, in which case the display emission color of the fourth sub-pixel 14 can be white. The specific display emission color of the fourth sub-pixel 14 can be designed according to actual needs, and this embodiment of the invention does not impose specific limitations on it.

[0203] Understandably, when the display emission color of the fourth sub-pixel 14 is yellow, the fourth sub-pixel 14 can work in conjunction with the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 to expand the color gamut range of the display panel 100, especially to compensate for the deficiencies of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 in the yellow-green-red transition area. At the same time, the light-emitting layer material of the light-emitting element in the fourth sub-pixel 14 is yellow light-emitting material, the light-emitting layer material of the light-emitting element in the first sub-pixel 11 is red light-emitting material, and the light-emitting layer material of the light-emitting element in the second sub-pixel 12 is green light-emitting material. Generally, the conversion efficiency of yellow light-emitting material is higher than that of red and green light-emitting materials. Therefore, by adding a fourth sub-pixel, the overall display emission brightness of the display panel can be improved to a certain extent, and the power consumption of the display panel can be reduced.

[0204] It is also understandable that when the display emission color of the fourth sub-pixel 14 is white, the fourth sub-pixel 14 does not need to be mixed with sub-pixels of other colors to emit white light, so that the fourth sub-pixel 14 has a high white light emission efficiency, thereby improving the display emission brightness of the display panel 100, improving visibility in high brightness environments, and helping to reduce the power consumption of the display panel 100.

[0205] However, regardless of whether the color of the light emitted by the fourth sub-pixel 14 is yellow or white, the human eye has a high visual sensitivity to the light emitted by the fourth sub-pixel 14. Therefore, when a large number of fourth sub-pixels 14 are abnormally emitting light at the beginning of a frame display, the human eye is more likely to see the displayed image on the display panel 100, thus causing screen flickering.

[0206] In this embodiment, the distance between the power signal line 3 and the fourth pixel circuit P4 in the row direction X is at least d1, that is, the minimum distance between the power signal line 3 and the fourth pixel circuit P4 is d1. In other words, the distance between the power signal line 3 and the fourth pixel circuit P4 can be greater than or equal to d1. At the same time, d1 is greater than the size d0 of a pixel circuit in the row direction X, that is, the distance between the power signal line 3 and the fourth pixel circuit P4 in the row direction X is greater than the size d0 of a pixel circuit in the row direction X. This results in a larger distance between the power signal line 3 and the fourth pixel circuit P4, reducing the size of the parasitic capacitance formed by the power signal line 3 and the fourth pixel circuit P4. This reduces the amount of positive power signal PVDD with instantaneous large current and fluctuating voltage transmitted on the power signal line 3 coupled to the fourth pixel circuit P4. This prevents the fourth pixel circuit 14 from producing excessively bright abnormal display light that can be captured by the human eye, thereby improving the screen flicker problem and enhancing the display effect of the display panel 100.

[0207] When the pixel circuits are arranged along the row direction X and the spacing between two adjacent pixel circuits is less than the size of the pixel circuit in the row direction X, by making the spacing d1 between the power signal line 3 and the fourth pixel circuit P4 in the row direction X greater than the size d0 of a pixel circuit in the row direction X, at least one other pixel circuit can be provided between the power signal line 3 and the fourth pixel circuit P4. This other pixel circuit can serve as an isolation structure between the power signal line 3 and the fourth pixel circuit P4, so that the power signal line 3 is not directly adjacent to the fourth pixel circuit P4, and the power signal line 3 cannot form a parasitic capacitance with the fourth pixel circuit P4. This prevents the positive power signal PVDD with instantaneous large current and fluctuating voltage transmitted by the power signal line 3 from coupling into the fourth pixel circuit P4, causing the light-emitting element driven by the fourth pixel circuit P4 to exhibit abnormal display light emission, thereby improving the screen flicker problem and enhancing the display effect of the display panel 100.

[0208] Furthermore, when at least one other pixel circuit is disposed between the power signal line 3 and the fourth pixel circuit P4, the pixel circuit spaced between the power signal line 3 and the fourth pixel circuit P4 can be at least one of the first pixel circuit P1, the second pixel circuit P2, and the third pixel circuit P3. The power signal line 3 can be disposed between adjacent first pixel circuits P1 and second pixel circuits P2 arranged along the row direction X, or between adjacent second pixel circuits P2 and third pixel circuits P3 arranged along the row direction X, or between adjacent first pixel circuits P1 and third pixel circuits P2 arranged along the row direction X. The correspondence between the power signal line 3 and the pixel circuits can be designed according to actual needs, and this embodiment of the invention does not impose specific limitations on this.

[0209] In an alternative embodiment, reference is made to... Figure 21 , Figure 24 and Figure 25 In the same pixel unit 1, the first pixel circuit P1, the second pixel circuit P2, the third pixel circuit P3 and the fourth pixel circuit P4 are arranged sequentially along the row direction X; the multiple power signal lines 3 include a second power signal line 32 located in the gap between adjacent first pixel circuit P1 and second pixel circuit P2, and / or a third power signal line 33 located in the gap between adjacent second pixel circuit P2 and third pixel circuit P3.

[0210] The power signal line 3 may include a second power signal line 32 and / or a third power signal line 33, i.e., as shown in the figure. Figure 21 As shown, power signal line 3 may include only the third power signal line 33, or, as... Figure 24 As shown, power signal line 3 may include only the second power signal line 32, or, as... Figure 25As shown, the second power signal line 32 may include both the second power signal line 32 and the third power signal line 33. The specific design can be made according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0211] In this embodiment, by including a second power signal line 32 located in the gap between adjacent first pixel circuit P1 and second pixel circuit P2, and / or a third power signal line 33 located in the gap between adjacent second pixel circuit P2 and third pixel circuit P3, the power signal line 3 can be moved away from the fourth pixel circuit P4. This prevents the positive power signal PVDD with instantaneous large current and fluctuating voltage transmitted by the power signal line 3 from coupling into the fourth pixel circuit P4, which would cause the light-emitting element driven by the fourth pixel circuit P4 to exhibit abnormal display light emission. This can improve the screen flicker problem and enhance the display effect of the display panel 100.

[0212] It should be noted that the above is only an exemplary description of the arrangement of pixel circuits in the same pixel unit. In the embodiments of the present invention, the arrangement of pixel circuits in the same pixel unit is not limited to this. It can be designed according to actual needs. The embodiments of the present invention do not make specific limitations in this regard.

[0213] In an alternative embodiment, reference is made to... Figure 22 , Figure 26 and Figure 27 In the same pixel unit 1, the fourth pixel circuit P4, the first pixel circuit P1, the second pixel circuit P2 and the third pixel circuit P3 are arranged sequentially along the row direction X. At this time, the power signal line 3 may also include the second power signal line 32 located in the gap between the adjacent first pixel circuit P1 and the second pixel circuit P2, and / or the third power signal line 33 located in the gap between the adjacent second pixel circuit P2 and the third pixel circuit P3.

[0214] In another alternative embodiment, refer to Figure 23 , Figure 28 and Figure 29 In the same pixel unit 1, the fourth pixel circuit P4, the first pixel circuit P1, the third pixel circuit P3 and the second pixel circuit P2 are arranged sequentially along the row direction X. At this time, the power signal line 3 may include the first power signal line 31 located in the gap between the adjacent first pixel circuit P1 and the third pixel circuit P3, and / or the third power signal line 33 located in the gap between the adjacent third pixel circuit P3 and the second pixel circuit P2.

[0215] In yet another alternative embodiment, refer to Figure 23 and Figure 30In the same pixel unit 1, the first pixel circuit P1 and the third pixel circuit P3 are adjacent, or in two adjacent pixel units 1, the first pixel circuit P1 and the third pixel circuit P3 are adjacent; the multiple power signal lines 3 include a first power signal line 31 located in the gap between the adjacent first pixel circuit P1 and the third pixel circuit P3.

[0216] When adjacent first pixel circuit P1 and third pixel circuit P3 exist in the pixel circuits arranged along the row direction, the power signal line 3 may include a first power signal line 31 located between adjacent first pixel circuits P1 and third pixel circuits P3 arranged along the row direction. In this case, the display panel 100 may only have the first power signal line 31, so that at the beginning of the display time of a frame, the positive power signal PVDD with a large instantaneous current and fluctuating voltage is coupled only to a portion of the first pixel circuit P1 and third pixel circuit P3, and not coupled to the second pixel circuit P2 and fourth pixel circuit P4. This causes the display light emitted due to the coupling effect of the positive power signal PVDD with a large instantaneous current and fluctuating voltage to tend towards purple, that is, the color of the display screen presented by the display panel 100 tends to be a color with low visual sensitivity to the human eye, making the instantaneous display screen of the display panel 100 less likely to be perceived by the human eye, thereby helping to improve the screen flicker problem of the display panel 100 and improve the display effect of the display panel 100.

[0217] It should be noted that the above description only illustrates the case where the arrangement of pixel circuits in each pixel unit is the same. In the embodiments of the present invention, the pixel circuits in each pixel unit may also have different arrangements. Provided that the distance between the power signal line and the fourth pixel circuit in the row direction is greater than the size of a pixel circuit in the row direction, the embodiments of the present invention do not limit the arrangement of pixel circuits in pixel units and the specific setting of power signal lines.

[0218] Optional, see reference Figure 31As shown, m adjacent pixel units constitute a display unit group 1B; the power signal line is electrically connected to the pixel circuits in the same display unit group; m is a positive integer; the p adjacent display unit groups 1B include a first display unit group 1B1, b second display unit groups 1B2, and c third display unit groups 1B3; p = a + b + c, where p, a, b, and c are all positive integers; the first display unit group 1B1 includes adjacent first pixel circuits P1 and the third pixel circuits P3, and the power signal line electrically connected to the pixel circuits in the first display unit group 1B1 is located in the adjacent... The gap between pixel circuit P1 and third pixel circuit P3; the second display unit group 1B2 includes adjacent first pixel circuit P1 and second pixel circuit P2, and the power signal line electrically connected to the pixel circuits in the second display unit group 1B2 is located in the gap between adjacent first pixel circuit P1 and second pixel circuit P3; the third display unit group 1B3 includes adjacent second pixel circuit P2 and third pixel circuit P3, and the power signal line electrically connected to the pixel circuits in the third display unit group 1B3 is located in the gap between adjacent second pixel circuit P2 and third pixel circuit P3.

[0219] Where p = a + b + c, and p, a, b, and c are all positive integers, such that p is a positive integer greater than or equal to 3. The specific value of p can be designed according to actual needs, and the embodiments of the present invention do not impose specific limitations on it. m is a positive integer greater than or equal to 2, that is, m can be equal to 2, or m can be other integers greater than 2. For the sake of simplicity in description and drawings, unless otherwise specified, the embodiments of the present invention use m equal to 2 as an example for illustrative explanation.

[0220] Specifically, by setting adjacent p display unit groups 1B to include a first display unit group 1B1, b second display unit group 1B2, and c third display unit group 1B3, the adjacent p display unit groups 1B can be used as a power signal line 3 for setting a cycle, which is beneficial for the uniform routing of power signal lines 3 in the display panel 100. Simultaneously, the power signal lines 3 electrically connected to the pixel circuits in the first display unit group 1B1 are located between adjacent first pixel circuits P1 and third pixel circuits P3; the power signal lines 3 electrically connected to the pixel circuits in the second display unit group 1B2 are located between adjacent first pixel circuits P1 and second pixel circuits P2; and the power signal lines 3 electrically connected to the pixel circuits in the third display unit group 1B3 are located between adjacent second pixel circuits P2 and third pixel circuits P3, so that within a frame... At the start of the display time, in the sub-pixels that are abnormally illuminated due to the instantaneous large current and fluctuating voltage of the positive power signal PVDD, the adjacent P display unit groups 1B may include a+b first sub-pixels 11, b+c second sub-pixels 12, and a+c third sub-pixels 13. This allows the abnormally illuminated first sub-pixels 11, second sub-pixels 12, and third sub-pixels 13 to be arranged periodically. This avoids the bright display image in a certain area being captured by the human eye due to a large number of abnormally illuminated sub-pixels in that area, thereby improving the overall display uniformity of the display panel 100. At the start of the display time of a frame, each area of ​​the display panel 100 has a low display brightness, improving the screen flicker problem and enhancing the display effect of the display panel 100.

[0221] It is understood that when the power signal line 3 located in the gap between adjacent first pixel circuit P1 and third pixel circuit P3 is the first power signal line 31, the power signal line 3 located in the gap between adjacent first pixel circuit P1 and second pixel circuit P2 is the second power signal line 32, and the power signal line 3 located in the gap between adjacent second pixel circuit P2 and third pixel circuit P3 is the third power signal line 33, p power signal lines 3 can be provided in the area where the adjacent p display unit groups 1B are located. The number a of the first power signal lines 31, the number b of the second power signal lines 32, and the number c of the third power signal lines 33 in the p power signal lines 3 can be designed according to actual needs. This embodiment of the invention does not make specific limitations on this.

[0222] In an alternative embodiment, reference continues. Figure 31In a series of adjacent p power signal lines 3, the number of first power signal lines 31 (a), the number of second power signal lines 32 (b), and the number of third power signal lines 33 (c) can satisfy the following ratio: a:b:c = 2:1:1. This arrangement ensures that the number of first power signal lines 31 (a) is equal to the sum of the number of second power signal lines 32 (b) and the number of third power signal lines 33 (c). This improves the uniformity of the signal line wiring in the display panel 100, balances the colors of the displayed image as perceived by the human eye, and thus helps to improve color distortion.

[0223] It is understood that when the four adjacent power signal lines 3 are sequentially the first power signal line 31, the second power signal line 32, the first power signal line 31 and the third power signal line 33, the spacing L11 between the adjacent first power signal line 31 and the second power signal line 32, and the spacing L12 between the adjacent first power signal line 31 and the third power signal line 33 can be the same or different. The specific design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0224] As one possible implementation, please continue to refer to Figure 31When the four adjacent power signal lines 3 are, in sequence, the first power signal line 311, the second power signal line 32, the second power signal line 312, and the third power signal line 33, and Ll1=Ll2, the four adjacent display unit groups 1B can be, respectively, the first display unit group 1B11, the second display unit group 1B2, the second display unit group 1B12, and the third display unit group 1B3. In the same pixel unit 1 of the first display unit group 1B11, the first pixel circuit P1, the second pixel circuit P2, the fourth pixel circuit P4, and the third pixel circuit P3 are arranged sequentially along the row direction X. At this time, the first power signal line 311 can be located at the gap between the pixel circuits of two adjacent pixel units 1 in the first display unit group 1B11. In the same pixel unit 1 of the second display unit group 1B2, the second pixel circuit P2, the third pixel circuit P3, the fourth pixel circuit P4, and the first pixel circuit P1 are arranged sequentially along the row direction X. At this time, the second power signal line 32 can be located at the gap between the pixel circuits of two adjacent pixel units 1 in the second display unit group 1B2. In the same pixel unit 1 of the second first display unit group 1B12, the third pixel circuit P3, the fourth pixel circuit P4, the second pixel circuit P2, and the first pixel circuit P1 are arranged sequentially along the row direction X. At this time, the second first power signal line 312 can be located at the gap between the pixel circuits of two adjacent pixel units 1 in the second first display unit group 1B12. In the same pixel unit 1 of the third display unit group 1B3, the third pixel circuit P3, the fourth pixel circuit P4, the first pixel circuit P1, and the second pixel circuit P2 are arranged sequentially along the row direction X. At this time, the third power signal line 33 can be located at the gap between the pixel circuits of two adjacent pixel units 1 in the third display unit group 1B3. With this configuration, the power signal line 3 can be located in the gap between the pixel circuits of two adjacent pixel units 1. When the power signal line 3 is electrically connected to the pixel circuits in the pixel units 1 on its opposite sides, the connection consistency of the power signal line 3 and the pixel circuits in the pixel units 1 on its opposite sides can be ensured. This ensures that the positive power signal PVDD provided by the power signal line 3 to the pixel circuits in the pixel units 1 on its opposite sides remains consistent, thereby improving the display uniformity of the display panel 100.

[0225] It should be noted that the above description only illustrates the arrangement of power signal lines under different pixel arrangements. However, the arrangement of power signal lines is not limited to this, provided that the core inventive points of this embodiment are achieved. Correspondingly, when the display panel includes both power signal lines and data signal lines, the position of the data signal lines can be adjusted according to the position of the power signal lines, or the position of the power signal lines can also be adjusted according to the arrangement of the data signal lines. The specific design can be tailored to actual needs. This embodiment of the invention does not impose specific limitations in this regard.

[0226] In an alternative embodiment, reference is made to... Figure 11 and Figure 32 The data signal line 2 is located in the gap between two pixel circuits P that are electrically connected to it and arranged along the row direction X.

[0227] The data signal line 2 can maintain the same spacing as the pixel circuits P located on its opposite sides, so that when the data signal line 2 is electrically connected to the pixel circuits P on its opposite sides, the connection path between the data signal line 2 and each pixel circuit P can be kept consistent, so that the transmission impedance of the data signal provided to each pixel circuit P is kept consistent, thereby ensuring that the data signal received by the pixel circuit P is consistent, and thus improving the display uniformity of the display panel 100.

[0228] Based on the above embodiments, optionally, the pixel circuits P of two adjacent sub-pixels 10 electrically connected by the same data signal line 2 are centrally symmetrical about the data signal line. In this way, with the data signal line 2 as the axis of symmetry, the signal transmission path length, parasitic capacitance distribution, and pixel circuit layout of the pixel circuits P on both sides can be kept consistent, which simplifies the design of the pixel circuit P and helps to improve the display uniformity of the display panel 100.

[0229] Based on the above embodiments, optionally, refer to the following: Figure 11 and Figure 32 The gap between two adjacent pixel circuits P arranged along the row direction X is called the pixel gap; the power signal line 3 and the data signal line 2 are respectively set in different pixel gaps. In this way, only one of the power signal line 3 and the data signal line 2 can be set in the gap between two adjacent pixel circuits P, preventing the power signal line 3 and the data signal line 2 from accumulating in the same pixel gap. This is beneficial to the uniformity of the signal line wiring in the display panel 100. While simplifying the design of the display panel 100, it can ensure that the parasitic capacitance between each pixel circuit P and the signal line remains consistent, thereby improving the display uniformity of the display panel 100.

[0230] Based on the above embodiments, optionally, refer to the following: Figure 11 and Figure 32 In the horizontal direction X, the line width of power signal line 3 is W1, and the line width of data signal line 2 is W2; where 2×W2≤W1≤6×W2.

[0231] Since data signal line 2 is electrically connected to two adjacent pixel circuits P, and power signal line 3 is electrically connected to multiple pixel circuits P, and the positive power signal transmitted by power signal line 3 is usually a fixed voltage signal, the voltage drop of the positive power signal caused by the transmission path cannot be compensated. By setting the line width W1 of power signal line 3 to be greater than the line width W2 of data signal line 2, it is possible to ensure that power signal line 3 has a wider width, so that power signal line 3 has a smaller impedance per unit length. This reduces the impedance of the positive power signal PVDD transmitted by power signal line 3, improves the accuracy of the positive power signal PVDD received by pixel circuit P, and enables pixel circuit P to accurately drive the light-emitting elements electrically connected to it to emit light for display, thereby improving the display quality of display panel 100.

[0232] It is understandable that the wider the power signal line 3, the larger its cross-sectional area, and the lower its impedance per unit length. However, when the power signal line 3 has a large width, it occupies more space, which is detrimental to the high resolution of the display panel 100. Therefore, by ensuring that the line width W1 of the power signal line 3 and the line width W2 of the data signal line 2 satisfy 2×W2≤W1≤6×W2, the resolution of the display panel 100 is guaranteed while maintaining a low impedance for the power signal line 3, thereby improving the display effect of the display panel 100.

[0233] Based on the above embodiments, optionally, such as Figure 33 and Figure 34 As shown, the display panel 100 may include a display area AA and a non-display area NA surrounding the display area AA; pixel unit 1, power signal line 3 and data signal line 2 are all located in the display area AA; the non-display area NA includes a fan-out area NA1 located on one side of the display area AA; the fan-out area NA1 is provided with multiple fan-out traces 7; the multiple fan-out traces 7 include multiple first fan-out traces 71 corresponding to multiple power signal lines 3, and multiple second fan-out traces 72 corresponding to multiple data signal lines 2, the first fan-out traces 71 are electrically connected to the power signal lines 3 respectively; the second fan-out traces 72 are electrically connected to the data signal lines 2 respectively; the display panel 100 also includes at least one conductive layer (Col1 and Col2); the first fan-out traces 71 are located in the same conductive layer Col1.

[0234] It is understood that the display panel 100 may include at least one conductive layer, that is, the display panel 100 may include one or more conductive layers. When the display panel 100 includes multiple conductive layers, an insulating layer is disposed between adjacent conductive layers. For example, when the display panel 100 includes conductive layers Col1 and Col2, both conductive layers Col1 and Col2 can be disposed at an insulating interval on one side of the substrate Cl1. In this case, an insulating layer In1 can be disposed between conductive layers Col1 and Col2 to insulate them from each other. Furthermore, when the display panel 100 includes multiple conductive layers, the multiple conductive layers can be made of the same or different conductive materials, so that the conductivity of the multiple conductive layers can be the same or different. The specific design can be tailored to actual needs, and this embodiment of the invention does not impose specific limitations on this.

[0235] The first outgoing trace 71 is electrically connected to the power signal line 3, so that the power signal line 3 receives the positive power signal provided by the power management chip or flexible circuit board through the first outgoing trace 71. By setting the first outgoing trace 71 in the same conductive layer Col1, the first outgoing trace 71 can have the same conductivity, thereby ensuring that the signal transmission impedance of each first outgoing trace 71 is consistent, so that the positive power signal received by the power signal line 3 is consistent, which helps to improve the display uniformity of the display panel 100.

[0236] Furthermore, when the first outgoing trace 71 is located in the same conductive layer Col1, the second outgoing trace 72, which is electrically connected to the data signal line 2, can also be located in the same conductive layer Col2 to ensure that the signal transmission impedance of each second outgoing trace 72 remains consistent, so that the data signal received by the data signal line 2 remains consistent, thereby improving the display uniformity of the display panel 100.

[0237] In other alternative embodiments, such as Figure 33 and Figure 35 As shown, the conductive layer may include a first conductive layer Col21 and a second conductive layer Col22 with insulating spacing; two adjacent second fan-out traces 72 are located in the first conductive layer Col21 and the second conductive layer Col22, respectively.

[0238] When the conductive layer includes a first conductive layer Col21 and a second conductive layer Col22 with an insulating gap, the first conductive layer Col21 and the second conductive layer Col22 may be provided with an insulating layer Inl2, so that the structure in the first conductive layer Col21 is insulated from the structure in the second conductive layer Col22.

[0239] Since the second outgoing trace 72 is electrically connected to the corresponding data signal line 2, the number of the second outgoing trace 72 and the data signal line 2 are kept consistent. When the number of second outgoing traces 72 is large, the wiring density of the second outgoing traces 72 in the fan-out area NA1 is large, resulting in a small spacing between two adjacent second outgoing traces 72, which can easily cause signal crosstalk. By setting two adjacent second fan-out traces 72 in the first conductive layer Col21 and the second conductive layer Col22 respectively, for example, two adjacent third fan-out traces 72 are the first second fan-out trace 721 and the second second fan-out trace 722 respectively. The first second fan-out trace 721 can be located in the first conductive layer Col21 and the second second fan-out trace 722 can be located in the second conductive layer Col22. In this way, two adjacent second fan-out traces 72 can be alternately set in the first conductive layer Col21 and the second conductive layer Col22, which can reduce the wiring density of the second fan-out traces 72 in one conductive layer, which is beneficial to increase the spacing of the second fan-out traces 72 in the same conductive layer and improve the signal crosstalk problem. Meanwhile, by alternately setting two adjacent second fan-out traces 72 in the first conductive layer Col21 and the second conductive layer Col22, the second fan-out traces 72 can have a large angle with the column direction Y, thereby reducing the space occupied by the second fan-out traces 72 in the column direction Y, which is beneficial to the narrow bezel of the display panel 100.

[0240] It is understandable that the first outgoing line 71 and the second outgoing line 72 can be located on different conductive layers. In this case, an insulating layer Inl1 can be provided between the conductive layer Col1 used to set the first outgoing line 71 and the conductive layer (Col21) used to set the second outgoing line 72, so that the first outgoing line 71 and the second outgoing line 72 are insulated from each other, and the positive power signal transmitted by the first outgoing line 71 and the positive power signal transmitted by the second outgoing line 72 do not interfere with each other.

[0241] It should be noted that the above description only illustrates the case where the first and second outgoing traces are located on different conductive layers. In the embodiments of the present invention, the display panel may also have some first outgoing traces and some second outgoing traces located on the same conductive layer. The specific design can be made according to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0242] In an alternative embodiment, reference is made to... Figure 33 and Figure 36The display panel 100 includes a display area AA and a non-display area NA surrounding the display area AA. Pixel units 1, power signal lines 3, and data signal lines 2 are all located in the display area AA. The non-display area NA includes a fan-out area NA1 located on one side of the display area AA, and the fan-out area NA1 is provided with multiple fan-out traces 7. The multiple fan-out traces 7 include multiple first fan-out traces 71 corresponding to multiple power signal lines 3, and multiple second fan-out traces 72 corresponding to multiple data signal lines 2. The first fan-out traces 71 are electrically connected to the power signal lines 3, and the second fan-out traces 72 are electrically connected to the data signal lines 2. The display panel 100 includes a first conductive layer Col21 and a second conductive layer Col22 disposed with insulating intervals. Two adjacent fan-out traces 7 are located in the first conductive layer Col21 and the second conductive layer Col22, respectively.

[0243] In this configuration, two adjacent fan-out traces 7 arranged along the row direction of pixel unit 1 can be either a first fan-out trace 71 and a second fan-out trace 72, or two second fan-out traces 72. By placing the two adjacent fan-out traces 7 in the first conductive layer Col21 and the second conductive layer Col22 respectively, the density of fan-out traces 7 in the same conductive layer can be relatively reduced, signal crosstalk between fan-out traces 7 can be reduced, and the space occupied by the fan-out traces 7 in the column direction Y can be relatively reduced, which is beneficial for the narrow bezel of the display panel 100. Furthermore, since the two adjacent fan-out traces 7 can be either a first fan-out trace 71 and a second fan-out trace 72, or two second fan-out traces 72, some of the second fan-out traces 72 can be located in the same conductive layer as the first fan-out trace 71, eliminating the need for separate additional film layers for the first fan-out trace 71 or the second fan-out trace 72. This simplifies the film layer structure of the display panel 100 and contributes to the thinning and lightening of the display panel 100.

[0244] It is understood that when two adjacent fan-out traces 7 are located in the first conductive layer Col21 and the second conductive layer Col22 respectively, multiple first fan-out traces 71 can be located in the same conductive layer, or multiple first fan-out traces 71 can be distributed in the first conductive layer Col21 and the second conductive layer Col22. The design can be made according to actual needs, and the embodiments of the present invention do not make specific limitations in this regard.

[0245] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, this display device possesses the technical features of the display panel provided in the embodiments of the present invention and can achieve the beneficial effects of the display panel provided in the embodiments of the present invention. Similarities can be found in the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0246] For example, Figure 37This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 37 As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0247] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: The array consists of multiple pixel units, multiple power signal lines, and multiple data signal lines. The pixel unit includes multiple sub-pixels with different emission colors; The sub-pixel includes an electrically connected pixel circuit and a light-emitting element; The pixel circuits in two adjacent columns are electrically connected to the same data signal line; The power signal lines are arranged along the row direction of the pixel unit and extend along the column direction of the pixel unit; the spacing between two adjacent power signal lines is Ll; where Ll ≥ Lp, and Lp is the size of a pixel unit in the row direction.

2. The display panel according to claim 1, characterized in that, The spacing between two adjacent power signal lines is 2n×Lp; 1≤n≤5, and n is a positive integer.

3. The display panel according to claim 1, characterized in that, The power signal line is electrically connected to the pixel circuits in the 2n pixel units arranged along the row direction; n is a positive integer.

4. The display panel according to claim 3, characterized in that, n adjacent pixel units arranged along the row direction constitute a pixel unit group; The power signal lines are electrically connected to the pixel circuits in the two pixel unit groups on their opposite sides.

5. The display panel according to claim 4, characterized in that, The power signal line is located in the gap between two adjacent pixel unit groups arranged along the row direction.

6. The display panel according to claim 1, characterized in that, The pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along the row direction; the pixel circuit of the first sub-pixel is a first pixel circuit, the pixel circuit of the second sub-pixel is a second pixel circuit, and the pixel circuit of the third sub-pixel is a third pixel circuit. The emission wavelength of the first sub-pixel is greater than that of the second sub-pixel, and the emission wavelength of the second sub-pixel is greater than that of the third sub-pixel; Two adjacent pixel circuits arranged along the row direction constitute a sub-display group; the sub-display group includes a first sub-display group, and the two pixel circuits in the first sub-display group are the first pixel circuit and the third pixel circuit, respectively; The plurality of power signal lines include a first power signal line located in the gap between two adjacent pixel circuits in the first sub-display group.

7. The display panel according to claim 6, characterized in that, The sub-display group further includes a second sub-display group and a third sub-display group; The two pixel circuits in the second sub-display group are the first pixel circuit and the second pixel circuit, respectively; the two pixel circuits in the third sub-display group are the second pixel circuit and the third pixel circuit, respectively; The plurality of power signal lines include a second power signal line located in the gap between two adjacent pixel circuits in the second sub-display group, and a third power signal line located in the gap between two adjacent pixel circuits in the third sub-display group.

8. The display panel according to claim 7, characterized in that, Of the multiple power signal lines, the number of the first power signal lines is greater than the number of the second power signal lines, and the number of the first power signal lines is greater than the number of the third power signal lines.

9. The display panel according to claim 8, characterized in that, Of the multiple power signal lines, the number of the first power signal lines is k1, the number of the second power signal lines is k2, and the number of the third power signal lines is k3. Where k1:k2:k3 = 2:1:

1.

10. The display panel according to claim 9, characterized in that, Along the row direction, the four adjacent power signal lines are, in sequence, the first power signal line, the second power signal line, the first power signal line, and the third power signal line.

11. The display panel according to claim 10, characterized in that, The spacing between adjacent first power signal lines and second power signal lines is Ll1; the spacing between adjacent first power signal lines and third power signal lines is Ll3; wherein, Ll1=Ll3.

12. The display panel according to claim 7, characterized in that, A group of m adjacent pixel units arranged along the row direction constitutes a display unit group; m is a positive integer greater than or equal to 2. The p adjacent display unit groups include a first display unit groups, b second display unit groups, and c third display unit groups; p = a + b + c, where p, a, b, and c are all positive integers; The first display unit group includes a first sub-display group with the first power signal line provided, the second display unit group includes a second sub-display group with the second power signal line provided, and the third display unit group includes a third sub-display group with the third power signal line provided.

13. The display panel according to claim 10, characterized in that, a:b:c = 2:1:

1.

14. The display panel according to claim 1, characterized in that, The pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged along the row direction; the pixel circuit of the first sub-pixel is a first pixel circuit, the pixel circuit of the second sub-pixel is a second pixel circuit, the pixel circuit of the third sub-pixel is a third pixel circuit, and the pixel circuit of the fourth sub-pixel is a fourth pixel circuit. The emission wavelength of the first sub-pixel is greater than that of the second sub-pixel, the emission wavelength of the second sub-pixel is greater than that of the third sub-pixel, and the display emission color of the fourth sub-pixel includes at least the combined emission colors of the first sub-pixel and the second sub-pixel; In the row direction, the distance between the power signal line and the fourth pixel circuit is at least d1; where d1>d0, and d0 is the size of the pixel circuit in the row direction.

15. The display panel according to claim 14, characterized in that, In the same pixel unit, the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are arranged sequentially along the row direction; the plurality of power signal lines include a second power signal line located in the gap between adjacent first pixel circuits and second pixel circuits, and / or a third power signal line located in the gap between adjacent second pixel circuits and third pixel circuits.

16. The display panel according to claim 14, characterized in that, In the same pixel unit, the first pixel circuit and the third pixel circuit are adjacent to each other, or in two adjacent pixel units, the first pixel circuit and the third pixel circuit are adjacent to each other. The plurality of power signal lines include a first power signal line located in the gap between adjacent first pixel circuits and third pixel circuits.

17. The display panel according to claim 14, characterized in that, m adjacent pixel units form a display unit group; the power signal line is electrically connected to the pixel circuit in the same display unit group; m is a positive integer; The p adjacent display unit groups include a first display unit groups, b second display unit groups, and c third display unit groups; p = a + b + c, where p, a, b, and c are all positive integers; The first display unit group includes adjacent first pixel circuits and third pixel circuits, and the power signal line electrically connected to the pixel circuits in the first display unit group is located in the gap between the adjacent first pixel circuits and third pixel circuits. The second display unit group includes adjacent first pixel circuits and second pixel circuits, and the power signal line electrically connected to the pixel circuits in the second display unit group is located in the gap between adjacent first pixel circuits and second pixel circuits; The third display unit group includes adjacent second pixel circuits and third pixel circuits, and the power signal line electrically connected to the pixel circuits in the third display unit group is located in the gap between adjacent second pixel circuits and third pixel circuits.

18. The display panel according to claim 17, characterized in that, a:b:c = 2:1:

1.

19. The display panel according to claim 1, characterized in that, Also includes: Multiple power connection lines extending along the row direction; The power signal line is electrically connected to the pixel circuit via the power connection line.

20. The display panel according to claim 19, characterized in that, The power connection line has a line width of W3 in the column direction, and the power signal line has a line width of W1 in the row direction; wherein, W1>W3.

21. The display panel according to claim 19, characterized in that, In the interconnected power signal lines and power connection lines, the distance between the power signal lines and the pixel circuits closest to the power signal lines in the row direction is a1, and the distance between the power connection lines and the pixel circuits closest to the power connection lines in the column direction is a2; wherein a2>a1.

22. The display panel according to claim 19, characterized in that, Also includes: Multiple first signal lines extending along the row direction and arranged along the column direction; at least a portion of the pixel circuits located in the same row are electrically connected to the same first gate signal line; At least one first signal line is provided between the power connection line and the pixel circuit.

23. The display panel according to claim 1, characterized in that, include: A display area and a non-display area surrounding the display area; the non-display area includes a fan-out area located on one side of the display area; the fan-out area is provided with multiple fan-out traces; The pixel unit, the power signal line, and the data signal line are all located in the display area; The multiple fan-out traces include multiple first fan-out traces corresponding to the multiple power signal lines, and multiple second fan-out traces corresponding to the multiple data signal lines. The first fan-out traces are electrically connected to the corresponding power signal lines; the second fan-out traces are electrically connected to the corresponding data signal lines. The display panel further includes at least one conductive layer; the first fan-out trace is located in the same conductive layer.

24. The display panel according to claim 23, characterized in that, The conductive layer includes a first conductive layer and a second conductive layer with an insulating gap; the two adjacent second fan-out traces are located in the first conductive layer and the second conductive layer, respectively.

25. The display panel according to claim 1, characterized in that, include: A display area and a non-display area surrounding the display area; the non-display area includes a fan-out area located on one side of the display area; the fan-out area is provided with multiple fan-out traces; The pixel unit, the power signal line, and the data signal line are all located in the display area; The multiple fan-out traces include multiple first fan-out traces corresponding to the multiple power signal lines, and multiple second fan-out traces corresponding to the multiple data signal lines. The first fan-out traces are electrically connected to the corresponding power signal lines; the second fan-out traces are electrically connected to the corresponding data signal lines. The display panel includes a first conductive layer and a second conductive layer that are insulated from each other; the two adjacent fan-out traces are located on the first conductive layer and the second conductive layer, respectively.

26. The display panel according to claim 1, characterized in that, The data signal line is located in the gap between the two pixel circuits that are electrically connected to it and arranged along the row direction.

27. The display panel according to claim 26, characterized in that, The pixel circuits of two adjacent sub-pixels that are electrically connected to the same data signal line are centrally symmetrical about the data signal line.

28. The display panel according to claim 26, characterized in that, The gap between two adjacent pixel circuits arranged along the row direction is the pixel gap. The power signal line and the data signal line are respectively located at different pixel gaps.

29. The display panel according to claim 1, characterized in that, In the row direction, the line width of the power signal line is W1, and the line width of the data signal line is W2; wherein, 2×W2≤W1≤6×W2.

30. The display panel according to claim 1, characterized in that, Also includes: Multiple first gate signal lines; The pixel circuit includes at least a driving module and a data writing module; the data writing module is electrically connected to the data signal line, the first gate signal line, and the driving module, respectively. The data writing modules of the two pixel circuits located in the same row and electrically connected to the same data signal line are respectively electrically connected to different first gate signal lines.

31. A display device, characterized in that, include: The display panel according to any one of claims 1-30.

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