Display device and driving method thereof

Abstract

A display device includes: a display panel including a first pixel connected to a first data line and a second pixel connected to a second data line; a source driver, comprising a data output channel configured to output a first data voltage to be supplied to a first data line in a first period of time during a refresh frame and a second data voltage to be supplied to a second data line in a second period of time after the first period of time during the refresh frame, and a data output channel configured to output a data voltage to be supplied to the first data line in the first period of time, an auxiliary output channel that supplies a first pre-charge voltage to the second data line and outputs a second pre-charge voltage to be supplied to the first data line in a second period of time; and a multiplexer switching circuit configured to connect the data output channel to the first data line and the auxiliary output channel to the second data line in a first time period and to connect the data output channel to the second data line and the auxiliary output channel to the first data line in a second time period.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0109169, filed on August 14, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to a display device and a driving method thereof. Background Technology

[0004] The display device includes multiple pixels arranged in a matrix, and achieves a target brightness corresponding to a data voltage by using the pixels in the display panel. Each pixel includes a light-emitting element, and the target brightness is achieved by utilizing the amount of light emitted by the light-emitting element.

[0005] The data voltage output from the source driver is supplied to the pixel via the data line. The level of the data voltage supplied via the data line can change continuously over time. The image quality achieved at the pixel level depends on the data voltage's data transition. The data transition can be defined as the rate at which the potential of the data line follows the target level of the data voltage.

[0006] To improve data conversion, one could consider extending the output enable range of the data voltage or increasing the length of the horizontal time used to drive a row of pixels, but such methods are detrimental to power consumption. Summary of the Invention

[0007] Therefore, the purpose of this disclosure is to provide a display device and a driving method thereof that substantially eliminates one or more limitations and disadvantages associated with the related art.

[0008] For example, this disclosure provides a display device and a driving method thereof, which can improve data conversion with low power consumption to enhance image quality.

[0009] Additional advantages and features of this disclosure will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the following, or may be learned from practice of this disclosure. The purposes and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0010] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel including: a first pixel in a first pixel row and connected to a first data line; and a second pixel in a second pixel row adjacent to the first pixel and connected to a second data line; a source driver including: a data output channel configured to output a first data voltage to be supplied to the first data line during a first time period during a refresh frame, and to output a second data voltage to be supplied to the second data line during a second time period after the first time period during the refresh frame; an auxiliary output channel configured to output a first pre-charge voltage to be supplied to the second data line during the first time period, and to output a second pre-charge voltage to be supplied to the first data line during the second time period; and a multiplexer switching circuit configured to: connect the data output channel to the first data line and the auxiliary output channel to the second data line during the first time period; and connect the data output channel to the second data line and the auxiliary output channel to the first data line during the second time period.

[0011] In another aspect of this disclosure, a method for driving a display device is disclosed, wherein the display device includes a display panel having a first pixel in a first pixel row and connected to a first data line, and a second pixel in a second pixel row adjacent to the first pixel and connected to a second data line. The method includes: during a first time period during a refresh frame, providing a first data voltage to the first data line through a data output channel of a source driver, and providing a first pre-charge voltage to the second data line through an auxiliary output channel of the source driver; during a second time period after the first time period during the refresh frame, providing a second data voltage to the second data line through the data output channel, and providing a second pre-charge voltage to the first data line through the auxiliary output channel; during the first time period during the refresh frame, connecting the data output channel to the first data line and connecting the auxiliary output channel to the second data line; and during the second time period during the refresh frame, connecting the data output channel to the second data line and connecting the auxiliary output channel to the first data line.

[0012] In another aspect of this disclosure, a display device includes: a source driver having a first data output channel and a first auxiliary output channel, the source driver being configured to: output a first data voltage via the first data output channel and output a first pre-charge voltage via the first auxiliary output channel during a first time period during a refresh frame; and output a second data voltage via the first data output channel and output a second pre-charge voltage via the first auxiliary output channel during a second time period after the first time period during the refresh frame; and a display panel including a plurality of pixels, the plurality of pixels including: a first pixel in a first column and in an odd-numbered pixel row, and connected to a first data line, the first data line being configured to receive the first data voltage during the first time period and receive the second pre-charge voltage during the second time period; and a second pixel in the first column and in an even-numbered pixel row, and connected to a second data line, the second data line being configured to receive the first pre-charge voltage during the first time period and receive the second data voltage during the second time period.

[0013] It should be understood that the foregoing general description and the following detailed description are provided as examples and are intended to offer further explanation of the claimed disclosure. Attached Figure Description

[0014] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0015] Figure 1 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0016] Figure 2 This is a diagram showing a portion of an example pixel array included in the active region;

[0017] Figure 3 This is a diagram illustrating an example of variable refresh rate (VRR) technology applied to a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 4 This is a schematic diagram illustrating an example configuration in which the source driver is connected to the pixel array via a multiplexer switching circuit;

[0019] Figures 5 to 8 This is a diagram illustrating the drive timing and connection configuration of a multiplexer switch circuit for improving data conversion of data lines with respect to various image patterns according to a first example embodiment;

[0020] Figure 9A It is shown in Figure 6 and Figure 8 A diagram showing the operational state of the multiplexer switching circuit as it is implemented in real time;

[0021] Figure 9B It is shown in Figure 6 and Figure 8 A diagram showing the operating states of the multiplexer switching circuit implemented in the second time.

[0022] Figure 10 This is a diagram illustrating an example connection configuration of pixels applied to a display device according to an example embodiment of the present disclosure;

[0023] Figure 11 It is a diagram showing the driving waveforms of pixels in a refresh frame;

[0024] Figure 12 This is a diagram showing the driving waveform of pixels skipped in a frame;

[0025] Figure 13 This is a diagram illustrating some components of a multiplexer switching circuit and a source driver connected thereto, according to a first exemplary embodiment;

[0026] Figure 14 This is a diagram showing the data output and auxiliary output of the source driver during refresh frames and skip frames;

[0027] Figure 15A This is a diagram showing the operational state of the multiplexer switching circuit implemented at the first moment of the refresh frame;

[0028] Figure 15B This is a diagram showing the operating state of the multiplexer switching circuit implemented in the second time of the refresh frame;

[0029] Figure 15C This is a diagram showing the operating state of the multiplexer switching circuit implemented in the skip frame;

[0030] Figure 16 This is a diagram illustrating another example connection configuration of pixels applied to a display device according to an example embodiment of the present disclosure;

[0031] Figure 17 This diagram illustrates the supply of precharge voltage and on-bias stress (OBS) voltage to the data line via an auxiliary output channel at different timings of the refresh frame.

[0032] Figure 18 This diagram illustrates the situation where a line stabilization voltage and an OBS voltage are supplied to the data line through an auxiliary output channel at different timings of the skipped frame.

[0033] Figure 19This is a diagram illustrating the operating states of a multiplexer switching circuit used to selectively output line-stabilized voltage and OBS voltage during skipped frames; and

[0034] Figure 20 This is a diagram illustrating the connection configuration of a multiplexer switching circuit for improving data conversion of a data line according to a second example embodiment. Detailed Implementation

[0035] In the following description, the present disclosure will be more fully described with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that the present disclosure will be more thorough and complete, and will fully convey to those skilled in the art the various concepts of the present disclosure. Furthermore, the scope of protection of the present disclosure may be defined by the claims and their equivalents.

[0036] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings for describing various exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, unless otherwise stated, the same elements are represented by the same reference numerals.

[0037] As used herein, the terms “including,” “having,” “comprising,” etc., imply that additional parts may be added unless a more restrictive term such as “only” is used. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0038] Even without explicit statements, elements in the various embodiments of this disclosure will be interpreted as including error margins.

[0039] When describing positional relationships, for example, where the positional relationship between two parts is described as “on top of,” “above,” “below,” and “next to,” one or more other parts may be placed between the two parts, unless more restrictive terms such as “exactly” or “directly” are used.

[0040] It should be understood that although terms such as "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to refer to an element that is separate from the others. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0041] In the following description, detailed descriptions of known functions or configurations may be omitted where such descriptions might unnecessarily obscure a feature or aspect of this disclosure. Hereinafter, exemplary embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 This is a diagram illustrating a display device according to an example embodiment of the present disclosure. Figure 2 This is a diagram showing a portion of an example pixel array included in the active region.

[0043] like Figure 1 and Figure 2 As shown, the display device according to the example embodiments of this disclosure may be an organic light-emitting display device, but this disclosure is not limited thereto. The display panel 100 may include an active area AA configured to reproduce an input image. The active area AA may include a pixel array displaying pixel data (hereinafter referred to as "image data") DATA of the input image. The pixel array may include multiple data lines DL, multiple gate lines GL intersecting the data lines DL, and multiple pixels SP.

[0044] Pixels SP can be arranged in a matrix type on the active region AA, defined by the intersection of data lines DL and gate lines GL. Pixels SP can be arranged in various types on the region AA, such as stripe type and diamond type, based on the positions of pixels SP that emit light of the same color.

[0045] A pixel array may include multiple pixel columns and multiple pixel rows L1 to Ln intersecting the pixel columns. Each pixel column may include pixels SP arranged in the Y-axis direction. A pixel row may include pixels SP arranged in the X-axis direction. A vertical time period may be a frame time period for writing a frame of image data DATA in all pixels of the active region. A horizontal time period may be the time obtained by dividing a frame time period by the number of pixel rows L1 to Ln. A horizontal time period may be the time for writing a pixel row of image data DATA in a pixel SP of a pixel row (shared gate line GL).

[0046] Pixel SP may include the first pixel that generates red (R) light. Figure 2 The second pixel (R) that generates green (G) light Figure 2 In the G) and the third pixel that generates blue (B) light ( Figure 2 In the first pixel (B), various color combinations are used. Pixel SP may also include a fourth pixel that generates white (W) light. The first to third pixels or the first to fourth pixels can be configured as a single unit pixel.

[0047] R, G, and B pixels can be configured with odd-numbered pixel rows (L-Odd) and even-numbered pixel rows (L-Even). In the odd-numbered pixel row (L-Odd), R, G, and B pixels can be connected to odd-numbered data lines, such as DL1, DL3, DL5, DL7, DL9, and DL11, while in the even-numbered pixel row (L-Even), R, G, and B pixels can be connected to even-numbered data lines, such as DL2, DL4, DL6, DL8, DL10, and DL12. Two pixels of the same color configured in the same pixel column and set adjacent to each other can be connected to different data lines. This connection structure is easier to implement with low power consumption compared to the conventional connection structure where two pixels of the same color are connected to the same data line.

[0048] Each pixel SP can be implemented using pixel circuitry connected to data line DL and gate line GL. Pixel circuitry may include a light-emitting element, a driving transistor, one or more switching transistors, and a capacitor. The light-emitting element can be implemented as an organic light-emitting diode (OLED). The driving current applied to the light-emitting element can be controlled based on the gate-source voltage of the driving transistor. The gate-source voltage of the driving transistor can be determined by the data voltage corresponding to the image data DATA.

[0049] The pixel circuitry can sample the threshold voltage of the driving transistor midway through a pixel programming operation performed within a frame period, and can allow the sampled threshold voltage to be reflected in the gate-source voltage (hereinafter referred to as Vgs) of the driving transistor. This can prevent or suppress distortion of the drive current due to changes in the threshold voltage of the driving transistor.

[0050] Pixel circuits can be implemented as hybrid types. In hybrid pixel circuits, the semiconductor layers of some transistors may include low-temperature polysilicon (hereinafter referred to as LTPS), and the semiconductor layers of other transistors may be configured with oxide.

[0051] Pixel circuits can be driven using variable refresh rate (VRR) technology. VRR technology can change the refresh rate of image data (DATA) based on image properties. According to VRR technology, as the changes in the image decrease, the data refresh cycle can be increased, thus reducing power consumption.

[0052] To implement VRR technology, one or more skip frames can be provided between adjacent refresh frames. Data refresh operations can be performed within refresh frames without skipping frames. The refresh rate (i.e., frame rate) can be determined based on the number of skip frames provided between adjacent refresh frames.

[0053] Data refresh operations, including pixel initialization and data programming, can be performed within the refresh frame. When performing a data refresh operation, the light-emitting element can be turned off. At this time, an anode reset operation can be performed, in which the light-emitting element is initialized to the anode reset voltage.

[0054] The data refresh operation for pixel SP can be omitted (or skipped) in the skip frame, and the data refresh condition Vgs (drive current) set in the refresh frame can be maintained in the skip frame. An anode reset operation to turn off the light-emitting element can be performed in the skip frame. Therefore, the duration of the light-emitting element's conduction in the skip frame can be substantially equal to the duration of its conduction in the refresh frame.

[0055] In each of the refresh frame and skip frame, a bias stress (OBS) operation can be performed on the drive transistor when an anode reset operation is performed.

[0056] In the hybrid pixel circuit according to this example embodiment, OBS operation can be used to prevent or suppress image quality defects caused by the hysteresis characteristics of the driving transistor. When the grayscale value of image data DATA changes from black to white, the grayscale response time can increase in the first frame reproducing the white image due to the time required to change the hysteresis characteristics of the driving transistor. Therefore, a dark first frame (DFF) phenomenon can occur. At this time, the DFF characteristic can be mitigated when the Vgs of the driving transistor is increased by applying an OBS voltage to one electrode of the driving transistor. This can be referred to as OBS operation.

[0057] A touch sensor may be further disposed on the display panel 100. The touch sensor may be arranged as an on-cell or add-on type on the active area AA of the display panel 100, or it may be implemented as an in-cell type touch sensor embedded in the pixel array. Even without a touch sensor, touch input can be sensed by the pixels SP, and in this case, the touch sensor can be omitted.

[0058] The display panel driver may include a source driver 110 and gate drivers 120L and 120R. The display panel driver may write image data DATA into the pixels SP of the display panel 100 under the control of a timing controller 130.

[0059] Source driver 110 can generate a data voltage by converting image data DATA received from timing controller 130 into a gamma-compensated voltage using a digital-to-analog converter (DAC). Source driver 110 can supply the data voltage to data line DL. The data voltage can be supplied to data line DL and can also be applied to the gate electrode of the drive transistor via the switching transistor of the sub-pixel SP. Source driver 110 can be implemented using multiple source driver integrated circuits (ICs).

[0060] To reduce RC delay bias occurring in the display panel 100, which includes a large active area, gate drivers 120L and 120R can be implemented as dual-bank type. That is, gate drivers 120L and 120R can be configured as in-panel (GIP) gate drivers in the left bezel region BZ and right bezel region BZ, respectively, and can supply gate signals with the same phase to the same gate line GL on the corresponding sides of the display panel 100. The left bezel region BZ and right bezel region BZ are located outside the active area AA of the display panel 100. Gate drivers 120L and 120R can include a first-side gate driver 120L located in the left bezel region BZ of the display panel 100 and a second-side gate driver 120R located in the right bezel region BZ of the display panel 100.

[0061] Under the control of the timing controller 130, the gate drivers 120L and 120R on both sides can sequentially supply gate signals to the gate line GL. The gate signals can select pixel rows L1 to Ln charged with data voltage and can simultaneously activate pixels SP set in the corresponding pixel rows. The gate drivers 120L and 120R can output gate signals for pixel driving and can shift the gate signals on a pixel row basis. The gate signals may include a transmit control signal that swings between on and off levels and multiple scan signals. The gate drivers 120L and 120R on both sides may include multiple scan drivers (not shown) that generate multiple scan signals and an EM driver (not shown) that generates transmit control signals.

[0062] The timing controller 130 can receive video data DATA and one or more timing signals synchronized with the video data DATA from a host system (not shown). The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync can define a vertical time period. The horizontal synchronization signal Hsync can define a horizontal time period. The data enable signal DE can define the time for transmitting video data DATA within a vertical or horizontal time period. The vertical and horizontal time periods can be determined by counting the data enable signal DE. Therefore, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0063] The timing controller 130 can generate a source timing control signal DDC for controlling the operating timing of the source driver 110 and a gate timing control signal GDC for controlling the operating timing of the gate drivers 120L and 120R based on the timing signals Vsync, Hsync and DE received from the host system.

[0064] The host system can be one of a television (TV), set-top box, navigation system, personal computer (PC), home theater, automotive display system, mobile device, or wearable device. In mobile devices and wearable devices, the source driver 110, timing controller 130, and level shifters 140L and 140R can be integrated into a single driver IC.

[0065] Level shifters 140L and 140R can convert the voltage of the gate timing control signal GDC output from the timing controller 130 into on-level voltage and off-level voltage, and can supply the on-level voltage and off-level voltage to the gate drivers 120L and 120R.

[0066] Level shifters 140L and 140R may include a first level shifter 140L connected to a first-side gate driver 120L via a first signal line, and a second level shifter 140R connected to a second-side gate driver 120R via a second signal line.

[0067] Figure 3 This is a diagram illustrating an example of VRR technology applied to a display device according to an exemplary embodiment of the present disclosure.

[0068] like Figure 3 As shown, the data refresh cycle implemented in the pixels of the display panel can vary based on the attributes of the input image. When the image changes significantly, the data refresh cycle can be decreased, and when the image changes slightly, the data refresh cycle can be increased. Increasing the data refresh cycle allows for low-speed driving, while decreasing it allows for high-speed driving.

[0069] The data refresh cycle can be 1 / frame frequency. For example, the data refresh cycle can be 1 / 120 at 120Hz, 1 / 60 at 60Hz, 1 / 24 at 24Hz, and 1 second at 1Hz.

[0070] The number of skipped frames provided between two adjacent refresh frames can vary based on the frame rate. For example, the number of skipped frames can be 0 at 120Hz, 1 at 60Hz, 4 at 24Hz, and 119 at 1Hz.

[0071] Figure 4 This is a schematic diagram illustrating an example configuration in which the source driver is connected to the pixel array via a multiplexer switching circuit.

[0072] like Figure 4 As shown, in a display device according to an exemplary embodiment of the present disclosure, a multiplexer switching circuit MX-ARY can be provided, which can electrically connect a low-power pixel array to the source driver 110 to improve data conversion.

[0073] In a pixel array, two pixels of the same color that are configured in the same pixel column and are adjacent to each other can be connected to different data lines. For example, the first data line DL1 and the second data line DL2 can be connected to R pixels R1 and R2 that are adjacent to each other in the same pixel column, respectively; the third data line DL3 and the fourth data line DL4 can be connected to G pixels G1 and G2 that are adjacent to each other in the same pixel column, respectively; and the fifth data line DL5 and the sixth data line DL6 can be connected to B pixels B1 and B2 that are adjacent to each other in the same pixel column, respectively.

[0074] In addition to the data output channels DCH1, DCH2 and DCH3, the source driver 110 may also include an auxiliary output channel ACH for improving data conversion.

[0075] Data output channels DCH1, DCH2, and DCH3 can output a first data voltage to be supplied to the odd-numbered data line DL-Odd during the first time interval of the refresh frame, and can output a second data voltage to be supplied to the even-numbered data line DL-Even during a second time interval after the first time interval of the refresh frame. The first time interval of the refresh frame can be the data programming time for pixels R1, G1, and B1 of the first pixel row, and the second time interval of the refresh frame can be the data programming time for pixels R2, G2, and B2 of the second pixel row.

[0076] The auxiliary output channel ACH can output a first pre-charge voltage to be supplied to the even-numbered data line DL-Even during the first time period of the refresh frame, and a second pre-charge voltage to be supplied to the odd-numbered data line DL-Odd during the second time period of the refresh frame. The first pre-charge voltage can be used to increase the data conversion of the even-numbered data line DL-Even in the refresh frame, and can vary over time within a predetermined pre-charge voltage range. Similarly, the second pre-charge voltage can be used to increase the data conversion of the odd-numbered data line DL-Odd in the current refresh frame, and can also vary over time within a predetermined pre-charge voltage range. Here, the predetermined pre-charge voltage range can be greater than the minimum data voltage output from the source driver 110 and less than the maximum data voltage output from it. In other words, the lower end of the predetermined pre-charge voltage range can be greater than the minimum data voltage output from the source driver 110, and the higher end of the predetermined pre-charge voltage range can be less than the maximum data voltage output from the source driver 110.

[0077] Based on the multiplexer control signals MX1 and MX2, during the first time of the refresh frame, the multiplexer switching circuit MX-ARY can connect the data output channels DCH1, DCH2 and DCH3 to the odd data line DL-Odd, and can connect the auxiliary output channel ACH to the even data line DL-Even.

[0078] Based on the multiplexer control signals MX1 and MX2, during the second time interval of the refresh frame, the multiplexer switching circuit MX-ARY can connect the data output channels DCH1, DCH2 and DCH3 to the even-numbered data line DL-Even, and can connect the auxiliary output channel ACH to the odd-numbered data line DL-Odd.

[0079] Figures 5 to 8 This is a diagram illustrating the drive timing and connection configuration of a multiplexer switch circuit for improving data conversion of data lines with respect to various image patterns, according to a first example embodiment.

[0080] Figure 9A It is shown in Figure 6 and Figure 8 The diagram shows the operating state of the multiplexer switching circuit implemented by X1 in the first time step. Figure 9B It is shown in Figure 6 and Figure 8 The diagram shows the operating state of the multiplexer switching circuit implemented at the second time point X2.

[0081] like Figure 5 and Figure 7As shown, the multiplexer switch circuit MX-ARY according to the first example embodiment may include a first set of switches driving the first data line DL1 and the second data line DL2, a second set of switches driving the third data line DL3 and the fourth data line DL4, and a third set of switches driving the fifth data line DL5 and the sixth data line DL6.

[0082] The first set of switches may include first and second multiplexer switches M11 and M12, and first and second auxiliary switches A11 and A12.

[0083] The first multiplexer switch M11 can be connected between the first data output channel DCH1 and the first data line DL1, and can be turned on or off based on the first multiplexer control signal MX1. The first auxiliary switch A11 can be connected between the auxiliary output channel ACH and the second data line DL2, and can be turned on or off based on the first multiplexer control signal MX1.

[0084] The second multiplexer switch M12 can be connected between the first data output channel DCH1 and the second data line DL2, and can be turned on or off based on the second multiplexer control signal MX2. The second auxiliary switch A12 can be connected between the auxiliary output channel ACH and the first data line DL1, and can be turned on or off based on the second multiplexer control signal MX2.

[0085] In addition, the second set of switches may include third and fourth multiplexer switches M21 and M22, as well as third and fourth auxiliary switches A21 and A22.

[0086] The third multiplexer switch M21 can be connected between the second data output channel DCH2 and the third data line DL3, and can be turned on or off based on the first multiplexer control signal MX1. The third auxiliary switch A21 can be connected between the auxiliary output channel ACH and the fourth data line DL4, and can be turned on or off based on the first multiplexer control signal MX1.

[0087] The fourth multiplexer switch M22 can be connected between the second data output channel DCH2 and the fourth data line DL4, and can be turned on or off based on the second multiplexer control signal MX2. The fourth auxiliary switch A22 can be connected between the auxiliary output channel ACH and the third data line DL3, and can be turned on or off based on the second multiplexer control signal MX2.

[0088] In addition, the third set of switches may include the fifth and sixth multiplexer switches M31 and M32, as well as the fifth and sixth auxiliary switches A31 and A32.

[0089] The fifth multiplexer switch M31 can be connected between the third data output channel DCH3 and the fifth data line DL5, and can be turned on or off based on the first multiplexer control signal MX1. The fifth auxiliary switch A31 can be connected between the auxiliary output channel ACH and the sixth data line DL6, and can be turned on or off based on the first multiplexer control signal MX1.

[0090] The sixth multiplexer switch M32 can be connected between the third data output channel DCH3 and the sixth data line DL6, and can be turned on or off based on the second multiplexer control signal MX2. The sixth auxiliary switch A32 can be connected between the auxiliary output channel ACH and the fifth data line DL5, and can be turned on or off based on the second multiplexer control signal MX2.

[0091] The R1, G1, and B1 pixels connected to the odd-numbered data lines DL1, DL3, and DL5 can be set in the odd-numbered pixel row L-Odd, and the R2, G2, and B2 pixels connected to the even-numbered data lines DL2, DL4, and DL6 can be set in the even-numbered pixel row L-Even.

[0092] First, the following will refer to Figure 5 , Figure 6 , Figure 9A and Figure 9B An implementation example of a first image pattern (an image pattern in which black grayscale level and white grayscale level alternate in one pixel row) connected to a multiplexer switching circuit according to a first example embodiment is described.

[0093] like Figure 5 and Figure 6 As shown, based on the operation of the multiplexer switching circuit MX-ARY according to the first example embodiment, the data voltage of the black grayscale level can be charged in the odd-numbered pixel row L-Odd during the first time X1, and the data voltage of the white grayscale level can be charged in the even-numbered pixel row L-Even during the second time X2.

[0094] Therefore, within the first time interval X1, the first data output channel DCH1 can output the first R data voltage DR1 for black grayscale, the second data output channel DCH2 can output the first G data voltage DG1 for black grayscale, and the third data output channel DCH3 can output the first B data voltage DB1 for black grayscale. Within the first time interval X1, the auxiliary output channel ACH can output the first pre-charge voltage PC1.

[0095] like Figure 5 , 6As shown in 9A, within the first time X1, the first multiplexer control signal MX1 can be input at the on level, and the second multiplexer control signal MX2 can be input at the off level.

[0096] Within the first time interval X1, the first multiplexer switch M11, the third multiplexer switch M21, and the fifth multiplexer switch M31, as well as the first auxiliary switch A11, the third auxiliary switch A21, and the fifth auxiliary switch A31 of the multiplexer switching circuit MX-ARY can be turned on based on the first multiplexer control signal MX1 at the on level. On the other hand, the second multiplexer switch M12, the fourth multiplexer switch M22, and the sixth multiplexer switch M32, as well as the second auxiliary switch A12, the fourth auxiliary switch A22, and the sixth auxiliary switch A32 of the multiplexer switching circuit MX-ARY can be turned off based on the second multiplexer control signal MX2 at the off level.

[0097] Within the first time interval X1, based on the conduction operation of each of the first, third, and fifth multiplexer switches M11, M21, and M31, the first data output channel DCH1 can be connected to the first data line DL1, the second data output channel DCH2 can be connected to the third data line DL3, and the third data output channel DCH3 can be connected to the fifth data line DL5. As a result, the first R data voltage DR1 of the black grayscale level BLv can be supplied to the first data line DL1, the first G data voltage DG1 of the black grayscale level BLv can be supplied to the third data line DL3, and the first B data voltage DB1 of the black grayscale level BLv can be supplied to the fifth data line DL5. The first data line DL1, the third data line DL3, and the fifth data line DL5 can be... Figure 6 The odd-numbered data line DL-Odd in the middle.

[0098] Furthermore, within the first time interval X1, based on the conduction operation of each of the first auxiliary switch A11, the third auxiliary switch A21, and the fifth auxiliary switch A31, the auxiliary output channel ACH can be connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6. As a result, the first pre-charge voltage PC1 of the pre-charge level PLV can be supplied to the second data line DL2, the fourth data line DL4, and the sixth data line DL6, which are even-numbered data lines DL-Even.

[0099] Furthermore, during the second time period X2, the first data output channel DCH1 can output the second R data voltage DR2 for white grayscale, the second data output channel DCH2 can output the second G data voltage DG2 for white grayscale, and the third data output channel DCH3 can output the second B data voltage DB2 for white grayscale. During the second time period X2, the auxiliary output channel ACH can output the second pre-charge voltage PC2.

[0100] like Figure 5 , Figure 6 and Figure 9B As shown, during the second time X2, the first multiplexer control signal MX1 can be input at the off level, and the second multiplexer control signal MX2 can be input at the on level.

[0101] During the second time period X2, the first multiplexer switch M11, the third multiplexer switch M21, and the fifth multiplexer switch M31, as well as the first auxiliary switch A11, the third auxiliary switch A21, and the fifth auxiliary switch A31 of the multiplexer switching circuit MX-ARY can be turned off based on the first multiplexer control signal MX1 at the off level. On the other hand, the second multiplexer switch M12, the fourth multiplexer switch M22, and the sixth multiplexer switch M32, as well as the second auxiliary switch A12, the fourth auxiliary switch A22, and the sixth auxiliary switch A32 of the multiplexer switching circuit MX-ARY can be turned on based on the second multiplexer control signal MX2 at the on level.

[0102] During the second time period X2, based on the conduction operation of each of the second multiplexer switch M12, the fourth multiplexer switch M22, and the sixth multiplexer switch M32, the first data output channel DCH1 can be connected to the second data line DL2, the second data output channel DCH2 can be connected to the fourth data line DL4, and the third data output channel DCH3 can be connected to the sixth data line DL6. Therefore, the second R data voltage DR2 of the white grayscale level WLv can be supplied to the second data line DL2, the second G data voltage DG2 of the white grayscale level WLv can be supplied to the fourth data line DL4, and the second B data voltage DB2 of the white grayscale level WLv can be supplied to the sixth data line DL6. The second, fourth, and sixth data lines DL2, DL4, and DL6 can be... Figure 6 The even-numbered data lines in the DL-Even.

[0103] Furthermore, during the second time period X2, based on the conduction operation of each of the second auxiliary switch A12, the fourth auxiliary switch A22, and the sixth auxiliary switch A32, the auxiliary output channel ACH can be connected to the first data line DL1, the third data line DL3, and the fifth data line DL5. As a result, the second pre-charge voltage PC2 of the pre-charge level PLv can be supplied to the first data line DL1, the third data line DL3, and the fifth data line DL5, which are odd-numbered data lines DL-Odd.

[0104] Next, the following will refer to Figure 7 , Figure 8 , Figure 9A and Figure 9BAn implementation example of a second image pattern (an image pattern in which black grayscale levels and white grayscale levels alternate in units of one pixel) connected to a multiplexer switching circuit according to a first example embodiment is described.

[0105] like Figure 7 and Figure 8 As shown, based on the operation of the multiplexer switching circuit MX-ARY according to the first example embodiment, black grayscale data voltage and white grayscale data voltage can be alternately charged in odd-numbered pixel rows L-Odd in a first time X1, and white grayscale data voltage and black grayscale data voltage can be alternately charged in even-numbered pixel rows L-Even in a second time X2.

[0106] Therefore, within the first time interval X1, the first data output channel DCH1 can output the first R data voltage DR1 for black grayscale, the second data output channel DCH2 can output the first G data voltage DG1 for white grayscale, and the third data output channel DCH3 can output the first B data voltage DB1 for black grayscale. Within the first time interval X1, the auxiliary output channel ACH can output the first pre-charge voltage PC1.

[0107] As in Figure 7 , Figure 8 and Figure 9A As shown, within the first time X1, the first multiplexer control signal MX1 can be input at the on level, and the second multiplexer control signal MX2 can be input at the off level.

[0108] Within the first time interval X1, the first multiplexer switch M11, the third multiplexer switch M21, and the fifth multiplexer switch M31 of the multiplexer switching circuit MX-ARY, as well as the first auxiliary switch A11, the third auxiliary switch A21, and the fifth auxiliary switch A31, can be turned on by the first multiplexer control signal MX1 at the on level. On the other hand, the second multiplexer switch M12, the fourth multiplexer switch M22, and the sixth multiplexer switch M32 of the multiplexer switching circuit MX-ARY, as well as the second auxiliary switch A12, the fourth auxiliary switch A22, and the sixth auxiliary switch A32, can be turned off by the second multiplexer control signal MX2 at the off level.

[0109] Within the first time interval X1, based on the conduction operation of each of the first, third, and fifth multiplexer switches M11, M21, and M31, the first data output channel DCH1 can be connected to the first data line DL1, the second data output channel DCH2 can be connected to the third data line DL3, and the third data output channel DCH3 can be connected to the fifth data line DL5. As a result, the first R data voltage DR1 of the black grayscale level BLv can be supplied to the first data line DL1, the first G data voltage DG1 of the white grayscale level WLv can be supplied to the third data line DL3, and the first B data voltage DB1 of the black grayscale level BLv can be supplied to the fifth data line DL5.

[0110] Furthermore, within the first time interval X1, based on the conduction operation of each of the first auxiliary switch A11, the third auxiliary switch A21, and the fifth auxiliary switch A31, the auxiliary output channel ACH can be connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6. As a result, the first precharge voltage PC1 of the precharge level PLv can be supplied to the second data line DL2, the fourth data line DL4, and the sixth data line DL6.

[0111] Furthermore, during the second time period X2, the first data output channel DCH1 can output the second R data voltage DR2 for white grayscale, the second data output channel DCH2 can output the second G data voltage DG2 for black grayscale, and the third data output channel DCH3 can output the second B data voltage DB2 for white grayscale. During the second time period X2, the auxiliary output channel ACH can output the second pre-charge voltage PC2.

[0112] As in Figure 7 , Figure 8 and Figure 9B As shown, during the second time X2, the first multiplexer control signal MX1 can be input at the off level, and the second multiplexer control signal MX2 can be input at the on level.

[0113] During the second time period X2, the first multiplexer switch M11, the third multiplexer switch M21, and the fifth multiplexer switch M31 of the multiplexer switching circuit MX-ARY, as well as the first auxiliary switch A11, the third auxiliary switch A21, and the fifth auxiliary switch A31, can be turned off by the first multiplexer control signal MX1 at the off level. On the other hand, the second multiplexer switch M12, the fourth multiplexer switch M22, and the sixth multiplexer switch M32 of the multiplexer switching circuit MX-ARY, as well as the second auxiliary switch A12, the fourth auxiliary switch A22, and the sixth auxiliary switch A32, can be turned on by the second multiplexer control signal MX2 at the on level.

[0114] During the second time period X2, based on the conduction operation of each of the second multiplexer switch M12, the fourth multiplexer switch M22, and the sixth multiplexer switch M32, the first data output channel DCH1 can be connected to the second data line DL2, the second data output channel DCH2 can be connected to the fourth data line DL4, and the third data output channel DCH3 can be connected to the sixth data line DL6. As a result, the second R data voltage DR2 of the white grayscale level WLv can be supplied to the second data line DL2, the second G data voltage DG2 of the black grayscale level BLv can be supplied to the fourth data line DL4, and the second B data voltage DB2 of the white grayscale level WLv can be supplied to the sixth data line DL6.

[0115] Furthermore, during the second time period X2, based on the conduction operation of each of the second auxiliary switch A12, the fourth auxiliary switch A22, and the sixth auxiliary switch A32, the auxiliary output channel ACH can be connected to the first data line DL1, the third data line DL3, and the fifth data line DL5. As a result, the second pre-charge voltage PC2 of the pre-charge level PLv can be supplied to the first data line DL1, the third data line DL3, and the fifth data line DL5, which are odd-numbered data lines DL-Odd.

[0116] Figure 10 This is a diagram illustrating an example connection configuration of pixels applied to a display device according to an example embodiment of the present disclosure.

[0117] like Figure 10 As shown, the pixel SP(n) set in the nth pixel row Ln can be implemented by a pixel circuit, which includes a light-emitting element OLED, a driving transistor DT, a plurality of switching transistors (e.g., the first to the seventh switching transistors) T1 to T7 and a capacitor Cst.

[0118] The driving transistor DT, switching transistors T1 to T7, and capacitor Cst can control the driving current flowing in the light-emitting element OLED to drive the OLED. Each of the driving transistor DT and switching transistors T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0119] Each of the second to sixth transistors T2 to T6 and the driving transistor DT can be implemented as a PMOS type including a semiconductor layer with LTPS, which has good response characteristics. On the other hand, the first transistor T1 and the seventh transistor T7 connected to the gate electrode of the driving transistor DT can be implemented as an NMOS type including an oxide semiconductor layer, which has good turn-off characteristics.

[0120] For PMOS transistors, the turn-on voltage can be a low gate voltage, and the turn-off voltage can be a high gate voltage. Conversely, for NMOS transistors, the turn-on voltage can be a high gate voltage, and the turn-off voltage can be a low gate voltage.

[0121] An OLED (Optical Display Panel) may include an anode electrode (or pixel electrode), a cathode electrode (or common electrode), and an organic compound layer disposed therebetween (configured with a common layer and an emission layer). The anode electrode of the OLED may be connected to a fourth node N4, and the cathode electrode may be connected to a second source voltage ELVSS.

[0122] The driving transistor DT may include a gate electrode connected to a first node N1, a source electrode connected to a second node N2, and a drain electrode connected to a third node N3. The driving transistor DT can generate a driving current based on the voltage of the first node N1 (or the data voltage stored in the capacitor Cst), and can apply the driving current to the light-emitting element OLED.

[0123] The first switching transistor T1 may include a gate electrode that receives a first scan signal SCAN1 via a first scan line SL1, a drain electrode connected to a third node N3, and a source electrode connected to a first node N1. The first switching transistor T1 can be turned on in response to the first scan signal SCAN1, and can short-circuit the gate and drain electrodes of the driving transistor DT to each other. Therefore, when the first switching transistor T1 is turned on, the driving transistor DT can operate like a diode.

[0124] The second switching transistor T2 may include a gate electrode for receiving the second scan signal SCAN2 via the second scan line SL2, a source electrode connected to a data line (or receiving data voltage Vdata), and a drain electrode connected to the second node N2. The second switching transistor T2 can be turned on in response to the second scan signal SCAN2 and can transmit the data voltage Vdata to the second node N2.

[0125] A capacitor Cst can be connected between the first node N1 and the input terminal of the first source voltage ELVDD. The capacitor Cst maintains the voltage of the first node N1.

[0126] The third switching transistor T3 and the fourth switching transistor T4 can be connected between the first source voltage ELVDD and the light-emitting diode OLED, and can form a current movement path through which the driving current generated by the driving transistor DT moves.

[0127] The third switching transistor T3 may include a source electrode connected to the input terminal of the first source voltage ELVDD, a drain electrode connected to the second node N2, and a gate electrode configured to receive the transmit control signal EM via the transmit control line EL. The fourth switching transistor T4 may include a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode configured to receive the transmit control signal EM via the transmit control line EL.

[0128] The third switching transistor T3 and the fourth switching transistor T4 can be turned on in response to the emission control signal EM. When the third switching transistor T3 and the fourth switching transistor T4 are turned on, the light-emitting element OLED can receive the driving current from the driving transistor DT and can emit light with a brightness corresponding to the driving current.

[0129] The fifth switching transistor T5 may include a source electrode connected to the input terminal of the OBS voltage Vobs, a drain electrode connected to the second node N2, and a gate electrode configured to receive the third scan signal SCAN3 via the third scan line SL3. The fifth switching transistor T5 can be turned on based on the third scan signal SCAN3 and can apply the OBS voltage Vobs to the second node N2.

[0130] The sixth switching transistor T6 may include a source electrode connected to the input terminal of the anode reset voltage Var, a drain electrode connected to the fourth node N4, and a gate electrode configured to receive the third scan signal SCAN3 via the third scan line SL3. The sixth switching transistor T6 may be turned on based on the third scan signal SCAN3 and may transmit the anode reset voltage Var to the fourth node N4.

[0131] The seventh switching transistor T7 may include a source electrode connected to the input terminal of the initialization voltage Vini, a drain electrode connected to the first node N1, and a gate electrode configured to receive the fourth scan signal SCAN4 via the fourth scan line SL4. The seventh switching transistor T7 may be turned on based on the fourth scan signal SCAN4 and may apply the initialization voltage Vini to the first node N1.

[0132] Figure 11 This is a diagram showing the driving waveform of pixel SP(n) in the refresh frame.

[0133] like Figure 11 As shown, the first OBS time period Tobs1, the initialization time period Ti, the programming time period Ts, the second OBS time period Tobs2, and the transmission time period Te can be arranged in chronological order in the refresh frame.

[0134] The second scan signal SCAN2 can define the programming period Ts of the supply data voltage Vdata. The programming period Ts can be the on-level (Lon) period of the second scan signal SCAN2.

[0135] The third scan signal SCAN3 can be defined as a first OBS period Tobs1 before the programming period Ts and a second OBS period Tobs2 after the programming period Ts and before the transmission period Te. The first OBS period Tobs1 and the second OBS period Tobs2 can each be the on-level (Lon) period of the third scan signal SCAN3.

[0136] The fourth scan signal SCAN4 can define an initialization period Ti positioned between the first OBS period Tobs1 and the programming period Ts. The initialization period Ti can be the on-level (Lon) period of the fourth scan signal SCAN4.

[0137] The transmit control signal EM can define the transmit period Te after the second OBS period Tobs2. The transmit period Te can be the on-level (Lon) period of the transmit control signal EM.

[0138] like Figure 10 and Figure 11 As shown, during the first OBS period Tobs1, in response to the third scan signal SCAN3 which is at the on level Lon, the fifth switching transistor T5 and the sixth switching transistor T6 can be turned on, and the other switching transistors T1 to T4 and T7 can be turned off.

[0139] During the first OBS period Tobs1, when the fifth switching transistor T5 is turned on, the OBS voltage Vobs can be applied to the second node N2. Based on the OBS voltage Vobs, the drain-source channel of the driving transistor DT can be maximally disconnected, and the driving transistor DT can maintain a stronger saturation state. Therefore, the hysteresis characteristics of the driving transistor DT can be recovered before data programming.

[0140] During the first OBS period Tobs1, when the sixth switching transistor T6 is turned on, the anode reset voltage Var can be applied to the fourth node N4. Based on the anode reset voltage Var, the residual charge in the parasitic capacitor formed between the anode and cathode electrodes of the OLED light-emitting element can be reset.

[0141] like Figure 10 and Figure 11As shown, during the initialization period Ti, in response to the first scan signal SCAN1 and the fourth scan signal SCAN4 at the on-level Lon, the first switching transistor T1 and the seventh switching transistor T7 can be turned on, and the other switching transistors T2 to T6 can be turned off. When the seventh switching transistor T7 is turned on, the first node N1 can be initialized to the initialization voltage Vini, and when the first switching transistor T1 is turned on, the driving transistor DT can operate like a diode.

[0142] like Figure 10 and Figure 11 As shown, during the programming period Ts, when the first switching transistor T1 and the second switching transistor T2 are turned on, the threshold voltage sampling operation and the data programming operation can be performed sequentially or simultaneously.

[0143] During the programming period Ts, the potential of the data line DL can be converted from the pre-charge voltage Vpc to the data voltage Vdata. Because the voltage difference between the pre-charge voltage Vpc and the data voltage Vdata is small, the data conversion of the data line DL can be improved.

[0144] During the programming period Ts, the data voltage Vdata charged in the data line DL can be applied to the second node N2 via the second switching transistor T2. The data voltage Vdata can be applied to the third node N3 via the driving transistor DT, and then to the first node N1 via the first switching transistor T1. The driving transistor DT can operate like a diode when the first switching transistor T1 is turned on, and the potential at the gate electrode of the driving transistor DT connected to the first node N1 can be programmed as "Vdata - |Vth|". The threshold voltage Vth can be sampled and reflected in the programming potential at the gate electrode of the driving transistor DT.

[0145] like Figure 10 and Figure 11 As shown, during the second OBS period Tobs2, in response to the third scan signal SCAN3 which is at the on level Lon, the fifth switching transistor T5 and the sixth switching transistor T6 can be turned on, and the other switching transistors T1 to T4 and T7 can be turned off.

[0146] During the second OBS period Tobs2, when the fifth switching transistor T5 is turned on, the OBS voltage Vobs can be applied to the second node N2. Based on the OBS voltage Vobs, the drain-source channel of the driving transistor DT can be maximally disconnected, and the driving transistor DT can maintain a stronger saturation state. Therefore, the hysteresis characteristics of the driving transistor DT can be recovered before light emission.

[0147] During the second OBS period Tobs2, when the sixth switching transistor T6 is turned on, the anode reset voltage Var can be applied to the fourth node N4. Therefore, the remaining charge in the parasitic capacitor of the OLED light-emitting element can be reset.

[0148] like Figure 10 and Figure 11 As shown, during the transmission period Te, in response to the transmission control signal EM which is at the on level Lon, the third switching transistor T3 and the fourth switching transistor T4 can be turned on, and the other switching transistors T1, T2, T5, T6 and T7 can be turned off.

[0149] During the emission period Te, the driving current supplied from the driving transistor DT to the light-emitting element OLED can be based on the Vgs of the driving transistor DT set during the programming period Ts. The driving current can be independent of the threshold voltage of the driving transistor DT and can be associated with the data voltage Vdata.

[0150] As described above, in a refresh frame, the data line DL can be pre-connected to the auxiliary output channel before being connected to the data output channel of the source driver, and therefore can be supplied with a pre-charge voltage Vpc through the auxiliary output channel. The data line DL can be pre-charged with the pre-charge voltage Vpc before the data voltage Vdata, and thus the data conversion of the data line DL can be improved.

[0151] Figure 12 A diagram illustrating the driving waveform of pixel SP(n) in a skipped frame.

[0152] like Figure 12 As shown, the third OBS period Tobs3, the fourth OBS period Tobs4, and the transmission period Te can be arranged sequentially in time within the skip frame.

[0153] The transmit control signal EM can define the transmit period Te of the skip frame. The transmit period Te can be the on-level (Lon) period of the transmit control signal EM. The on-level (Lon) period of the transmit control signal EM in the skip frame can be substantially the same as that in the refresh frame.

[0154] The third scan signal SCAN3 can be defined as the third OBS period Tob3 and the fourth OBS period Tobs4, which are sequentially arranged before the transmission period Te in the skip frame. In the skip frame, the third OBS period Tob3 and the fourth OBS period Tobs4 can each be the on-level (Lon) period of the third scan signal SCAN3.

[0155] Furthermore, the initialization and programming phases can be skipped and are not implemented in the skip frame. Additionally, the fourth OBS phase, Tobs4, can be skipped in the skip frame.

[0156] like Figure 10 and Figure 12 As shown, the hysteresis characteristics of the driving transistor DT can be improved again in the third OBS period (Tobs3) and the fourth OBS period (Tobs4). Therefore, the hysteresis characteristic deviation between skipped frames and refresh frames can be significantly reduced.

[0157] The first OBS period (Tobs1) and the second OBS period (Tobs2) of the refresh frame can be included in the Loff period of the transmit control signal EM. Furthermore, the third OBS period (Tobs3) and the fourth OBS period (Tobs4) of the skip frame can be included in the Loff period of the transmit control signal EM.

[0158] The length of the off-level (Loff) period of the transmit control signal EM can be equal in the refresh frame and the skip frame. Therefore, the length of the transmit maintenance time can be equal in the refresh frame and the skip frame.

[0159] Furthermore, during skip frames, the data line DL can be connected to the auxiliary output channel of the source driver, and a DC-level line-stabilized voltage Vpark can be supplied through the auxiliary output channel. The line-stabilized voltage Vpark can fix the potential of the data line DL during skip frames, and thus prevent or suppress the problem of distortion caused by voltage changes in the pixel due to potential variations in the data line DL.

[0160] Figure 13 This is a diagram illustrating some components of a multiplexer switching circuit and a source driver connected thereto, according to a first example embodiment. Figure 14 This is a diagram showing the data output and auxiliary output of the source driver during refresh frames and skip frames.

[0161] like Figure 13 and Figure 14 As shown, the source driver may include multiple digital-to-analog converters RDAC, GDAC, BDAC and PDAC, as well as first to fourth output control switches SW1 to SW4.

[0162] The RDAC can generate and output the first R data voltage DR1 and the second R data voltage DR2.

[0163] The first output control switch SW1 can be connected between the output of the RDAC and the first data output channel DCH1, and can be turned on or off based on the first source output control signal SOE1.

[0164] The GDAC can generate and output the first and second G data voltages, DG1 and DG2.

[0165] The second output control switch SW2 can be connected between the output of GDAC and the second data output channel DCH2, and can be turned on or off based on the first source output control signal SOE1.

[0166] BDAC can generate and output the first and second B data voltages DB1 and DB2.

[0167] The third output control switch SW3 can be connected between the output of BDAC and the third data output channel DCH3, and can be turned on or off based on the first source output control signal SOE1.

[0168] The PDAC can generate and output a first precharge voltage PC1, a second precharge voltage PC2, and a line-stabilized voltage Vpark.

[0169] The first pre-charge voltage PC1 and the second pre-charge voltage PC2 can each be a voltage that varies over time within a predetermined pre-charge voltage range. The image grayscale level realized in the same pixel and the target data voltage used to represent the image grayscale level can vary over time. Data slew can be defined as the rate at which the potential of the data line follows the target level of the data voltage. Therefore, as the target data voltage changes over time, the first pre-charge voltage PC1 and the second pre-charge voltage PC2 can follow the target data voltage to vary over time in order to increase data slew. Here, the pre-charge voltage range can be arranged between the upper and lower limits of the data output of the source driver. That is, the pre-charge voltage range can be greater than the minimum data voltage and less than the maximum data voltage.

[0170] The line-stabilized voltage Vpark can be fixed within the pre-charge voltage range. The level of the line-stabilized voltage Vpark can be fixed and not change over time. The line-stabilized voltage Vpark can have a DC level.

[0171] The fourth output control switch SW4 can be connected between the output of the PDAC and the auxiliary output channel ACH, and can be turned on or off based on the second source output control signal SOE2.

[0172] The first source output control signal SOE1 and the second source output control signal SOE2 can remain on during the refresh frame. The first multiplexer control signal MX1 and the second multiplexer control signal MX2 can be alternately turned on or off during the refresh frame.

[0173] Figure 15A This is a diagram showing the operating state of the multiplexer switching circuit MX-ARY implemented by X1 at the first moment of the refresh frame.

[0174] like Figure 14 and Figure 15A As shown, at the first time X1 of the refresh frame, the first multiplexer control signal MX1 can be turned on, and the second multiplexer control signal MX2 can be turned off.

[0175] At the first time X1 of the refresh frame, the first R data voltage DR1 output from the RDAC can be supplied to the first data line DL1 through the first output control switch SW1 and the first multiplexer switch M11.

[0176] At the first time X1 of the refresh frame, the first G data voltage DG1 output from the GDAC can be supplied to the third data line DL3 through the second output control switch SW2 and the third multiplexer switch M21.

[0177] At the first time X1 of the refresh frame, the first B data voltage DB1 output from the BDAC can be supplied to the fifth data line DL5 through the third output control switch SW3 and the fifth multiplexer switch M31.

[0178] At the first time X1 of the refresh frame, the first pre-charge voltage PC1 output from the PDAC can be supplied to the second data line DL2, the fourth data line DL4 and the sixth data line DL6 through the fourth output control switch SW4 and the first auxiliary switch A11, the third auxiliary switch A21 and the fifth auxiliary switch A31.

[0179] Figure 15B This is a diagram showing the operating state of the multiplexer switching circuit MX-ARY implemented in the second time X2 of the refresh frame.

[0180] like Figure 14 and Figure 15B As shown, at the second time X2 of the refresh frame, the first multiplexer control signal MX1 can be turned off, and the second multiplexer control signal MX2 can be turned on.

[0181] At the first time X2 of the refresh frame, the second R data voltage DR2 output from the RDAC can be supplied to the second data line DL2 through the first output control switch SW1 and the second multiplexer switch M12.

[0182] At the second time X2 of the refresh frame, the second G data voltage DG2 output from the GDAC can be supplied to the fourth data line DL4 through the second output control switch SW2 and the fourth multiplexer switch M22.

[0183] At the second time X2 of the refresh frame, the second B data voltage DB2 output from the BDAC can be supplied to the sixth data line DL6 through the third output control switch SW3 and the sixth multiplexer switch M32.

[0184] At the second time X2 of the refresh frame, the second pre-charge voltage PC2 output from the PDAC can be supplied to the first data line DL1, the third data line DL3 and the fifth data line DL5 through the fourth output control switch SW4 and the second auxiliary switch A12, the fourth auxiliary switch A22 and the sixth auxiliary switch A32.

[0185] Figure 15C This is a diagram showing the operating state of the multiplexer switch circuit MX-ARY implemented in a skip frame.

[0186] like Figure 14 and Figure 15C As shown, during the skip frame, the first source output control signal SOE1 can be turned off, and the second source output control signal SOE2 can be turned on. Based on the turn-off operation of the first source output control signal SOE1, data output channels DCH1, DCH2, and DCH3 can be placed in the floating state Hi-Z during the skip frame. Based on the turn-on operation of the second source output control signal SOE2, the fourth output control switch SW4 can remain on during the skip frame.

[0187] During a skip frame, the PDAC can output a line-stabilized voltage Vpark. The line-stabilized voltage Vpark output from the PDAC can be supplied to the first to sixth data lines DL1 to DL6 via the fourth output control switch SW4 and the first to sixth auxiliary switches A11 to A32, and can prevent or reduce potential changes in the data lines caused by the external environment.

[0188] The main components used to generate the pre-charge voltages PC1 and PC2 and the line-stabilized voltage Vpark, and their power supply paths, can be identical. Therefore, the circuit can be simplified, and power consumption can be reduced.

[0189] Figure 16 This is a diagram illustrating another example connection configuration of pixels applied to a display device according to an example embodiment of the present disclosure.

[0190] exist Figure 16 In the example pixel circuit, other components besides the connection configuration of the fifth switching transistor T5 can be connected to... Figure 10 The pixel circuits are the same.

[0191] like Figure 16 As shown, the source electrode of the fifth switching transistor T5 can be directly connected to the data line DL, and the OBS voltage Vobs can be received through the data line DL.

[0192] The data line DL can be connected to the data output channel and auxiliary output channel of the source driver via the aforementioned multiplexer switching circuit MX-ARY.

[0193] During a refresh frame, as described above, the source driver can output a data voltage Vdata through the data output channel and a pre-charge voltage Vpc through the auxiliary output channel. Furthermore, during a skip frame, the source driver can output the pre-charge voltage Vpc through the auxiliary output channel.

[0194] The source driver can float the data output channel during the OBS period of each of the refresh and skip frames, and can output the OBS voltage Vobs to be supplied to the data line DL through the auxiliary output channel.

[0195] The multiplexer switching circuit MX-ARY can connect the data line DL to the auxiliary output channel during OBS periods (single or multiple). As a result, during OBS periods (single or multiple), synchronized with the OLED light-emitting elements included in the pixels SP(n) being initialized to the anode reset voltage Var, the OBS voltage can be applied to the second node connected to the source electrode of the driving transistor DT.

[0196] As described above, used for driving Figure 16 The source driver of the pixel circuit can also output the OBS voltage Vobs through the auxiliary output channel during refresh frames and skip frames, and thus can additionally help simplify the circuit.

[0197] According to this example embodiment, as Figure 17 As shown, the precharge voltage Vpc and OBS voltage Vobs can be charged into a data line through an auxiliary output channel at different times during the refresh frame.

[0198] According to this example embodiment, as Figure 18 As shown, the line-stabilized voltage Vpark and the OBS voltage Vobs can be charged into a single data line at different times during the skip frame period via an auxiliary output channel.

[0199] Figure 19 This is a diagram showing the operating states of the multiplexer switching circuit MX-ARY used to selectively output the line-stabilized voltage Vpark and the OBS voltage Vobs in skip frames.

[0200] like Figure 19 As shown, during the skip frame, the first source output control signal SOE1 can be turned off, and the second source output control signal SOE2 can be turned on. Based on the turn-off operation of the first source output control signal SOE1, data output channels DCH1, DCH2, and DCH3 can be placed in a floating state Hi-Z during the skip frame (see example). Figure 14 Based on the conduction operation of the second source output control signal SOE2, the fourth output control switch SW4 can remain on during skip frames.

[0201] During skip frames, the PDAC can alternately output the line-stabilized voltage Vpark and the OBS voltage Vobs. The line-stabilized voltage Vpark output from the PDAC can be supplied to the first to sixth data lines DL1 to DL6 through the fourth output control switch SW4 and the first to sixth auxiliary switches A11 to A32, and can prevent or reduce potential changes in the data lines caused by the external environment.

[0202] The OBS voltage Vobs output from the PDAC can be supplied to the first data line DL1 to the sixth data line DL6 through the fourth output control switch SW4 and the first auxiliary switch A11 to the sixth auxiliary switch A32, and thus can help improve the hysteresis characteristics of the pixel.

[0203] Figure 20 This is a diagram illustrating the connection configuration of the multiplexer switch circuit MX-ARY for improving data conversion of data lines according to a second example embodiment.

[0204] According to the above reference Figure 5 and Figure 7 Compared to the multiplexer switch circuit MX-ARY of the first example embodiment described, Figure 20 The multiplexer switching circuit MX-ARY can have the following differences.

[0205] according to Figure 5 and Figure 7 The multiplexer switching circuit MX-ARY can independently provide data output channels DCH1, DCH2 and DCH3 for each of the R, G and B pixels, and can provide auxiliary output channel ACH together to the R, G and B pixels.

[0206] according to Figure 20 The multiplexer switching circuit MX-ARY can independently provide data output channels DCH1, DCH2 and DCH3 for each of the R, G and B pixels, and can also independently provide auxiliary output channels (e.g., first to third auxiliary output channels) ACH1, ACH2 and ACH3 for each of the R, G and B pixels.

[0207] The first auxiliary output channel ACH1 can be selectively connected only to data lines DL1 and DL2 connected to pixels R1 and R2. The output of the first auxiliary output channel ACH1 can be supplied to the second data line DL2 via the first auxiliary switch A11, and can be supplied to the first data line DL1 via the second auxiliary switch A12.

[0208] The second auxiliary output channel ACH2 can be selectively connected only to the data lines DL3 and DL4 connected to G pixels G1 and G2. The output of the second auxiliary output channel ACH2 can be supplied to the fourth data line DL4 via the third auxiliary switch A21, and can be supplied to the third data line DL3 via the fourth auxiliary switch A22.

[0209] The third auxiliary output channel ACH3 can be selectively connected only to data lines DL5 and DL6 connected to pixels B1 and B2. The output of the third auxiliary output channel ACH3 can be supplied to the sixth data line DL6 via the fifth auxiliary switch A31, and can be supplied to the fifth data line DL5 via the sixth auxiliary switch A32.

[0210] The above embodiments of this disclosure can achieve the following exemplary effects.

[0211] The above embodiments of this disclosure can supply a pre-charge voltage to the display panel through the connection configuration between the source driver and the multiplexer switching circuit, and thus can improve data conversion with low power consumption to enhance image quality.

[0212] The embodiments disclosed above can be uniformly used to generate main components and their power supply paths that generate line-stabilized voltage and / or OBS voltage in addition to pre-charge voltage, and thus can simplify the circuitry used to drive the display panel and achieve low power consumption.

[0213] The effects of this disclosure are not limited to the examples above, and various additional effects can be achieved from this disclosure.

[0214] It will be apparent to those skilled in the art that this disclosure is not limited to the exemplary embodiments and drawings described above, and that various substitutions, modifications, and variations may be made in this disclosure without departing from its spirit or scope. Therefore, the exemplary embodiments described above are provided for illustrative purposes and are not intended to limit the scope or technical concept of this disclosure.

Claims

1. A display device, comprising: The display panel includes: The first pixel, located in the first pixel row and connected to the first data line; and The second pixel is in the second pixel row and adjacent to the first pixel, and is connected to the second data line; Source drivers, including: A data output channel is configured to output a first data voltage to be supplied to the first data line during a first time period during a refresh frame, and to output a second data voltage to be supplied to the second data line during a second time period after the first time period during the refresh frame; and An auxiliary output channel is configured to output a first pre-charge voltage to be supplied to the second data line during the first time period, and to output a second pre-charge voltage to be supplied to the first data line during the second time period; and The multiplexer switching circuit is configured as follows: During the first time period, the data output channel is connected to the first data line and the auxiliary output channel is connected to the second data line; and During the second time period, the data output channel is connected to the second data line and the auxiliary output channel is connected to the first data line.

2. The display device according to claim 1, wherein, The multiplexer switching circuit includes: A first multiplexer switch is connected between the data output channel and the first data line and is configured to be turned on or off based on a first multiplexer control signal. A first auxiliary switch is connected between the auxiliary output channel and the second data line and is configured to be turned on or off based on the first multiplexer control signal; A second multiplexer switch is connected between the data output channel and the second data line, and is configured to be turned on or off based on a second multiplexer control signal; and A second auxiliary switch, connected between the auxiliary output channel and the first data line, is configured to be turned on or off based on the second multiplexer control signal. During the first time period, the first multiplexer control signal is at the ON level, and the second multiplexer control signal is at the OFF level. During the second time period, the first multiplexer control signal is at the off level, and the second multiplexer control signal is at the on level.

3. The display device according to claim 1, wherein: The first pre-charge voltage and the second pre-charge voltage vary with time within a predetermined pre-charge voltage range; and The lower end of the predetermined precharge voltage range is greater than the minimum data voltage output from the source driver, and the higher end of the predetermined precharge voltage range is less than the maximum data voltage output from the source driver.

4. The display device according to claim 3, wherein, During at least one skipped frame before or after the refresh frame: The source driver is configured to float the data output channel and output a line-stabilized voltage to be supplied to the first data line and the second data line through the auxiliary output channel; and The multiplexer switching circuit is configured to simultaneously connect the first data line and the second data line to the auxiliary output channel.

5. The display device according to claim 4, wherein: The line-stabilized voltage is the voltage within the predetermined pre-charge voltage range; and The potential of each of the first data line and the second data line is configured to be maintained at a stable voltage on the line during the at least one skipped frame.

6. The display device according to claim 1, wherein, During the bias stress (OBS) period in the refresh frame and outside of the first and second time periods: The source driver is configured to float the data output channel and output the OBS voltage to be jointly supplied to the first data line and the second data line through the auxiliary output channel; The multiplexer switching circuit is configured to simultaneously connect the first data line and the second data line to the auxiliary output channel during the OBS period. and The light-emitting elements included in each of the first pixel and the second pixel are initialized to an anode reset voltage, and the OBS voltage is applied to the driving elements included in each of the first pixel and the second pixel.

7. The display device according to claim 6, wherein, During at least one skipped frame before or after the refresh frame: The source driver is configured to float the data output channel and output a line-stabilized voltage to be supplied to the first data line and the second data line through the auxiliary output channel. and The multiplexer switching circuit is configured to connect both the first data line and the second data line to the auxiliary output channel simultaneously.

8. The display device according to claim 7, wherein: The first pre-charge voltage and the second pre-charge voltage are within a predetermined pre-charge voltage range; The line-stabilized voltage is the voltage within the predetermined pre-charge voltage range; and The potential of each of the first data line and the second data line is configured to be maintained at a stable voltage on the line during the at least one skipped frame.

9. The display device according to claim 1, wherein: The first pixel and the second pixel are pixels of the same color.

10. A method of driving a display device, the display device comprising a display panel having a first pixel in a first pixel row and connected to a first data line, and having a second pixel in a second pixel row adjacent to the first pixel and connected to a second data line, the method comprising: During the first time period of the refresh frame, a first data voltage is provided to the first data line through the data output channel of the source driver, and a first pre-charge voltage is provided to the second data line through the auxiliary output channel of the source driver; During the second time period following the first time period during the refresh frame, a second data voltage is provided to the second data line through the data output channel, and a second pre-charge voltage is provided to the first data line through the auxiliary output channel; During the first time period of the refresh frame, the data output channel is connected to the first data line and the auxiliary output channel is connected to the second data line; as well as During the second time period of the refresh frame, the data output channel is connected to the second data line and the auxiliary output channel is connected to the first data line.

11. The method according to claim 10, wherein: The first pre-charge voltage and the second pre-charge voltage vary with time within a predetermined pre-charge voltage range; and The lower end of the predetermined precharge voltage range is greater than the minimum data voltage output from the source driver, and the higher end of the predetermined precharge voltage range is less than the maximum data voltage output from the source driver.

12. The method of claim 11, further comprising at least one skip frame period after the refresh frame: Make the data output channel of the source driver float; The auxiliary output channel of the source driver provides line-stabilized voltages to the first and second data lines; and Connect the auxiliary output channel to both the first data line and the second data line simultaneously.

13. The method according to claim 12, wherein: The line-stabilized voltage is a fixed voltage within the predetermined pre-charge voltage range; and The potential of each of the first data line and the second data line is configured to be maintained at a stable voltage on the line during the at least one skipped frame.

14. The method of claim 10, further comprising: The data output channel of the source driver is floated during the bias stress (OBS) period in the refresh frame, the OBS period being outside the first and second time periods of the refresh frame; During the OBS period of the refresh frame, the OBS voltage is output through the auxiliary output channel of the source driver; as well as During the OBS period, the auxiliary output channel is simultaneously connected to both the first data line and the second data line to provide the OBS voltage to both the first data line and the second data line. During the OBS period, the light-emitting elements included in each of the first pixel and the second pixel are initialized to an anode reset voltage, and the OBS voltage is applied to the source electrode of the driving element included in each of the first pixel and the second pixel.

15. The method of claim 14, further comprising, in at least one skip frame before or after the refresh frame: Make the data output channel of the source driver float; The voltage is stabilized by the auxiliary output channel output line of the source driver; and The auxiliary output channel is connected to both the first data line and the second data line to provide the line-stabilized voltage to both the first data line and the second data line.

16. The method of claim 10, wherein: The first pixel and the second pixel are pixels of the same color.

17. A display device, comprising: A source driver having a first data output channel and a first auxiliary output channel, the source driver being configured as follows: During a first time period within the refresh frame, a first data voltage is output via the first data output channel and a first pre-charge voltage is output via the first auxiliary output channel; and During the refresh frame, in the second time period after the first time period, a second data voltage is output via the first data output channel and a second pre-charge voltage is output via the first auxiliary output channel; as well as The display panel includes multiple pixels, wherein the multiple pixels include: A first pixel, in a first column and in an odd-numbered pixel row, and connected to a first data line, the first data line being configured to receive the first data voltage during the first time period and to receive the second pre-charge voltage during the second time period; as well as The second pixel is located in the first column and in an even-numbered pixel row, and is connected to a second data line configured to receive the first pre-charge voltage during the first time period and the second data voltage during the second time period.

18. The display device according to claim 17, further comprising a multiplexer circuit, the multiplexer circuit being configured to: During a first time period within the refresh frame, the first data output channel is connected to the first data line, and the first auxiliary output channel is connected to the second data line; and During the second time period of the refresh frame, the first data output channel is connected to the second data line, and the first auxiliary output channel is connected to the first data line.

19. The display device according to claim 18, wherein: The source driver is also configured to float the first data output channel and stabilize the voltage via the output line of the first auxiliary output channel during skip frames before or after the refresh frame. The multiplexer circuit is further configured to simultaneously connect the first auxiliary output channel to both the first data line and the second data line during the skipped frame; and The first data line and the second data line are also configured to receive the line-stabilized voltage during the skip frame.

20. The display device according to claim 18, wherein: The source driver is also configured to float the first data output channel and output an OBS voltage via the first auxiliary output channel during a bias stress (OBS) period within the refresh frame, the OBS period being outside the first and second time periods within the refresh frame; The multiplexer circuit is further configured to simultaneously connect the first auxiliary output channel to both the first data line and the second data line during the OBS period; and The first data line and the second data line are also configured to receive the OBS voltage during the OBS period.

21. The display device according to claim 17, wherein: The display panel includes multiple red (R), green (G), and blue (B) pixels; The first pixel and the second pixel are pixels of the same color among the plurality of R, G and B pixels; The source driver includes multiple data output channels to output corresponding data voltages for the R, G and B pixels respectively, and the multiple data output channels include the first data output channel; and The source driver is configured to output the first precharge voltage or the second precharge voltage via the first auxiliary output channel shared by the R, G, and B pixels.

22. The display device according to claim 17, wherein: The display panel includes multiple red (R), green (G), and blue (B) pixels; The first pixel and the second pixel are pixels of the same color among the plurality of R, G and B pixels; and The source driver includes: Multiple data output channels are provided to output corresponding data voltages for the R, G, and B pixels, and the multiple data output channels include the first data output channel; as well as Multiple auxiliary output channels output pre-charge voltages corresponding to the R, G, and B pixels, and the multiple auxiliary output channels include the first auxiliary output channel.

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