Memory system and signal monitoring device thereof

Abstract

The invention provides a memory system and a signal monitoring device thereof. The signal monitoring device comprises a signal receiver, a first sampler, a second sampler, a third sampler and a fourth sampler. The signal receiver receives an input signal and a reference voltage, and generates a first received signal and a second received signal. The first sampler and the second sampler respectively sample a first receiving signal and a second receiving signal according to a first clock signal and a second clock signal, and respectively generate a first sampling signal and a second sampling signal. The third sampler samples the first receiving signal and the second receiving signal according to one of a plurality of third clock signals and the first sampling reference voltage so as to generate a third sampling signal. The fourth sampler samples the first sampling signal and the second receiving signal according to one of a plurality of fourth clock signals and a second sampling reference voltage to generate a fourth sampling signal.

Description

Technical Field

[0001] This invention relates to a memory system and a signal monitoring device thereof, and more particularly to a memory system and a signal monitoring device thereof capable of real-time monitoring of an eye diagram of a signal. Background Technology

[0002] In Double Data Rate Synchronous Dynamic Random Access Memory (DDR) systems, the increasing data transfer rate presents greater challenges to signal transmission at the storage interface (especially high-speed interfaces). This is because higher data transfer rates lead to more severe inter-symbol interference (ISI), signal reflection, and crosstalk, all of which compromise signal integrity. To improve signal integrity, existing technologies employ equalization training of the storage interface to mitigate ISI and other signal problems. For example, initial equalization training is used to obtain the optimal sampling phase and ISI equalization coefficients for the initial signal. However, during normal operation of the storage system, changes in ambient temperature, humidity, and operating voltage can alter the characteristics of the transmission link. The sampling phase and ISI equalization coefficients obtained through training may not keep pace with real-time environmental changes, potentially degrading the eye diagram of the input signal at the storage interface. Therefore, existing technologies require periodic training during normal operation of the DDR storage system to continuously adjust the optimal sampling phase and ISI equalization coefficients to adapt to environmental changes. However, the time cost and bandwidth degradation caused by periodic training are intolerable. Summary of the Invention

[0003] This invention discloses a memory system and its signal monitoring device, which can monitor the eye diagram quality of the input signal in real time, so that when the eye diagram deteriorates, the relevant interface can be retrained in a timely and targeted manner.

[0004] According to an embodiment of the present invention, a signal monitoring device includes: a signal receiver for receiving an input signal and a reference voltage, and generating a first received signal and a second received signal, wherein the first received signal and the second received signal are differential signals; a first sampler for sampling the first received signal and the second received signal according to a first clock signal to generate a first sampled signal; a second sampler for sampling the first received signal and the second received signal according to a second clock signal to generate a second sampled signal; a third sampler for sampling the first received signal and the second received signal according to one of a plurality of third clock signals and based on a first sampling reference voltage to generate a third sampled signal; and a fourth sampler for sampling the first received signal and the second received signal according to one of a plurality of fourth clock signals and based on a second sampling reference voltage to generate a fourth sampled signal; wherein the plurality of third clock signals are sequentially separated by a first time delay, the plurality of fourth clock signals are sequentially separated by a second time delay, and the phases of the first clock signal and the second clock signal are complementary.

[0005] According to an embodiment of the present invention, the memory system includes a memory controller and a central buffer, the central buffer being coupled to the memory controller, and the central buffer including the signal monitoring device as described above.

[0006] The memory system also includes multiple data buffers coupled between the central buffer and the memory controller; each of the multiple data buffers includes the signal monitoring device described above. Attached Figure Description

[0007] Figure 1 A schematic diagram of a signal monitoring device according to an embodiment of the present invention is shown.

[0008] Figure 2 This diagram illustrates the monitoring of the eye diagram of the input signal of the signal monitoring device of the present invention.

[0009] Figure 3 A schematic diagram of a signal monitoring device according to another embodiment of the present invention is shown.

[0010] Figure 4 A schematic diagram of a memory system according to an embodiment of the present invention is shown. Detailed Implementation

[0011] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other.

[0012] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be changed arbitrarily, and the layout of the components may also be more complex.

[0013] Please refer to Figure 1 , Figure 1 A schematic diagram of a signal monitoring device according to an embodiment of the present invention is shown. The signal monitoring device 100 includes a signal receiver 110 and samplers 121, 122, 131, and 132. The signal receiver 110 is used to receive an input signal and a reference voltage, and generate a first received signal and a second received signal based on the input signal and the reference voltage. The input signal may be a command / address signal DCA or a data signal DQ. Figure 1 The illustration uses the command / address signal DCA as an example only, but those skilled in the art will understand that the signal monitoring device of this application can also be applied to other signals of the memory system or interface signals of other systems / devices, and this application does not impose any limitations on this. The following description will use the monitoring of the command / address signal DCA as an example.

[0014] In some embodiments, the signal receiver 110 may be a differential amplifier. The positive input of the differential amplifier is used to receive the command / address signal DCA, and the negative input is used to receive the reference voltage VREFCA. The differential amplifier can generate a first received signal RS1 and a second received signal RS2 based on the reference voltage VREFCA and the command / address signal DCA. The command / address signal DCA may be an AC signal, and the reference voltage VREFCA may be between the minimum and maximum voltage of the command / address signal DCA. In some embodiments, the reference voltage VREFCA may be set based on the intermediate value between the minimum and maximum voltage of the command / address signal DCA to maximize the upper and lower voltage margins sampled by the first and second samplers.

[0015] The signal receiver 110 can generate a first received signal RS1 and a second received signal RS2 by performing a differential operation on the command / address signal DCA and the reference voltage VREFCA, wherein the first received signal RS1 and the second received signal RS2 are a pair of differential signals.

[0016] Samplers 121 and 122 are used to receive the first received signal RS1 and the second received signal RS2. Samplers 121 and 122 also receive clock signals CK_t and CK_c respectively, and sample the first received signal RS1 and the second received signal RS2 according to the clock signals CK_t and CK_c respectively, to generate the first sampled signal DT_e and the second sampled signal DT_o respectively. In this embodiment, the clock signals CK_t and CK_c can be complementary signals (180 degrees out of phase). The first sampled signal DT_e and the second sampled signal DT_o can be expressed by the following mathematical formulas:

[0017] At the rising edge of the clock signal CK_t, DT_e = sign(RS1–RS2);

[0018] At the rising edge of the clock signal CK_c, DT_o = sign(RS1–RS2);

[0019] The sign() function is an operation function that determines the sign of a real number.

[0020] Additionally, samplers 131 and 132 are also used to receive the first received signal RS1 and the second received signal RS2. Sampler 131 can sample the first received signal RS1 and the second received signal RS2 based on one of a plurality of clock signals CK1_t, CK_t, and CK2_t, and based on the first sampling reference voltage VSref1 (not shown in the figure), to generate a third sampled signal MON1_e. Specifically, when at the rising edge of clock signals CK1_t, CK_t, or CK2_t, the third sampled signal MON1_e can be expressed as MON1_e = sign(RS1 – RS2 – VSref1).

[0021] Sampler 132 can sample the first received signal RS1 and the second received signal RS2 based on one of multiple clock signals CK1_c, CK_c, and CK2_c, and based on the second sampling reference voltage VSref2 (not shown in the figure), to generate a fourth sampled signal MON1_o. Specifically, when the clock signal CK1_c, CK_c, or CK2_c is at its rising edge, the fourth sampled signal MON1_o can be represented as MON1_o = sign(RS1 – RS2 – VSref2).

[0022] In this embodiment, clock signals CK1_t, CK_t, and CK2_t are sequentially delayed by a first time delay; that is, clock signals CK1_t and CK_t have a first time delay, and clock signals CK_t and CK2_t have the same first time delay. Similarly, clock signals CK1_c, CK_c, and CK2_c are sequentially delayed by a second time delay; that is, clock signals CK1_c and CK_c have a second time delay, and clock signals CK_c and CK2_c have the same second time delay. In this embodiment, the first time delay and the second time delay may be the same. In other embodiments of the present invention, the first time delay and the second time delay may be different. In terms of phase relationship, the phase of clock signal CK1_t may lead the phase of clock signal CK_t, and the phase of clock signal CK_t may lead the phase of clock signal CK2_t. Similarly, the phase of clock signal CK1_c may lead the phase of clock signal CK_c, and the phase of clock signal CK_c may lead the phase of clock signal CK2_c.

[0023] The signal monitoring device 100 also includes selectors 141 and 142. Selectors 141 and 142 can be multiplexers (MUX). Selector 141 can select one of the clock signals CK1_t, CK_t, and CK2_t each time according to the selection signal SEL1 and send it to sampler 131. Selector 142 can select one of the clock signals CK1_c, CK_c, and CK2_c each time according to the selection signal SEL2 and send it to sampler 132.

[0024] Please refer to the following as well. Figure 1 as well as Figure 2 , Figure 2 This diagram illustrates how the signal monitoring device of the present invention monitors the eye diagram of an input signal. Figure 2 In this example, the signal monitoring device 100 samples the eye diagram EYED of the command / address signal DCA through the sampler 131. The sampler 131 can sample at time points ts1, ts2, and ts3 respectively according to the clock signals CK1_t, CK_t, and CK2_t. Among them, the time point ts2 is the same as the sampling time point of the sampler 121, while the time point ts1 can be earlier than the time point ts2, and the time point ts3 can be later than the time point ts2.

[0025] It is worth mentioning that the sampler 131 is provided with a first sampling reference voltage VSref1. The value of the first sampling reference voltage can be adjusted by setting a first offset voltage Voffset1 to obtain sampling points corresponding to different voltage values. For example, at time points ts1 and ts3, the first sampling reference voltage VSref1 can be equal to the reference voltage VB, the reference voltage VB plus the first offset voltage Voffset1, and the reference voltage VB minus the first offset voltage Voffset1, respectively.

[0026] like Figure 2 As shown, by adjusting the first sampling reference voltage VSref1 and selecting different clock signals CK1_t, CK_t, and CK2_t to sample at different time points ts1 to ts3, multiple sampling points A, A′, A″ at time point ts1 and multiple sampling points B, B′, B″ at time point ts3 can be obtained. Specifically, the first sampling reference voltage VSref1 corresponding to sampling points A and B″ is equal to the reference voltage VB plus the first offset voltage Voffset1; the first sampling reference voltage VSref1 corresponding to sampling points A′ and B′ is equal to the reference voltage VB; and the first sampling reference voltage VSref1 corresponding to sampling points A″ and B is equal to the reference voltage VB minus the first offset voltage Voffset1.

[0027] Similarly, sampler 132 can sample the eye diagram EYED of the command / address signal DCA at three different time points according to clock signals CK1_c, CK_c, and CK2_c, respectively, to obtain multiple sampling points. Sampler 132 can be set with a second sampling reference voltage VSref2, the value of which can be adjusted by setting a second offset voltage Voffset2. For example, at each sampling time point, the second sampling reference voltage VSref2 can be equal to the reference voltage VB, the reference voltage VB plus the second offset voltage Voffset2, and the reference voltage VB minus the second offset voltage Voffset2, respectively. It should be noted that the second offset voltage Voffset2 can be different from the first offset voltage Voffset1, that is, the second sampling reference voltage VSref2 can be different from the first sampling reference voltage VSref1. This allows samplers 131 and 132 to obtain more sampling points, which helps to improve the accuracy of monitoring.

[0028] It is worth mentioning that in this embodiment, the clock signals CK_t and CK_c are complementary in phase. Therefore, samplers 131 and 132 will not sample simultaneously, but can sample sequentially.

[0029] By comparing the first sampled signal DT_e generated by sampler 121 and the third sampled signal MON1_e generated by sampler 131, and by comparing the second sampled signal DT_o generated by sampler 122 and the fourth sampled signal MON1_o generated by sampler 132, it can be determined whether the eye diagram EYED of the command / address signal DCA has deteriorated. Furthermore, by adjusting the sampling time points of samplers 131 and 132, and comparing the first sampled signal DT_e with the third sampled signal MON1_e, and comparing the second sampled signal DT_o with the fourth sampled signal MON1_o, the change state of the eye diagram EYED of the command / address signal DCA can be further determined.

[0030] Please refer to Figure 3 , Figure 3 A schematic diagram of a signal monitoring device according to another embodiment of the present invention is shown. The signal monitoring device 300 includes a signal receiver 310, samplers 321, 322, 331, 332, selectors 341, 342, a comparator 350, and a clock signal generator 360. In this embodiment, the signal receiver 310, samplers 321, 322, 331, 332, and selectors 341, 342 are connected to the signal receiver 310, samplers 321, 322, 331, 332, and selectors 341, 342. Figure 1 The implementation methods are similar, so I will not go into detail here.

[0031] In this embodiment, comparator 350 is coupled to the output terminals of samplers 321, 322, 331, and 332, and is used to receive the first sampled signal DT_e, the second sampled signal DT_o, the third sampled signal MON1_e, and the fourth sampled signal MON1_o. Comparator 350 compares the first sampled signal DT_e with the third sampled signal MON1_e, and compares the second sampled signal DT_o with the fourth sampled signal MON1_o, to generate comparison result information CI.

[0032] In this embodiment, the clock signal generator 360 includes a differential amplifier 361 and delay units 362 and 363. The positive and negative input terminals of the differential amplifier 361 receive clock signals DCK_t and DCK_c with complementary phases, respectively. The two output terminals of the differential amplifier 361 output clock signals CK1_t and CK1_c, respectively, and are coupled to delay units 362 and 363. Delay unit 362 has multiple cascaded buffers and outputs clock signals CK_t and CK2_t sequentially by delaying the clock signal CK1_t, wherein the clock signals CK1_t, CK_t, and CK2_t are sequentially delayed by a first time delay. Delay unit 363 also has multiple cascaded buffers and outputs clock signals CK_c and CK2_c sequentially by delaying the clock signal CK1_c, wherein the clock signals CK1_c, CK_c, and CK2_c are sequentially delayed by a second time delay.

[0033] In this embodiment, each buffer in delay units 361 and 362 can have the same transmission delay, that is, the first time delay and the second time delay are the same. In other words, the phase difference between clock signals CK1_t and CK_t, the phase difference between clock signals CK_t and CK2_t, the phase difference between clock signals CK1_c and CK_c, and the phase difference between clock signals CK_c and CK2_c can be the same.

[0034] Incidentally, in this embodiment, sampler 331 can sample the eye diagram of the signal according to three clock signals (CK1_t, CK_t, CK2_t), and sampler 332 can also sample the eye diagram of the signal according to three clock signals (CK1_c, CK_c, CK2_c). In other embodiments of the present invention, samplers 331 and 332 can also select more than three clock signals to perform the sampling operation to improve the accuracy of the eye diagram sampling operation on the time axis. Similarly, in this embodiment, sampler 331 can select three voltage values ​​(reference voltage VB, reference voltage VB plus first offset voltage Voffset1, and reference voltage VB minus first offset voltage Voffset1) as the first sampling reference voltage for sampling, and sampler 332 can also select three voltage values ​​(reference voltage VB, reference voltage VB plus second offset voltage Voffset2, and reference voltage VB minus second offset voltage Voffset2) as the second sampling reference voltage for sampling. In other embodiments of the present invention, samplers 331 and 332 may also select three or more voltage values ​​as corresponding sampling reference voltages to improve the accuracy of the eye diagram sampling operation in terms of voltage values.

[0035] Please refer to Figure 4 , Figure 4A schematic diagram of a memory system according to an embodiment of the present invention is shown. The memory system 400 may be a memory system conforming to the JEDEC Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM) standard, such as JEDEC DDR, DDR2, DDR3, DDR4, DDR5, and other double data rate memory standards. Alternatively, the memory system 400 may be an internal memory conforming to other standards or protocols, such as RAMBUS internal memory, or it may be a memory conforming to future memory standards or protocols.

[0036] The memory system 400 includes multiple data buffers 410, a central buffer 420, and a memory controller 430. Data buffers 410 store multiple data items and are coupled to the memory controller 430 and the central buffer 420. The memory controller 430 performs read or write operations on the data signal DQ with the data buffers 410 via a data strobe signal DQS. The central buffer 420 is coupled to the memory controller 430 to receive command / address signals DCA from the memory controller 430 and to send data access commands generated based on the command / address signals DCA to the data buffers 410. In some embodiments, the central buffer 420 may be a register clock driver (RCD). The memory controller 430 may be a master controller, such as a CPU.

[0037] The central buffer 420 has a signal monitoring device 421. The signal monitoring device 421 is coupled to the memory controller 430 and receives the clock signal CK and the command / address signal DCA sent by the memory controller 430. The signal monitoring device 421 can be implemented by the aforementioned signal monitoring devices 100 or 300. Taking signal monitoring device 300 as an example, signal monitoring device 421 can generate clock signals DCK_t and DCK_c in signal monitoring device 300 based on the clock signal CK, and monitor the eye diagram of the command / address signal DCA based on the clock signals DCK_t and DCK_c.

[0038] The signal monitoring device 421 can generate comparison result information CI by comparing the sampled signals generated by its sampler. The signal monitoring device 421 can transmit the comparison result information CI to the memory controller 430, which can determine whether to perform re-training based on the comparison result information CI. When the comparison result information CI indicates that the eye diagram of the command / address signal DCA has deteriorated, the memory controller 430 determines to perform re-training.

[0039] The data buffer 410 also includes a signal monitoring device 411. The signal monitoring device 411 can be implemented using the aforementioned signal monitoring devices 100 or 300. The signal monitoring device 411 is coupled between the memory controller 430 and the central buffer 420, and receives the data signal DQ and the data strobe signal DQS sent by the memory controller 430. The signal monitoring device 411 can generate complementary clock signals DQS_t and DQS_c based on the data strobe signal DQS to monitor the eye diagram of the data signal DQ. The clock signals DQS_t and DQS_c are respectively coupled with… Figure 3 The clock signals DCK_t and DCK_c in the embodiment are similar and will not be described again here. The signal monitoring device 411 generates comparison result information CI by comparing the sampled signals of its sampler. The comparison result information CI can be fed back to the memory controller 430 via the central buffer 420.

[0040] In this embodiment, for example, when the operating environment and operating voltage of the memory system 400 change, the eye diagrams of the data signal DQ and the command / address signal DCA may deteriorate. Correspondingly, the comparison result information CI generated by the signal monitoring devices 411 and 421 can reflect the aforementioned deterioration, thereby prompting the memory controller 430 to perform retraining.

[0041] Please refer to the same time. Figure 3 as well as Figure 4During retraining, the signal monitoring device in this embodiment can also be used to monitor the quality of the signal eye diagram. Taking the signal monitoring device 421 as an example, during retraining, the memory controller 430 can first adjust the phase of the clock signal selected by the samplers 331 and 332 in the signal monitoring device 421. For example, when not retraining, the samplers 331 and 332 sample according to the clock signals CK_t and CK_c, respectively. During retraining, the sampling clock signals of the samplers 331 and 332 can be adjusted. For example, the samplers 331 and 332 can first sample according to the clock signals CK1_t and CK1_c, respectively, and then the first sample signal DT_e is compared with the third sample signal MON1_e, and the second sample signal DT_o is compared with the fourth sample signal MON1_o to generate the first comparison result information CI. Furthermore, samplers 331 and 332 can sample according to clock signals CK2_t and CK2_c respectively, and continue to compare the first sample signal DT_e with the third sample signal MON1_e, and compare the second sample signal DT_o with the fourth sample signal MON1_o, to generate a second comparison result information CI. When the first comparison result information CI indicates that the first sample signal DT_e and the third sample signal MON1_e are the same, and the second sample signal DT_o and the fourth sample signal MON1_o are the same, while the second comparison result information CI indicates that the first sample signal DT_e and the third sample signal MON1_e are different, and / or the second sample signal DT_o and the fourth sample signal MON1_o are different, the memory controller 430 can adjust the clock signals CK_t and CK_c by advancing their phases. On the other hand, when the first comparison result information CI indicates that the first sampled signal DT_e is different from the third sampled signal MON1_e, and / or the second sampled signal DT_o is different from the fourth sampled signal MON1_o, while the second comparison result information CI indicates that the first sampled signal DT_e is the same as the third sampled signal MON1_e, and the second sampled signal DT_o is the same as the fourth sampled signal MON1_o, the memory controller 430 can adjust the clock signals CK_t and CK_c by delaying the phase of the clock signals CK_t and CK_c.

[0042] Furthermore, during retraining, the memory controller 430 can also monitor the quality of the signal eye diagram by adjusting the voltage values ​​of the sampling reference voltages of the samplers 331 and 332. Similarly, the memory controller 430 can make corresponding adjustments to the reference voltage VREFCA received by the signal receiver 310 based on the comparison result information CI.

[0043] Based on the above, this embodiment of the invention uses a signal monitoring device to monitor in real time whether the eye diagram of a signal (such as a command / address signal or data signal) deteriorates due to changes in environmental or voltage conditions. Only when deterioration of the signal's eye diagram is detected is a retraining mechanism triggered. This reduces the time cost of periodic retraining in existing technologies and avoids the bandwidth degradation problem caused by frequent retraining. Furthermore, the signal monitoring device in this embodiment uses multiple clock signals and a sampling reference voltage value for sampling. When the signal's eye diagram deteriorates, the specific area of ​​deterioration can be identified, making retraining more targeted and improving retraining efficiency.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A signal monitoring device, characterized in that, The signal monitoring device includes: A signal receiver receives an input signal and a reference voltage, and generates a first received signal and a second received signal, wherein the first received signal and the second received signal are differential signals; The first sampler samples the first received signal and the second received signal according to the first clock signal to generate a first sampled signal; The second sampler samples the first received signal and the second received signal according to the second clock signal to generate a second sampled signal; A third sampler samples the first received signal and the second received signal based on one of a plurality of third clock signals and a first sampling reference voltage to generate a third sampled signal; and The fourth sampler samples the first received signal and the second received signal based on one of a plurality of fourth clock signals and a second sampling reference voltage to generate a fourth sampled signal. The plurality of third clock signals are sequentially delayed by a first time, and the plurality of fourth clock signals are sequentially delayed by a second time, wherein the first clock signal and the second clock signal are complementary in phase.

2. The signal monitoring device according to claim 1, characterized in that, The signal monitoring device also includes: A comparator compares the first sampled signal with the third sampled signal and the second sampled signal with the fourth sampled signal to generate comparison result information, which is used to indicate whether the eye diagram of the input signal has deteriorated.

3. The signal monitoring device according to claim 1, characterized in that, The value of the first sampling reference voltage is adjusted according to the first offset voltage, and the value of the second sampling reference voltage is adjusted according to the second offset voltage.

4. The signal monitoring device according to claim 1, characterized in that, The signal monitoring device further includes a first selector and a second selector. The first selector selects one of the plurality of third clock signals according to a first selection signal and transmits it to the third sampler. The second selector selects one of the plurality of fourth clock signals according to a second selection signal and transmits it to the fourth sampler.

5. The signal monitoring device according to claim 1, characterized in that, The input signal is a command / address signal or a data signal from the memory controller.

6. The signal monitoring device according to claim 1, characterized in that, The signal monitoring device also includes: A clock signal generator, including: A differential amplifier receives a first external clock signal and a second external clock signal corresponding to the input signal, and generates a first output signal and a second output signal. A first delay unit is coupled to the first output terminal of the differential amplifier to receive the first output signal, and obtains the plurality of third clock signals by sequentially delaying the first output signal; and The second delay unit is coupled to the second output terminal of the differential amplifier to receive the second output signal, and obtains the plurality of fourth clock signals by sequentially delaying the second output signal.

7. The signal monitoring device according to claim 1, characterized in that, The signal receiver is a differential amplifier. The first input terminal of the differential amplifier receives the input signal, the second input terminal of the differential amplifier receives the reference voltage, the first output terminal of the differential amplifier outputs the first received signal, and the second output terminal of the differential amplifier outputs the second received signal.

8. The signal monitoring device according to claim 1, characterized in that, The reference voltage is between the maximum and minimum voltages of the input signal.

9. A memory system, comprising: Memory controller; A central buffer is coupled to the memory controller; The central buffer includes a first signal monitoring device, which comprises: A first signal receiver receives a first input signal and a first reference voltage, and generates a first received signal and a second received signal, wherein the first received signal and the second received signal are differential signals. The first sampler samples the first received signal and the second received signal according to the first clock signal to generate a first sampled signal; The second sampler samples the first received signal and the second received signal according to the second clock signal to generate a second sampled signal; A third sampler samples the first received signal and the second received signal based on one of a plurality of third clock signals and a first sampling reference voltage to generate a third sampled signal; and The fourth sampler samples the first received signal and the second received signal based on one of a plurality of fourth clock signals and a second sampling reference voltage to generate a fourth sampled signal. The plurality of third clock signals are sequentially delayed by a first time, and the plurality of fourth clock signals are sequentially delayed by a second time, wherein the first clock signal and the second clock signal are complementary in phase.

10. The memory system according to claim 9, characterized in that, The memory system also includes: Multiple data buffers are coupled between the central buffer and the memory controller; each of the multiple data buffers includes a second signal monitoring device, the second signal monitoring device comprising: The second signal receiver receives the second input signal and the second reference voltage, and generates a third received signal and a fourth received signal, wherein the third received signal and the fourth received signal are differential signals. The fifth sampler samples the third and fourth received signals according to the fifth clock signal to generate a fifth sampled signal; The sixth sampler samples the third and fourth received signals according to the sixth clock signal to generate a sixth sampled signal; A seventh sampler samples the third received signal and the fourth received signal based on one of a plurality of seventh clock signals and a third sampling reference voltage to generate a seventh sampled signal; and The eighth sampler samples the third received signal and the fourth received signal based on one of a plurality of eighth clock signals and a fourth sampling reference voltage to generate an eighth sampled signal. The plurality of seventh clock signals are sequentially delayed by a third time, the plurality of eighth clock signals are sequentially delayed by a fourth time, and the fifth clock signal and the sixth clock signal are complementary in phase.

11. The memory system according to claim 9, characterized in that, The first signal monitoring device further includes: A first comparator compares the first sampled signal with the third sampled signal and compares the second sampled signal with the fourth sampled signal to generate first comparison result information, which is used to indicate whether the eye diagram of the first input signal has deteriorated.

12. The memory system according to claim 10, characterized in that, The second signal monitoring device also includes: The second comparator compares the fifth sampled signal with the seventh sampled signal and the sixth sampled signal with the eighth sampled signal to generate second comparison result information, which is used to indicate whether the eye diagram of the second input signal has deteriorated.

13. The memory system according to claim 11, characterized in that, The memory controller receives the first comparison result information and determines whether to retrain the interface corresponding to the first input signal based on the first comparison result information.

14. The memory system according to claim 12, characterized in that, The memory controller receives the second comparison result information and determines whether to retrain the interface corresponding to the second input signal based on the second comparison result information.

15. The memory system according to claim 9, characterized in that, The value of the first sampling reference voltage is adjusted according to the first offset voltage, and the value of the second sampling reference voltage is adjusted according to the second offset voltage.

16. The memory system according to claim 10, characterized in that, The value of the third sampling reference voltage is adjusted according to the third offset voltage, and the value of the fourth sampling reference voltage is adjusted according to the fourth offset voltage.

17. The memory system according to claim 9, characterized in that, The first signal monitoring device further includes: The first clock signal generator includes: The first differential amplifier receives a first external clock signal and a second external clock signal corresponding to the first input signal, and generates a first output signal and a second output signal. A first delay unit is coupled to the first output terminal of the first differential amplifier to receive the first output signal, and obtains the plurality of third clock signals by sequentially delaying the first output signal; and The second delay unit is coupled to the second output terminal of the first differential amplifier to receive the second output signal, and obtains the plurality of fourth clock signals by sequentially delaying the second output signal.

18. The memory system according to claim 10, characterized in that, The second signal monitoring device also includes: The second clock signal generator includes: The second differential amplifier receives a third external clock signal and a fourth external clock signal corresponding to the second input signal, and generates a third output signal and a fourth output signal. A third delay unit is coupled to the first output terminal of the second differential amplifier to receive the third output signal, and obtains the plurality of seventh clock signals by sequentially delaying the third output signal; and The fourth delay unit is coupled to the second output terminal of the second differential amplifier to receive the fourth output signal, and obtains the plurality of eighth clock signals by sequentially delaying the fourth output signal.

19. The memory system according to claim 9, characterized in that, The first input signal is a command / address signal from the memory controller.

20. The memory system according to claim 10, characterized in that, The second input signal is a data signal from the memory controller.

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