Memory device using on-chip ECC scheme and testing method thereof

Abstract

The invention relates to a memory device employing an on-chip ECC scheme and a testing method thereof. A memory device includes: a normal cell region and a parity cell region; an error correction circuit configured to perform an error correction operation on read data output from the normal cell region based on a read parity bit output from the parity cell region to generate error-corrected data; an error correction detection circuit configured to detect whether an error correction operation is performed on read data not including an error bit to generate an error correction detection signal; and a test output circuit configured to generate a test result signal corresponding to the error corrected data in a test mode in a case where the test result signal is masked in accordance with the error correction detection signal.

Description

Cross-reference to related applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0111157, filed on August 20, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] Various embodiments of this disclosure relate to a semiconductor design technique, and more specifically to a testing method for a memory device employing an on-chip ECC scheme. Background Technology

[0003] In the early days of the semiconductor memory industry, many initial good dies with defect-free memory cells existed in memory chips manufactured using on-wafer semiconductor fabrication processes. However, as the capacity of memory devices has gradually increased, it has become difficult to manufacture memory devices with completely defect-free memory cells; currently, it can be said that it is impossible to manufacture memory devices with defect-free memory cells. As a solution to overcome this situation, a method is being used to repair defective memory cells in a memory device with redundant memory cells, or a method is being used to correct errors in the data of memory cells using error correction circuits.

[0004] In the case of memory devices employing on-chip ECC schemes, a method has been proposed for allocating and storing parity bits for ECC into a portion of the memory cell array (hereinafter referred to as the "parity cell region"). Recently, various methods for effectively testing the normal cell region and parity cell region of memory devices employing on-chip ECC schemes have been investigated. Summary of the Invention

[0005] Embodiments of this disclosure relate to a testing method for a memory device employing an on-chip ECC scheme.

[0006] According to one embodiment of the present disclosure, a memory device includes: a normal cell region and a parity check cell region; an error correction circuit configured to perform an error correction operation on read data output from the normal cell region based on read parity bits output from the parity check cell region to generate error-corrected data; a miscorrection detection circuit configured to detect whether an error correction operation has been performed on read data that does not contain error bits to generate a miscorrection detection signal; and a test output circuit configured to generate a test result signal corresponding to the error-corrected data in a test mode when a test result signal is masked according to the miscorrection detection signal.

[0007] According to one embodiment of this disclosure, a memory device includes: an error correction circuit configured to generate an error position signal indicating the position of an error bit in read data based on a read parity bit, and to perform an error correction operation on the read data according to the error position signal to generate error-corrected data; an error correction detection circuit configured to detect whether an error correction operation has been performed on read data that does not contain an error bit, based on the read data and the error position signal, to generate an error correction detection signal; and a test output circuit configured to generate a test result signal corresponding to the error-corrected data in a test mode when a test result signal is masked according to the error correction detection signal.

[0008] According to one embodiment of this disclosure, a testing method for a memory device includes: generating an error position signal indicating the location of an error bit in read data based on reading a parity bit; performing an error correction operation on the read data according to the error position signal to generate error-corrected data; detecting whether an error correction operation was performed on read data that does not contain an error bit according to the read data and the error position signal to generate a false correction detection signal; and generating a test result signal corresponding to the error-corrected data if a test result signal is masked according to the false correction detection signal.

[0009] According to embodiments of this disclosure, the memory device can prevent misjudgment of normal cells due to erroneous corrections by the on-chip ECC circuitry during testing operations. Therefore, yield can be improved by preventing unnecessary repair operations.

[0010] Those skilled in the art will clearly understand these and other features and advantages of embodiments of the present disclosure from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A detailed configuration diagram of the storage unit area.

[0013] Figure 3 This is a diagram used to describe the incorrect correction of the error correction circuit due to a failure of the sub-word line driver.

[0014] Figure 4 It is shown Figure 1 Detailed configuration diagram of the error correction circuit.

[0015] Figure 5 It is shown Figure 4 The circuit diagram of the error corrector.

[0016] Figure 6 It is shown Figure 1 The circuit diagram of the error correction detection circuit.

[0017] Figure 7 It is shown Figure 1 The circuit diagram of the test output circuit.

[0018] Figure 8 It is a table used to describe the signal states for each situation according to embodiments of the present disclosure.

[0019] Figures 9A to 9D This is a diagram used to describe test operations for each situation according to embodiments of the present disclosure.

[0020] Figure 10 This is a flowchart describing test operations of a memory device according to embodiments of the present disclosure. Detailed Implementation

[0021] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, embodiments of the present disclosure may take different forms and should not be construed as limited to those described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, and to fully convey the scope of the present disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same parts in the various figures and embodiments of the present disclosure.

[0022] It should be understood that when an element is referred to as "coupled" or "connected" to another element, it can mean that the two are directly coupled, or that the two are electrically connected to each other with another circuit or element between them. It should also be understood that the terms "comprising," "including," "having," etc., as used in this specification specify the presence of the stated features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this disclosure, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0023] Figure 1 This is a block diagram illustrating a memory device 100 according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 Detailed configuration diagram of storage unit area 110.

[0024] refer to Figure 1 The memory device 100 may include a memory cell area 110, a read circuit 130, a write circuit 140, an error correction code (ECC) engine 150, a data input circuit 162, a data output circuit 164, an error correction detection circuit 170, and a test output circuit 180.

[0025] Storage cell region 110 may include a normal cell region 112 for storing normal data (or user data) and a parity check cell region 114 for storing parity bits used to correct errors in the normal data. The parity bits may be referred to as error correction codes. Multiple cell blocks arranged in an array along the row and column directions may be arranged in the normal cell region 112 and the parity check cell region 114. Each cell block may include multiple storage cells MC coupled between multiple word lines WL and multiple bit lines BL. In one embodiment of this disclosure, a "cell block" may be defined as a group of storage cells sharing word lines WL and bit lines BL and arranged in the same manner. Although not shown, multiple sub-word line drivers may be arranged between cell blocks arranged along the row direction, and multiple bit line sense amplifiers may be arranged between cell blocks arranged along the column direction.

[0026] refer to Figure 2 The diagram illustrates multiple cell blocks arranged along a row direction. Multiple cell blocks (e.g., normal cell blocks MB0 to MB15) can be arranged in normal cell region 112, and at least one cell block (e.g., parity cell block MBECC) can be arranged in parity cell region 114. Each of cell blocks MB0 to MB15 and MBECC may include multiple memory cells MC coupled between multiple word lines WL and multiple bit lines BL.

[0027] Each of the cell blocks MB0 through MB15 and MBECC can alternately share a sub-word line driver SWD with its adjacent cell blocks. The rectangle between cell blocks MB0 through MB15 and MBECC can represent the sub-word line driver SWD, and the lines extending to the left and right of the sub-word line driver SWD can represent word lines (or sub-word lines, WL). A sub-word line driver SWD can be assigned to up to four cell blocks in the row direction. In practice, there are far more sub-word line drivers and word lines than this, but only a few are shown here to illustrate a simple structure.

[0028] During a read or write operation, each of the cell blocks MB0 through MB15 and MBECC can input or output data in units of predetermined bits. In the following description, as an example, the case where each of the cell blocks MB0 through MB15 and MBECC inputs or outputs data in units of 8 bits during a write or read operation will be described. Each of the cell blocks MB0 through MB15 and MBECC can read 8 bits of data from a memory cell coupled between a word line specified by a row address and a predetermined number (e.g., 8) of bit lines specified by a column address, or write 8 bits of data to a memory cell. Therefore, the memory device 100 can input or output 128 bits of data and use 8 bits of error correction code during a single write or read operation. For reference, all sub-word line drivers SWD located at the same level in the row direction can be activated to select the word line specified by the row address.

[0029] Return to reference Figure 1 The read circuit 130 may include a normal read circuit (IOSA) 132 and a parity read circuit (IOSA_PTY) 134. During a read operation, the normal read circuit 132 can sense and amplify the data output from the normal cell region 112 and output the sensed and amplified data as 128-bit read data RDATA. During a read operation, the parity read circuit 134 can sense and amplify the data output from the parity cell region 114 and output the sensed and amplified data as 8-bit read parity bit RPTY. The normal read circuit 132 and the parity read circuit 134 may be implemented using I / O sense amplifiers.

[0030] The write circuit 140 may include a normal write circuit (WDRV) 142 and a parity write circuit (WDRV_PTY) 144. During a write operation, the normal write circuit 142 may write 128 bits of write data WDATA transmitted from the data input circuit 162 into the normal cell area 112. During a write operation, the parity write circuit 144 may write 8 bits of write parity bit WPTY transmitted from the ECC engine 150 into the parity cell area 114. The normal write circuit 142 and the parity write circuit 144 may be implemented using a write driver.

[0031] According to an embodiment, in test mode, the normal write circuit 142 and the parity write circuit 144 can set the write data WDATA and the write parity bit WPTY to a preset target test pattern, so as to write the preset target test pattern into the normal cell area 112 and the parity cell area 114. The normal read circuit 132 and the normal write circuit 142 can input / output data to / from the normal cell area 112 through the local input / output line LIO, while the parity read circuit 134 and the parity write circuit 144 can input / output data to / from the parity cell area 114 through the local input / output line LIO.

[0032] The ECC engine 150 may include a parity generation circuit 152 and an error correction circuit 154. The ECC engine 150 may also be referred to as an on-chip ECC engine.

[0033] The parity generation circuit 152 can use the write data WDATA transmitted from the data input circuit 162 to calculate the write parity bit WPTY. The write parity bit WPTY can be data used to correct errors in the write data WDATA. The parity generation circuit 152 can use 128 bits of write data WDATA to generate an 8-bit write parity bit WPTY.

[0034] Error correction circuit 154 can output error-corrected data CDATA by performing an error correction operation on read data RDATA using the parity bit RPTY. Error correction circuit 154 can generate an error location signal based on the read parity bit RPTY. Figure 5 The error location signal CORR indicates the position of the erroneous bit (hereinafter referred to as the "error bit") within the bits of the read data RDATA (hereinafter referred to as the "read bits"). The error correction circuit 154 can perform an error correction operation based on the error location signal CORR to invert the error bit of the read data RDATA. The error correction circuit 154 can output the inverted error location signal CORRB, generated by inverting the error location signal CORR, to the error correction detection circuit 170. Each of the error location signal CORR and the inverted error location signal CORRB may include bits corresponding to the number of bits in the read data RDATA (i.e., 128 bits). When an error bit occurs beyond the error correction capability, the error correction circuit 154 may generate the error location signal CORR for a normal bit instead of an error bit.

[0035] The data input circuit 162 can receive write data WDATA via a buffered external data DIO input to the global input / output line GIO through a data pad (not shown). The data input circuit 162 can transmit the write data WDATA to the normal write circuit 142 and the parity generation circuit 152 respectively.

[0036] Data output circuit 164 can receive error-corrected data CDATA transmitted from error correction circuit 154 to output external data DIO to global input / output line GIO. For reference, error correction circuit 154 and data output circuit 164 can operate according to strobe signals having a preset delay time for timing margins. For example, error correction circuit 154 can operate synchronously with a first strobe signal IO_STB, while data output circuit 164 can operate synchronously with a second strobe signal IOD_STB generated by delaying the first strobe signal IO_STB. Data output circuit 164 can be implemented using a driver (or inverter) for receiving read data RDATA to output external data DIO to global input / output line GIO synchronously with the second strobe signal IOD_STB. Although not shown, a normal mode signal activated in normal mode (excluding test mode) is provided to data output circuit 164, and data output circuit 164 can operate only in normal mode.

[0037] The error correction detection circuit 170 generates an error correction detection signal MIS_CORR based on the read data RDATA, the inverted error position signal CORRB, and the on-chip ECC mode signal T_ECC_ONB. When the ECC engine 150 operates in test mode for the on-chip ECC scheme, the on-chip ECC mode signal T_ECC_ONB can be activated to a logic low level. The error correction detection circuit 170 can determine whether the read data RDATA includes error bits by checking whether the read data RDATA corresponds to the target test pattern, and determine whether error correction has been performed on the read data RDATA based on the inverted error position signal CORRB. Therefore, in test mode where the on-chip ECC scheme is applied, the error correction detection circuit 170 can generate the error correction detection signal MIS_CORR by detecting the case where the read data RDATA does not contain error bits but error correction has been performed on the read data RDATA (i.e., error correction has been performed on read data that does not contain error bits).

[0038] The test output circuit 180 can output a test result signal TOUT based on the test mode signal TEST_ENB, the error correction detection signal MIS_CORR, and the error-corrected data CDATA. The test mode signal TEST_ENB can be activated to a logic low level in test mode. The test output circuit 180 can generate a test result signal TOUT corresponding to the error-corrected data CDATA in test mode, even if the test result signal TOUT is masked according to the error correction detection signal MIS_CORR. The test output circuit 180 can output the test result signal TOUT, indicating pass / fail, to the test input / output line TGIO. In one embodiment, the test mode may include parallel test operations. However, embodiments of this disclosure are not limited to this and may include various types of test operations.

[0039] Although Figure 1 Although not shown, the data input circuit 162, parity generation circuit 152, normal write circuit 142, and parity write circuit 144 can be activated during a write operation. For example, the data input circuit 162, parity generation circuit 152, normal write circuit 142, and parity write circuit 144 can be activated according to a write command. On the other hand, the normal read circuit 132, parity read circuit 134, error correction circuit 154, data output circuit 164, error correction detection circuit 170, and test output circuit 180 can be activated during a read operation. For example, the normal read circuit 132, parity read circuit 134, error correction circuit 154, data output circuit 164, error correction detection circuit 170, and test output circuit 180 can be activated according to a read command.

[0040] Figure 3 This is a diagram used to describe the incorrect correction of the error correction circuit 154 due to a failure of the sub-word line driver.

[0041] See Figure 3 Because adjacent cell blocks MB0 to MB15 and MPECC share a sub-word line driver, there is a high probability that errors will occur in the cell blocks on both sides of the sub-word line driver when a defect occurs in the sub-word line driver. For example, since the second normal cell block MB1 and the third normal cell block MB2 share a sub-word line driver, errors will occur simultaneously in the first to fourth normal cell blocks MB0 to MB3 when a defect occurs in the shared sub-word line driver.

[0042] In this situation, due to an error exceeding the error correction capability of the error correction circuit 154, a false correction occurs, performing error correction on the data of a normal cell block that did not have an error. Because of this false correction, the number of erroneous bits in the data output from the memory device 100 further increases.

[0043] During parallel testing of the compressed and outputted error-corrected data CDATA, an inappropriate test result signal TOUT is generated due to incorrect correction. The external test unit (or memory controller) then instructs a repair operation based on this inappropriate TOUT signal. As a result, unnecessary repair operations are performed on normal cells, leading to reduced redundancy efficiency.

[0044] According to one embodiment of this disclosure, the error correction detection circuit 170 can generate an error correction detection signal MIS_CORR by detecting a situation where the read data RDATA in test mode does not contain error bits but error correction has already been performed on the read data RDATA. The test output circuit 180 can generate a test result signal TOUT corresponding to the error-corrected data CDATA by masking the test result signal TOUT based on the error correction detection signal MIS_CORR. Therefore, by preventing the generation of an inappropriate test result signal TOUT due to error correction, unnecessary repair operations can be prevented, thereby improving the yield rate.

[0045] The following will refer to Figures 4 to 7 describe Figure 1 Detailed configuration of each circuit.

[0046] Figure 4 It is shown Figure 1 Detailed configuration diagram of the error correction circuit 154.

[0047] Reference Figure 4 The error correction circuit 154 may include a code arithmetic unit 210, an error location detector 220, and an error corrector 230.

[0048] Code processor 210 can use 128 bits to read data RDATA<127:0> to generate an 8-bit preliminary parity check bit E_P<7:0>. The preliminary parity check bit E_P<7:0> can also be referred to as the preliminary error-correcting code. For example, code processor 210 can use a parity check matrix (also called an H matrix) to generate the preliminary parity check bit E_P<7:0>. However, embodiments of this disclosure are not limited thereto; code processor 210 can generate the error-correcting code by applying known BCH codes, Hamming codes, or RS codes, or by applying another type of parity check code.

[0049] For reference only. Figure 1 The parity check generation circuit 152 can be adopted with Figure 4The code arithmetic unit 210 included in the error correction circuit 154 is implemented with essentially the same configuration. According to one embodiment, the code arithmetic units of the parity generation circuit 152 and the error correction circuit 154 can be combined into a single configuration. That is, the parity generation circuit 152 can be used for write operations, while the code arithmetic unit of the error correction circuit 154 can be used for read operations.

[0050] Error location detector 220 compares the preliminary parity bit E_P<7:0> with the read parity bit RPTY<7:0> to generate a 128-bit error location signal CORR<127:0>. Error location detector 220 compares the preliminary parity bit E_P<7:0> with the read parity bit RPTY<7:0> for each bit to generate an 8-bit checksum (which is obtained by encoding the error location information), and decodes the checksum to generate the 128-bit error location signal CORR<127:0>. The bits of the 128-bit error location signal CORR<127:0> (hereinafter referred to as "error location bits") correspond to the read bits of the 128-bit read data RDATA<127:0>, and the error location bits corresponding to the error bits in the read bits can be set to high bits. For example, if the checksum is (0, 1, 0, 0, 0, 0, 1), then the error location detector 220 can detect the 81st read bit RDATA. <80> Error bit 81 CORR <80> Set to the high bit. That is, the error location signal CORR<127:0> can be a signal that identifies the error bit in the read data RDATA<127:0>.

[0051] Error corrector 230 can generate error-corrected data CDATA<127:0> by correcting errors in the read data RDATA<127:0> based on the error position signal CORR<127:0>. Error corrector 230 can perform an error correction operation that inverts the error bits of the read data RDATA<127:0> based on the error position signal CORR<127:0>. Furthermore, error corrector 230 can output a 128-bit inverted error position signal CORRB<127:0> by inverting the error position signal CORR<127:0>.

[0052] If the error correction circuit 154 has the error correction capability to correct a 1-bit error, when an error bit occurs within the error correction capability range (i.e., when a 1-bit error occurs), the error location detector 220 can set the error location bit corresponding to the error bit in the read bits to a high bit. However, when an error bit occurs beyond the error correction capability, i.e., when a multi-bit error occurs, the error location detector 220 will not set the error location bit corresponding to the error bit in the read bits to a high bit, but will instead perform a erroneous action of setting the error location bit corresponding to the normal read bits to a high bit. Due to this erroneous action, the error corrector 230 performs an error correction operation that reverses the normal read bits. As a result, when an error bit occurs beyond the error correction capability, the error correction circuit 154 performs a erroneous correction.

[0053] Figure 5 It is shown Figure 4 Circuit diagram of error corrector 230.

[0054] See Figure 5 The error corrector 230 may include first to 128 error correction components 230_0 to 230_127 corresponding to each bit of the read data RDATA<127:0>.

[0055] Each of the first to 128 error correction units 230_0 to 230_127 can receive the corresponding read bit in sync with the first strobe signal IO_STB, selectively invert the received read bit in response to the corresponding error position bit, and output the received read bit as the corresponding bit in the bit of the error-corrected data CDATA<127:0> (hereinafter referred to as "error-corrected bit"). In the following description, since the first to 128 error correction units 230_0 to 230_127 have essentially the same configuration, the first error correction unit 230_0 will be used as an example.

[0056] The first error correction unit 230_0 may include an input unit 310 and a selective inversion unit 320. Furthermore, the first error correction unit 230_0 may include: a first inverter INV11 for inverting the first strobe signal IO_STB to generate a first inverted strobe signal IO_STBB; and a second inverter INV12 for inverting the first error position bit CORR. <0> To generate the first inverted error position bit CORRB <0> .exist Figure 5 In the diagram, the first inverter INV11 and the second inverter INV12 are shown as being included in the first error correction component 230_0. However, this embodiment is not limited to this. The first inverter INV11 and / or the second inverter INV12 may be located outside the first error correction component 230_0 and may be shared by other error correction components.

[0057] Input unit 310 can receive the first read bit RDATA synchronously with the first strobe signal IO_STB and the first inverted strobe signal IO_STBB. <0> To output internal data bits IDATA <0> Input unit 310 may include an even number of inverters, which buffer the first read bit RDATA according to the first strobe signal IO_STB and the first inverted strobe signal IO_STBB. <0> Output internal data bits IDATA <0> .

[0058] Selective inversion unit 320 can adjust the CORR based on the first error position bit. <0> And the first inverted error position bit CORRB <0> Selectively reverse the internal data bits IDATA <0> Output the first corrected bits CDATA <0> For example, when the first error bit is CORR. <0> When the bit becomes a high bit, the selective inversion unit 320 can invert the internal data bit IDATA. <0> Output the first error-corrected bits CDATA <0> When the first inverted error bit CORRB <0> When the bit becomes a high bit, the selective inversion unit 320 can output the internal data bit IDATA. <0> As the first bit after error correction, CDATA <0> .

[0059] In detail, the selective inversion unit 320 may include a third inverter INV13 and a transmission gate TG11.

[0060] The first error bit CORR is set in response to a logic high level (i.e., the high bit). <0> The first inverted error position bit CORRB of logic low level (i.e., low bit) <0> The third inverter, INV13, can invert the internal data bits IDATA. <0> To output the first error-corrected bits CDATA <0> The first inverted error position bit CORRB responds to a logic high level. <0> The first error bit CORR is set to the logic low level. <0> The transmission gate TG11 can transmit internal data bits IDATA <0> The output is the first error-corrected bit CDATA. <0> .

[0061] With the above configuration, one of the first to the 128th error correction units 230_0 to 230_127 is selected by the error position signal CORR<127:0>, and the read bits input to the selected error correction unit can be inverted (i.e., corrected) to be output as the corrected bits.

[0062] Figure 6 It is shown Figure 1 The circuit diagram of the error correction detection circuit 170.

[0063] refer to Figure 6 The error correction detection circuit 170 may include first to 128 detection components (i.e., detection logic) 170_0 to 170_127 corresponding to each read bit of the read data RDATA<127:0>.

[0064] The first to the 128th detection units 170_0 to 170_127 can be activated according to the on-chip ECC mode signal T_ECC_ONB. When the corresponding read bit is the target bit and the corresponding error position bit is a high bit, each of the first to the 128th detection units 170_0 to 170_127 can output the corresponding bit in the error correction detection signal MIS_CORR (hereinafter referred to as the "error correction detection bit") as a high bit. The target bit can be the bit in the target test pattern corresponding to the read bit. For example, when the target test pattern includes all zero bits, the target bit can be set to a low bit. In the following description, since the first to the 128th detection units 170_0 to 170_127 have basically the same configuration, the first detection unit 170_0 will be used as an example.

[0065] The first detection component 170_0 may include a NOR gate NR31, which is used to detect the first read bit RDATA. <0> The first inverted error position bit CORRB <0> The on-chip ECC mode signal T_ECC_ONB is used to perform a logical OR-NOT operation to output the first error correction detection bit MIS_CORR. <0> When the first bit RDATA is read... <0> The first inverted error position bit CORRB <0> When either the on-chip ECC mode signal T_ECC_ONB is at a logic high level, the first detection unit 170_0 can output the first error correction detection bit MIS_CORR at a logic low level. <0> Furthermore, when the first bit RDATA is read... <0> The first inverted error position bit CORRB <0> When all on-chip ECC mode signals T_ECC_ONB are at logic low, the first detection unit 170_0 can output the first error correction detection bit MIS_CORR at logic high. <0> .

[0066] In this case, when the first read bit RDATA <0> When a bit is detected as an error, the first inverted error position bit CORRB <0> It can be activated to a logic low level, thereby activating the first read bit RDATA. <0> Perform error correction. When the ECC engine 150 operates in test mode for the on-chip ECC scheme, the on-chip ECC mode signal T_ECC_ONB can be activated to a logic low level. Therefore, the first detection unit 170_0 is activated in test mode where the on-chip ECC scheme is applied, and when the first read bit RDATA... <0> The first read bit RDATA is at a logic low level (i.e., the target bit). <0> When performing error correction, the first error correction detection bit MIS_CORR is output as a high logic level. <0> .

[0067] With the above configuration, the first to the 128th detection units 170_0 to 170_127 can respectively detect the case where the corresponding read bit of the read data RDATA is not an error bit but has already performed error correction operation in the test mode of the on-chip ECC scheme, so as to generate the corresponding error correction detection bit of the error correction detection signal MIS_CORR.

[0068] Figure 7 It is shown Figure 1 The circuit diagram of the test output circuit 180.

[0069] See Figure 7 The test output circuit 180 may include a masking circuit 182 and a compression circuit 184.

[0070] The masking circuit 182 can generate 128-bit test data TDATA<127:0> by selectively masking the 128-bit error-corrected data CDATA<127:0> based on the 128-bit error correction detection signal MIS_CORR<127:0> in test mode.

[0071] Specifically, the masking circuit 182 may include first to 128 masking components (i.e., masking logic) 182_0 to 182_127 corresponding to the error-corrected bits, respectively.

[0072] The first to the 128th masking components 182_0 to 182_127 can be activated according to the test mode signal TEST_ENB. Each of the first to the 128th masking components 182_0 to 182_127 can selectively mask the corresponding erroneously corrected bits according to the corresponding erroneously corrected detection bits to output the corresponding bits in the test data TDATA<127:0> (hereinafter referred to as the "test bits"). In the following description, since the first to the 128th masking components 182_0 to 182_127 have essentially the same configuration, the first masking component 182_0 will be used as an example.

[0073] The first masking component 182_0 may include an inverter INV41 and a NOR gate NR41. The inverter INV41 can convert the first error-corrected bits CDATA <0> Inverting. The NOR gate NR41 can be used to invert the output of the inverter INV41 and the first error correction detection bit MIS_CORR. <0> The test mode signal TEST_ENB is used to perform a logical OR-NOT operation to output the first test bit TDATA. <0> When the first error correction detection bit MIS_CORR <0> When both the test mode signal TEST_ENB and the test mode signal TEST_ENB are at a low logic level, the first masking component 182_0 can transmit the first error-corrected bit CDATA. <0> The output is the first test bit TDATA. <0> On the other hand, when the first miscorrection detection bit MIS_CORR... <0> When either the test mode signal TEST_ENB or the test mode signal is at a logic high level, the first masking component 182_0 can transmit the first test bit TDATA. <0> It is fixed and output at a logic low level.

[0074] With the above configuration, each of the first to the 128th masking components 182_0 to 182_127 can be activated in test mode, and when the corresponding error correction detection bit is at a logic high level, the corresponding test bit is set to the target bit (i.e., logic low level), regardless of the logic level of the corresponding error-corrected bit.

[0075] Compression circuit 184 can compress 128 bits of test data TDATA<127:0> to output a 1-bit test result signal TOUT. Compression circuit 184 can output a test result signal TOUT indicating a pass to the test input / output line TGIO when all test bits of test data TDATA<127:0> are at logic low. For reference, in test mode, a pass can be determined when no error is detected or a detected error is corrected. Compression circuit 184 can also output a test result signal TOUT indicating a failure to the test input / output line TGIO when any test bit is at logic high. For example, the test result signal TOUT can be at logic high when the test result is pass, and at logic low when the test result is failure. Compression circuit 184 can be implemented using logic gates that perform XOR or XNOR operations to compare the test bits.

[0076] According to one embodiment, compression circuit 184 can compress 128-bit test data TDATA<127:0> into a predetermined bit unit (e.g., 32 bits) to output a test result signal TOUT. For example, compression circuit 184 can compress and... Figure 2 The test result signal TOUT is output by corresponding test bits to the data output from the first to fourth normal unit blocks MB0 to MB3, through compression and from Figure 2 The test result signal TOUT is output by compressing the test bits corresponding to the data output from normal unit blocks MB4 to MB7 (from the 13th to the 16th) and in this way, by compressing the test bits corresponding to the data output from normal unit blocks MB12 to MB15 (from the 13th to the 16th). In other words, the compression circuit 184 can group the unit blocks according to a predetermined number and output a test result signal TOUT corresponding to each test result of the grouped unit blocks. The compression circuit 184 can output each test result as a 4-bit test result signal TOUT at once, or output each test result as a 1-bit test result signal TOUT sequentially.

[0077] The following will refer to Figures 8 to 9D The operation for each situation is described according to embodiments of this disclosure.

[0078] Figure 8 It is a table used to describe the signal states for each situation according to embodiments of this disclosure. Figures 9A to 9D This is a diagram used to describe test operations for each situation according to embodiments of the present disclosure.

[0079] Reference Figure 8This will describe the application and non-application of the on-chip ECC solution in test mode and normal mode. Figure 1 The logic level of the signal. In the table, the reference number "#" can specify the number of bits of the corresponding data. For example, # can include integers from 0 to 127.

[0080] When the on-chip ECC scheme is applied in test mode, there are four types of error conditions. The first error condition "[1] No error" is when no error occurs in the read bit RDATA<#>, while the second error condition "(2) 1 bit error" is when an error occurs in the read bit RDATA<#> but the error has been corrected. The third error condition "[3] Uncorrected" and the fourth error condition "[4] Miscorrected" are when a multi-bit error of 2 bits or more occurs that exceeds the error correction capability of the error correction circuit 154. The third error condition "[3] Uncorrected" is when an error occurs in the read bit RDATA<#> when a multi-bit error has occurred but the error has not yet been corrected, while the fourth error condition "[4] Miscorrected" is when a miscorrection occurs because no error occurs in the read bit RDATA<#> but the read bit RDATA<#> has been corrected. In the first to fourth error conditions, the test mode signal TEST_ENB and the on-chip ECC mode signal T_ECC_ONB can both be activated to a logic low level.

[0081] First, in the first error case, the read bit RDATA<#> is at logic low, which is the target bit. Since no error has occurred, the error position detector 220 generates an error position bit CORR<#> corresponding to the read bit RDATA<#> at logic low. Therefore, the inverted error position bit CORRB<#> can be output at logic high.

[0082] refer to Figure 9AThe error correction component 230_# of the error corrector 230 can output the read bit RDATA<#> as the error-corrected bit CDATA<#> based on the logic low (L) level error position bit CORR<#>. When any of the read bit RDATA<#>, the inverted error position bit CORRB<#>, and the on-chip ECC mode signal T_ECC_ONB has a logic high (H) level, the detection component 170_# of the error correction detection circuit 170 can output the error correction detection bit MIS_CORR<#> with a logic low level. That is, the detection component 170_# can output the error correction detection bit MIS_CORR<#> with a logic low level based on the inverted error position bit CORRB<#> with a logic high level. The masking component 182_# of the masking circuit 182 can generate the test bit TDATA<#> by selectively masking the error-corrected bit CDATA<#> based on the error correction detection bit MIS_CORR<#>. In this case, the masking component 182_# can output the error-corrected bit CDATA<#> with a logic low level as the test bit TDATA<#> based on the error correction detection bit MIS_CORR<#> with a logic low level.

[0083] Next, in the second error case, the read bit RDATA<#>, which is the error bit, goes high. The error position detector 220 generates an error position bit CORR<#> corresponding to the high-level read bit RDATA<#>, so the inverted error position bit CORRB<#> can be output at a low level.

[0084] refer to Figure 9B The error correction unit 230_# can invert the error position bit CORR<#> based on the logic high level error location bit to read bit RDATA<#> and output the error-corrected bit CDATA<#> with a logic low level. The detection unit 170_# can output the error correction detection bit MIS_CORR<#> with a logic low level based on the read bit RDATA<#> with a logic high level. The masking unit 182_# can output the error-corrected bit CDATA<#> with a logic low level based on the error correction detection bit MIS_CORR<#> with a logic low level as the test bit TDATA<#>.

[0085] Next, in the third error case, the read bit RDATA<#> becomes logic high, serving as one of the error bits. When a multi-bit error occurs, because the number of error bits exceeds the error correction capability of the error correction circuit 154, the error location detector 220 generates an error location bit CORR<#> corresponding to the read bit RDATA<#> at a logic low level. Therefore, the inverted error location bit CORRB<#> can be output at a logic high level.

[0086] See Figure 9C The error correction unit 230_# can output the logic high-level read bit RDATA<#> as the corrected bit CDATA<#> based on the logic low-level error position bit CORR<#>. The detection unit 170_# can output the logic low-level error correction detection bit MIS_CORR<#> based on the logic high-level read bit RDATA<#> or the logic high-level inverted error position bit CORRB<#>. The masking unit 182_# can output the logic high-level error-corrected bit CDATA<#> as the test bit TDATA<#> based on the logic low-level error correction detection bit MIS_CORR<#>.

[0087] Next, in the fourth error case, the read bit RDATA<#> goes low because it is a normal read bit, not an error bit. When a false correction occurs, the read bit RDATA<#> is low, but the error position detector 220 malfunctions and generates the error position bit CORR<#> as a high level, corresponding to the normal read bit RDATA<#>. Therefore, the inverted error position bit CORRB<#> can be output as a low level.

[0088] refer to Figure 9D Error correction unit 230_# can read bit RDATA<#> by reversing the error position bit CORR<#> at a logic high level to output the error-corrected bit CDATA<#> at a logic high level. Detection unit 170_# can output the error correction detection bit MIS_CORR<#> at a logic high level by reading bit RDATA<#> at a logic low level and reversing the error position bit CORRB<#> at a logic low level. Masking unit 182_# can mask the error-corrected bit CDATA<#> at a logic high level by using the error correction detection bit MIS_CORR<#> at a logic high level to output the test bit TDATA<#> at a logic low level.

[0089] Subsequently, the compression circuit 184 can compress the 128-bit test data TDATA<127:0> to output the test result signal TOUT. For example... Figure 9A As described in the first error case, if no error occurs in the 128-bit read data RDATA<127:0>, the compression circuit 184 can output a test result signal TOUT to the test input / output line TGIO, indicating that the test result has passed. Therefore, all test bits have a logic low level. Furthermore, as... Figure 9B As described in the second error case, if an error occurs in one of the read bits RDATA<#> of the 128-bit read data RDATA<127:0> but the error has been corrected, the compression circuit 184 can output a test result signal TOUT to the test input / output line TGIO indicating that the test result has passed. Therefore, all test bits have a logic low level.

[0090] On the other hand, such as Figure 9C As described in the third error case, if a multi-bit error occurs during the reading of 128-bit data RDATA<127:0> and all erroneous bits are not corrected, then because the test bits corresponding to the uncorrected erroneous bits have a logic high level, the compression circuit 184 can output a test result signal TOUT indicating a test failure to the test input / output line TGIO. Furthermore, as... Figure 9D As described in the third error case, if a multi-bit error occurs in the 128-bit read data RDATA<127:0>, and a erroneous correction is performed on the normally read bits, the compression circuit 184 can output a test result signal TOUT to the test input / output line TGIO indicating that the test result has passed. In this case, when a predetermined number of cell blocks in all cell blocks are grouped and tested, a erroneous correction occurs but no actual error occurs. In this case, the masking circuit 182 can output all grouped test bits as logic low, and the compression circuit 184 can output a test result signal TOUT to the test input / output line TGIO indicating that the test result of the grouped cell blocks has passed. That is, in the embodiments of this disclosure, when an error correction operation is performed in test mode due to a erroneous correction by the on-chip ECC circuit when the read data does not contain erroneous bits, the test result can be forced to pass and an external device can be notified. Therefore, unnecessary repair operations can be prevented by preventing fault determination errors, thereby improving the yield.

[0091] In the above embodiments, the miscorrection detection circuit 170 and the masking circuit 182 have been described as having NOR gates, but the embodiments of this disclosure are not limited thereto. For example, the miscorrection detection circuit 170 and the masking circuit 182 may be formed by NAND gates, and in this case, the polarity (phase) of the input / output signals may be changed.

[0092] The following will refer to Figures 1 to 10 Parallel test operations of a memory device 100 according to embodiments of the present disclosure are described.

[0093] Figure 10 This is a flowchart describing a test operation of a memory device 100 according to an embodiment of the present disclosure.

[0094] refer to Figure 10 When a write command is input in test mode, a test write operation can be performed at operation S110. During the test write operation, the data input circuit 162 can buffer the external data DIO input to the global input / output line GIO and receive the buffered data as write data WDATA. The parity generation circuit 152 can use the write data WDATA transmitted from the data input circuit 162 to calculate the write parity bit WPTY. The normal write circuit 142 and the parity write circuit 144 can write the 128-bit write data WDATA and the 8-bit write parity bit WPTY to cell blocks MB0 to MB15 and MBECC, respectively. In this case, the write data WDATA provided in test mode can have a specific target test pattern. For example, the write data WDATA can consist of all zero bits.

[0095] According to one embodiment, the normal write circuit 142 and the parity write circuit 144 can set the write data WDATA and the write parity bit WPTY as the target test pattern (e.g., all zero bits) and write them into the normal cell area 112 and the parity cell area 114, respectively.

[0096] Next, when the read command is input, a test read operation can be performed at operation S120. During the test read operation, the normal read circuit 132 and the parity read circuit 134 can read 128 bits of read data RDATA and 8 bits of read parity bit RPTY from cell blocks MB0 to MB15 and MBECC.

[0097] Subsequently, the error correction circuit 154 can perform an error correction operation at operation S130. The error correction circuit 154 can output the error-corrected data CDATA by performing an error correction operation on the read data RDATA using the parity bit RPTY. The error correction circuit 154 can perform an error correction operation by inverting the error bits in the read bits of the read data RDATA.

[0098] The error correction detection circuit 170 can detect error correction in test mode at operation S140 to generate an error correction detection signal MIS_CORR. The error correction detection circuit 170 can generate the error correction detection signal MIS_CORR by detecting a situation where the data RDATA read in test mode does not contain error bits but an error correction operation has been performed on the read data RDATA.

[0099] The test output circuit 180 can mask the test result signal TOUT based on the error correction detection signal MIS_CORR at operation S150. The test output circuit 180 generates a test result signal TOUT corresponding to the error-corrected data CDATA when selectively masking the test result signal TOUT based on the error correction detection signal MIS_CORR. The test output circuit 180 can output the test result signal TOUT, indicating pass / fail, to the test input / output line TGIO.

[0100] While the invention has been described with reference to specific embodiments, those skilled in the art will understand that various changes and modifications can be made without departing from the spirit and scope of this disclosure as defined in the following claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A memory device, comprising: Normal cell region and parity check cell region; An error correction circuit performs an error correction operation on the read data output from the normal unit area based on the read parity bit output from the parity check unit area, so as to generate error-corrected data; A false correction detection circuit, comprising: detecting whether the error correction operation has been performed on the read data that does not contain error bits, to generate a false correction detection signal; and The test output circuit generates, in test mode, the test result signal corresponding to the corrected data when the test result signal is masked according to the error correction detection signal.

2. The memory device according to claim 1, in, The error correction circuit generates an error position signal based on the parity bit read, indicating the position of the erroneous bit in the read data, and performs the error correction operation on the read data according to the error position signal. The error correction detection circuit determines whether to perform the error correction operation on the read data based on the error location signal.

3. The memory device according to claim 2, wherein, When an error bit occurs in the read data that exceeds the error correction capability, the error correction circuit generates the error location signal for the normal bits of the read data other than the error bit.

4. The memory device according to claim 2, wherein, The error correction circuit includes: A code arithmetic unit that generates preliminary parity bits based on the read data; An error location detector, comprising: comparing the initial read parity bit with the read parity bit to generate the error location signal; and An error corrector performs the error correction operation on the read data based on the error location signal.

5. The memory device according to claim 2, in, The error correction detection circuit includes multiple detection logics, each corresponding to a read bit of the read data. Among them, each of the plurality of detection logics: when the corresponding read bit of the read bit is the target bit and the corresponding bit of the error position signal is the first bit, the corresponding bit of the miscorrection detection signal is output as the first bit.

6. The memory device according to claim 1, wherein, The test output circuit includes: A masking circuit, wherein, in the test mode, it selectively masks the error-corrected data according to the miscorrection detection signal to generate test data; and A compression circuit that compresses the test data to output the test result signal.

7. The memory device according to claim 6, in, The masking circuit includes multiple masking logics, each corresponding to a bit of the corrected data. When the test mode signal is activated, each of the plurality of masking logics selectively masks the corresponding error-corrected bits according to the corresponding bits of the error correction detection signal, so as to output the corresponding bits of the test data.

8. The memory device according to claim 7, wherein, Each of the plurality of masking logics: when the corresponding bit of the miscorrection detection signal is at a first logic level, the corresponding bit of the test data is set as the target bit, regardless of the logic level of the corresponding corrected bit.

9. The memory device according to claim 6, wherein, The compression circuit outputs a test result signal indicating that the test result is passed when all bits of the test data are target bits.

10. The memory device of claim 1, further comprising: A parity generation circuit that generates parity bits based on the written data; as well as The writing circuit writes the written data and the written parity bit into the normal cell area and the parity cell area, respectively.

11. The memory device of claim 10, wherein, In the test mode, the writing circuit: Receive the write data with the target test pattern and the write parity bit from an external source, or Set the written data and the written parity bit as the target test pattern.

12. A memory device, comprising: An error correction circuit, which: generates an error position signal based on reading parity bits to indicate the position of error bits in the read data; and performs an error correction operation on the read data according to the error position signal to generate error-corrected data; A false correction detection circuit, comprising: detecting, based on the read data and the error position signal, whether the error correction operation was performed on the read data that does not contain error bits, to generate a false correction detection signal; and The test output circuit generates, in test mode, the test result signal corresponding to the corrected data when the test result signal is masked according to the error correction detection signal.

13. The memory device according to claim 12, wherein, When an error bit occurs in the read data that exceeds the error correction capability, the error correction circuit generates the error location signal for the normal bits of the read data other than the error bit.

14. The memory device of claim 12, further comprising: A parity generation circuit that generates parity bits based on the written data; The writing circuit writes the written data and the written parity bit into the normal cell area and the parity cell area, respectively. as well as The reading circuit reads the parity check bit and the read data from the parity check unit area and the normal unit area, respectively.

15. A method for testing a memory device, the method comprising: Based on reading the parity bit, an error position signal is generated to indicate the position of the erroneous bit in the read data. Based on the error location signal, an error correction operation is performed on the read data to generate corrected data; Based on the read data and the error position signal, detect whether the error correction operation was performed on the read data that does not contain error bits, so as to generate a false correction detection signal; as well as The test result signal corresponding to the error-corrected data is generated when the test result signal is masked based on the error correction detection signal.

16. The test method according to claim 15, wherein, Generating the error location signal includes: When an error bit occurs in the read data that exceeds the error correction capability, an error position signal is generated for the normal bits of the read data other than the error bit.

17. The test method according to claim 15, wherein, Detecting whether the error correction operation was performed on the read data that does not contain the error bit includes: Whether the read data contains the error bit is determined by checking whether the read data is the target test pattern; and Determine whether the error correction operation has been performed based on the error location signal.

18. The test method according to claim 15, wherein, Generating the test result signal includes: Selectively mask the corrected data based on the miscorrection detection signal to generate test data; and The test data is compressed to output the test result signal.

19. The test method according to claim 18, in, The bits of the error correction detection signal, the bits of the error-corrected data, and the bits of the test data correspond one-to-one. The selective masking of the error-corrected data includes: When the corresponding bit of the error correction detection signal is at the first logic level, the corresponding bit of the test data is set as the target bit, regardless of the logic level of the corresponding bit of the corrected data.

20. The test method according to claim 15, further comprising: Generate write parity bits based on the written data; The written data and the written parity bit are written into the normal cell area and the parity cell area, respectively. as well as The parity check bit and the read data are read from the parity check unit area and the normal unit area, respectively.

21. The test method according to claim 20, wherein, Writing the write data and the write parity bit includes setting the write data and the write parity bit as a target test pattern.

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