A low mismatch ultra-wideband active balun
By employing a two-stage amplifier structure and cross-coupling capacitor technology in the active balun, the problem of large phase and gain errors in the bandwidth expansion process of existing active baluns is solved, realizing a compact and highly reliable differential signal conversion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NORTHWESTERN POLYTECHNICAL UNIV
- Filing Date
- 2026-01-28
- Publication Date
- 2026-05-12
AI Technical Summary
Existing active balun designs, while expanding the operating bandwidth, suffer from large phase and gain errors, increased circuit area, and high sensitivity to process deviations, making it difficult to meet the compact and high-reliability requirements of modern high-speed wireless communication systems.
A two-stage amplifier structure is adopted, in which the first stage uses a differential pair structure for signal conversion, and the second stage uses a positive feedback and voltage recovery structure for amplitude and phase balance. The equivalent transconductance of the transistor is enhanced by cross-coupling capacitors to cancel parasitic capacitance and reduce phase and gain mismatch.
It achieves smaller phase and gain mismatch, improves bandwidth and isolation, reduces circuit area, enhances common-mode rejection ratio and output matching, and stabilizes the phase and amplitude of the output signal.
Smart Images
Figure CN121602959B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to a low-mismatch ultrawideband active balun. Background Technology
[0002] In radio frequency (RF) transceiver systems, the receiver is one of the key modules. However, the transmitter typically emits a single-ended signal. To eliminate glitches and interference in the signal and enhance the system's control over common-mode signals, the receiver often employs a differential configuration. Compared to single-ended circuits, differential circuits can improve operating bandwidth, increase common-mode rejection ratio (CMRR), suppress even-order harmonic distortion, and enhance signal immunity. Furthermore, balun circuits can convert RF signals from single-ended to differential while providing the system with a certain level of gain, linearity, and better reverse isolation.
[0003] Baluns are divided into passive and active baluns. Due to non-ideal factors such as parasitic resistance, capacitance, dielectric loss, and electromagnetic loss, passive baluns have a certain insertion loss. Low-frequency passive baluns have a large area, which is not conducive to system integration and increases application costs. Active baluns are based on transistor active amplifiers, occupy a small area, are easy to integrate on-chip, and can provide a certain gain while converting signals. They are also easier to achieve wide bandwidth and impedance matching.
[0004] In existing active balun designs, to improve high-frequency gain compensation and suppress output amplitude and phase errors, a Chinese patent (CN114938206A) for a low-noise ultra-wideband active balun uses inductors for phase and gain compensation. However, this approach significantly increases the circuit area, reducing chip integration and increasing manufacturing costs. Furthermore, the parasitic effects of the inductor cause high-frequency performance degradation, and it is excessively sensitive to process variations. This approach severely restricts the urgent need for compact, high-reliability balun circuits in modern high-speed wireless communication systems.
[0005] Therefore, how to maintain small phase and gain errors while expanding the operating bandwidth of active baluns has become an urgent problem to be solved. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides a low-mismatch ultrawideband active balun. The technical problem to be solved by this invention is achieved through the following technical solution:
[0007] This invention provides a low-mismatch ultrawideband active balun, comprising: a first-stage amplifier and a second-stage amplifier arranged sequentially;
[0008] The first-stage amplifier adopts a differential pair structure to realize the conversion of single-ended signal to equal-amplitude inverted differential signal, eliminate the unbalanced signal of common-mode transmission, and thus obtain a balanced output signal;
[0009] The second-stage amplifier employs a positive feedback structure and a voltage recovery structure. The positive feedback structure reduces the phase and amplitude mismatch of the balanced output signal while expanding the bandwidth. The voltage recovery structure increases the amplitude of the input signal it receives, effectively increasing the transconductance and further stabilizing the phase and amplitude of the output signal to achieve amplitude-phase balance and output the amplified signal.
[0010] The voltage recovery structure includes:
[0011] The eighth NMOS transistor M8, the ninth NMOS transistor M9, the first capacitor C1, and the second capacitor C2;
[0012] The voltage recovery structure couples the voltage of the output node on the opposite side to the gates of the eighth NMOS transistor M8 and the ninth NMOS transistor M9 through the first capacitor C1 and the second capacitor C2, thereby enhancing the amplitude of the gate-source voltage of its internal transistors and increasing the equivalent transconductance of the eighth NMOS transistor M8 and the ninth NMOS transistor M9. At the same time, it cancels the gate-source parasitic capacitance of the internal transistors at high frequencies.
[0013] The beneficial effects of this invention are:
[0014] In the solution provided by this invention, the low-mismatch ultrawideband active balun employs a two-stage structure to increase isolation and reduce the impact of the subsequent load on the preceding stage. The first-stage amplifier uses a differential structure, possessing excellent common-mode rejection ratio and good output matching. The second-stage amplifier, through positive feedback, reduces phase and amplitude mismatch, achieving amplitude-phase balance. Furthermore, the positive feedback increases the operating speed of the second-stage amplifier, thereby increasing the bandwidth. Further, this invention introduces cross-coupling capacitors to increase the gate-source signal amplitudes of the eighth and ninth NMOS transistors, achieving equivalent transconductance amplification. At high frequencies, this also cancels parasitic capacitance, further reducing the phase and gain mismatch of the active balun and stabilizing the phase and amplitude of the output signal. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of a low-mismatch ultrawideband active balun provided in an embodiment of the present invention;
[0016] Figure 2 This is a simulation curve of the gain error of a low-mismatch ultrawideband active balun provided in an embodiment of the present invention;
[0017] Figure 3 The simulation curve of phase error of a low-mismatch ultrawideband active balun provided in the embodiment of the present invention is shown. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0019] This invention provides a low-mismatch ultrawideband active balun, such as... Figure 1 As shown, it may include:
[0020] The first-stage amplifier and the second-stage amplifier are set sequentially;
[0021] The first-stage amplifier uses a differential pair structure to convert a single-ended signal into a differential signal with equal amplitude and inverted phase, eliminating the unbalanced signal of common-mode transmission, thereby obtaining a balanced output signal.
[0022] The second-stage amplifier employs a positive feedback structure and a voltage recovery structure. The positive feedback structure reduces the phase and amplitude mismatch of the balanced output signal while expanding the bandwidth. The voltage recovery structure increases the amplitude of the input signal it receives, effectively increasing the transconductance and further stabilizing the phase and amplitude of the output signal to achieve amplitude and phase balance, resulting in an amplified output signal.
[0023] Voltage recovery structures may include:
[0024] The eighth NMOS transistor M8, the ninth NMOS transistor M9, the first capacitor C1, and the second capacitor C2;
[0025] The voltage recovery structure couples the voltage of the output node on the opposite side to the gates of the eighth NMOS transistor M8 and the ninth NMOS transistor M9 through the first capacitor C1 and the second capacitor C2, thereby enhancing the amplitude of the gate-source voltage of its internal transistors and thus enhancing the equivalent transconductance of the eighth NMOS transistor M8 and the ninth NMOS transistor M9. At the same time, it cancels the gate-source parasitic capacitance of the internal transistors at high frequencies.
[0026] The low-mismatch ultrawideband active balun provided in this embodiment of the invention adopts a two-stage structure to increase isolation and reduce the impact of the load of the subsequent stage on the preceding stage. The first-stage amplifier adopts a differential structure, which has excellent common-mode rejection ratio and good output matching. The second-stage amplifier reduces phase and amplitude mismatch through positive feedback, and completes amplitude and phase balance. In addition, the positive feedback structure improves the operating speed of the second-stage amplifier, thereby increasing the bandwidth.
[0027] First-stage amplifier, such as Figure 1 As shown, it may include:
[0028] First NMOS transistor M1, second NMOS transistor M2, third NMOS transistor M3, first resistor R1, second resistor R2;
[0029] The source of the first NMOS transistor M1 is connected to the drain of the third NMOS transistor M3, the gate is connected to the input signal, and the drain of the first NMOS transistor M2 is connected to the drain of the second NMOS transistor M2 as the differential output terminal of the first stage amplifier.
[0030] The source of the second NMOS transistor M2 is connected to the drain of the third NMOS transistor M3, and the gate is grounded;
[0031] The source of the third NMOS transistor M3 is grounded, and its gate is connected to a fixed voltage V. B ;
[0032] The first end of the first resistor R1 is connected to the power supply voltage, and the second end is connected to the drain of the first NMOS transistor M1.
[0033] The first end of the second resistor R2 is connected to the power supply voltage, and the second end is connected to the drain of the second NMOS transistor M2.
[0034] Understandably, compared to traditional active baluns, the first-stage amplifier in the active balun provided in this embodiment of the invention adopts a differential structure, which ultimately realizes the conversion of single-ended signals to equal-amplitude inverted differential signals. Due to the elimination of common-mode unbalanced transmission by the differential structure, a completely balanced output signal can be obtained.
[0035] Second stage amplifier, such as Figure 1 As shown, it may include:
[0036] Fourth NMOS transistor M4, fifth NMOS transistor M5, sixth NMOS transistor M6, seventh NMOS transistor M7, eighth NMOS transistor M8, ninth NMOS transistor M9, tenth NMOS transistor M 10 The third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the first capacitor C1, and the second capacitor C2;
[0037] The source of the fourth NMOS transistor M4 is grounded, and its gate is connected to a fixed voltage V. B The drain is connected to the source of the fifth NMOS transistor M5;
[0038] The source of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6, and the gate of the sixth NMOS transistor M6 serves as the differential input terminal of the second-stage amplifier. The drain is connected to the source of the seventh NMOS transistor M7, the source of the eighth NMOS transistor M8, and the first terminal of the first capacitor C1, respectively.
[0039] The drain of the sixth NMOS transistor M6 is connected to the source of the ninth NMOS transistor M9 and the tenth NMOS transistor M6, respectively. 10 The source of the capacitor is connected to the first terminal of the second capacitor C2;
[0040] The gate of the seventh NMOS transistor M7 is connected to the gate of the tenth NMOS transistor M 10 The gate of the seventh NMOS transistor M7 serves as the differential output terminal of the second-stage amplifier. The gate of the seventh NMOS transistor M7 is connected to the drain of the ninth NMOS transistor M9 and the tenth NMOS transistor M10, respectively. 10 The drain of the first resistor is connected to the first terminal of the fourth resistor R4, and the drain is connected to the drain of the eighth NMOS transistor M8 and the tenth NMOS transistor M10, respectively. 10 The gate and the first end of the third resistor R3 are connected;
[0041] The gate of the eighth NMOS transistor M8 is connected to the first terminal of the fifth resistor R5 and the second terminal of the second capacitor C2, respectively.
[0042] The gate of the ninth NMOS transistor M9 is connected to the first terminal of the sixth resistor R6 and the second terminal of the first capacitor C1, respectively.
[0043] The second terminal of the third resistor R3 is connected to the power supply voltage;
[0044] The second terminal of the fourth resistor R4 is connected to the power supply voltage;
[0045] The second terminal of the fifth resistor R5 is connected to the second terminal of the sixth resistor R6, and a fixed voltage V is applied. B .
[0046] The second-stage amplifier employs a positive feedback structure and a voltage recovery structure. The positive feedback structure reduces phase and amplitude mismatch in the balanced output signal while expanding the bandwidth. The voltage recovery structure increases the amplitude of the received input signal through source voltage recovery, effectively increasing the transconductance and further stabilizing the phase and amplitude of the output signal to achieve amplitude-phase balance and output the amplified signal. The second-stage amplifier also acts as a unity-gain voltage buffer, isolating the load of the subsequent stage from the preceding stage and ensuring the symmetry of the differential signal.
[0047] In the second-stage amplifier, the seventh NMOS transistor M7 and the tenth NMOS transistor M 10 This forms a positive feedback structure.
[0048] Positive feedback reduces the phase and amplitude mismatch of the output signal while expanding the bandwidth. The increase in gate-source voltage increases the equivalent transconductance of the eighth NMOS transistor M8 and the ninth NMOS transistor M9, further stabilizing the phase and amplitude of the output signal.
[0049] This invention increases the gate-source voltage difference between the eighth and ninth NMOS transistors by introducing a cross-coupling capacitor, thus achieving voltage recovery. In the voltage recovery structure, the first capacitor C1 and the second capacitor C2 constitute the cross-coupling capacitor. By introducing the cross-coupling capacitor, the amplitude of the gate-source voltage of the eighth NMOS transistor M8 and the ninth NMOS transistor M9 is increased. This achieves current doubling while keeping the transconductance of the eighth and ninth NMOS transistors constant, and simultaneously cancels the gate-source parasitic capacitance of the eighth and ninth NMOS transistors M8 and M9 at high frequencies. Optionally, signals with frequencies above 5 GHz are considered high-frequency signals. It is understood that the positive feedback and the cross-coupling capacitor do not form a unity-gain buffer; they cannot be interchanged as the first-level load and function as the second-stage load. The function of the cross-coupling capacitor is to increase the AC gain by doubling the AC input voltage without changing the circuit power consumption, transistor bias, or size (i.e., keeping the transconductance constant), without increasing the transistor gate voltage or transconductance.
[0050] The low-mismatch ultrawideband active balun couples the voltage of the output node on the opposite side to the gates of the eighth NMOS transistor M8 and the ninth NMOS transistor M9 through the first capacitor C1 and the second capacitor C2. When the output signal changes, it increases the transient gate-source voltage, further increasing the equivalent transconductance of the eighth NMOS transistor M8 and the ninth NMOS transistor M9.
[0051] In this low-mismatch ultrawideband active balun, when the V output of the differential output terminal OUTP is... OUTP When the voltage increases by ΔV, the tenth NMOS transistor M 10 The gate voltage increases, causing the tenth NMOS transistor M... 10 The increased drain current further pulls down the V output at the differential output terminal OUTN through the fourth resistor R4. OUTN Voltage, the original V OUTP The rise leads to V OUTN The decrease amplifies the differential signal, forming positive feedback. The analysis of the seventh NMOS transistor M7 is similar.
[0052] This low-mismatch ultrawideband active balun improves bandwidth and affects differential balance through a positive feedback structure.
[0053] When there is no seventh NMOS transistor M7 and tenth NMOS transistor M 10 The bandwidth is limited by the RC time constant of the output impedance and parasitic capacitance. ,in, This indicates the 3dB bandwidth of the active balun. Indicates the output resistance. This indicates the output capacitor.
[0054] The seventh NMOS transistor M7 and the tenth NMOS transistor M 10 It can provide some current at high frequencies to offset the phase delay caused by parasitic capacitance.
[0055] ; ;
[0056] ;
[0057] in, This represents the sum of the seventh and eighth impedances. This indicates the transconductance of the eighth NMOS transistor M8. This indicates the transconductance of the seventh NMOS transistor M7. This represents the sum of the ninth and tenth impedances. Indicates the tenth NMOS transistor M 10 transconductance, This represents the equivalent 3dB bandwidth of an active balun. This represents the total impedance of the second-stage amplifier.
[0058] Therefore, the positive feedback structure increases the equivalent transconductance, enhances the high-frequency driving capability of the circuit, and directly improves the bandwidth by 3dB.
[0059] Phase mismatch is reduced through a positive feedback structure:
[0060] When V OUTP Because parasitic delays cause phase lag, the positive feedback path will automatically compensate for this delay, and vice versa.
[0061] The positive feedback structure reduces the magnitude mismatch:
[0062] In the second-stage amplifier, if the gain of the left-side circuit is lower due to manufacturing process differences, then V OUTP It will be less than V OUTN Because of V OUTP Smaller, the drain current in the right branch decreases, resulting in V OUTN The increase makes the feedback of the seventh NMOS transistor M7 stronger, so the left branch is compensated, and the gain on both sides is automatically balanced instead of deviating further, thus reducing the amplitude mismatch.
[0063] Understandably, the positive feedback structure in this low-mismatch ultrawideband active balun is not a traditional static positive feedback structure. Instead, it is used to change the equivalent impedance characteristics of the output node under wideband conditions. Under differential-mode conditions, the positive feedback structure enhances the equivalent transconductance, making the output node present a more efficient impedance. Under common-mode conditions, the positive feedback structure suppresses common-mode components and expands the effective operating bandwidth. Even if the feedback signal acts on the output-dependent node, under small-signal conditions, this structure will not cause system instability.
[0064] The cross-coupling capacitors C1 and C2 provided in this embodiment of the invention couple the voltage of the opposite output node to the transistor gate. When the output signal changes, they increase the transient gate-source voltage, further improving the equivalent transconductance of the transistor. In traditional RF amplifiers, cross-coupling capacitors are used to neutralize the drain capacitance of the transistor, maintaining linear signal amplification, and a feedback path exists. In this embodiment of the invention, cross-coupling capacitors are used to recover the source voltage, rapidly inverting the voltages on both sides in the time domain. Furthermore, these capacitors connect the source and gate terminals of the transistor, not the drain and gate terminals as in other RF circuits, thus eliminating the feedback path. Their functions are fundamentally different.
[0065] Cross-coupling capacitors can effectively increase the equivalent transconductance of transistors, eliminate gate-source parasitic capacitance, and improve operating bandwidth.
[0066] After adding a cross-coupling capacitor, Node change rate The current is amplified by the capacitor, and the amplified current is then fed by the seventh NMOS transistor M7 and the tenth NMOS transistor M... 10 Feedback is then provided again. Therefore, through the first capacitor C1 and the second capacitor C2, the voltage change at the opposite output node is coupled more rapidly to the transistor gate, causing its current to change faster. Furthermore, the cross-coupling capacitors provide an equivalent negative capacitance, offsetting the parasitic capacitance of the output node and increasing the operating bandwidth. When the output signal changes, the changing signal is injected into the gate of the opposite transistor, increasing the transient gate-source voltage and further improving the transistor's equivalent transconductance. This represents the current flowing through the eighth NMOS transistor M8. This indicates the voltage of the ninth NMOS transistor M9. This indicates the voltage of the eighth NMOS transistor M8.
[0067] The following simulation experiment is conducted on the low-mismatch ultrawideband active balun provided in the embodiment of the present invention to verify the beneficial effects of the low-mismatch ultrawideband active balun.
[0068] The simulation experimental components of this invention employ SMIC 130nm CMOS technology, and a simulation circuit for a low-mismatch ultrawideband active balun is built based on the Cadence IC618 simulation experimental platform. The Spectre RF simulation tool is used to simulate the circuit of the low-mismatch ultrawideband active balun, with a given supply voltage V. DD It has a voltage of 1.8V and an operating temperature of 27 degrees Celsius.
[0069] Simulation 1: Under the above operating conditions, the low-mismatch ultrawideband active balun is simulated and verified. The simulation curve of the gain error of the low-mismatch ultrawideband active balun is shown in the figure below. Figure 2 As shown, Figure 2 The horizontal axis represents the frequency scanning range in GHz, and the vertical axis represents the output signal phase error value in degrees. In the simulation, the operating frequency of the active balun circuit was set to 0-8 GHz, and the phase error was obtained by subtracting the phases of the two differential output ports. Figure 2 As can be seen, the maximum deviation of the phase error is 0.06°.
[0070] Simulation 2: Under the above operating conditions, current mismatch simulation was performed on the low-mismatch ultra-wideband active balun. The simulated phase error curve of the low-mismatch ultra-wideband active balun is shown in the figure below. Figure 3 As shown, Figure 3 The horizontal axis in the graph represents the frequency scanning range, in GHz. Figure 3 The vertical axis represents the output signal gain error value, in dB. During the simulation, the operating frequency of the active balun circuit was set to 0. At 8GHz, the gain error is obtained by subtracting the gains of the two differential output ports. From Figure 3 As can be seen, the gain error between the two output ports is less than 0.2dB.
[0071] Figure 2 and Figure 3 Simulation results show that the two output signals obtained by the low-mismatch ultrawideband active balun have good differential performance and can effectively realize the basic function of converting signals from single-ended to dual-ended.
[0072] The low-mismatch ultrawideband active balun provided in this embodiment of the invention employs a two-stage structure to increase isolation and reduce the impact of the subsequent stage load on the preceding stage. The first-stage amplifier uses a differential structure, possessing excellent common-mode rejection ratio and good output matching. The second-stage amplifier, through positive feedback, reduces phase and amplitude mismatch, achieving amplitude-phase balance. Furthermore, the positive feedback increases the operating speed of the second-stage amplifier, thereby increasing the bandwidth. Further, by introducing cross-coupling capacitors, this invention increases the gate-source signal amplitude of the eighth and ninth NMOS transistors, achieving equivalent transconductance amplification. This also cancels parasitic capacitance at high frequencies, further reducing the phase and gain mismatch of the active balun and stabilizing the phase and amplitude of the output signal.
[0073] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0074] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A low-mismatch ultrawideband active balun, characterized in that, include: The first-stage amplifier and the second-stage amplifier are set sequentially; The first-stage amplifier adopts a differential pair structure to realize the conversion of single-ended signal to equal-amplitude inverted differential signal, eliminate the unbalanced signal of common-mode transmission, and thus obtain a balanced output signal; The second-stage amplifier employs a positive feedback structure and a voltage recovery structure. The positive feedback structure reduces phase and amplitude mismatch in the balanced output signal while expanding the bandwidth. The voltage recovery structure increases the amplitude of the received input signal, effectively increasing the transconductance and further stabilizing the phase and amplitude of the output signal to achieve amplitude-phase balance and output the amplified signal. In the second-stage amplifier, the seventh NMOS transistor M7 and the tenth NMOS transistor M... 10 This constitutes a positive feedback structure; The voltage recovery structure includes: The eighth NMOS transistor M8, the ninth NMOS transistor M9, the first capacitor C1, and the second capacitor C2; The voltage recovery structure couples the voltage of the output node on the opposite side to the gates of the eighth NMOS transistor M8 and the ninth NMOS transistor M9 through the first capacitor C1 and the second capacitor C2, thereby enhancing the amplitude of the gate-source voltage of its internal transistors and thus enhancing the equivalent transconductance of the eighth NMOS transistor M8 and the ninth NMOS transistor M9. At the same time, it cancels the gate-source parasitic capacitance of the internal transistors at high frequencies. In the voltage recovery structure, the first capacitor C1 and the second capacitor C2 constitute a cross-coupling capacitor. By introducing the cross-coupling capacitor, the amplitude of the gate-source voltage of the eighth NMOS transistor M8 and the ninth NMOS transistor M9 is increased. With the transconductance of the eighth NMOS transistor and the ninth NMOS transistor remaining unchanged, the current is doubled, and the gate-source parasitic capacitance of the eighth NMOS transistor M8 and the ninth NMOS transistor M9 is canceled at high frequency. The source of the seventh NMOS transistor M7 is connected to the source of the eighth NMOS transistor M8 and the first terminal of the first capacitor C1, respectively. Its gate is connected to the drain of the ninth NMOS transistor M9 and the tenth NMOS transistor M1, respectively. 10 The drain is connected to the drain of the eighth NMOS transistor M8 and the drain of the tenth NMOS transistor M10, respectively. 10 The gate connection of the seventh NMOS transistor M7 is connected to the gate of the tenth NMOS transistor M1. 10 The gate of the second stage amplifier is used as the differential output terminal; The tenth NMOS transistor M 10 The source of the capacitor is connected to the source of the ninth NMOS transistor M9 and the first terminal of the second capacitor C2, respectively.
2. The low-mismatch ultrawideband active balun according to claim 1, characterized in that, The first stage amplifier includes: First NMOS transistor M1, second NMOS transistor M2, third NMOS transistor M3, first resistor R1, second resistor R2; The source of the first NMOS transistor M1 is connected to the drain of the third NMOS transistor M3, the gate is connected to the input signal, and the drain of the first NMOS transistor M2 is connected to the drain of the second NMOS transistor M2 as the differential output terminal of the first stage amplifier. The source of the second NMOS transistor M2 is connected to the drain of the third NMOS transistor M3, and the gate is grounded; The source of the third NMOS transistor M3 is grounded, and its gate is connected to a fixed voltage V. B ; The first end of the first resistor R1 is connected to the power supply voltage, and the second end is connected to the drain of the first NMOS transistor M1; The first end of the second resistor R2 is connected to the power supply voltage, and the second end is connected to the drain of the second NMOS transistor M2.
3. The low-mismatch ultrawideband active balun according to claim 1, characterized in that, The second stage amplifier includes: Fourth NMOS transistor M4, fifth NMOS transistor M5, sixth NMOS transistor M6, seventh NMOS transistor M7, eighth NMOS transistor M8, ninth NMOS transistor M9, tenth NMOS transistor M 10 The third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the first capacitor C1, and the second capacitor C2; The source of the fourth NMOS transistor M4 is grounded, and its gate is connected to a fixed voltage V. B The drain is connected to the source of the fifth NMOS transistor M5; The source of the fifth NMOS transistor M5 is connected to the source of the sixth NMOS transistor M6, and the gate of the sixth NMOS transistor M6 serves as the differential input terminal of the second stage amplifier. The drain is connected to the source of the seventh NMOS transistor M7, the source of the eighth NMOS transistor M8, and the first terminal of the first capacitor C1, respectively. The drain of the sixth NMOS transistor M6 is connected to the source of the ninth NMOS transistor M9 and the tenth NMOS transistor M6, respectively. 10 The source and the first terminal of the second capacitor C2 are connected; The gate of the seventh NMOS transistor M7 is connected to the gate of the tenth NMOS transistor M 10 The gate of the seventh NMOS transistor M7 serves as the differential output terminal of the second-stage amplifier. The gate of the seventh NMOS transistor M7 is connected to the drain of the ninth NMOS transistor M9 and the tenth NMOS transistor M10, respectively. 10 The drain of the first resistor is connected to the first terminal of the fourth resistor R4, and the drain is connected to the drain of the eighth NMOS transistor M8 and the tenth NMOS transistor M10, respectively. 10 The gate and the first end of the third resistor R3 are connected; The gate of the eighth NMOS transistor M8 is connected to the first terminal of the fifth resistor R5 and the second terminal of the second capacitor C2, respectively. The gate of the ninth NMOS transistor M9 is connected to the first terminal of the sixth resistor R6 and the second terminal of the first capacitor C1, respectively. The second terminal of the third resistor R3 is connected to the power supply voltage; The second terminal of the fourth resistor R4 is connected to the power supply voltage; The second terminal of the fifth resistor R5 is connected to the second terminal of the sixth resistor R6, and a fixed voltage V is applied. B .