Clock recovery mode and circuit for low-speed communication and communication system
By utilizing the sampling units of the sampling clock and counter in low-speed communication, clock recovery is achieved based on the transition edge characteristics of the code. This solves the problems of high cost and low speed caused by multiple CDR links in the existing technology, and achieves low-cost and high-speed clock recovery effect, which is suitable for low-end domestic chips.
Patent Information
- Application Number
- CN202411144284.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2026-03-03
AI Technical Summary
In existing technologies, low-speed communication involves a number of clock data recovery (CDR) steps, resulting in high circuit processing costs, slow processing speeds, and difficulty in implementing it using domestically produced chips.
The sampling unit, which uses a sampling clock and a counter, achieves frequency locking and clock recovery by utilizing the edge characteristics of the data signal, eliminating the need for phase detection, phase locking, low-frequency oscillation, compensation, and other steps. It extracts the clock signal by using the clock embedded in Manchester encoding, 1B/4B encoding, CMI encoding, and C37.94 protocol encoding.
It reduces clock recovery costs, simplifies circuit flow, improves processing speed, and can be implemented using low-end domestic chips such as CPLD and FPGA.
Smart Images
Figure CN121602991A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic communication technology, and more specifically to a clock recovery method, circuit, and communication system for low-speed communication. Background Technology
[0002] In the field of electronic communication technology, when a signal is transmitted over a certain distance, especially over long distances, the waveform of the signal will be distorted to a certain extent, so that the receiving end cannot obtain the data we need. At this time, the signal needs to be regenerated, which includes re-amplification, reshaping, and retiming. Retiming refers to clock data recovery (CDR).
[0003] In the prior art, clock data recovery (CDR) includes at least phase detection, feedback, and compensation. For example, authorized patent CN118100915B discloses a CDR circuit, which includes a frequency discriminator, a first circuit module, a charge pump, a low-pass filter, a voltage-controlled oscillator, and other devices. It realizes clock signal recovery through phase detection and phase-locked loop working principles.
[0004] For communication technology fields such as low-speed E1 systems, existing clock data recovery (CDR) involves many steps, resulting in high circuit processing costs and slow processing speeds. At the same time, it is difficult to implement clock data recovery (CDR) using domestically produced chips. Summary of the Invention
[0005] This invention addresses the technical problems of high cost and long recovery process in existing phase detection and phase-locked loop clock data recovery (CDR) technologies by providing a clock recovery method for low-speed communication, which has advantages such as good localization, low cost, simple recovery process, and low latency.
[0006] First aspect
[0007] This invention provides a clock recovery method for low-speed communication, comprising:
[0008] S1. Configure a sampling unit according to the data signal to be input. The sampling unit includes a sampling clock and a counter. The clock frequency of the sampling clock is 2N times the clock frequency of the data signal, and the counter has a counting function of 2N numbers.
[0009] S2. Receive the data signal;
[0010] S3. Align the sampling clock with the data signal, and increment the counter by 1 at intervals of 1 / 2N of the clock period of the data signal:
[0011] S4. During the auto-incrementing process of the counter, the following operation is triggered according to the conditions:
[0012] When the encoding of the data signal has a rising edge, the counter is cleared to zero and the output recovery clock is set to low level.
[0013] When the count reaches N, the recovery clock is set to high.
[0014] When the count reaches 2N, the counter is reset to zero, and the recovery clock is set to low.
[0015] S5. Align the recovery clock with the data signal and output the recovery signal;
[0016] Where N is a positive integer greater than 1.
[0017] Specifically, one of the main concepts of this invention is based on the characteristic that the encoding in low-speed communication has sufficient transition edges. By using a sampling unit with a sampling clock and a counter, frequency locking and clock recovery of data signals are realized. This eliminates the need for phase detection, phase locking, low-frequency oscillation, compensation and other links required in the existing CDR (clock recovery technology), thereby reducing the cost of clock recovery.
[0018] It is worth understanding that Manchester encoding, 1B / 4B encoding, CMI encoding, and C37.94 protocol encoding are commonly used in low-speed communication. These encodings share the characteristic of avoiding long consecutive coded 1s or coded 0s, thus allowing for a sufficient number of transitions in the encoded signal. Furthermore, these encoding methods embed the clock signal within the encoding. Additionally, a short level in these codes contains at least one embedded clock signal, while a long level contains at least one or more embedded clock signals. Therefore, the concept of this invention is based on these characteristics of encoding by providing a sampled clock with a counter. By combining the sampled clock with the counter, the clock signal embedded in the encoding is extracted, thereby achieving clock recovery for these low-speed communication systems.
[0019] The data signal is a communication signal received after long-distance transmission, and the sampling clock is a high-frequency sampling signal.
[0020] Furthermore, the value of N is between 10 and 25.
[0021] Specifically, the higher the multiple of the sampling clock frequency compared to the data signal clock frequency, the more accurate the clock extraction. It can be understood that as the multiple of the sampling clock increases, the sampling interval becomes shorter, thus resulting in more accurate extraction of the embedded clock of the data signal.
[0022] Furthermore, the data signal is transmitted through a communication system with communication coding having a transition edge;
[0023] The communication encoding is any one of Manchester encoding, 1B / 4B encoding, CMI encoding, or C37.94 encoding.
[0024] Specifically, the present invention has better implementation effects for communication systems with communication codes that have transition edges.
[0025] Furthermore, in the E1 communication system using Manchester encoding, the clock frequency is 2.048MHz;
[0026] When N is 10, the sampling clock frequency is 40.96MHz and the counter count is 20.
[0027] Second aspect
[0028] The present invention provides a clock recovery circuit for low-speed communication, the clock recovery circuit including a clock recovery method for low-speed communication as provided in any embodiment of the first aspect.
[0029] Optionally, the clock recovery circuit includes an input terminal, an output terminal, and a sampling clock. The input terminal is used to acquire a data signal, the sampling clock is used to extract a recovery clock based on the data signal, and the output terminal is used to output a recovery signal based on the data signal and the recovery clock.
[0030] Third aspect
[0031] The present invention provides a clock recovery chip for low-speed communication, the clock recovery chip comprising the clock recovery circuit for low-speed communication provided in any embodiment of the second aspect.
[0032] Specifically, the working principle of the clock recovery circuit provided by this invention is relatively simple and can be implemented using low-end domestic chips, such as CPLD and FPGA.
[0033] Fourth aspect
[0034] The present invention provides a clock recovery communication system for low-speed communication, including a clock recovery circuit for low-speed communication as provided in any embodiment of the second aspect or a clock recovery chip for low-speed communication as provided in any embodiment of the third aspect.
[0035] In summary, the present invention provides a clock recovery method, circuit, and communication system for low-speed communication, which has at least the following advantages:
[0036] 1. Based on the characteristic that the encoding in low-speed communication has sufficient transition edges, this invention utilizes a sampling unit with a sampling clock and a counter to realize frequency locking and clock recovery of data signals, eliminating the need for phase detection, phase locking, low-frequency oscillation, compensation, and other steps required in the existing CDR (clock recovery technology), thus reducing the cost of clock recovery.
[0037] 2. The clock recovery circuit provided by the invention has a relatively simple working principle and can be implemented using low-end domestic chips, such as CPLD and FPGA, which effectively reduces the cost of circuits and chips. Attached Figure Description
[0038] The present invention will be further described in detail below with reference to the accompanying drawings and preferred embodiments. However, those skilled in the art will understand that these drawings are drawn only for the purpose of explaining the preferred embodiments and therefore should not be construed as limiting the scope of the invention. Furthermore, unless specifically indicated, the drawings are only schematic representations of the composition or structure of the described objects and may contain exaggerated depictions, and the drawings are not necessarily drawn to scale.
[0039] Figure 1 A flowchart illustrating a clock recovery method for low-speed communication provided in this embodiment of the invention;
[0040] Figure 2 A schematic diagram illustrating the working principle of a clock recovery method for low-speed communication provided in this embodiment of the invention (taking Manchester code as an example);
[0041] Figure 3 A flowchart illustrating a clock recovery method for low-speed communication provided in one embodiment of the present invention;
[0042] Figure 4 This invention provides a schematic diagram of a clock recovery circuit for low-speed communication. Detailed Implementation
[0043] The following is in conjunction with the appendix Figures 1 to 4 The present invention will be described in detail below.
[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0045] The main concept of this invention is to provide a method for transmitting data signals with sufficient transition edges during low-speed communication. By combining a high-frequency sampling clock with the use of a counter, frequency locking and clock recovery of the data signal are achieved. This eliminates the need for phase detection, phase locking, low-frequency oscillation, compensation, and other steps required in existing CDR (clock recovery technology), thereby reducing clock recovery costs, shortening the clock recovery process, and reducing signal transmission delay.
[0046] Please see Figure 1 The diagram shown is a flowchart of a clock recovery method for low-speed communication provided by an embodiment of the present invention.
[0047] Specifically, the clock recovery of the present invention includes at least the following: Figure 1 Steps S1-S5 are shown.
[0048] Step S1 configures a sampling unit based on the input data signal. The sampling unit includes a sampling clock and a counter. The sampling clock frequency is 2N times the clock frequency of the data signal. The counter increments by 1 at intervals of 1 / 2N of the clock cycle of the data signal. It is understood that within one clock cycle of the data signal, the sampling clock completes 2N clock cycles, and within those 2N clock cycles, the counter counts once and increments by 1 every other clock cycle.
[0049] Optionally, low-speed communication systems such as the E1 communication system employ Manchester encoding, with a clock frequency of 2.048 MHz (megahertz), corresponding to a period of approximately 488.28 ns (nanoseconds). In this case, the clock frequency of the sampling clock is 2N times the frequency of the data signal, i.e., the clock frequency of the sampling clock is 2N * 2.048 MHz.
[0050] In step S2, the transmitted data signal is received.
[0051] Furthermore, in step S3, the counter increments by 1 at intervals of 1 / 2N of the clock cycle of the data signal.
[0052] It is understood that within one period of the data signal, 488.28 ns, the counter completes the counting of 2N numbers. This is because the clock frequency of the sampling clock is 2N times the clock frequency of the data signal, resulting in a period of 1 / 2N. The counter can then count exactly 2N numbers; that is, within one period of the data signal, 488.28 ns, the counter can complete the counting of 2N numbers according to the frequency change of the sampling clock.
[0053] Optionally, the counting range of the counter is 0 to 2N-1.
[0054] In order to restore the clock of the data signal, the counter does not simply count in a loop, but counts according to different conditions in different counting cycles. That is, the counter in step S4 includes at least the following triggering operations:
[0055] ① When a transition edge occurs in the encoding of the data signal, the counter is cleared and the output recovery clock is set to low level;
[0056] ② When the count reaches N, set the recovery clock to high level;
[0057] ③ When the count reaches 2N, the counter is reset to zero, and the recovery clock is set to low level.
[0058] It is understood that the incrementing count is the underlying operation of the counter, and operations ①-③ are execution operations of the counter, without any specific order. When the data signal's transition edge is encountered, the counter performs a reset operation and sets the recovery clock to a high level; when the counter counts to N, it sets the recovery clock to a high level; when the counter counts to 2N, it performs a reset operation and sets the recovery clock to a low level. Thus, the counter completes the clock recovery of the data signal through the above operations.
[0059] It should be noted that the principle by which the counter recovers the clock of the data signal through the above operation is based on the fact that the encoding in low-speed communication systems has sufficient transition edges, and this type of encoding embeds the clock into the encoding. Furthermore, a short level of these codes contains at least one embedded clock, and a long level contains at least one or more embedded clocks. According to the above theory, a short level of the data signal contains at least one embedded clock, which is precisely located between two transition edges of the data signal. Similarly, a long level contains one or more embedded clocks, which are also located between two transition edges. The counter can be reset to zero and set the recovered clock to a low level at the transition edge, or set the recovered clock to a high level when the count reaches N, or reset to zero and set the recovered clock to a low level when the count reaches 2N. Therefore, by adjusting the level in the above manner, one or more embedded clocks in the data signal are recovered.
[0060] Optionally, when a long level contains multiple clocks, the counter counts and clears according to the extraction operation provided in step S4, and the level adjustment of the recovery clock also changes according to the extraction operation, set to a high level or a low level, thereby realizing the recovery of multiple clocks embedded in a long level in the encoding.
[0061] Finally, the recovered data signal is output through step S5.
[0062] Where N is a positive integer greater than 1.
[0063] Optionally, the value of N is 10-25.
[0064] Specifically, the selection of the value of N stems from a balance between counting cost and accuracy. A higher multiplication factor for the sampling clock results in higher clock recovery accuracy, but this also increases the range of counter counts and necessitates the production of a high-frequency sampling clock, leading to increased recovery costs. Therefore, the preferred value of N in this invention is 10-25.
[0065] In theory, the larger the value of N, the higher the accuracy of clock recovery. However, in practice, a value of 10 for N is sufficient to achieve the required clock recovery accuracy.
[0066] To further explain the working principle of this invention, please refer to [link / reference]. Figure 2 The diagram shown illustrates the working principle of a clock recovery method for low-speed communication provided in an embodiment of the present invention (using Manchester code as an example).
[0067] Specifically, this embodiment uses Manchester encoding as an example. Encoding methods with common characteristics, such as 1B / 4B encoding, CMI encoding, and C37.94 protocol encoding, can be understood by referring to these examples.
[0068] In low-speed communication systems, the original signal does not have long 0s or long 1s (see the waveform diagram in the first row). When generating Manchester codes, the codes will not have long transition edge intervals. Each transition edge interval contains only one or more embedded clocks.
[0069] Therefore, the counter is reset to zero and output clock according to the sudden edge of Manchester encoding. As the count increments, when it reaches N, the clock is set to 1. When the count continues to increment to 2N-1, the count is reset to zero and the clock is output clock, thus completing the recovery of the clock embedded in Manchester encoding.
[0070] Among them, a jump edge refers to a waveform that suddenly drops from high to low or rises from low to high.
[0071] Optional, please see Figure 3 The diagram shown is a flowchart illustrating a clock recovery method for low-speed communication according to another embodiment of the present invention.
[0072] Specifically, while Manchester encoding can well adapt to the counting scheme provided by this invention, recovering one embedded clock from a short level and one or two embedded clocks from a long level, for situations where a long level embeds two or more embedded clocks, to improve the compatibility of this invention, in step S41, when a long level contains multiple clocks, the counter counts and resets according to the extraction operation provided in step S4, and the level adjustment of the recovered clock also changes according to the extraction operation, set to a high level or a low level, thereby realizing the recovery of multiple clocks embedded in a long level in the encoding, thus improving the application scenarios of this invention and making it suitable for encoding application scenarios where a long level embeds multiple embedded clocks.
[0073] For further details, please see Figure 4 The diagram shown is a schematic diagram of a clock recovery circuit for low-speed communication provided in an embodiment of the present invention.
[0074] Specifically, the clock recovery circuit includes an input terminal, an output terminal, and a sampling clock. The input terminal is used to acquire data signals, the sampling clock is used to extract a recovery clock based on the data signals, and the output terminal is used to output a recovery signal based on the data signals and the recovery clock.
[0075] Optionally, the recovery clock and data signals need to be aligned to eliminate the time delay between the acquired recovery signal and the recovery clock.
[0076] Optionally, the present invention provides a clock recovery chip for low-speed communication, wherein the clock recovery chip includes the clock recovery circuit for low-speed communication provided in any embodiment.
[0077] Specifically, the working principle of the clock recovery circuit provided by this invention is relatively simple and can be implemented using low-end domestic chips, such as CPLD and FPGA.
[0078] Optionally, the present invention provides a clock recovery communication system for low-speed communication, including a clock recovery method for low-speed communication provided in any embodiment or a clock recovery chip for low-speed communication provided in any embodiment.
[0079] The present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of the embodiments above are only for the purpose of helping to understand the invention and its core ideas. For those skilled in the art, several modifications can be made to the invention without departing from the principles of the invention, and these modifications also fall within the protection scope of the claims of the present invention.
Claims
1. A clock recovery method for low-speed communication, characterized in that, include: S1. Configure a sampling unit according to the data signal to be input. The sampling unit includes a sampling clock and a counter. The clock frequency of the sampling clock is 2N times the clock frequency of the data signal, and the counter has a counting function of 2N numbers. S2. Receive the data signal; S3. Align the sampling clock with the data signal, and increment the counter by 1 at intervals of 1 / 2N of the clock period of the data signal: S4. During the auto-incrementing process of the counter, the following operation is triggered according to the conditions: When the encoding of the data signal has a rising edge, the counter is cleared to zero and the output recovery clock is set to low level. When the count reaches N, the recovery clock is set to high. When the count reaches 2N, the counter is reset to zero, and the recovery clock is set to low. S5. Align the recovery clock with the data signal and output the recovery signal; Where N is a positive integer greater than 1.
2. The clock recovery method for low-speed communication as described in claim 1, characterized in that, The value of N is between 10 and 25.
3. A clock recovery method for low-speed communication as described in any one of claims 1 or 2, characterized in that, The data signal is transmitted through a communication system with communication codes having a transition edge; The communication encoding is any one of Manchester encoding, 1B / 4B encoding, CMI encoding, or C37.94 encoding.
4. The clock recovery method for low-speed communication as described in claim 3, characterized in that, One or more embedded clocks are embedded between the transition edges of the communication code.
5. A clock recovery method for low-speed communication as described in claim 3, characterized in that, In an E1 communication system using Manchester encoding, the clock frequency is 2.048MHz; When N is 10, the sampling clock frequency is 40.96MHz and the counter count is 20.
6. A clock recovery circuit for low-speed communication, characterized in that, The clock recovery circuit includes a clock recovery method for low-speed communication as described in any one of claims 1-5.
7. A clock recovery chip for low-speed communication, characterized in that, The clock recovery chip includes a clock recovery circuit for low-speed communication as described in claim 6.
8. A clock recovery communication system for low-speed communication, characterized in that, The clock recovery communication system includes a clock recovery circuit for low-speed communication as described in claim 6 or a clock recovery chip for low-speed communication as described in claim 7.