Signal synchronization method and signal synchronization device

Abstract

The invention provides a signal synchronization method and a signal synchronization device, and the method comprises the steps: providing a first chip and at least one second chip which are connected in parallel, and enabling the first chip and the at least one second chip to control the working state of a load through outputting a periodic current waveform to the load; the first chip sends a waveform synchronizing signal and a frequency deviation adjusting signal to at least one second chip, and outputs a first current waveform to a load when the waveform synchronizing signal is ended; the second chip responds to the received waveform synchronizing signal and the frequency deviation adjusting signal, adjusts the frequency of the current waveform output in the waveform emission period after the waveform synchronizing signal and the frequency deviation adjusting signal are received, and outputs an adjusted second current waveform to the load when the waveform synchronizing signal is finished; a first current waveform output by the first chip in the waveform emission period and a second current waveform synchronously output by the second chip in the corresponding waveform emission period are mutually superposed to form a superposed waveform, and the superposed waveform is transmitted to the second chip in each waveform emission period after the second chip receives the waveform synchronization signal. The superposed waveforms tend to be consistent in at least one waveform emission period. Compared with the prior art, a plurality of chips connected in parallel can synchronously output respective current waveforms.

Description

Technical Field

[0001] This invention relates to a signal synchronization method and a signal synchronization device, which are applied in the field of lighting technology. Background Technology

[0002] Existing lighting fixtures controlled by the return-to-zero code protocol rely on the current output by the protocol control chip to control the working state of the lamp beads. By relying on the current output by the protocol control chip, the lighting fixture tends to be stable during operation.

[0003] However, when the outputs of two or more chips are connected in parallel, periodic current changes will occur due to the clock refresh rate deviation within each chip, causing the lamp to flicker. When the frequency of the current change is within the human eye's refresh rate perception range, the human eye can easily perceive the flickering of the lamp. Prolonged exposure to this environment can cause visual fatigue and subsequently lead to decreased vision. Summary of the Invention

[0004] The purpose of this invention is to provide a signal synchronization method that enables multiple parallel-connected chips to output current waveforms, thereby preventing lamps from flickering.

[0005] To achieve the above objectives, the present invention provides a signal synchronization method, comprising:

[0006] A first chip and at least one second chip are provided in parallel with each other. The first chip and at least one second chip control the operating state of the load by synchronously outputting periodic current waveforms to the load.

[0007] The first chip sends a waveform synchronization signal and a frequency deviation adjustment signal to at least one second chip, and outputs a first current waveform to the load when the waveform synchronization signal ends.

[0008] The second chip responds to the received waveform synchronization signal and frequency deviation adjustment signal, and adjusts the frequency of the current waveform output during the waveform transmission cycle after receiving the waveform synchronization signal and frequency deviation adjustment signal, and outputs the adjusted second current waveform to the load when the waveform synchronization signal ends.

[0009] In this design, the first current waveform output by the first chip during its waveform transmission cycle and the second current waveform synchronously output by the second chip during its corresponding waveform transmission cycle are superimposed to form a superimposed waveform. After the second chip receives the waveform synchronization signal, the superimposed waveform tends to be consistent within at least one waveform transmission cycle. This avoids flickering of the load due to inconsistencies in the superimposed waveform, which could be detected by the human eye and affect the user's vision.

[0010] As a further improvement of the present invention, the waveform transmission period is the sum of the high-level duration and the low-level duration of the first current waveform, and the frequency deviation adjustment signal includes the high-level duration of the first chip within the waveform transmission period.

[0011] As a further improvement of the present invention, the high-level duration of the first chip within the waveform transmission cycle is defined as the first duration, the frequency of the first chip within the first duration is defined as the first frequency, the high-level duration of the second chip within the waveform transmission cycle is defined as the second duration, the frequency of the second chip within the second duration is defined as the second frequency, and the step of the second chip adjusting the frequency of the second current waveform after receiving the frequency deviation adjustment signal is as follows:

[0012] 1) Compare the second duration with the first duration to obtain the deviation ratio;

[0013] 2) Multiply the second frequency by the deviation ratio to obtain the third frequency, which is the frequency of the adjusted second current waveform. This ensures that the frequencies output by the two chips during the high-level duration of the same waveform transmission cycle are nearly identical, preventing the load brightness from being affected by the frequency deviation between the two chips.

[0014] As a further improvement of the present invention, since there is a frequency deviation between the current waveforms output by the first chip and the second chip, the signal synchronization method further includes: widening the waveform emission period of the first chip at least according to the frequency deviation. By widening, the second chip is given space to adjust the dimming level of the high gray portion, that is, given an idle waiting period, which makes the light output of the load more uniform and the effect more excellent.

[0015] As a further improvement of the present invention, the waveform transmission period is the sum of the high-level duration and the low-level duration of the current waveform. The step of at least widening the waveform transmission period of the first chip is to at least extend the low-level duration of the current waveform output by the first chip.

[0016] As a further improvement of the present invention, the frequency deviation is proportional to the widened range of the first chip.

[0017] As a further improvement of the present invention, the first chip outputs a first current waveform to the load when the waveform synchronization signal ends, and / or the second chip outputs an adjusted second current waveform to the load when the waveform synchronization signal ends, including:

[0018] Immediately upon the end of the waveform synchronization signal, output a current waveform to the load; or

[0019] The current waveform is output to the load after a set delay after the waveform synchronization signal ends.

[0020] As a further improvement of the present invention, after each waveform transmission cycle, the first chip sends a waveform synchronization signal and a frequency deviation adjustment signal to at least one second chip.

[0021] The purpose of this invention is to provide a signal synchronization device that enables multiple parallel chips to output current waveforms synchronously, thereby preventing lamps from flickering.

[0022] To achieve the above objectives, the present invention provides a signal synchronization device that applies the aforementioned signal synchronization method. The first chip and at least one second chip are both externally equipped with synchronization pins, and the synchronization pins of the first chip and at least one second chip communicate with each other. The waveform synchronization signal and the frequency deviation adjustment signal are both sent to the synchronization pin of at least one second chip through the synchronization pin of the first chip.

[0023] As a further improvement of the present invention, multiple loads are provided and connected in parallel. The first chip and the second chip are both provided with pins connected to the corresponding loads to control the same or different working states of the multiple loads.

[0024] As a further improvement of the present invention, each pin of the first chip and the second chip is connected in series with a voltage divider resistor to the corresponding load.

[0025] The beneficial effects of this invention are as follows: The signal synchronization method of this invention sends a waveform synchronization signal and a frequency deviation adjustment signal to at least one second chip before the first chip outputs a first current waveform to the load. This enables the second chip to receive the waveform synchronization signal and the frequency deviation adjustment signal, and adjust the frequency of the second current waveform output in the waveform transmission cycle after the timing sequence. When the waveform synchronization signal ends, the second current waveform is synchronously output to the load. In each waveform transmission cycle after the second chip receives the waveform synchronization signal, the first current waveform output by the first chip in the corresponding waveform transmission cycle and the second current waveform synchronously output by the second chip in the corresponding waveform transmission cycle are superimposed to form a superimposed waveform. This superimposed waveform tends to be consistent within at least one waveform transmission cycle. In this way, multiple chips can synchronously output current waveforms in different cycles, and the output current waveforms tend to be consistent, thereby avoiding light flickering. Attached Figure Description

[0026] Figure 1 This is a control circuit diagram of a signal synchronization device conforming to a preferred embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram of the current waveforms of the signal synchronization device of the present invention with and without the synchronization function enabled.

[0028] Figure 3This is a schematic diagram of the current waveform after the waveform transmission period is widened by the signal synchronization device of the present invention.

[0029] Figure 4 This is a comparison diagram of the current waveforms of the signal synchronization device of the present invention when it does not receive the frequency deviation adjustment signal and when it does receive the frequency deviation adjustment signal.

[0030] Figure 5 This is a flowchart of a signal synchronization method conforming to the present invention.

[0031] Figure label:

[0032] 100 - Signal synchronization device, 1 - Chip, 2 - Load. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Please see Figure 1 As shown, this invention discloses a signal synchronization device 100, including a chip 1 and a load 2. The chip 1 and the load 2 are electrically connected. The chip 1 outputs a periodic current waveform to the load 2 to control the operating state of the load 2. Preferably, the load 2 is a lamp bead of a lamp, that is, the chip 1 controls the brightness, on / off state, etc. of the lamp bead. Of course, in other embodiments, the load 2 is not limited to a lamp bead, and can be other carriers, which is not limited.

[0035] In this embodiment, the signal synchronization device 100 adopts a single-wire return-to-zero (RZ) code protocol digital communication encoding method. First, current is input to the current input terminal of chip 1 from the power supply, causing chip 1 to enter the working state. Then, the controller inputs data to the signal input terminal DIN of chip 1 via the data signal DATA_IN. The data is then decoded by the decoder inside chip 1, and subsequently, different duty cycle control signals are generated at the output terminals (OUTR, OUTG, OUTB, OUTW) of chip 1 to output the drive current. In this encoding method, high and low levels are represented by binary "1" and "0" respectively. Each code starts with a high level, and the duration of the high level determines whether it is a "1" or a "0" code.

[0036] Optionally, multiple loads 2 are provided and connected in parallel. The output terminals (OUTR, OUTG, OUTB, OUTW) of chip 1 correspond to multiple parallel loads 2. When the number of loads 2 increases, the output terminals of chip 1 can also increase synchronously. In this way, different loads 2 can be controlled to have the same or different operating states.

[0037] Voltage divider resistors RR, RG, RB, and RW are also connected between multiple loads 2 and the output terminals (OUTR, OUTG, OUTB, OUTW) of chip 1. Specifically, the output terminal OUTR of chip 1, the voltage divider resistor RR, and the load 2 are connected in series; the output terminal OUTG of chip 1, the voltage divider resistor RG, and the load 2 are connected in series; the output terminal OUTB of chip 1, the voltage divider resistor RB, and the load 2 are connected in series; and the output terminal OUTW of chip 1, the voltage divider resistor RW, and the load 2 are connected in series. In other words, a voltage divider resistor is connected in series between each output terminal / output pin of chip 1 and a load 2.

[0038] Specifically, chip 1 includes a first chip IC1 and at least one second chip IC2. The first chip IC1 and at least one second chip IC2 are connected in parallel and communicate with each other. The first chip IC1 first extracts the data input from the controller, processes it in the decoder inside the first chip IC1, and then transmits it to the next cascaded second chip IC2 through the DOUT port, so that both the first chip IC1 and the second chip IC2 can output drive current according to the data input from the controller.

[0039] In other words, the state of the drive current output by the first chip IC1 and the second chip IC2 can be changed in real time by adjusting the data inside the controller, thereby changing the working state of the load 2.

[0040] Preferably, a voltage divider resistor RD1 is connected in series between the data signal DATA_IN and the signal input terminal of chip 1, and a voltage divider resistor RD0 and a voltage divider resistor RD1 are connected in series between the first chip IC1 and the second chip IC2.

[0041] Please see Figure 2 As shown, taking a typical current waveform with a frequency of 4kHz as an example, there is a frequency deviation of approximately ±5% between the oscillators that generate the respective current waveform frequencies of the first chip IC1 and the second chip IC2. Of course, the frequency of the current waveform can also be set to 8kHz, 16kHz, etc., without limitation.

[0042] In this embodiment, the first chip IC1 has a waveform frequency 5% faster than the conventional waveform frequency, at 4.2kHz; the second chip IC2 has a waveform frequency 5% slower than the conventional waveform frequency, at 3.8kHz. Correspondingly, the waveform transmission period T1 of the first chip IC1 is approximately 237.5µs, and the waveform transmission period T2 of the second chip IC2 is approximately 262.5µs. The output current waveform range accounts for approximately 90% of the entire waveform transmission period; that is, the period of the first current waveform output by the first chip IC1 is 0.9T1, approximately 213.75µs, and the period of the second current waveform output by the second chip IC2 is 0.9T2, approximately 236.25µs. Therefore, the waveform transmission period of the second chip IC2 is significantly longer than that of the first chip IC1.

[0043] In other words, there will be a clock deviation between the first chip IC1 and the second chip IC2 connected in parallel. This causes an error in the timing of the first chip IC1 starting to output the first current waveform and the second chip IC2 starting to output the second current waveform. As a result, the first current waveform output by the first chip IC1 within the same waveform transmission cycle and the second current waveform output by the second chip IC2 within the same waveform transmission cycle will have superimposed waveforms and non-superimposed waveforms.

[0044] The brightness output of load 2 under the superimposed waveform is different from the brightness output without the superimposed waveform, which causes load 2 to flicker. When the frequency of the current waveform is within the human eye's refresh rate perception range, this flickering will be observed by the human eye. Long-term exposure to such an environment will cause visual fatigue and subsequently lead to decreased vision.

[0045] Therefore, an external synchronization pin SYNC is provided on both the first chip IC1 and at least one second chip IC2, and the synchronization pins SYNC of the first chip IC1 and at least one second chip IC2 communicate with each other.

[0046] Before the first chip IC1 outputs the first current waveform to the load 2, a waveform synchronization signal is sent to the synchronization pin SYNC of at least one second chip IC2 through the synchronization pin SYNC of the first chip IC1. The second chip IC2 receives the waveform synchronization signal and outputs the second current waveform to the load 2 when the waveform synchronization signal ends.

[0047] It is understood that in this invention, the first chip IC1 outputs a current waveform to the load 2 when the waveform synchronization signal it sends to the second chip IC2 ends. This "current waveform" output can be a first current waveform output by the first chip IC1 to the load 2 simultaneously with the completion of the waveform synchronization signal transmission; or, after a set delay (e.g., 1 μs) after the completion of the waveform synchronization signal transmission, the first chip IC1 outputs the first current waveform to the load 2. Similarly, the second chip IC2 outputs a current waveform to the load 2 when the waveform synchronization signal it receives from the first chip IC1 ends. This "current waveform" output can be a second current waveform output by the second chip IC1 to the load 2 simultaneously with the completion of the waveform synchronization signal reception; or, after a set delay (e.g., 1 μs) after the completion of the waveform synchronization signal transmission, the second chip IC1 outputs the second current waveform to the load 2.

[0048] Therefore, since the first chip IC1 starts outputting the first current waveform to the load 2 after transmitting the waveform synchronization signal, and the second chip IC2 starts outputting the second current waveform to the load 2 immediately after receiving the waveform synchronization signal, the first chip IC1 and the second chip IC2 can start transmitting waveforms almost simultaneously, making it impossible for the human eye to detect the flickering of the load 2. At the same time, this also ensures that the first chip IC1 and the second chip IC2 maintain a synchronized output of current waveforms without the need for pre-tuning, thus improving adaptability. After each waveform transmission cycle, the first chip IC1 sends a waveform synchronization signal to at least one second chip IC2. This configuration ensures that even after the controller adjusts the data information in real time, the first chip IC1 and the second chip IC2 can still synchronously output their respective current waveforms.

[0049] Please see Figure 3 As shown, after each waveform transmission cycle of the first chip IC1 ends, that is, while the second chip IC2 sends a waveform synchronization signal and receives the waveform synchronization signal, because the waveform transmission cycle of the second chip IC2 is significantly longer than that of the first chip IC1, the second chip IC2 continues to output the second current waveform. After the waveform synchronization signal ends, the next waveform transmission cycle immediately begins. In other words, the second current waveform output by the second chip IC2 is uninterrupted, which causes the second chip IC2 to lose its dimming level in the high grayscale region.

[0050] Therefore, in this embodiment, the waveform transmission period of the first chip IC1 needs to be widened at least. Since the second chip IC2 starts a new waveform transmission period immediately after receiving the waveform synchronization signal, its waveform transmission period must be the same as that of the first chip IC1. That is, the waveform transmission period of the second chip IC2 can also be appropriately widened synchronously with the widening of the waveform transmission period of the first chip IC1. Of course, the waveform transmission periods of both the first chip IC1 and the second chip IC2 can also be widened simultaneously. Widening the waveform transmission period provides the second chip IC2 with space to adjust the dimming level of the high gray portion, i.e., it gives the second chip IC2 an idle waiting period, resulting in more uniform light output from the load 2 and a better overall effect.

[0051] To meet different application scenarios, the widening range / widening ratio of the waveform transmission period has different levels, such as 2%, 5%, 8%, and 11% of the waveform transmission period. In other words, the widening range can be determined based on the waveform frequency deviation. That is, the frequency deviation between the current waveforms output by the first chip IC1 and the second chip IC2 is proportional to the widening range of the first chip IC1. The smaller the widening ratio, the less idle signal synchronization waiting time, reducing resource consumption, less brightness sacrifice in high grayscale, and closer linearity to the untransmitted waveform synchronization signal.

[0052] like Figure 3 As shown, when the waveform emission period of the first chip IC1 is widened by 11%, the widened waveform emission period of the first chip IC1 is the same as the synchronously widened waveform emission period of the second chip IC2, both being T3 = 263.625us. This setting allows for a certain amount of idle time for the second chip IC2, resulting in more uniform light output from the load 2 and a better overall effect.

[0053] Typically, the waveform transmission period is the sum of the high-level duration and the low-level duration of the current waveform. Therefore, the waveform transmission period of the first chip IC1 can also be widened by extending the low-level duration of the current waveform output by the first chip IC1. This is not a limitation here.

[0054] Please see Figure 4 As shown, when the first chip IC1 sends a waveform synchronization signal to at least one second chip IC2, the first chip IC1 simultaneously sends a frequency deviation adjustment signal to at least one second chip IC2. After receiving the frequency deviation adjustment signal, the second chip IC2 adjusts the frequency of the second current waveform output after receiving the frequency deviation adjustment signal, so that the frequency of the first current waveform output by the first chip IC1 is consistent with the frequency of the second current waveform synchronously output by the second chip IC2.

[0055] Preferably, the frequency deviation adjustment signal is a frequency deviation adjustment code, which includes the high-level duration within the waveform transmission cycle of the first chip IC1. The purpose of setting this frequency deviation adjustment code is to ensure that after the second chip IC2 receives the frequency deviation adjustment code sent by the first chip IC1, the frequency deviation between the frequency of the second current waveform output and the frequency of the first current waveform synchronously output by the first chip IC1 is less than or equal to 1%.

[0056] Specifically, the high-level duration of the first chip IC1 within the waveform transmission cycle is defined as the first duration, and the frequency of the first chip IC1 within the first duration is defined as the first frequency. The high-level duration of the second chip IC2 within the waveform transmission cycle is defined as the second duration, and the frequency of the second chip IC2 within the second duration is defined as the second frequency. Then, the steps for the second chip IC2 to adjust the frequency of the second current waveform after receiving the frequency deviation adjustment signal are as follows:

[0057] 1) Compare the second duration with the first duration to obtain the deviation ratio;

[0058] 2) Multiply the second frequency by the deviation ratio to obtain the third frequency, which is the frequency of the adjusted second current waveform.

[0059] Therefore, by adjusting the frequency deviation signal, the deviation between the third frequency and the first frequency is made less than or equal to 1%, thereby making the frequency of the first current waveform output by the first chip IC1 consistent with the frequency of the second current waveform synchronously output by the second chip IC2, thus avoiding the impact on the brightness of the load 2 due to the frequency deviation between the two chips.

[0060] Please see Figure 5 As shown, the present invention also provides a signal synchronization method, comprising:

[0061] A first chip IC1 and at least one second chip IC2 are provided in parallel. The first chip IC1 and at least one second chip IC2 control the operating state of the load 2 by outputting a periodic current waveform to the load 2.

[0062] The low-level duration of the current waveform output by the first chip IC1 is extended at least to broaden the waveform transmission period of the first chip IC1;

[0063] The first chip IC1 sends a waveform synchronization signal and a frequency deviation adjustment signal to at least one second chip IC2, and outputs a first current waveform to the load 2 when the waveform synchronization signal ends.

[0064] The second chip IC2 responds to the received waveform synchronization signal and frequency deviation adjustment signal, and adjusts the frequency of the current waveform output within the waveform transmission cycle after receiving the waveform synchronization signal and frequency deviation adjustment signal, and outputs the adjusted second current waveform to the load 2 when the waveform synchronization signal ends.

[0065] The first current waveform output by the first chip IC1 during the waveform transmission cycle and the second current waveform output synchronously by the second chip IC2 during the corresponding waveform transmission cycle are superimposed to form a superimposed waveform. In each waveform transmission cycle after the second chip IC2 receives the waveform synchronization signal, the superimposed waveform tends to be consistent in at least one waveform transmission cycle.

[0066] In other words, it generally includes the following steps:

[0067] 1. Expand the first chip IC1;

[0068] 2. Before the first chip IC1 outputs the first current waveform to the load 2, a waveform synchronization signal and a frequency deviation adjustment signal are sent to at least one second chip IC2;

[0069] 3. The second chip IC2 responds to the received waveform synchronization signal and frequency deviation adjustment signal, and adjusts the frequency of the current waveform output within the waveform transmission cycle after receiving the waveform synchronization signal and frequency deviation adjustment signal, and immediately outputs the second current waveform after the waveform synchronization signal ends.

[0070] In summary, this invention sends a waveform synchronization signal to at least one second chip IC2 before the first chip IC1 outputs the first current waveform to the load 2. This allows the second chip IC2 to receive the waveform synchronization signal and synchronously output the second current waveform to the load 2 when the waveform synchronization signal ends. This enables multiple chips 1 to synchronously output current waveforms in different cycles, thus avoiding light flickering. Simultaneously, by widening the first chip IC1 and synchronously sending a frequency deviation adjustment signal with the waveform synchronization signal, the first current waveform output by the first chip IC1 and the second current waveform synchronously output by the second chip IC2 are superimposed on each other in each waveform transmission cycle after the second chip IC2 receives the waveform synchronization signal, forming a superimposed waveform. This superimposed waveform tends to be consistent within at least one waveform transmission cycle.

[0071] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A signal synchronization method, characterized in that, include: A first chip and at least one second chip are provided in parallel, and the first chip and at least one second chip control the operating state of the load by outputting a periodic current waveform to the load (2); The first chip sends a waveform synchronization signal and a frequency deviation adjustment signal to at least one second chip, and outputs a first current waveform to the load (2) when the waveform synchronization signal ends; The second chip responds to the received waveform synchronization signal and frequency deviation adjustment signal, adjusts the frequency of the current waveform output during the waveform transmission cycle after receiving the waveform synchronization signal and frequency deviation adjustment signal, and outputs the adjusted second current waveform to the load (2) when the waveform synchronization signal ends. Wherein, the first current waveform output by the first chip in the waveform transmission cycle and the second current waveform output synchronously by the second chip in the corresponding waveform transmission cycle are superimposed to form a superimposed waveform. In each waveform transmission cycle after the second chip receives the waveform synchronization signal, the superimposed waveform tends to be consistent in at least one waveform transmission cycle.

2. The signal synchronization method according to claim 1, characterized in that, The waveform transmission period is the sum of the high-level duration and the low-level duration of the first current waveform, and the frequency deviation adjustment signal includes the high-level duration of the first chip within the waveform transmission period.

3. The signal synchronization method according to claim 2, characterized in that, The high-level duration of the first chip within the waveform transmission cycle is defined as the first duration, and the frequency of the first chip within the first duration is defined as the first frequency. The high-level duration of the second chip within the waveform transmission cycle is defined as the second duration, and the frequency of the second chip within the second duration is defined as the second frequency. The steps for the second chip to adjust the frequency of the second current waveform after receiving the frequency deviation adjustment signal are as follows: 1) Compare the second duration with the first duration to obtain the deviation ratio; 2) Multiply the second frequency by the deviation ratio to obtain the third frequency, which is the frequency of the adjusted second current waveform.

4. The signal synchronization method according to claim 1, characterized in that, The current waveforms output by the first chip and the second chip have a frequency deviation. The signal synchronization method further includes: widening the waveform transmission period of the first chip at least according to the frequency deviation.

5. The signal synchronization method according to claim 4, characterized in that, The waveform transmission period is the sum of the high-level duration and the low-level duration of the current waveform. The step of at least widening the waveform transmission period of the first chip is to at least extend the low-level duration of the current waveform output by the first chip.

6. The signal synchronization method according to claim 4, characterized in that, The frequency deviation is proportional to the widened range of the first chip.

7. The signal synchronization method according to claim 1, characterized in that, The first chip outputs a first current waveform to the load (2) when the waveform synchronization signal ends, and / or the second chip outputs an adjusted second current waveform to the load (2) when the waveform synchronization signal ends, including: Immediately upon the end of the waveform synchronization signal, a current waveform is output to the load (2); or A current waveform is output to the load (2) after a set delay following the end of the waveform synchronization signal.

8. A signal synchronization device, employing the signal synchronization method as described in any one of claims 1-7, characterized in that, Both the first chip and at least one second chip have external synchronization pins, and the synchronization pins of the first chip and at least one second chip communicate with each other. The waveform synchronization signal and the frequency deviation adjustment signal are both sent to the synchronization pin of at least one second chip through the synchronization pin of the first chip.

9. The signal synchronization device according to claim 8, characterized in that, The load (2) is provided in multiple ways and connected in parallel. The first chip and the second chip are both provided with pins connected to the corresponding load (2) to control the same or different working states of the multiple loads (2).

10. The signal synchronization device according to claim 9, characterized in that, Each pin of the first chip and the second chip is connected in series with a voltage divider resistor to the corresponding load (2).

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