Chip, memory and electronic equipment

Abstract

The embodiment of the invention provides a chip, a memory and electronic equipment, and aims to reduce the power consumption of chip operation. According to the chip provided by the embodiment of the invention, a bit line is connected with a plurality of storage units; and each bit line is connected with one first gate tube and one second gate tube. In the chip reading process, the first gate tubes correspondingly connected with all the bit lines are closed, the second gate tubes correspondingly connected with all the bit lines are opened, the bit lines are made to be at the preset voltage, then the second gate tubes connected with the selected bit lines are closed, the first gate tubes are opened, the selected bit lines are made to be in the suspended state, and then data in the selected storage units are read. At the moment, the first gate tube of the non-selected bit line is still in a closed state, the second gate tube is still in an open state, and the non-selected bit line keeps a predetermined voltage, so that the change of charge quantity in the storage unit connected with the non-selected bit line is reduced, the refreshing frequency of the storage unit is further reduced, and the power consumption of chip operation is reduced.

Description

Technical Field

[0001] This application relates to the field of data backup technology, specifically to a chip, memory, and electronic device. Background Technology

[0002] The storage transistors in a memory cell have a cutoff current. When the storage transistor is not turned on, the charge in the storage capacitor connected to the transistor will increase or decrease, thus affecting the stability of the data stored in the capacitor. To improve the stability of the data in the capacitor, each memory cell needs to be refreshed at a certain time, which increases the chip's operating power consumption. Summary of the Invention

[0003] This application provides a chip, a memory, and an electronic device, which aim to reduce the power consumption of the chip during operation.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] On one hand, embodiments of this application provide a chip, which includes a substrate and a memory array disposed on the substrate. The memory array includes at least one memory layer. The memory layer includes multiple bit lines, multiple memory cells, multiple first gate transistors, and multiple second gate transistors. The bit lines extend along a first direction, and the multiple bit lines are spaced apart along a second direction. The first direction and the second direction intersect and are all parallel to the plane of the substrate. Multiple memory cells are connected to a bit line, and the multiple memory cells connected to the same bit line are spaced apart along the first direction. The memory cells are used to store data. Each bit line is connected to a first gate transistor and a second gate transistor. With the above settings, during chip reading, the first selector connected to all bit lines is turned off and the second selector is turned on, so that all bit lines are pre-energized to a predetermined voltage. Then, the second selector connected to the selected bit line is turned off and the first selector is turned on, so that the selected bit line is in a floating state, and the data in the selected memory cell is read. At this time, the first selector of the unselected bit line is still in the off state and the second selector is still in the on state, and the predetermined voltage is maintained on the unselected bit line, which reduces the change in charge in the memory cell connected to the unselected bit line, thereby reducing the refresh frequency of the memory cell and thus reducing the power consumption of the chip. Reducing the refresh frequency of the memory cell also reduces the switching frequency of the first selector and the second selector connected to the unselected bit line, which can also reduce the power consumption of the chip.

[0006] In some embodiments, the storage layer includes a first connection portion and a second connection portion, and a plurality of bit lines are located between the first connection portion and the second connection portion; a first end of the bit line is connected to the first connection portion through a first gate, and a second end of the bit line is connected to the second connection portion through a second gate; on the same bit line, the first gate, a plurality of storage cells, and the second gate are arranged sequentially at intervals along a first direction.

[0007] With the above configuration, multiple first select transistors located on multiple bit lines within the memory layer are connected to the first connection portion, allowing for the extraction of these transistors and simplifying the circuitry for extraction. Similarly, multiple second select transistors located on multiple bit lines within the memory layer are connected to the second connection portion, allowing for the extraction of these transistors and simplifying the circuitry for extraction.

[0008] In some embodiments, multiple memory cells connected to the same bit line are located on the same side of the bit line, which helps to reduce the volume of the memory layer and thus increase the storage density of the chip.

[0009] In some embodiments, the storage layer further includes a third connection portion, wherein multiple bit lines are located on the same side of the third connection portion; the first end of the bit line is connected to the third connection portion via a first gate, and a second gate is located between multiple storage cells.

[0010] With the above configuration, multiple first select transistors located on multiple bit lines within the memory layer are connected to the third connection portion. This third connection portion allows for the extraction of these first select transistors, simplifying the circuitry for extraction. Compared to embodiments where the first and second select transistors are located at opposite ends of the bit lines, this configuration, with the second select transistor situated between multiple memory cells, eliminates the need for a second connection portion, thus reducing the chip area.

[0011] In some embodiments, multiple memory cells connected to the same bit line and the second gate are all located on the same side of the bit line, so that the second gate is located between multiple memory cells, avoiding increasing the size of the chip.

[0012] In some embodiments, the memory cell includes a memory transistor and a memory capacitor, the memory capacitor being connected to a bit line of the memory transistor, and the memory transistor and memory capacitor being disposed along a second direction; the memory array further includes a lead-out portion, the lead-out portion being connected to a bit line via a second gate, the second gate and the lead-out portion being disposed along a second direction; the second gate and memory transistor connected to the same bit line are spaced apart along a first direction, and the lead-out portion and memory capacitor connected to the same bit line are spaced apart along the first direction.

[0013] With the above settings, the second selector can be formed simultaneously with the formation of the storage transistor, and the lead-out portion can be formed simultaneously with the formation of the storage capacitor, thereby simplifying the chip formation process.

[0014] In some embodiments, the lead-out portion includes metal to improve the conductivity of the lead-out portion, facilitating the lead-out of the second selector tube.

[0015] In some embodiments, the memory layers include multiple layers stacked along a third direction; the third direction is perpendicular to the first and second directions. This can increase the memory capacity of the chip.

[0016] In some embodiments, two adjacent memory layers have two bit lines spaced apart along a third direction, and two leads connected to the two bit lines spaced apart along a third direction are connected in the third direction.

[0017] The above configuration reduces the number of second selector pinout structures in the memory array, simplifying the chip's complexity.

[0018] In another aspect, embodiments of this application also provide a memory, which includes a controller and the aforementioned chip, with the controller electrically connected to the chip.

[0019] In some embodiments, the controller is connected to the first gate and the second gate, and the controller is used to control the opening or closing of the first gate and the second gate;

[0020] Specifically, the controller controls the first selector connected to all bit lines to turn off and the second selector to turn on, so as to pre-energize the bit lines to a predetermined voltage; then, for the first selector and the second selector connected to the selected bit line, the controller controls the second selector to turn off and controls the first selector to turn on; for the first selector and the second selector connected to the unselected bit line, the controller controls the second selector to remain on and controls the first selector to remain off.

[0021] With the above settings, during memory access, the controller keeps the first selector connected to the unselected bit line in the off state and the second selector in the on state, so that the unselected bit line maintains a predetermined voltage, reducing the change in charge in the memory cell connected to the unselected bit line, thereby reducing the refresh frequency of the memory cell and reducing the power consumption of the chip. Reducing the refresh frequency of the memory cell also reduces the switching frequency of the first and second selectors connected to the unselected bit line, which can also reduce the power consumption of the chip.

[0022] In another aspect, embodiments of this application also provide an electronic device, which includes a circuit board and the aforementioned memory, wherein the memory is disposed on the circuit board and connected to the circuit board.

[0023] It is understood that the beneficial effects of the memory and electronic device provided in the above embodiments of this application can be referred to the beneficial effects of the chip mentioned above, and will not be repeated here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0025] Figure 1 This is a block diagram of the electronic device in the embodiments of this application;

[0026] Figure 2 This is a block diagram of the memory in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of the storage array structure in the embodiments of this application. Figure 1 ;

[0028] Figure 4 This is a schematic diagram of the storage array structure in the embodiments of this application. Figure 2 ;

[0029] Figure 5 This is a schematic diagram of the storage array structure in the embodiments of this application. Figure 3 ;

[0030] Figure 6 for Figure 5 The equivalent circuit diagram;

[0031] Figure 7 This is a schematic diagram of the storage array structure in the embodiments of this application. Figure 4 ;

[0032] Figure 8 for Figure 7 The equivalent circuit diagram;

[0033] Figure 9 This is a schematic diagram of the storage array structure in the embodiments of this application. Figure 5 ;

[0034] Figure 10 This is a timing diagram of the memory access process in an embodiment of this application.

[0035] Explanation of reference numerals in the attached drawings: 30, electronic device; 20, circuit board; 10, memory; 200, controller; 100, memory array; 110, bit line; 113, first bit line; 114, second bit line; 120, memory cell; 121, memory transistor; 122, memory capacitor; 123, word line; 130, selector; 131, first selector; 132, second selector; 1321, lead-out portion; 140, memory layer; 142, first connection portion; 143, second connection portion; 144, connection portion. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0038] Furthermore, in the embodiments of this application, directional terms such as "up," "down," "left," "right," "horizontal," and "vertical" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0039] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0040] In the embodiments of this application, the X, Y, and Z directions in the accompanying drawings are perpendicular to each other.

[0041] It should be noted that, in the description of the embodiments of this application, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection or an integral connection; they can also refer to a mechanical connection or a link; they can refer to a direct connection or an indirect connection through an intermediate medium; or they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0042] Please refer to Figure 1 Some embodiments of this application provide an electronic device 30. This electronic device 30 can be a terminal device, such as a mobile phone, tablet computer, or smart bracelet, or it can be a personal computer (PC), server, workstation, etc. The electronic device 30 may include a memory 10 and a circuit board 20. The memory 10 is disposed on and connected to the circuit board 20. The circuit board 20 can be connected to a power source and provides operating voltage to the memory 10. The electronic device 30 may include multiple memories 10.

[0043] Please refer to Figure 2 Some embodiments of this application also provide a memory 10, which may include Dynamic Random Access Memory (DRAM). This memory 10 is used in the aforementioned electronic device 30, and may include a controller 200 and a chip, with the controller 200 electrically connected to the chip. The chip includes a substrate and a memory array 100 disposed on the substrate, wherein the memory array 100 may include multiple arrays; the controller 200 is connected to the memory array 100 to control the memory array 100 to store data.

[0044] The memory 10 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the memory 10 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0045] Please refer to Figure 3In some embodiments, the memory array 100 may include at least one memory layer 140. The memory layer 140 includes multiple bit lines 110 and multiple memory cells 120. Each memory cell 120 is connected to only one bit line 110, and multiple memory cells 120 are connected to each bit line 110. The bit lines 110 extend along a first direction (X direction), and the multiple bit lines 110 within the same memory layer 140 are spaced apart along a second direction (Y direction). The first and second directions intersect and are both parallel to the plane of the substrate; that is, the substrate extends in the XY direction. In this embodiment, the first and second directions are perpendicular to each other. Multiple memory layers 140 may be provided, and the multiple memory layers 140 are spaced apart along a third direction (Z direction). This ensures that adjacent bit lines 110 are correspondingly positioned in the Z direction.

[0046] The memory cell 120 includes a memory transistor 121 and a memory capacitor 122. The source of the memory transistor 121 is connected to the bit line 110, and the drain of the memory transistor 121 is connected to the memory capacitor 122. The gates of the memory transistors 121, which are correspondingly arranged in the Z direction, form a word line 123. During access, the word line 123 is set, turning on the memory transistor 121 and connecting the memory capacitor 122 to the bit line 110, so that data can be written to or read from the memory capacitor 122. Different amounts of charge in the memory capacitor 122 can represent "0" or "1" in binary; for example, a fully charged memory capacitor 122 represents "1", and an empty memory capacitor 122 represents "0". In embodiments where the memory 10 includes DRAM, the memory transistor 121 may include a single-gate vertical transistor, a double-gate vertical transistor, a tri-gate vertical transistor, or a GAA (gate all around) vertical transistor, etc.

[0047] In some embodiments, one plate of the storage capacitor 122 is connected to the storage transistor 121, and the other plate of the storage capacitor 122 is connected to a plate line configured to a fixed potential, wherein the fixed potential may be half of the operating voltage; or, one plate of the storage capacitor 122 is connected to the storage capacitor 122, and the other plate of the storage capacitor 122 is grounded.

[0048] Reference Figure 2 and Figure 3During the chip read process, the same memory layer 140 includes both selected and unselected bit lines 110. The controller 200 pre-energizes the selected bit line 110 to a predetermined voltage and then disconnects it. The predetermined voltage can be half of the operating voltage of the memory 10; for example, if the operating voltage of the DRAM is 3V, then the bit line 110 will be pre-energized to 1.5V. In this process, although the energizing process is very short, the bit line 110 is different from a capacitor and can be regarded as still being charged. This state is called the floating state. Then, the controller 200 sets the selected word line 123, turning on the storage transistor 121. If the selected storage capacitor 122 is fully charged, some charge in the storage capacitor 122 will move to the selected word line 110 through the storage transistor 121, causing the voltage of the selected word line 110 to rise. If the storage capacitor 122 is empty, some charge in the selected word line 110 will move to the storage capacitor 122 through the storage transistor 121, causing the voltage of the selected word line 110 to decrease. It is understandable that the amount of charge in the storage capacitor 122 changes during the reading process, which is a destructive reading. To ensure the stability of the data in the storage capacitor 122, the charge in the already read storage capacitor 122 needs to be rewritten.

[0049] During the reading process, the voltage rise or fall of bit line 110 is very small. The memory 10 in this embodiment also includes a differential amplifier, which is disposed between two adjacent memory arrays 100 and connected to bit lines 110 in two memory layers 140 located in the two adjacent memory arrays 100 respectively. It can be understood that when one memory array 100 is read, the voltage of bit line 110 in a certain memory layer 140 will rise or fall, while the voltage of bit line 110 in the corresponding memory layer 140 of the other memory array 100 remains at a predetermined voltage. Thus, the differential amplifier compares the voltages of the two bit lines 110 and amplifies the voltage difference to determine whether the selected memory capacitor 122 stores "1" or "0".

[0050] Reference Figure 4In the above embodiment, the memory array 100 includes a gate transistor 130, which is disposed at one end of a bit line 110. The bit line 110 is connected to a differential amplifier through the gate transistor 130. The gate transistor 130 can be a transistor with a selection function. The source of the gate transistor 130 is connected to the bit line 110, and the drain of the gate transistor 130 is connected to the differential amplifier. After the selected bit line is pre-energized and then disconnected, making the selected bit line float, the corresponding gate transistor 130 turns on. The differential amplifier can compare the voltages of the two bit lines 110 connected to it, read the data in the selected memory cell 120, and rewrite it. However, after the unselected bit line is pre-energized and then disconnected, since the gate transistor 130 connected to the unselected bit line will not turn on, the differential amplifier will not read the data in the memory cell 120 connected to the unselected bit line. However, the storage transistor 121 in storage cell 120 has a cutoff current. When the storage transistor 121 is not turned on, the charge in the storage capacitor 122 connected to the storage transistor 121 will also exchange with the charge in the bit line 110, causing the amount of charge in the storage capacitor 122 to increase or decrease, thus affecting the stability of the data stored in the storage capacitor 122. In order to ensure the stability of the data in the storage capacitor 122, the storage cell 120 connected to the unselected bit line needs to be refreshed, which increases the power consumption of the chip. Furthermore, refreshing requires turning on the selector 130 connected to the unselected bit line, which increases the switching frequency of the selector 130, also increasing the power consumption of the chip.

[0051] Reference Figure 5To address the aforementioned issues, this application provides a chip in which the memory array 100 includes the aforementioned memory layer 140; the memory layer 140 further includes a plurality of first select transistors 131 and a plurality of second select transistors 132, and each bit line 110 is connected to a first select transistor 131 and a second select transistor 132. The bit lines 110 include selected bit lines and unselected bit lines. During the reading process of the memory array 100, the first selector 131 corresponding to all bit lines 110 is turned off and the second selector 132 is turned on, so that all bit lines 110 are pre-energized to a predetermined voltage. Then, the second selector 132 connected to the selected bit line is turned off and the first selector 131 is turned on, so that the selected bit line is floating, and then the data in the selected memory cell 120 is read. At this time, the first selector 131 connected to the unselected bit line remains in the off state and the second selector 132 remains in the on state, so that the unselected bit line maintains a predetermined voltage, reducing the change in charge in the memory cell 120 connected to the unselected bit line, thereby reducing the refresh frequency of the memory cell 120 and thus reducing the power consumption of the chip. Reducing the refresh frequency of the memory cell 120 also reduces the switching frequency of the first selector 131 and the second selector 132 connected to the unselected bit line, which can also reduce the power consumption of the chip.

[0052] Reference Figure 5 and Figure 6 In an embodiment where the storage array 100 includes a storage layer 140, the storage layer 140 is provided with the aforementioned bit lines 110 and storage cells 120, a first selector 131, and a second selector 132 connected to the bit lines 110; exemplaryly, the storage layer 140 can extend in the XY plane, and multiple bit lines 110 can be provided on the storage layer 140. Figure 6 In the example, BL1, BLn, etc., multiple bit lines 110 extend in the same direction, and each bit line 110 is connected to a first selector 131 (MUX01), a second selector 132 (MUX02), and a memory cell 120.

[0053] In some embodiments, all memory cells 120 connected to the same bit line 110 are located between the first select transistor 131 and the second select transistor 132. The first select transistor 131 and the second select transistor 132 are located at opposite ends of the bit line 110. The memory layer 140 includes a first connection portion 142 and a second connection portion 143, with multiple bit lines 110 located between the first connection portion 142 and the second connection portion 143. The first end of the bit line 110 is connected to the first connection portion 142 via the first select transistor 131, and the first connection portion 142 can be used to connect the aforementioned differential amplifier. The second end of the bit line 110 is connected to the second connection portion 143 via the second select transistor 132, and the second connection portion 143 can be used to connect external circuitry, such as a circuitry for providing voltage to the bit line 110. For example, on the same bit line 110, the first select transistor 131, multiple memory cells 120, and the second select transistor 132 are sequentially spaced along the X direction.

[0054] With the above configuration, multiple first selectors 131 on multiple bit lines 110 within the memory layer 140 are connected to the first connection portion 142, allowing the multiple first selectors 131 to be brought out through the first connection portion 142, thus simplifying the circuit for bringing out the first selectors 131. Similarly, multiple second selectors 132 on multiple bit lines 110 within the memory layer 140 are connected to the second connection portion 143, allowing the multiple second selectors 132 to be brought out through the second connection portion 143, thus simplifying the circuit for bringing out the second selectors 132.

[0055] In the above embodiments, multiple memory cells 120 connected to the same bit line 110 are all located on the same side of the bit line 110, which facilitates reducing the volume of the memory layer 140 and thereby increasing the chip's storage density. For example, the bit line 110 extends along the X direction, and the memory cells 120 connected to the bit line 110 and the bit line 110 are arranged in the Y direction; and in embodiments where multiple bit lines 110 are provided within the same memory layer 140, the memory cells 120 are all located to the right of their corresponding bit lines 110.

[0056] Reference Figure 7 , Figure 8 In other embodiments, on the same bit line 110, a first gate transistor 131 is located at one end of the bit line 110, and a second gate transistor 132 is located between multiple memory cells 120. The memory layer 140 also includes a third connection portion 144, with the first end of the bit line 110 connected to the third connection portion 144 via the first gate transistor 131. The third connection portion can be used to connect the aforementioned differential amplifier.

[0057] With the above configuration, multiple first select transistors 131 on multiple bit lines 110 within the storage layer 140 are all connected to the third connection portion 144. The third connection portion 144 allows for the extraction of the multiple first select transistors 131, simplifying the circuitry for extracting the first select transistors 131. Compared to the embodiment where the first select transistors 131 and 132 are respectively located at opposite ends of the bit line 110, the second select transistor 132 is located between multiple storage cells 120, eliminating the need for a second connection portion 143 connected to the second select transistor 132, thus reducing the chip area.

[0058] In the above embodiment, the multiple memory cells 120 connected to the same bit line 110 and the second gate transistor 132 are all located on the same side of the bit line 110, so that the second gate transistor 132 is located between the multiple memory cells 120, thus avoiding increasing the size of the chip.

[0059] In the above embodiment, the storage cell 120 includes a storage transistor 121 and a storage capacitor 122. One end of the storage transistor 121 is connected to a bit line 110, and the other end of the storage transistor 121 is connected to the storage capacitor 122, so that the storage capacitor 122 is connected to the bit line 110 through the storage transistor 121. The storage array 100 also includes a lead-out portion 1321, which is connected to the bit line 110 through a second selector 132. The second selector 132 and the lead-out portion 1321 are arranged along the Y direction. The second selector 132 and the storage transistor 121 connected to the same bit line 110 are spaced apart along the X direction, and the lead-out portion 1321 and the storage capacitor 122 connected to the same bit line 110 are spaced apart along the X direction.

[0060] In the direction of bit line 110 extension, the first selector 131, the memory cell 120, the second selector 132, and the memory cell 120 are arranged sequentially, which can be considered as the second selector 132 being inserted into the memory cell 120. For example, bit line 110 can serve as the source of the second selector 132, the gate 1322 of the second selector 132 is correspondingly disposed with the memory transistor 121 in the memory cell 120, and the lead-out portion 1321 is correspondingly disposed with the memory capacitor 122 in the memory cell 120. Each lead-out portion 1321 can be led out for connection to external circuitry, such as a circuit for providing voltage to bit line 110.

[0061] With the above configuration, the second selector 132 can be formed simultaneously with the formation of the storage transistor 121, and the lead-out portion 1321 can be formed simultaneously with the formation of the storage capacitor 122, thereby simplifying the chip formation process.

[0062] In the above embodiment, the lead-out portion 1321 includes metal to improve the conductivity of the lead-out portion 1321, thereby facilitating the lead-out of the second selector tube 132.

[0063] Reference Figure 7 , Figure 9 In embodiments where multiple memory layers 140 are included, stacking multiple memory layers 140 can increase the chip's storage capacity. Two adjacent memory layers 140 have two bit lines 110 spaced apart along the Z-direction, and two leads 1321 connected to the two bit lines 110 spaced apart along the Z-direction are connected in the Z-direction. Through this arrangement, multiple second selectors 132 arranged in the Z-direction can be simultaneously brought out, reducing the number of second selector 132 lead-out structures in the memory array 100 and simplifying the chip's complexity.

[0064] Please refer to Figure 2 and Figure 5 In an embodiment where the memory 10 includes a controller 200, the controller 200 is connected to a first selector 131 and a second selector 132, and the controller 200 is used to control the opening or closing of the first selector 131 and the second selector 132. Figure 10 As shown, Figure 10 This is a timing diagram of the memory 10 access process in an embodiment of this application. The access process may include a standby phase, a charge sharing phase, an amplification phase, and a write-back phase. Throughout the entire access process of the memory 10, the board line PL connected to the storage capacitor 122 in the storage cell 120 is always configured to a fixed potential.

[0065] During the standby phase, the controller 200 controls the first selector 131 connected to all bit lines 110 to turn off and the second selector 132 to turn on, so as to pre-energize the bit lines 110 to a predetermined voltage.

[0066] In this configuration, the second selector 132 (MUX02) is turned on, and the first selector 131 (MUX01) is turned off, pre-energizing the bit line 110 (BL) to a predetermined voltage Vw. At the same time, all word lines 123 (VWL) are not set, and VWL is at 0 voltage (V0).

[0067] During the charge sharing phase, for the first gate 131 and the second gate 132 connected to the selected bit line 110, the controller 200 controls the second gate 132 to be turned off and controls the first gate 131 to be turned on; for the first gate 131 and the second gate 132 connected to the unselected bit line 110, the controller 200 controls the second gate 132 to remain on and controls the first gate 131 to remain off.

[0068] Specifically, MUX02 connected to the selected bit line BL is turned off, and MUX01 is turned on, so that the selected bit line BL is in a floating state; and the selected VWL is set, so that the storage transistor 121 in the corresponding storage cell 120 is turned on, and the charge in the corresponding storage capacitor 122 is shared with the charge in the selected bit line; for example, if the selected storage capacitor 122 is fully charged, some of the charge in the storage capacitor 122 will move to the selected bit line BL through the storage transistor 121, causing the voltage of the selected bit line BL to rise (e.g., Figure 10 The voltage of BL rises from Vw to Vrd1; if the storage capacitor 122 is empty, some charge in the selected bit line BL will move to the storage capacitor 122 through the storage transistor 121, causing the voltage of the selected bit line BL to decrease (e.g., Figure 10 The voltage in BL drops from Vw to Vrd0.

[0069] Meanwhile, the first selector 131 connected to the unselected center line remains closed, the second selector 132 connected to the unselected center line remains open, and a predetermined voltage is maintained on the unselected center line.

[0070] During the amplification stage, the first selector 131 connected to the selected bit line remains on, the second selector 132 remains off, and the word line 123 remains set. A differential amplifier connects two bit lines 110, which are respectively connected to the selected bit line BL in one memory array 100 and the corresponding bit line BLN in another memory array 100. The voltage of the selected bit line will rise or fall, while the voltage of the corresponding bit line BLN in the other memory array 100 remains at a predetermined voltage. Thus, the differential amplifier compares the voltages of the selected bit line BL and the corresponding bit line BLN and amplifies the voltage difference to determine whether the selected storage capacitor 122 stores a "1" or a "0", and outputs the data. Then, if the voltage of the selected bit line BL is higher than that of the corresponding bit line BLN, the controller 200 adjusts the voltage of the selected bit line BL to the operating voltage (e.g., ...). Figure 10 The voltage of the selected bit line BL rises from Vrd1 to Vcore); if the voltage of the selected bit line BL is lower than that of the corresponding bit line BLN, the controller 200 adjusts the voltage of the selected bit line BL to V0 (e.g., the voltage of ...). Figure 10 The voltage of BL in the middle drops from Vrd0 to V0.

[0071] During the write-back phase, the first selector 131 connected to the selected bit line BL remains on, the second selector 132 remains off, and the word line 123 remains set. The storage capacitor 122 is written back based on the current voltage of the selected bit line BL. For example, if the storage capacitor 122 in the read storage cell 120 represents "1", then the charge in the storage capacitor 122 is fully charged. During the read process, the charge in the storage capacitor 122 moves to the selected bit line BL, causing the voltage of the selected bit line BL to rise, and the charge in the storage capacitor 122 to decrease. Before the write-back phase, if the voltage of the selected bit line BL rises to Vcore, then the selected bit line BL can charge the storage capacitor 122, restoring it to a fully charged state, thus completing the data write-back. If the storage capacitor 122 in the read storage cell 120 is represented as "0", then the charge in the storage capacitor 122 is empty. During the reading process, the charge in the selected bit line BL moves to the storage capacitor 122, causing the voltage of the selected bit line BL to drop and the charge in the storage capacitor 122 to increase. Before the write-back stage, the voltage of the selected bit line BL drops to V0, so the storage capacitor 122 can discharge to the selected bit line BL, restoring it to an empty state and completing the data write-back.

[0072] In the standby state, the first selector 131 (MUX01) of the selected bit line BL is turned off, and the second selector 132 (MUX02) of the selected bit line BL is turned on, so that the first selector 131 connected to all bit lines 110 is in the off state and the second selector 132 is in the on state, so as to pre-energize the bit line 110 to a predetermined voltage Vw.

[0073] With the above settings, during the access process of memory 10, the first selector 131 connected to the unselected bit line remains in the off state and the second selector 132 remains in the on state, so that the unselected bit line maintains a predetermined voltage, reducing the change in charge in the memory cell 120 connected to the unselected bit line, thereby reducing the refresh frequency of the memory cell 120 and reducing the power consumption of the chip. Reducing the refresh frequency of the memory cell 120 also reduces the switching frequency of the first selector 131 and the second selector 132 connected to the unselected bit line, which can also reduce the power consumption of the chip.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A chip, characterized in that, include: A substrate and a memory array disposed on the substrate, the memory array comprising: At least one storage layer, the storage layer comprising: Multiple bit lines, the bit lines extending along a first direction, the multiple bit lines being spaced apart along a second direction, the first direction and the second direction intersecting and both being parallel to the substrate; Multiple storage cells are connected to a bit line, and the multiple storage cells connected to the same bit line are spaced apart along a first direction. The storage cells are used to store data. A plurality of first gates and a plurality of second gates, each of the bit lines being connected to one of the first gates and one of the second gates.

2. The chip according to claim 1, characterized in that, The storage layer includes a first connection portion and a second connection portion, and a plurality of bit lines are located between the first connection portion and the second connection portion; a first end of the bit line is connected to the first connection portion through a first gate, and a second end of the bit line is connected to the second connection portion through a second gate; on the same bit line, the first gate, a plurality of storage cells, and the second gate are arranged sequentially at intervals along a first direction.

3. The chip according to claim 2, characterized in that, The multiple memory cells connected to the same bit line are all located on the same side of the bit line.

4. The chip according to claim 1, characterized in that, The storage layer further includes a third connection portion, and the plurality of bit lines are all located on the same side of the third connection portion; the first end of the bit line is connected to the third connection portion through the first gate, and the second gate is located between the plurality of storage cells.

5. The chip according to claim 4, characterized in that, Multiple memory cells connected to the same bit line and the second gate are all located on the same side of the bit line.

6. The chip according to claim 5, characterized in that, The memory cell includes a memory transistor and a memory capacitor. The memory capacitor is connected to the bit line through the memory transistor. The memory transistor and the memory capacitor are arranged along a second direction. The memory array also includes a lead-out portion. The lead-out portion is connected to the bit line through a second gate transistor. The second gate transistor and the lead-out portion are arranged along a second direction. The second selector and the storage transistor, which are connected to the same bit line, are spaced apart along a first direction, and the lead-out portion and the storage capacitor, which are connected to the same bit line, are spaced apart along the first direction.

7. The chip according to claim 6, characterized in that, The lead-out portion comprises a metallic material.

8. The chip according to claim 7, characterized in that, The storage layer comprises multiple layers, which are stacked along a third direction; the third direction is perpendicular to the first direction and the second direction.

9. The chip according to claim 8, characterized in that, Two adjacent memory layers have two bit lines spaced apart along a third direction, and two leads connected to the two bit lines spaced apart along a third direction are connected in the third direction.

10. A memory, characterized in that, The memory includes a controller and a chip according to any one of claims 1-9, wherein the controller is electrically connected to the chip.

11. The memory according to claim 10, characterized in that, The controller is connected to the first gate and the second gate, and the controller is used to control the opening or closing of the first gate and the second gate; Specifically, the controller controls the first gate connected to all the bit lines to turn off and the second gate connected to turn on, so as to pre-energize the bit lines to a predetermined voltage; then, for the first gate and the second gate connected to the selected bit lines, the controller controls the second gate to turn off and controls the first gate to turn on; for the first gate and the second gate connected to the unselected bit lines, the controller controls the second gate to remain on and controls the first gate to remain off.

12. An electronic device, characterized in that, It includes a circuit board and the memory as described in claim 10 or 11, the memory being disposed on and connected to the circuit board.

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