Memory, access method thereof and electronic equipment
By dividing the word lines of the memory cell array into multiple word line groups and using gating sub-circuits to connect them to different word line drivers, the problem of excessive word line drivers is solved, the device area and cost are reduced, and the layout difficulty is simplified.
Patent Information
- Application Number
- CN202411140868.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2026-03-03
AI Technical Summary
In semiconductor devices, as critical dimensions shrink and the number of devices increases, the excessive number of word line drivers leads to increased device area and cost, and increases layout difficulty.
By dividing the word lines of the memory cell array into multiple word line groups, each word line group is connected to a different word line driver, reducing the number of word line drivers, and using a gating sub-circuit to activate and deactivate the word lines.
It reduces the number of word line drivers, lowers device area and cost, simplifies layout, and improves device integration.
Smart Images
Figure CN121604394A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.
[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0005] This application provides a memory and its access method, as well as an electronic device, which reduces the number of word line drivers.
[0006] This application provides a memory, including: a multilayer memory cell array stacked perpendicular to the substrate direction; the memory cell array includes: a plurality of memory cells arrayed along a first direction and a second direction.
[0007] The memory further includes: multiple word lines extending perpendicular to the substrate and distributed along a first direction and a second direction; the memory cell array further includes: multiple bit lines extending along the second direction and spaced apart along the first direction; each bit line connects to a column of memory cells distributed along the second direction; the word lines connect multiple memory cells at the same position in different layers; and the word lines in the same column distributed along the second direction are divided into K first word line groups; the word lines of the memory cell array are divided into multiple second word line groups, each second word line group including K rows of word lines, and each word line in the K rows of word lines is connected to a different first word line driver;
[0008] Alternatively, the memory may further include: multiple bit lines extending perpendicular to the substrate and distributed along a first direction and a second direction; the memory cell array may further include: multiple word lines extending along the second direction and spaced apart along the first direction; each word line connects to a column of memory cells distributed along the second direction, and the bit lines connect multiple memory cells at the same position in different layers; and the multiple layers of word lines distributed in the same column perpendicular to the substrate are divided into K first word line groups; the word lines of the memory cell array are divided into multiple second word line groups, each second word line group including K layers of word lines, and each word line in the K layers of word lines is connected to a different first word line driver;
[0009] Each word line corresponds to a gating sub-circuit, and the word lines of the same first word line group are respectively connected to the same first word line driver through the corresponding gating sub-circuit; the word lines of the same second word line group are respectively connected to the same second word line driver through the corresponding gating sub-circuit, wherein K is greater than or equal to 2, and the first direction and the second direction are parallel to the substrate and intersect.
[0010] In some embodiments, adjacent word lines in the same first word line group are spaced apart by K-1 word lines; every K consecutive rows or K layers of word lines are divided into a second word line group.
[0011] In some embodiments, K = 2.
[0012] In some embodiments, the gating sub-circuit and the memory cell array are located on the same die, but on a different die from the first word line driver and the second word line driver.
[0013] In some embodiments, the gating sub-circuit includes a first transistor and a second transistor, the first transistor and the second transistor having opposite polarities, the first transistor including a first gate electrode, a first electrode and a second electrode, and the second transistor including a second gate electrode, a third electrode and a fourth electrode;
[0014] The first gate electrode and the second gate electrode are connected to the first word line driver. The first electrode is connected to a preset voltage terminal, the second electrode is connected to the third electrode and to the output terminal, and the fourth electrode is connected to the second word line driver; or, the first gate electrode and the second gate electrode are connected to the second word line driver. The first electrode is connected to the preset voltage terminal, the second electrode is connected to the third electrode and to the output terminal, and the fourth electrode is connected to the first word line driver.
[0015] The output terminal is connected to the word line corresponding to the gating sub-circuit.
[0016] In some embodiments, the first transistor is an N-type transistor and the second transistor is a P-type transistor.
[0017] In some embodiments, the first word line driver is loaded with an on-state voltage and an off-state voltage, the second word line driver is loaded with a first voltage and a second voltage, the preset voltage terminal is loaded with the first voltage, wherein the first voltage is less than the off-state voltage and the second voltage is greater than the on-state voltage.
[0018] This disclosure provides an access method applied to the aforementioned memory, including:
[0019] During the data read / write phase, based on the first word line group and the second word line group to which the word line connected to the target memory cell to be operated belongs, corresponding signals are loaded on the first word line driver connected to the word line of the first word line group and the second word line driver connected to the word line of the second word line group, so as to output an activation signal to the target memory cell through the gating sub-circuit.
[0020] In some embodiments, applying corresponding signals to the first word line driver connected to the word lines of the first word line group and the second word line driver connected to the word lines of the second word line group includes:
[0021] When the first gate electrode and the second gate electrode are connected to the first word line driver and the fourth electrode is connected to the second word line driver, a signal opposite to the activation level signal level is loaded in the first word line driver and an activation level signal is loaded in the second word line driver.
[0022] When the first gate electrode and the second gate electrode are connected to the second word line driver, and the fourth electrode is connected to the first word line driver, a signal opposite to the activation level signal level is loaded in the second word line driver, and an activation level signal is loaded in the first word line driver.
[0023] This disclosure provides an electronic device including any of the memory described above.
[0024] This application includes a memory and its access method, and an electronic device. The memory includes: a multilayer memory cell array stacked perpendicular to a substrate direction; multiple word lines extending perpendicular to the substrate and distributed along a first direction and a second direction; each word line corresponds to a gating sub-circuit; the first direction and the second direction are parallel to the substrate and intersect; the memory cell array includes: multiple memory cells distributed along the first direction and the second direction; multiple bit lines extending along the second direction and spaced apart along the first direction; each bit line connects to a column of memory cells distributed along the second direction; the word lines connect multiple memory cells at the same position in different layers; word lines in the same column distributed along the second direction are divided into K first word line groups; word lines in the same first word line group are respectively connected to the same first word line driver through corresponding gating sub-circuits; K is greater than or equal to 2; the word lines of the memory cell array are divided into multiple second word line groups; each second word line group includes K rows of word lines, and each word line in the K rows of word lines is connected to a different first word line driver; word lines in the same second word line group are respectively connected to the same second word line driver through corresponding gating sub-circuits. The solution provided in this disclosure can reduce the number of word line drivers in the bit line extension direction and thus reduce the number of word line drivers.
[0025] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.
[0026] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description
[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0028] Figure 1 A schematic diagram of a memory provided for an exemplary embodiment;
[0029] Figure 2 A schematic diagram showing the connection between each column of word lines and the first word line driver, provided for an exemplary embodiment;
[0030] Figure 3 A schematic diagram showing the connection between a word line and a first word line driver and a second word line driver, provided for an exemplary embodiment;
[0031] Figure 4 A schematic diagram of a gating subcircuit is provided for an exemplary embodiment;
[0032] Figure 5A schematic diagram of a gating subcircuit is provided for another exemplary embodiment;
[0033] Figure 6 A schematic diagram showing the connection between a gating sub-circuit and a first word line driver and a second word line driver, provided as an exemplary embodiment;
[0034] Figure 7 A schematic diagram of the connection between a memory chip and a peripheral circuit chip is provided for an exemplary embodiment. Detailed Implementation
[0035] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.
[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.
[0037] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values shown in the drawings.
[0038] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.
[0039] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.
[0040] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.
[0041] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0042] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.
[0043] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0044] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0045] Figure 1 A schematic diagram of a memory provided for an exemplary embodiment. (See diagram below.) Figure 1 As shown, the memory includes a multilayer array of memory cells stacked along a direction perpendicular to the substrate. Figure 1 The diagram shows only one layer, along with multiple word lines (WLs) extending perpendicular to the substrate direction. Each layer of the memory cell array may include multiple memory cells 11 arrayed along a first direction X and a second direction Y, and multiple bit lines (BLs, not shown in the diagram) extending along the second direction Y. Multiple bit lines in the same layer are spaced apart along the first direction X. Memory cells 11 in the same column of the same layer distributed along the second direction Y are connected to the same BL. Memory cells 11 in different columns are connected to different BLs. Memory cells 11 at the same position in different layers are connected to the same WL. Multiple WLs are arrayed along the first direction X and the second direction Y.
[0046] In one technical solution, a row of word lines can be connected to a first word line driver, and a column of word lines can be connected to a second word line driver. A word line is selected by the first drive signal of the first word line driver and the second drive signal of the second word line driver. When there are M rows and N columns of word lines, M+N word line drivers are required. In this solution, the number of word line drivers is relatively large.
[0047] The storage unit 11 includes, but is not limited to, a 1T1C storage unit.
[0048] Each word line corresponds to a gating sub-circuit 20. The word lines are connected to the first word line driver SWD_X and the second word line driver SWD_Y through the corresponding gating sub-circuit 20.
[0049] Word lines distributed along the second direction Y in the same column are divided into K first word line groups. Word lines within the same first word line group are connected to the same first word line driver SWD_X via corresponding gating sub-circuits 20. Word lines from different first word line groups are connected to different first word line drivers SWD_X. Word lines in different first word line groups do not overlap; that is, a word line belongs to only one first word line group. Taking a memory cell array with N columns of word lines as an example, K*N first word line drivers SWD_X are required. K is greater than or equal to 2. For example, K could be 2, 3, or 4.
[0050] In some embodiments, adjacent word lines in the same first word line group may be spaced apart by K-1 word lines.
[0051] For example, such as Figure 2 As shown, when K=2, the 1st, 3rd, 5th, ..., M-1th word lines in the same column are in one first word line group, and the 2nd, 4th, 6th, ..., Mth word lines in the same column are in another first word line group. Adjacent word lines in the same first word line group are separated by one word line (for example, the 1st and 3rd word lines are separated by the 2nd word line). Adjacent word lines in the same first word line group refer to two word lines that are adjacent in position after the word lines in the first word line group are arranged in the order of the word lines in that column. In this case, 2N first word line drivers SWD_X(i) are needed, where i is from 0 to 2N-1. For example... Figure 2 As shown, the word line in the first column of row 1, 3, 5, ..., M-1 is connected to SWD_X(0), the word line in the first column of row 2, 4, 6, ..., M is connected to SWD_X(1), the word line in the second column of row 1, 3, 5, ..., M-1 is connected to SWD_X(2), the word line in the second column of row 2, 4, 6, ..., M is connected to SWD_X(3), and so on. The word line in the Nth column of row 1, 3, 5, ..., M-1 is connected to SWD_X(2N-2), and the word line in the Nth column of row 2, 4, 6, ..., M-1 is connected to SWD_X(2N-1).
[0052] In some embodiments, within M rows of word lines, K rows of word lines form a second word line group, and each word line in these K rows is connected to a different first word line driver SWD_X. Word lines within the same second word line group are connected to the same second word line driver SWD_Y via corresponding gating sub-circuits. Word lines from different second word line groups are connected to different second word line drivers SWD_Y. Word lines in different second word line groups do not overlap; that is, a word line belongs to only one second word line group. Taking a memory cell array comprising M rows of word lines as an example, M / K second word line drivers SWD_Y are required.
[0053] In some embodiments, a second word line group can be formed every K consecutive lines of word lines.
[0054] For example, such as Figure 3 As shown, the word lines in rows 1 and 2 are in one second word line group, the word lines in rows 3 and 4 are in another second word line group, and so on, with the word lines in rows M-1 and M in another second word line group. At this point, M / 2 second word line drivers SWD_Y(j) are needed, where j is from 0 to M / 2-1. The word lines in rows 1 and 2 are connected to SWD_Y(0), the word lines in rows 3 and 4 are connected to SWD_Y(1), and so on, with the word lines in rows M-1 and M connected to SWD_Y(M / 2-1).
[0055] Therefore, when K=2, the number of word line drivers required for this memory cell array is 2N+M / 2. Compared to the scheme using M+N word line drivers, when M>>N, the number of word line drivers can be greatly reduced, which can reduce device area, lower cost, and make layout easier. Typically, M is 512 or even more, and N is less than or equal to 50. M+N-(2N+M / 2)=M / 2-N. When M is large, the number of word line drivers can be greatly reduced.
[0056] In some embodiments, multiple consecutive word lines in the same column can be divided into a first word line group, and multiple non-consecutive word lines can be divided into a second word line group. The division into first and second word line groups ensures that word lines in the second word line group are connected to different first word line drivers, and word lines in the first word line group are connected to different second word line drivers. Therefore, Figure 3 The connection methods shown are merely examples, and this disclosure does not limit the scope of the embodiments. However, Figure 3 The connection method shown is relatively convenient for wiring.
[0057] In some embodiments, when the memory cell is a 1T1C memory cell, the memory cell has an active drain, a channel, and a capacitor arranged along the first direction X. Therefore, the dimension 'a' along the first direction X is larger than the dimension 'b' along the second direction Y. Consequently, the layout difficulty of the second word line driver SWD_Y is greater than that of the first word line driver SWD_X. Therefore, reducing the number of second word line drivers SWD_Y can reduce the layout difficulty of SWD_Y without significantly affecting the layout difficulty of the first word line driver SWD_X. A suitable K value can be determined by balancing the layout difficulty and the number of word line drivers.
[0058] The selection sub-circuit 20 can have various structures, and a word line can be selected by using the first word line driver SWD_X and the second word line driver SWD_Y. In some embodiments, the selection sub-circuit 20 can be an inverter. Figure 4 Equivalent circuit diagrams of the gating sub-circuit 20 provided for some embodiments. For example... Figure 4 As shown, the gating sub-circuit 20 may include a first transistor T1 and a second transistor T2. The first transistor T1 includes a first gate electrode G1, a first electrode E11, and a second electrode E12. The second transistor T2 includes a second gate electrode G2, a third electrode E21, and a fourth electrode E22. The first gate electrode G1 and the second gate electrode G2 are connected to the first word line driver SWD_X. The first electrode E11 is connected to the preset voltage terminal Vkk. The second electrode E12 is connected to the third electrode E21 and is also connected to the output terminal SWD. The fourth electrode E22 is connected to the second word line driver SWD_Y. The output terminal SWD can be connected to the word line corresponding to the gating sub-circuit.
[0059] In some embodiments, the first transistor T1 and the second transistor T2 have opposite polarities. For example, the first transistor T1 may be an N-type transistor and the second transistor T2 may be a P-type transistor.
[0060] When the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, the operation of the selection sub-circuit 20 is as follows: When the first word line driver SWD_X is loaded with a high-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the voltage at the preset voltage terminal is applied to the output terminal SWD. At this time, the voltage of the second word line driver SWD_Y can be the first voltage Vkk. When the first word line driver SWD_X is loaded with a low-level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the voltage Vpp of the second word line driver SWD_Y is applied to the output terminal SWD. The voltage of the second word line driver SWD_Y can be the second voltage Vpp. The voltage applied to the first word line driver SWD_X can be 0 or VDD, and the voltage applied to the second word line driver SWD_Y can be the first voltage Vkk or the second voltage Vpp. The preset voltage terminal is loaded with the first voltage, where the first voltage Vkk < 0 and the second voltage Vpp > VDD. The signal at the output terminal SWD is applied to the corresponding word line, thereby activating or deactivating the memory cell connected to that word line. That is, the output terminal can output a first voltage Vkk or a second voltage Vpp, one of which serves as the activation signal for the memory cell, and the other as the deactivation signal. When an activation level signal needs to be output to the corresponding word line, since the selection sub-circuit 20 is an inverter, a signal with the opposite level to the activation level signal can be applied to the first word line driver SWD_X. For example, when the activation level signal is Vpp, the first word line driver SWD_X applies a low-level signal; when the activation level signal is Vkk, the first word line driver SWD_X applies a high-level signal.
[0061] In some embodiments, VDD is, for example, 1.1 volts (V) to 1.2V, Vkk is, for example, -0.5V to -0.3V, and Vpp is, for example, 2.5V to 3.0V. This is merely an example, and the embodiments disclosed herein are not limited thereto; other values may be set as needed.
[0062] In some embodiments, such as Figure 5 As shown, the first gate electrode G1 and the second gate electrode G2 can be connected to the second word line driver SWD_Y, and the fourth electrode E22 can be connected to the first word line driver SWD_X. At this time, the voltage applied to the second word line driver SWD_Y is 0 or VDD, and the voltage applied to the first word line driver SWD_X can be either a first voltage Vkk or a second voltage Vpp.
[0063] Figure 6 This is a schematic diagram illustrating the connection between the gating sub-circuit and the first word line driver and the second word line driver, as provided in some embodiments. Figure 6As shown, the memory includes M rows and N columns of word lines, 2N first word line drivers SWD_X(i), where i is from 0 to 2N-1, and M / 2 second word line drivers SWD_Y(j), where j is from 0 to M / 2-1. The first word line drivers SWD_X(i) and the second word line drivers SWD_Y(j) are connected to a gating sub-circuit 20. The gating sub-circuit 20 outputs signals to the corresponding word lines through its output terminal SWD_ij. Therefore:
[0064] The word line in the first row and first column is connected to SWD_00, the word line in the first row and second column is connected to SWD_20, the word line in the first row and third column is connected to SWD_40, and so on, with the word line in the first row and Nth column connected to SWD_(2N-2)0.
[0065] The word line in the 2nd row and 1st column is connected to SWD_10, the word line in the 2nd row and 2nd column is connected to SWD_30, the word line in the 2nd row and 3rd column is connected to SWD_50, and so on, with the word line in the 2nd row and Nth column connected to SWD_(2N-1)0.
[0066] The word line in the 3rd row and 1st column is connected to SWD_01, the word line in the 3rd row and 2nd column is connected to SWD_21, the word line in the 3rd row and 3rd column is connected to SWD_41, and so on, with the word line in the 3rd row and Nth column connected to SWD_(2N-2)1.
[0067] The word line in the 4th row and 1st column is connected to SWD_11, the word line in the 4th row and 2nd column is connected to SWD_31, the word line in the 4th row and 3rd column is connected to SWD_51, and so on, with the word line in the 4th row and Nth column connected to SWD_(2N-1)1.
[0068] Similarly, the word line in the first column of row M-1 is connected to SWD_0(M / 2-1), the word line in the second column of row M-1 is connected to SWD_2(M / 2-1), the word line in the third column of row M-1 is connected to SWD_4(M / 2-1), and so on, with the word line in the Nth column of row M-1 connected to SWD_(2N-2)(M / 2-1);
[0069] The word line in row M, column 1 is connected to SWD_1(M / 2-1), the word line in row M, column 2 is connected to SWD_3(M / 2-1), the word line in row M, column 3 is connected to SWD_5(M / 2-1), and so on, with the word line in row M, column N connected to SWD_(2N-1)(M / 2-1).
[0070] In some embodiments, the gating sub-circuit 20 and the memory cell 11 may be disposed on the same die. For example... Figure 7As shown, the gating sub-circuit 20 and the storage cell 11 are disposed on the memory chip, and the first word line driver SWD_X and the second word line driver SWD_Y are disposed on the peripheral circuit chip. The peripheral circuit chip loads the signals of the first word line driver SWD_X and the second word line driver SWD_Y to the memory chip, and only K*N+M / K signals need to be transmitted between the two chips. Compared with the scheme of disposing of the gating sub-circuit 20 on the peripheral circuit chip (in which case M+N signals need to be transmitted between the two chips), the number of signals transmitted between them can be greatly reduced. The memory chip and the peripheral circuit chip can be connected by a hybrid bonding method, but the embodiments of this disclosure are not limited to this, and can be connected by other methods. Figure 7 The positions and shapes of the SWD_X and SWD_Y hybrid bonding regions shown are merely examples, and the embodiments disclosed herein are not limited thereto.
[0071] In the above embodiments, word lines extend in a direction perpendicular to the substrate, and bit lines extend in a direction parallel to the substrate. In other embodiments, the word lines may extend in a direction parallel to the substrate, and the bit lines may extend in a direction perpendicular to the substrate. That is, the memory may include a multilayer memory cell array stacked perpendicular to the substrate, and multiple bit lines distributed along a first direction X and a second direction Y extending in a direction perpendicular to the substrate; each word line corresponds to a gating sub-circuit 20;
[0072] The memory cell array may include: a plurality of memory cells 11 distributed along the first direction X and the second direction Y; a plurality of word lines extending along the second direction Y and spaced apart along the first direction X; each word line connects to a column of memory cells 11 distributed along the second direction Y; and the bit lines connect to a plurality of memory cells 11 at the same position in different layers.
[0073] The word lines distributed in multiple columns along the direction perpendicular to the substrate (i.e., word lines in the same column of each layer) are divided into K first word line groups. The word lines of the same first word line group are connected to the same first word line driver SWD_X through corresponding gating sub-circuits; K is greater than or equal to 2.
[0074] The word lines of the memory cell array are divided into multiple second word line groups. Each second word line group includes K layers of word lines, and each word line in the K layers of word lines is connected to a different first word line driver SWD_X. The word lines of the same second word line group are connected to the same second word line driver SWD_Y through corresponding gating sub-circuits 20.
[0075] In some embodiments, adjacent word lines in the same first word line group can be spaced apart by K-1 word lines (the K-1 word lines are word lines in the same column of K-1 layers). For example, when K=2, word lines in the same column of layers 1, 3, 5, ..., r-1 are in one first word line group, and word lines in the same column of layers 2, 4, 6, ..., r are in another first word line group. r is the number of layers in the memory cell array stack; the explanation will be based on an even number of r.
[0076] In some embodiments, every K consecutive word lines can be divided into a second word line group. For example, the first and second word lines are in one second word line group, the third and fourth word lines are in another second word line group, and so on, with the (r-1)th and rth word lines in another second word line group.
[0077] The embodiments disclosed herein are not limited to the above-described division of the first word line group and the second word line group. For example, multiple consecutive word lines in the same column can be divided into a first word line group, and multiple non-continuous word lines can be divided into a second word line group. The division of the first word line group and the second word line group is such that the word lines in the second word line group are all connected to different first word line drivers, and the word lines in the first word line group are all connected to different second word line drivers.
[0078] The structure of the selection sub-circuit 20 and its connection with the first word line driver SWD_X and the second word line driver SWD_Y can be referred to the previous embodiment and will not be repeated here.
[0079] This disclosure also provides an electronic device, including the memory described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0080] This disclosure provides a method for accessing the memory described above, applied to the memory described in any of the above embodiments, including:
[0081] During the data read / write phase, based on the first word line group and the second word line group to which the word line connected to the target memory cell to be operated belongs, corresponding signals are loaded on the first word line driver connected to the word line of the first word line group and the second word line driver connected to the word line of the second word line group, so as to output an activation signal to the target memory cell through the gating sub-circuit.
[0082] Selecting the circuit as Figure 4 When the circuit shown is used, applying corresponding signals to the first word line driver connected to the word lines of the first word line group and the second word line driver connected to the word lines of the second word line group includes:
[0083] The first word line driver SWD_X loads a signal with the opposite level to the activation level signal, and the second word line driver SWD_Y loads the activation level signal (here, the signal required to activate the memory cell connected to the word line); for example, the second word line driver SWD_Y loads Vpp, and the first word line driver SWD_X loads a voltage value of 0.
[0084] Selecting the circuit as Figure 5 When the circuit shown is used, applying corresponding signals to the first word line driver connected to the word lines of the first word line group and the second word line driver connected to the word lines of the second word line group includes:
[0085] The second word line driver SWD_Y loads a signal with the opposite level to the activation level signal, while the first word line driver SWD_X loads the activation level signal. For example, the first word line driver SWD_X loads Vpp, and the second word line driver SWD_Y loads a voltage value of 0.
[0086] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.
Claims
1. A memory, characterized in that, include: A multilayer memory cell array stacked perpendicular to the substrate direction; The storage cell array includes a plurality of storage cells distributed along the first direction and the second direction; The memory further includes: multiple word lines extending perpendicular to the substrate and distributed along a first direction and a second direction, the word lines connecting multiple memory cells at the same position on different layers; the memory cell array further includes: multiple bit lines extending along the second direction and spaced apart along the first direction; each bit line connects to a column of memory cells distributed along the second direction; and the word lines in the same column distributed along the second direction are divided into K first word line groups; the word lines of the memory cell array are divided into multiple second word line groups, each second word line group including K rows of word lines, and each word line in the K rows of word lines is connected to a different first word line driver; Alternatively, the memory may further include: multiple bit lines extending perpendicular to the substrate and distributed along a first direction and a second direction, the bit lines connecting multiple memory cells at the same position on different layers; the memory cell array may further include: multiple word lines extending along the second direction and spaced apart along the first direction; each word line connects to a column of memory cells distributed along the second direction, and the multiple layers of word lines in the same column distributed perpendicular to the substrate are divided into K first word line groups; the word lines of the memory cell array are divided into multiple second word line groups, each second word line group including K layers of word lines, and each word line in the K layers of word lines is connected to a different first word line driver; Each word line corresponds to a gating sub-circuit, and the word lines of the same first word line group are respectively connected to the same first word line driver through the corresponding gating sub-circuit; the word lines of the same second word line group are respectively connected to the same second word line driver through the corresponding gating sub-circuit, wherein K is greater than or equal to 2, and the first direction and the second direction are parallel to the substrate and intersect.
2. The memory according to claim 1, characterized in that, Adjacent word lines in the same first word line group are spaced K-1 word lines apart; every K consecutive rows or K layers of word lines are divided into a second word line group.
3. The memory according to claim 1, characterized in that, The value of K is 2.
4. The memory according to claim 1, characterized in that, The gating sub-circuit and the memory cell array are located on the same die, but on a different die from the first word line driver and the second word line driver.
5. The memory according to any one of claims 1 to 4, characterized in that, The gating sub-circuit includes a first transistor and a second transistor, the first transistor and the second transistor having opposite polarities, the first transistor including a first gate electrode, a first electrode and a second electrode, and the second transistor including a second gate electrode, a third electrode and a fourth electrode; The first gate electrode and the second gate electrode are connected to the first word line driver. The first electrode is connected to a preset voltage terminal. The second electrode is connected to the third electrode and to the output terminal. The fourth electrode is connected to the second word line driver. Alternatively, the first gate electrode and the second gate electrode are connected to the second word line driver, the first electrode is connected to a preset voltage terminal, the second electrode is connected to the third electrode and to the output terminal, and the fourth electrode is connected to the first word line driver. The output terminal is connected to the word line corresponding to the gating sub-circuit.
6. The memory according to claim 5, characterized in that, The first transistor is an N-type transistor, and the second transistor is a P-type transistor.
7. The memory according to claim 6, characterized in that, The first word line driver is loaded with an on-state voltage and an off-state voltage. The second word line driver is loaded with a first voltage and a second voltage. The preset voltage terminal is loaded with the first voltage, wherein the first voltage is less than the off-state voltage and the second voltage is greater than the on-state voltage.
8. An access method, characterized in that, Applied to the memory as described in any one of claims 1 to 7, comprising: During the data read / write phase, based on the first word line group and the second word line group to which the word line connected to the target memory cell to be operated belongs, corresponding signals are loaded on the first word line driver connected to the word line of the first word line group and the second word line driver connected to the word line of the second word line group, so as to output an activation signal to the target memory cell through the gating sub-circuit.
9. The access method according to claim 8, characterized in that, The memory is the memory as described in claim 7, and loading corresponding signals on the first word line driver connected to the word lines of the first word line group and the second word line driver connected to the word lines of the second word line group includes: When the first gate electrode and the second gate electrode are connected to the first word line driver and the fourth electrode is connected to the second word line driver, a signal opposite to the activation level signal level is loaded in the first word line driver and an activation level signal is loaded in the second word line driver. When the first gate electrode and the second gate electrode are connected to the second word line driver, and the fourth electrode is connected to the first word line driver, a signal opposite to the activation level signal level is loaded in the second word line driver, and an activation level signal is loaded in the first word line driver.
10. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 7.