Reverse conducting IGBT (Insulated Gate Bipolar Translator) device, manufacturing method and chip

Abstract

The embodiment of the invention provides a reverse conducting IGBT device, a manufacturing method and a chip. The reverse conducting IGBT device comprises an N-type substrate; the grooves are arranged at intervals in the transverse direction and are parallel to one another, and the gate oxide layers are located on the side walls and the bottoms of the grooves; the polycrystalline silicon layer is located on the gate oxide layer and fills the internal space of the groove; the device comprises a buried P layer, a carrier storage N layer, a P-type well, an N + electron emission region and a hole injection P + region. Through a Schottky diode structure composed of an N-type region and front Schottky metal and a buried P layer, a barrier n layer is communicated with a columnar n region, and electron current directly flows to a surface electrode through the n region and does not enter a top p layer and a P + layer, so that forward bias of a top p / barrier n interface is avoided, hole injection from the top p layer is inhibited, and the performance of the Schottky diode is improved. Compared with the prior art, the IGBT structure has low hole injection efficiency, the reverse recovery loss of the diode part can be reduced, and the on resistance of the IGBT part can be reduced by the carrier storage N layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a reverse-conducting IGBT device, its manufacturing method, and a chip. Background Technology

[0002] A reverse-conducting insulated-gate bipolar transistor (RC-IGBT) is a power device that integrates an insulated-gate bipolar transistor (IGBT) and a fast recovery diode (FRD) on the same semiconductor substrate. By sharing part of the drift region and termination structure, it achieves a significant reduction in chip area, which is beneficial for increasing power density and reducing packaging costs. To achieve low-power operation, the losses of both the IGBT and FRD cells must be reduced simultaneously. However, there is an inherent contradiction between the two in terms of performance optimization. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a reverse-conducting IGBT device, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0004] To address the aforementioned problems, this invention discloses a reverse-conducting IGBT device, which includes: N-type substrate; Multiple trenches are arranged laterally at intervals and parallel to each other, located in a first region and a second region of the N-type substrate; the first region includes at least one set of trenches, the number of trenches in a set of trenches is three, wherein the trenches at both ends are emitter trenches and the trench in the middle is a gate trench; the second region includes at least one trench. A gate oxide layer is located on the sidewalls and bottom of each of the trenches; A polycrystalline silicon layer is located above the gate oxide layer in the first region and fills the internal space of the trench corresponding to the gate oxide layer in the first region. A buried P-layer is located within the N-type substrate; the depth of the buried P-layer is greater than the depth of the trench. A carrier storage N-layer is located within the buried P-layer; the depth of the carrier storage N-layer is less than the depth of the trench; The P-type well is located within the N-layer of the carrier storage; The N+ electron emission region is located inside the P-type well and on both sides of the gate trench, and is connected to the sidewall region of the gate trench covered by the gate oxide layer. The hole is injected into the P+ region, which is located on the side of each N+ electron emission region away from the gate trench in the first region and is connected to the side of the N+ electron emission region; and located on both sides of the trench in the second region and connected to the sidewall region of the trench covered by the gate oxide layer. The N-type region is located in the second region, within the hole injection P+ region and the P-type well, and is connected to the carrier storage N-layer; The front Schottky metal is located on the surface of the N-type region and on a portion of the surface of the hole-injected P+ region connected to the N-type region.

[0005] Optionally, the polysilicon layer is also located above the gate oxide layer in the second region and fills the internal space of the trench corresponding to the gate oxide layer in the second region.

[0006] Optionally, the reverse-conducting IGBT device further includes: An ohmic contact metal is located on a portion of the surface of the hole-injected P+ region in the first region; An interlayer dielectric layer is located on the surface of the P-type well, a portion of the surface of the hole-injected P+ region, the surface of the N+ electron emission region, the surface of the polysilicon layer, and the surface of the gate oxide layer in the first region. The front metal layer is located on the surface of the interlayer dielectric layer in the first region, the surface of the ohmic contact metal, the surface of the hole injection P+ region in the second region, and the surface of the front Schottky metal.

[0007] Optionally, the reverse-conducting IGBT device further includes: An N-type buffer zone is located inside the back side of the N-type substrate; The back P+ region is located within the N-type buffer zone in the first region; The back N+ region is located within the N-type buffer zone in the second region.

[0008] Optionally, the polysilicon layer within the emitter trench serves as a dummy gate structure.

[0009] Accordingly, this invention discloses a method for manufacturing a reverse-conducting IGBT device, used to manufacture the reverse-conducting IGBT device as described in any of the preceding claims, the manufacturing method comprising: Provide N-type substrates; In the first and second regions of the N-type substrate, a plurality of trenches are etched to form laterally spaced and parallel trenches; the first region includes at least one set of trenches, and the number of trenches in one set is three, wherein the trenches at both ends are emitter trenches and the trench in the middle is a gate trench; the second region includes at least one trench. Thermal oxidation is performed on the sidewalls and bottom of each of the trenches to form a gate oxide layer; Polysilicon is deposited in the trench of the first region to form a polysilicon layer, which is located above the gate oxide layer of the first region and fills the internal space of the trench of the first region. P-type ions are implanted into the N-type substrate to form a buried P-layer; the depth of the buried P-layer is greater than the depth of the trench. N-type ions are injected into the buried P-layer to form a carrier storage N-layer; the depth of the carrier storage N-layer is less than the depth of the trench; P-type ions are injected into the N-layer of the carrier storage to form a P-type trap. Within the P-type well, N-type ions are implanted on both sides of the gate trench to form an N+ electron emission region; the N+ electron emission region is connected to the sidewall region of the gate trench covered by the gate oxide layer. Within the P-type well, P-type ions are implanted on the side of each N+ electron emission region away from the gate trench and on both sides of the trench in the second region to form a hole-implanted P+ region; the side of the hole-implanted P+ region in the first region is connected to the side of the N+ electron emission region; the hole-implanted P+ region in the second region is connected to the sidewall region of the trench in the diode region covered by the gate oxide layer. P+ ions are injected into the holes in the second region and N-type ions are injected into the P-type traps to form an N-type region; the N-type region is connected to the N-layer of carrier storage. A front-side Schottky metal is formed on the surface of the N-type region and a portion of the surface of the P+ region injected through the hole connected to the N-type region.

[0010] Optionally, the method further includes: Polysilicon is deposited in each trench of the second region to form a polysilicon layer, which is located above the gate oxide layer of the second region and fills the interior space of each trench of the second region.

[0011] Optionally, the method further includes: A portion of the surface of the P+ region is injected through a hole in the first region to form an ohmic contact metal; An interlayer dielectric layer is formed on the surface of the P-type well, a portion of the surface of the hole-injected P+ region, the surface of the N+ electron emission region, the surface of the polysilicon layer, and the surface of the gate oxide layer in the first region. A front metal layer is formed on the surface of the interlayer dielectric layer in the first region, the surface of the ohmic contact metal, the surface of the hole-injected P+ region in the second region, and the surface of the front Schottky metal.

[0012] Optionally, the method further includes: N-type ions are implanted on the back side of the N-type substrate to form an N-type buffer zone; P-type ions are injected into the N-type buffer zone in the first region to form the backside P+ region; N-type ions are injected into the N-type buffer zone in the second region to form a backside N+ region; A back metal layer is formed on the surface of the back P+ region and the back N+ region.

[0013] Optionally, before implanting N-type ions on the back side of the N-type substrate to form an N-type buffer, the method further includes: The back side of the N-type substrate is thinned.

[0014] Optionally, the polysilicon layer within the emitter trench serves as a dummy gate structure.

[0015] Accordingly, embodiments of the present invention disclose a chip including the reverse-conducting IGBT device as described in any of the preceding claims.

[0016] The embodiments of the present invention have the following advantages: The reverse-conducting IGBT device of this invention includes: an N-type substrate; a plurality of trenches arranged laterally at intervals and parallel to each other, located in a first region and a second region of the N-type substrate; the first region includes at least one set of trenches, the number of trenches in one set being three, wherein the trenches at both ends are emitter trenches and the trench in the middle is a gate trench; the second region includes at least one trench; a gate oxide layer located on the sidewalls and bottom of each trench; a polysilicon layer located above the gate oxide layer and filling the internal space of the trench; a buried P layer located within the N-type substrate; the depth of the buried P layer is greater than the depth of the trench; and a carrier storage N layer located within the buried P layer; the depth of the carrier storage N layer is less than the depth of the trench. The trench depth; P-type well, located within the N-layer for carrier storage; N+ electron emission region, located within the P-type well and on both sides of the gate trench, and connected to the sidewall region of the gate trench covered by the gate oxide layer; via-injected P+ region, located in the first region on the side of each N+ electron emission region away from the gate trench, and connected to the side of the N+ electron emission region; located on both sides of the trench in the second region, and connected to the sidewall region of the trench covered by the gate oxide layer; N-type region, located within the via-injected P+ region and the P-type well in the second region, and connected to the N-layer for carrier storage; front-side Schottky metal, located on the surface of the N-type region and a portion of the surface of the via-injected P+ region connected to the N-type region. This invention utilizes an N-type region, a Schottky diode structure composed of front-side Schottky metal, and a buried P-layer. The barrier n-layer and the columnar n-region are connected, allowing electron current to flow directly to the surface electrode through the n-region without entering the top p-layer and P+ layer. This avoids forward bias at the top p / barrier n-interface, thereby suppressing hole injection from the top p-layer and resulting in lower hole injection efficiency. This reduces the reverse recovery loss of the diode section. Furthermore, the carrier storage N-layer reduces the on-resistance of the IGBT section. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a reverse-conducting IGBT device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure for manufacturing a reverse-conducting IGBT device according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure for manufacturing another reverse-conducting IGBT device according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure for manufacturing another reverse-conducting IGBT device according to an embodiment of the present invention; Figure 5 This is a schematic diagram of another reverse-conducting IGBT device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of another reverse-conducting IGBT device according to an embodiment of the present invention; Figure 7This is a comparative schematic diagram of the hole concentration in the anode portion of a diode according to an embodiment of the present invention; Figure 8 This is a comparative schematic diagram of the reverse recovery time of a diode according to an embodiment of the present invention; Figure 9 This is a comparative schematic diagram of the forward voltage drop of a diode according to an embodiment of the present invention; Figure 10 This is a flowchart illustrating the manufacturing steps of a reverse-conducting IGBT device according to an embodiment of the present invention.

[0018] Reference numerals: N-type substrate 10, first region 101, second region 102, trench 11, gate oxide layer 12, polysilicon layer 13, buried P layer 14, carrier storage N layer 15, P-type well 16, N+ electron emission region 17, hole injection P+ region 18, N-type region 19, front Schottky metal 20, ohmic contact metal 21, interlayer dielectric layer 22, front metal layer 23, N-type buffer 24, back P+ region 25, back N+ region 26, back metal layer 27. Detailed Implementation

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Reverse-conducting insulated-gate bipolar transistors (IGBTs) are power devices that integrate an IGBT and a fast recovery diode (FRD) on the same semiconductor substrate. By sharing part of the drift region and termination structure, they achieve a significant reduction in chip area, which is beneficial for increasing power density and reducing packaging costs. To achieve low-power operation, it is necessary to reduce the losses of both IGBT and FRD cells. However, there is an inherent contradiction between the two in terms of performance optimization. For example, in IGBTs, hole carrier accumulation can reduce on-resistance. One example is the carrier storage structure, where the N-type CS layer acts as a barrier for holes, leading to carrier accumulation. However, in diodes, increased carrier accumulation increases reverse recovery charge and switching losses. Therefore, lifetime control is usually introduced to balance the trade-off between forward voltage and switching losses. Nevertheless, lifetime control increases the on-resistance of the IGBT. Another approach is to reduce the concentration of the P-body layer, but this affects the IGBT's threshold voltage. Furthermore, reducing the P-layer concentration only in the diode region does not prevent hole injection from the IGBT region. Optimizing FRD performance while maintaining IGBT characteristics has always been a challenge.

[0021] One of the core concepts of this invention is that, through the Schottky diode structure composed of an N-type region, a front-side Schottky metal, and a buried P-layer, the barrier n-layer and the columnar n-region are connected. The electron current flows directly to the surface electrode through the n-region without entering the top p-layer and P+ layer. This avoids the forward bias of the top p / barrier n-interface, thereby suppressing hole injection from the top p-layer, resulting in lower hole injection efficiency. This reduces the reverse recovery loss of the diode section. Furthermore, the carrier storage N-layer can reduce the on-resistance of the IGBT section.

[0022] Reference Figure 1 The diagram shows a schematic of the structure of a reverse-conducting IGBT device according to an embodiment of the present invention, which may specifically include the following structure: N-type substrate 10.

[0023] The N-type substrate 10 can be a Si (silicon) substrate.

[0024] Multiple trenches 11 are arranged laterally and parallel to each other, located in the first region 101 and the first region 102 of the N-type substrate 10; the first region 101 includes at least one set of trenches 11, the number of trenches in the set of trenches 11 is three, wherein the trenches 11 at both ends are emitter trenches and the trench 11 in the middle is a gate trench; the first region 102 includes at least one trench 11.

[0025] For example, the first region 101 is the IGBT region of the N-type substrate 10, and the first region 102 is the diode region of the N-type substrate 10. The reverse-conducting IGBT device integrates the IGBT region and the diode region on the N-type substrate 10.

[0026] Reference Figure 2 Within the N-type substrate 10, multiple trenches 11 arranged laterally parallel and spaced apart are formed through processes such as growing a mask medium, photolithography, dry etching, surface oxidation, and selective etching. Exemplarily, firstly, a mask medium layer, which can be silicon dioxide or silicon nitride, is grown on the surface of the N-type substrate 10 by thermal oxidation or chemical vapor deposition (CVD) as a hard mask for subsequent etching. Next, photoresist is coated onto the mask medium layer using photolithography, and the trench pattern is transferred to the photoresist layer by exposure and development using a mask. Then, using a dry etching technique (such as reactive ion etching, RIE), the pattern is transferred from the photoresist layer to the underlying mask medium layer using the photoresist as a mask, forming a mask medium pattern. Subsequently, a dry etching process (such as deep silicon etching Bosch process or continuous etching process) is used to penetrate the N-type substrate 10, etching trench structures with predetermined depths and morphologies at designated locations.

[0027] For example, the trench 11 has a depth of 4.5 μm to 5.5 μm and a width of 0.4 μm to 1.2 μm. The trenches 11 in the first region 101 and the first region 102 are arranged separately. The trenches 11 in the first region 101 are arranged in a cycle of three trenches, while the trenches 11 in the first region 102 are arranged in a cycle of a single trench.

[0028] Gate oxide layer 12 is located on the sidewalls and bottom of each trench 11.

[0029] On the inner walls of each trench 11, i.e., the sidewalls and bottom of each trench 11, a gate oxide layer 12 is formed by sacrificial oxidation, wet etching, gate dielectric oxidation, and annealing. Exemplarily, firstly, a sacrificial oxidation process is performed, i.e., the N-type substrate 10 is placed in a high-temperature oxidation environment to grow a thin sacrificial oxide layer on the surface of the trench 11 to cover and absorb the surface damage caused during dry etching. Then, the sacrificial oxide layer is wet etched to completely remove it, thereby removing the damaged silicon surface layer and achieving repair and cleaning of the trench silicon surface. Next, a thermal oxide layer is grown on the clean inner wall of the trench 11 as the gate oxide layer 12 by a high-temperature dry oxygen oxidation or nitrogen oxidation process. Finally, a high-temperature annealing process is performed.

[0030] For example, the annealing temperature is between 1000°C and 1200°C, the annealing time is between 50 min and 150 min, and the thickness of the gate oxide layer 12 is between 600 Å and 1500 Å.

[0031] The polysilicon layer 13 is located above the gate oxide layer 12 in the first region and fills the internal space of the trench 11 corresponding to the gate oxide layer 12 in the first region.

[0032] Polysilicon is deposited and etched using LPCVD deposition process to form a polysilicon layer 13. The polysilicon layer 13 is located above the gate oxide layer 12 of the first region 101 and fills the internal space of the trench 11 corresponding to the gate oxide layer 12 of the first region 101.

[0033] A buried P-layer 14 is located within an N-type substrate 10; the depth of the buried P-layer 14 is greater than the depth of the trench 11.

[0034] Reference Figure 3 Within the N-type substrate 10, a relatively deep buried P-layer 14 is formed through processes such as growing a mask medium, photolithography, ion implantation, and high-temperature annealing. The buried P-layer 14 is obtained through high-energy ion implantation, using P-type ions. The depth of the buried P-layer 14 is greater than the depth of the trench 11. For example, the depth of the buried P-layer 14 is in the range of 5µm to 7µm, the ion implantation energy is in the range of 1.5MeV to 3MeV, and the implantation concentration is in the range of 2e¹² cm⁻¹. -2 ~3e13 cm -2 .

[0035] The N-layer 15 for carrier storage is located within the buried P-layer 14; the depth of the N-layer 15 for carrier storage is less than the depth of the trench 11.

[0036] Within the buried P-layer 14, a carrier storage N-layer 15 is formed through processes such as growing a mask medium, photolithography, ion implantation, and high-temperature annealing. The depth of the carrier storage N-layer 15 is less than the depth of the trench 11. For example, the depth of the carrier storage N-layer 15 is in the range of 2.5 μm to 5 μm, the ion implantation energy is in the range of 100 keV to 3 MeV, the implanted ions are N-type ions, and the implantation concentration is in the range of 1e12 cm⁻¹. -2 ~3e13 cm -2 .

[0037] P-type well 16 is located within the N-layer 15 of carrier storage.

[0038] Within the N-layer 15 of the charge carrier storage, a P-type well 16 is formed through processes such as growing a mask medium, photolithography, ion implantation, and high-temperature annealing. The depth of the P-type well 16 is the shallowest compared to the N-layer 15 and the buried P-layer 14. For example, the depth of the P-type well 16 is in the range of 1.5 μm to 3 μm, the ion implantation energy is in the range of 50 keV to 150 keV, the implanted ions are P-type ions, and the implantation concentration is in the range of 1e13 cm⁻¹. -2 ~5e13 cm -2 .

[0039] The N+ electron emission region 17 is located inside the P-type well 16 and on both sides of the gate trench 11, and is connected to the sidewall region of the gate trench 11 covered by the gate oxide layer 12.

[0040] Reference Figure 4 Within the P-type well 16, an N+ electron emission region 17 is formed through processes such as growing a mask medium, photolithography, and ion implantation. The N+ electron emission region 17 is located on both sides of the gate trench 11 and is connected to the sidewall region of the gate trench 11 covered by the gate oxide layer 12. The surface of the N+ electron emission region 17 is flush with the surface of the P-type well 15. Exemplarily, the ion implantation energy of the N+ electron emission region 17 ranges from 30 keV to 100 keV, and the implantation concentration ranges from 5e14 cm⁻¹. -2 ~3e15 cm -2 .

[0041] The hole-injected P+ region 18 is located in the first region 101 on the side of each N+ electron emission region 17 away from the gate trench and is connected to the side of the N+ electron emission region 17; it is located on both sides of the trench 11 in the first region 102 and is connected to the sidewall region of the trench 11 covered by the gate oxide layer 12.

[0042] Within the P-type well 16, a hole-implanted P+ region 18 is formed through processes such as growing a mask medium, photolithography, and ion implantation. The surface of the hole-implanted P+ region 18 is flush with the surface of the P-type well 16. In the first region 101, the hole-implanted P+ region 18 is located on the side of each N+ electron emission region 17 away from the gate trench and is connected to the sidewall of the N+ electron emission region 17. In the first region 102, the hole-implanted P+ region 18 is located on both sides of the trench 11 and is connected to the sidewall region of the trench 11 covered by the gate oxide layer 12. Exemplarily, the ion implantation energy of the hole-implanted P+ region 18 ranges from 30 keV to 100 keV, and the implantation concentration ranges from 5e14 cm⁻¹. -2 ~3e15cm -2 .

[0043] The N-type region 19 is located in the hole injection P+ region 18 and P-type well 16 in the first region 102, and is connected to the carrier storage N layer 15.

[0044] Within the P+ region 18 implanted in the first region 102, a relatively deep N-type region 19 is formed through processes such as growing a mask medium, photolithography, ion implantation, and annealing. The N-type region 19 penetrates the P-type well and connects to the carrier storage N-layer 15. Exemplarily, the depth of the N-type region 19 is in the range of 1.5 μm to 3 μm, the ion implantation energy is in the range of 150 keV to 1 MeV, and the implantation concentration is in the range of 2e¹² cm⁻¹. -2 ~5e13 cm -2 .

[0045] The front Schottky metal 20 is located on the surface of the N-type region 19 and on a portion of the surface of the hole-injected P+ region 18 connected to the N-type region 19.

[0046] A front-side Schottky metal 20 is formed through photolithography, metallization, lift-off processes, and Schottky annealing. The front-side Schottky metal 20 is located on the surface of the N-type region 19 and a portion of the surface of the via-implanted P+ region 18 connected to the N-type region 19. Exemplarily, the metal thickness ranges from 100 nm to 200 nm.

[0047] The reverse-conducting IGBT device of this invention includes: an N-type substrate; a plurality of trenches arranged laterally parallel and spaced apart, located in a first region and a second region of the N-type substrate; the first region includes at least one set of trenches, the number of trenches in one set being three, wherein the trenches at both ends are emitter trenches and the trench in the middle is a gate trench; the second region includes at least one trench; a gate oxide layer located on the sidewalls and bottom of each trench; a polysilicon layer located above the gate oxide layer and filling the internal space of the trench; a buried P layer located within the N-type substrate; the depth of the buried P layer is greater than the depth of the trench; and a carrier storage N layer located within the buried P layer; the depth of the carrier storage N layer is less than... The trench depth; P-type well, located within the N-layer for carrier storage; N+ electron emission region, located within the P-type well and on both sides of the gate trench, and connected to the sidewall region of the gate trench covered by the gate oxide layer; via-injected P+ region, located in the first region on the side of each N+ electron emission region away from the gate trench, and connected to the side of the N+ electron emission region; located on both sides of the trench in the second region, and connected to the sidewall region of the trench covered by the gate oxide layer; N-type region, located within the via-injected P+ region and the P-type well in the second region, and connected to the N-layer for carrier storage; front-side Schottky metal, located on the surface of the N-type region and a portion of the surface of the via-injected P+ region connected to the N-type region. This invention utilizes an N-type region, a Schottky diode structure composed of front-side Schottky metal, and a buried P-layer. The barrier n-layer and the columnar n-region are connected, allowing electron current to flow directly to the surface electrode through the n-region without entering the top p-layer and P+ layer. This avoids forward bias at the top p / barrier n-interface, thereby suppressing hole injection from the top p-layer and resulting in lower hole injection efficiency. This reduces the reverse recovery loss of the diode section. Furthermore, the carrier storage N-layer reduces the on-resistance of the IGBT section.

[0048] This invention, through the introduction of a Schottky diode structure and a buried floating P-structure into an RC-IGBT, optimizes the reverse recovery performance of the diode and reduces diode losses while maintaining IGBT performance. The buried floating P-structure prevents holes from accumulating near the trench, while the Schottky diode structure reduces holes near the diode anode, thereby reducing reverse recovery charge and effectively lowering the reverse recovery loss of the diode in the RC-IGBT.

[0049] In this embodiment of the invention, the polysilicon layer 13 is also located above the gate oxide layer 12 of the second region 102 and fills the internal space of the trench 11 corresponding to the gate oxide layer 12 of the second region 102.

[0050] The trench 11 in the second region 102 is filled with a polysilicon layer 13 in order to maintain the consistency and integrity of the process flow and ensure the uniformity and reliability of the overall manufacturing process.

[0051] Reference Figure 5The diagram illustrates a structural schematic of another reverse-conducting IGBT device according to an embodiment of the present invention. The reverse-conducting IGBT device further includes: Ohmic contact metal 21 is located on a portion of the surface of the P+ region 18 injected into the hole in the first region 101.

[0052] Ohmic contact metal 21 is formed through photolithography, metallization, and lift-off processes. Ohmic contact metal 21 is located on a portion of the surface of the P+ region 18 implanted in the hole in the first region 101. Exemplarily, the metal thickness ranges from 100 nm to 200 nm.

[0053] Interlayer dielectric layer 22 is located on the surface of P-type well 16, part of the surface of hole-injected P+ region 18, surface of N+ electron emission region 17, surface of polysilicon layer 13 and surface of gate oxide layer 12 in the first region 20.

[0054] An interlayer dielectric layer 22 is deposited in the first region 101 using a deposition process as an isolation and protection layer.

[0055] The front metal layer 23 is located on the surface of the interlayer dielectric layer 22 in the first region 101, the surface of the ohmic contact metal 21, the surface of the hole injection P+ region 18 in the first region 102, and the surface of the front Schottky metal 20.

[0056] A front metal layer 23 is deposited on the surface of the interlayer dielectric layer 22 in the first region 101, the surface of the ohmic contact metal 21, the surface of the hole-injected P+ region 18 in the first region 102, and the surface of the front Schottky metal 20, serving as the front emitter region of the first region 101 and the anode region of the second region 102. The first region 101 and the second region 102 share a front metal layer 23.

[0057] Integrating the first region 101 and the second region 102 into the same N-type substrate 10 and sharing the front metal layer 23 can significantly reduce the total chip area and lower material and manufacturing costs.

[0058] Reference Figure 6 The diagram illustrates a structural schematic of another reverse-conducting IGBT device according to an embodiment of the present invention. The reverse-conducting IGBT device further includes: N-type buffer 24 is located inside the back side of N-type substrate 10.

[0059] The back P+ area 25 is located within the N-type buffer zone 24 in the first region 101.

[0060] The back N+ area 26 is located within the N-type buffer 24 of the second area 102.

[0061] The back metal layer 27 is located on the surface of the back P+ region 25 and the back N+ region 26.

[0062] Moving to the back-side process, the N-type substrate 10 is appropriately thinned, and then a back-side P+ region 25 of the first region 101 is formed by ion implantation. The back-side P+ region 25 serves as the collector region of the first region 101. Next, using front-back alignment technology, an N+ implantation region is formed in the second region 102, creating a back-side N+ region 26, which serves as the cathode region of the second region 102. Through back-side N+ implantation, a fast recovery diode with reverse current conduction capability is integrated.

[0063] Backside metal Al is deposited in the backside P+ region 25 and the backside N+ region 26 to form a backside metal layer 27, which serves as the backside electrode.

[0064] In this embodiment of the invention, the polysilicon layer 13 in the emitter trench 11 serves as a dummy gate structure.

[0065] The polysilicon layer 13 within the emitter trench 11 serves as a dummy gate structure, acting as a carrier control mechanism. The polysilicon layer 13 in the trench 11 of the second region 102 is designed to maintain the consistency and integrity of the process flow, ensuring the uniformity and reliability of the overall manufacturing process. A dummy gate structure refers to an electrode structure whose physical structure resembles a gate but is not connected to a drive signal or subject to voltage.

[0066] In the reverse-conducting IGBT device of this invention, the IGBT portion operates during forward conduction, and the FRD portion conducts reverse freewheeling during turn-off. Without significantly increasing process costs, this invention introduces a Schottky diode structure and a buried floating P-structure into a conventional RC-IGBT. This connects the barrier n-layer and the columnar n-region, allowing electron current to flow directly to the surface electrode through the n-region without entering the top p-layer and P+ layer. This avoids forward bias at the top p / barrier n-interface, thereby suppressing hole injection from the top p-layer. Simultaneously, the low doping concentration of the bottom p-layer contributes to the lower hole injection efficiency. Therefore, the Schottky diode structure and buried floating P-structure of this invention can reduce the hole concentration in the diode anode portion. (Refer to...) Figure 7 During the reverse recovery process of a diode, the depletion region extends from the P+N junction on the front side of the chip to the N-N+ junction on the back side. Holes are swept upwards by the electric field, while electrons are squeezed below the depletion region. Due to the reduced hole concentration at the anode, the current and reverse recovery time during the diode's reverse recovery process decrease, thereby significantly reducing the reverse recovery loss of the diode portion. (Refer to...) Figure 8 In this embodiment of the invention, the diode portion exhibits a forward voltage drop VF slightly higher than that of the conventional structure at 100A, but significantly lower than that of the conventional structure in the case of He injection. Figure 9As shown, the structure of this embodiment does not affect the forward conduction performance of the diode. This invention significantly reduces reverse recovery charge by suppressing hole injection during diode conduction.

[0067] Reference Figure 10 The diagram illustrates a flowchart of the manufacturing process of a reverse-conducting IGBT device according to an embodiment of the present invention, which may specifically include the following steps: Step 101, provide an N-type substrate; Step 102: Etching is performed in the first and second regions of the N-type substrate to form a plurality of trenches that are laterally spaced and parallel to each other; the first region includes at least one set of trenches, and the number of trenches in one set is three, wherein the trenches at both ends are emitter trenches and the trench in the middle is a gate trench; the second region includes at least one trench. Step 103: Perform thermal oxidation on the sidewalls and bottom of each of the trenches to form a gate oxide layer; Step 104: Deposit polysilicon in each trench of the first region to form a polysilicon layer. The polysilicon layer is located above the gate oxide layer of the first region and fills the internal space of each trench of the first region. Step 105: P-type ions are implanted into the N-type substrate to form a buried P-layer; the depth of the buried P-layer is greater than the depth of the trench; Step 106: N-type ions are injected into the buried P-layer to form a carrier storage N-layer; the depth of the carrier storage N-layer is less than the depth of the trench; Step 107: P-type ions are injected into the N-layer of the carrier storage to form a P-type trap; Step 108: In the P-type well, N-type ions are implanted on both sides of the gate trench to form an N+ electron emission region; the N+ electron emission region is connected to the sidewall region of the gate trench covered by the gate oxide layer. Step 109: Within the P-type well, P-type ions are implanted on the side of each N+ electron emission region away from the gate trench and on both sides of the trench in the second region to form a hole-implanted P+ region; the side of the hole-implanted P+ region in the first region is connected to the side of the N+ electron emission region; the hole-implanted P+ region in the second region is connected to the sidewall region of the trench in the diode region covered by the gate oxide layer. Step 110: P+ regions are injected into the holes in the second region and N-type ions are injected into the P-type traps to form an N-type region; the N-type region is connected to the N-layer of carrier storage. Step 111: A front-side Schottky metal is formed on the surface of the N-type region and a portion of the surface of the P+ region through the hole connected to the N-type region.

[0068] The reverse-conducting IGBT device of this invention includes: an N-type substrate; a plurality of trenches arranged laterally parallel and spaced apart, located in a first region and a second region of the N-type substrate; the first region includes at least one set of trenches, the number of trenches in one set being three, wherein the trenches at both ends are emitter trenches and the trench in the middle is a gate trench; the second region includes at least one trench; a gate oxide layer located on the sidewalls and bottom of each trench; a polysilicon layer located above the gate oxide layer and filling the internal space of the trench; a buried P layer located within the N-type substrate; the depth of the buried P layer is greater than the depth of the trench; and a carrier storage N layer located within the buried P layer; the depth of the carrier storage N layer is less than... The trench depth; P-type well, located within the N-layer for carrier storage; N+ electron emission region, located within the P-type well and on both sides of the gate trench, and connected to the sidewall region of the gate trench covered by the gate oxide layer; via-injected P+ region, located in the first region on the side of each N+ electron emission region away from the gate trench, and connected to the side of the N+ electron emission region; located on both sides of the trench in the second region, and connected to the sidewall region of the trench covered by the gate oxide layer; N-type region, located within the via-injected P+ region and the P-type well in the second region, and connected to the N-layer for carrier storage; front-side Schottky metal, located on the surface of the N-type region and a portion of the surface of the via-injected P+ region connected to the N-type region. This invention utilizes an N-type region, a Schottky diode structure composed of front-side Schottky metal, and a buried P-layer. The barrier n-layer and the columnar n-region are connected, allowing electron current to flow directly to the surface electrode through the n-region without entering the top p-layer and P+ layer. This avoids forward bias at the top p / barrier n-interface, thereby suppressing hole injection from the top p-layer and resulting in lower hole injection efficiency. This reduces the reverse recovery loss of the diode section. Furthermore, the carrier storage N-layer reduces the on-resistance of the IGBT section.

[0069] In this embodiment of the invention, the method further includes: Polysilicon is deposited in each trench of the second region to form a polysilicon layer, which is located above the gate oxide layer of the second region and fills the interior space of each trench of the second region.

[0070] In this embodiment of the invention, the method further includes: A portion of the surface of the P+ region is injected through a hole in the first region to form an ohmic contact metal; An interlayer dielectric layer is formed on the surface of the P-type well, a portion of the surface of the hole-injected P+ region, the surface of the N+ electron emission region, the surface of the polysilicon layer, and the surface of the gate oxide layer in the first region. A front metal layer is formed on the surface of the interlayer dielectric layer in the first region, the surface of the ohmic contact metal, the surface of the hole-injected P+ region in the second region, and the surface of the front Schottky metal.

[0071] In this embodiment of the invention, the method further includes: N-type ions are implanted on the back side of the N-type substrate to form an N-type buffer zone; P-type ions are injected into the N-type buffer zone in the first region to form the backside P+ region; N-type ions are injected into the N-type buffer zone in the second region to form a backside N+ region; A back metal layer is formed on the surface of the back P+ region and the back N+ region.

[0072] In this embodiment of the invention, before implanting N-type ions on the back side of the N-type substrate to form an N-type buffer, the method further includes: The back side of the N-type substrate is thinned.

[0073] In this embodiment of the invention, the polysilicon layer in the emitter trench serves as a dummy gate structure.

[0074] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0075] This invention also provides a chip, including the reverse-conducting IGBT device as described in any of the preceding embodiments.

[0076] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0077] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0078] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0079] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0080] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0081] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0082] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0083] The present invention has provided a detailed description of a reverse-conducting IGBT device, its manufacturing method, and its chip. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A reverse-conducting IGBT device, characterized in that, The reverse-conducting IGBT device includes: N-type substrate; Multiple trenches are arranged laterally at intervals and parallel to each other, located in a first region and a second region of the N-type substrate; the first region includes at least one set of trenches, the number of trenches in a set of trenches is three, wherein the trenches at both ends are emitter trenches and the trench in the middle is a gate trench; the second region includes at least one trench. A gate oxide layer is located on the sidewalls and bottom of each of the trenches; A polycrystalline silicon layer is located above the gate oxide layer in the first region and fills the internal space of the trench corresponding to the gate oxide layer in the first region. A buried P-layer is located within the N-type substrate; the depth of the buried P-layer is greater than the depth of the trench. A carrier storage N-layer is located within the buried P-layer; the depth of the carrier storage N-layer is less than the depth of the trench; The P-type well is located within the N-layer of the carrier storage; The N+ electron emission region is located inside the P-type well and on both sides of the gate trench, and is connected to the sidewall region of the gate trench covered by the gate oxide layer. The hole is injected into the P+ region, which is located on the side of each N+ electron emission region away from the gate trench in the first region and is connected to the side of the N+ electron emission region; and located on both sides of the trench in the second region and connected to the sidewall region of the trench covered by the gate oxide layer. The N-type region is located in the second region, within the hole injection P+ region and the P-type well, and is connected to the carrier storage N-layer; The front Schottky metal is located on the surface of the N-type region and on a portion of the surface of the hole-injected P+ region connected to the N-type region.

2. The reverse-conducting IGBT device according to claim 1, characterized in that, The polysilicon layer is also located above the gate oxide layer in the second region and fills the internal space of the trench corresponding to the gate oxide layer in the second region.

3. The reverse-conducting IGBT device according to claim 2, characterized in that, The reverse-conducting IGBT device also includes: An ohmic contact metal is located on a portion of the surface of the hole-injected P+ region in the first region; An interlayer dielectric layer is located on the surface of the P-type well, a portion of the surface of the hole-injected P+ region, the surface of the N+ electron emission region, the surface of the polysilicon layer, and the surface of the gate oxide layer in the first region. The front metal layer is located on the surface of the interlayer dielectric layer in the first region, the surface of the ohmic contact metal, the surface of the hole injection P+ region in the second region, and the surface of the front Schottky metal.

4. The reverse-conducting IGBT device according to claim 1, characterized in that, The reverse-conducting IGBT device also includes: An N-type buffer zone is located inside the back side of the N-type substrate; The back P+ region is located within the N-type buffer zone in the first region; The back N+ region is located within the N-type buffer zone in the second region; A back metal layer is located on the surface of the back P+ region and the back N+ region.

5. The reverse-conducting IGBT device according to claim 2, characterized in that, The polysilicon layer within the emitter trench serves as a virtual gate structure.

6. A method for manufacturing a reverse-conducting IGBT device, characterized in that, The method for manufacturing a reverse-conducting IGBT device as described in any one of claims 1-5 includes: Provide N-type substrates; In the first and second regions of the N-type substrate, a plurality of trenches are etched to form laterally spaced and parallel trenches; the first region includes at least one set of trenches, and the number of trenches in one set is three, wherein the trenches at both ends are emitter trenches and the trench in the middle is a gate trench; the second region includes at least one trench. Thermal oxidation is performed on the sidewalls and bottom of each of the trenches to form a gate oxide layer; Polysilicon is deposited in each trench of the first region to form a polysilicon layer, which is located above the gate oxide layer of the first region and fills the internal space of each trench of the first region. P-type ions are implanted into the N-type substrate to form a buried P-layer; the depth of the buried P-layer is greater than the depth of the trench. N-type ions are injected into the buried P-layer to form a carrier storage N-layer; the depth of the carrier storage N-layer is less than the depth of the trench; P-type ions are injected into the N-layer of the carrier storage to form a P-type trap. Within the P-type well, N-type ions are implanted on both sides of the gate trench to form an N+ electron emission region; the N+ electron emission region is connected to the sidewall region of the gate trench covered by the gate oxide layer. Within the P-type well, P-type ions are implanted on the side of each N+ electron emission region away from the gate trench and on both sides of the trench in the second region to form a hole-implanted P+ region; the side of the hole-implanted P+ region in the first region is connected to the side of the N+ electron emission region; the hole-implanted P+ region in the second region is connected to the sidewall region of the trench in the diode region covered by the gate oxide layer. P+ ions are injected into the holes in the second region and N-type ions are injected into the P-type traps to form an N-type region; the N-type region is connected to the N-layer of carrier storage. A front-side Schottky metal is formed on the surface of the N-type region and a portion of the surface of the P+ region injected through the hole connected to the N-type region.

7. The method for manufacturing a reverse-conducting IGBT device according to claim 6, characterized in that, The method further includes: Polysilicon is deposited in each trench of the second region to form a polysilicon layer, which is located above the gate oxide layer of the second region and fills the interior space of each trench of the second region.

8. The method for manufacturing a reverse-conducting IGBT device according to claim 7, characterized in that, The method further includes: A portion of the surface of the P+ region is injected through a hole in the first region to form an ohmic contact metal; An interlayer dielectric layer is formed on the surface of the P-type well, a portion of the surface of the hole-injected P+ region, the surface of the N+ electron emission region, the surface of the polysilicon layer, and the surface of the gate oxide layer in the first region. A front metal layer is formed on the surface of the interlayer dielectric layer in the first region, the surface of the ohmic contact metal, the surface of the hole-injected P+ region in the second region, and the surface of the front Schottky metal.

9. The method for manufacturing a reverse-conducting IGBT device according to claim 6, characterized in that, The method further includes: N-type ions are implanted on the back side of the N-type substrate to form an N-type buffer zone; P-type ions are injected into the N-type buffer zone in the first region to form the backside P+ region; N-type ions are injected into the N-type buffer zone in the second region to form a backside N+ region; A back metal layer is formed on the surface of the back P+ region and the back N+ region.

10. The method for manufacturing a reverse-conducting IGBT device according to claim 9, characterized in that, Before implanting N-type ions on the back side of the N-type substrate to form an N-type buffer, the method further includes: The back side of the N-type substrate is thinned.

11. The method for manufacturing a reverse-conducting IGBT device according to claim 7, characterized in that, The polysilicon layer within the emitter trench serves as a virtual gate structure.

12. A chip, characterized in that, Including the reverse-conducting IGBT device as described in any one of claims 1-5 above.

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