Silicon carbide semiconductor element

Abstract

A silicon carbide semiconductor element includes a silicon carbide substrate, a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a gate insulator, a gate electrode and a source electrode. The drift layer is provided on the silicon carbide substrate. The first doped region is disposed in the active region of the drift layer. The second doped region is disposed in the first doped region. The third doped region is disposed in the first doped region and adjoins the second doped region, and at least partially extends along a direction with the first doped region and the second doped region. The first doped region, the second doped region, and the third doped region are configured to form a multi-strip structure on a plane of the silicon carbide semiconductor element.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a silicon carbide semiconductor device. Background Technology

[0002] Silicon carbide (SiC) power devices have become a promising material for power transistors in power conversion applications. Power transistors include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), heterojunction field-effect transistors (HFETs), junction field-effect transistors (JFETs), and high electron mobility transistors (HEMTs). Compared with their silicon counterparts, silicon carbide power transistors, such as silicon carbide MOSFETs, have advantages such as high input impedance, low drive loss, low on-resistance, high blocking voltage, low switching loss, fast switching speed, and a large safe operating area.

[0003] One key consideration for SiC MOSFETs is reducing the on-resistance of specific regions. The total on-resistance of a SiC MOSFET includes channel resistance, JFET resistance, contact resistance, drift resistance, and substrate resistance. The active region of a SiC MOSFET consists of an array of unit cells. One strategy to reduce the total on-resistance is to increase the channel width density, thereby reducing the channel resistance by decreasing the cell spacing. Increasing the channel resistance is particularly important for SiC MOSFETs because the channel mobility of SiC MOSFETs is much lower than that of Si MOSFETs, and the channel resistance can account for more than 40% of the total on-resistance of a 650V rated SiC MOSFET. However, the JFET resistance increases with the narrowing of the JFET region due to the reduced cell pitch. To prevent the increased JFET resistance from exceeding the reduced channel resistance, a current spreading layer (CSL) is typically introduced. The CSL has a higher doping concentration than the drift layer to mitigate the JFET effect. The JFET resistance decreases with increasing CSL doping concentration. However, if the CSL doping concentration is too high, the blocking voltage will decrease. Reducing the on-resistance by reducing the cell pitch requires optimizing the trade-off between CSL doping and blocking voltage, and necessitates better process control. This poses a significant challenge to manufacturing SiC MOSFETs with high yield. Another limitation to further reducing the cell pitch is the minimum size of the source contact opening. The n+ and p+ regions must be connected to the source electrode through the source contact opening. The width of the contact opening must decrease with the reduction in cell pitch. Narrow, high aspect ratio source contact openings can negatively impact the performance, yield, and reliability of SiC MOSFETs. Summary of the Invention

[0004] In view of this, it is necessary to provide an improved semiconductor device to reduce on-resistance without defects associated with breakdown voltage.

[0005] One objective of this invention is to provide a silicon carbide semiconductor device that can improve the performance of silicon carbide semiconductor devices.

[0006] This invention discloses a silicon carbide semiconductor device, comprising a silicon carbide substrate, a drift layer having a first conductivity type, a plurality of first doped regions having a second conductivity type opposite to the first conductivity type, a plurality of second doped regions having the first conductivity type, a plurality of third doped regions having the second conductivity type, a gate insulator, a gate electrode, and a source electrode. The drift layer has a first doping concentration and is disposed on the silicon carbide substrate. The drift layer has a main surface and an active region. The first doped regions are disposed within the active region and include a plurality of first extensions extending laterally along a first direction and a plurality of first connection portions extending along a second direction different from the first direction. Each first connection portion laterally connects a pair of first extensions in the second direction, and the first doped region and the drift layer form a plurality of first pn junctions and a plurality of JFET regions. The second doped region is disposed within the first doped region and includes a plurality of second extensions extending laterally along the first direction and a plurality of second connecting portions extending laterally along the second direction. Each second connecting portion laterally connects a pair of second extensions along the second direction, and the second doped region and the first doped region form a plurality of second pn junctions. A plurality of channel regions are disposed along the main surface between the first pn junctions and the second pn junctions. The third doped region is disposed within the first extension of the first doped region and adjacent to the second extension of the second doped region. The third doped region extends at least partially along the first extension and the second extension along the first direction. The gate insulator is disposed on the main surface and extends over the JFET region, the channel region, and a portion of the second doped region. The gate electrode contacts the gate insulator. The source electrode contacts at least a portion of the second extension of the second doped region and the third doped region via a plurality of contact openings.

[0007] In one embodiment, the first direction is orthogonal to the second direction.

[0008] In one embodiment, the first extensions have the same width and are substantially equally spaced.

[0009] In one embodiment, the first connecting portions have the same width and are substantially equally spaced.

[0010] In one embodiment, the first extension has a different width.

[0011] In one embodiment, the first connecting portion has a different width.

[0012] In one embodiment, the first connecting portion has the same length.

[0013] In one embodiment, the first connecting portion has a different length.

[0014] In one embodiment, the first extension, the second extension, and the third doped region are configured to form a plurality of structures along the first direction in a planar view of the silicon carbide semiconductor element.

[0015] In one embodiment, the plurality of structures includes a plurality of segments, each of which is elongated and extends along an integral width of the active region.

[0016] In one embodiment, each of the segments extends parallel to each other.

[0017] In one embodiment, each of the third doped regions is elongated in the active region and extends along a width W, wherein the width W satisfies the following relationship: 3*W1≤W≤20000*W1, where W1 represents a width of the first connection portion.

[0018] In one embodiment, the multiple structures include multiple segments, each of which is elongated and extends along a portion of the overall width of the active region.

[0019] In one embodiment, each of the segments extends parallel to each other.

[0020] In one embodiment, the adjacent and parallel segments are spaced apart from each other.

[0021] In one embodiment, the displacement between adjacent and parallel segments is substantially equal to a distance between adjacent segments in the first direction.

[0022] In one embodiment, the length of the first connecting portion ranges from 3.2 μm to 100 μm.

[0023] In one embodiment, the JFET region has a second doping concentration of the first conductivity type, the second doping concentration being greater than the first doping concentration.

[0024] In one embodiment, the third doped region includes multiple dashed or dotted lines.

[0025] In one embodiment, the channel width density of the active region is higher than 0.2 μm⁻¹.

[0026] In one embodiment, the channel width density of the active region is higher than 0.4 μm⁻¹.

[0027] Other objects, features and advantages of the invention will be understood from the technical features further disclosed in the embodiments of the invention, wherein preferred embodiments of the invention are shown and described only by way of mode most suitable for illustrating and carrying out the invention. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view of a unit cell in an existing power MOSFET.

[0029] Figure 2 This is a planar schematic diagram of a silicon carbide semiconductor device according to an embodiment of the present invention.

[0030] Figure 3A For along Figure 2 Structural perspective views of facet lines A1-A2 and A1-A3.

[0031] Figure 3B For along Figure 2 Structural perspective views of facet lines A4-A5 and facet lines A4-A3.

[0032] Figure 3C For along Figure 2 Structural perspective views of facet lines A6-A5 and facet lines A6-A7.

[0033] Figure 4 According to Figure 2 A perspective view of the structure of a semiconductor element in an embodiment.

[0034] Figure 5 This is a planar schematic diagram of a silicon carbide semiconductor device according to another embodiment of the present invention.

[0035] Figure 6 For along Figure 5 Structural perspective view of secant lines B1-B2 and B1-B3. Detailed Implementation

[0036] It should be understood that although terms such as "first" and "second" are used herein to describe various elements, these terms are not intended to limit the elements. These terms are only used to distinguish one element from another. For example, a first element may be interpreted as a second element, and similarly, a second element may be interpreted as a first element, without departing from the scope of the invention.

[0037] As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0038] In the accompanying drawings, the thickness of each layer and region is exaggerated for clarity. It should also be understood that when an element such as a layer, portion, region, or substrate is referred to as "on," "covering," or "above" another element, it may be directly on, directly covering, or directly above that element; or there may be other elements in between. Conversely, when an element is referred to as "directly on," "directly covering," or "directly above" another element, there are no intermediate elements.

[0039] Relative terms may be used herein to describe the relationship between one element, layer, portion, or region and another element, layer, portion, or region in the accompanying drawings. It should be understood that these terms, like those described above, are intended to cover different orientations of elements other than those depicted in the figures. Several embodiments will be described below, with the same structural features identified by the same or similar reference numerals in the figures. As used herein, “lateral” or “lateral direction” should be understood to mean a direction or extent that extends generally parallel to the lateral extent of the semiconductor element, thus extending generally parallel to its surface or side. Conversely, the term “thickness direction” is understood to mean a direction that is generally perpendicular to its surface or side and therefore perpendicular to the lateral direction.

[0040] Throughout this document, the terminology used in the description of various embodiments is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates or intentionally limits the number of elements, the singular forms “a” and “the” used herein also include the plural forms. It will be further understood that the terms “comprising” and / or “including”, as used herein, indicate the presence of the described features, elements, and / or components, but do not preclude the addition or presence of one or more other features, elements, components, and / or groups thereof. Indefinite and definite articles should include both plural and singular forms unless the opposite is clearly apparent from the context.

[0041] In this document, n-type doping is referred to as the first conductivity type, and p-type doping as the second conductivity type. Alternatively, semiconductor devices can be formed using the opposite doping relationship, such that the first conductivity type can be p-type doping and the second conductivity type can be n-type doping. Furthermore, some figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type. For example, an "n-" doped region has a smaller doping concentration than an "n" doped region, while an "n+" doped region has a larger doping concentration than an "n" doped region. However, unless otherwise stated, indicating relative doping concentrations does not mean that doped regions with the same relative doping concentration must have the same absolute doping concentration. For example, two different n+ doped regions can have different absolute doping concentrations. This also applies to, for example, n+ doped regions and p+ doped regions.

[0042] Although the characteristics, materials, dimensions, shapes, positional relationships, and implementation conditions of the various components have been described in this invention, these are merely examples in all respects, and each embodiment is not limited to what has been described. Therefore, various modifications not exemplarily described are conceivable within the scope of each embodiment.

[0043] Power transistors consist of an active region with multiple unit cells, which are part of a basic MOS structure connected in parallel. These units are used to control the on / off state of voltage and current, and are fundamental components of various power converters and inverters. Power MOSFETs are among the most popular power transistors. Most power MOSFETs are normally-off (N-channel) MOSFETs, which include three terminals: gate, source, and drain. When a bias voltage (gate-to-source voltage, V) is applied between the gate and source... GS When the voltage is equal to or less than zero, the semiconductor device is in the off state and blocks a specific drain-to-source voltage (V). DS ), and in the applied V GS It conducts when the voltage is above the threshold voltage, where the drain current (I) D It flows between the drain end and the source end.

[0044] Figure 1 The cell structure of a conventional power SiC MOSFET is shown. This power SiC MOSFET includes an N+ type substrate 900, an N- type drift layer 901, a P-type well region 902, an N+ type region 903, a gate insulator 904, a gate electrode 905, a first metal 906, and a second metal 907. The gate electrode 905 is connected to a gate, the first metal 906 is connected to a source, and the second metal 907 is connected to a drain. Figure 1 In the diagram, "a" represents half the width of a contact opening, "b" represents the distance between the contact opening and the gate electrode 905, and "c" represents the overlap distance between the N+ type region 903 and the gate electrode 905 above it. Furthermore, L... ch W represents the length of the channel. Jfet Indicates the width of the JFET region. Figure 1 For example, for a traditional stripe layout, the inter-cell spacing (U) of one unit cell can be calculated using the following formula (1). cell ).

[0045] (1)

[0046] Channel width (W) ch) is the width of the groove extending in a direction perpendicular to the paper surface. Therefore, the groove width density (D) is calculated as the areal density of the groove width using equation (2). ch ).

[0047] (2)

[0048] To reduce cell pitch and increase channel width density, the aforementioned dimensions (e.g., a, b, and c) must be minimized as much as possible. Some dimensions can be reduced by improving photolithography and etching processes. However, there are limitations to reducing the size of the contact opening. When current flows through the channel and the N+ region 903 and eventually enters the contact opening, a current-crowding effect occurs near the edge of the contact opening. If the width of the contact opening is too small, the total contact resistance will increase significantly, which will reduce or even negate the benefits of higher channel width density. In summary, the following embodiments of this specification aim to provide a structure and layout of a silicon carbide semiconductor device with improved channel width density without increasing contact resistance.

[0049] Figure 2 This is a schematic diagram of a silicon carbide semiconductor element 1 along the XY plane according to an embodiment of the present invention. Figure 3A Show along Figure 2 Structural perspective views of facet lines A1-A2 and A1-A3. Figure 3B Show along Figure 2 Structural perspective views of facet lines A4-A5 and facet lines A4-A3. Figure 3C Show along Figure 2 Structural perspective views of facet lines A6-A5 and facet lines A6-A7.

[0050] The silicon carbide semiconductor device 1 may include a silicon carbide substrate 10, a drift layer 20, one or more first doped regions 30, one or more second doped regions 40, and one or more third doped regions 50, wherein the drift layer 20 includes an active region.

[0051] The silicon carbide substrate 10 has a first conductivity type (e.g., N-type) and in one example may be a nitrogen-doped 4H-SiC substrate. Other silicon carbide candidate polytypes may include 3C, 6H, and 15R polytypes. The drift layer 20 is disposed on the silicon carbide substrate 10 and has the first conductivity type. The first doped region 30 may be disposed in the drift layer 20 and adjacent to a main surface 21 of the drift layer 20. The first doped region 30 has a second conductivity type (e.g., P-type) opposite to the first conductivity type. The first doped region 30 can be formed by implanting aluminum ions as dopants into the N-type drift layer 20 to form an anti-doped P-type region adjacent to the main surface 21 of the drift layer 20, and the second doped region 40 can be formed by implanting nitrogen ions or phosphorus ions as dopants into the P-type first doped region 30 to form a heavily doped N-type region. In other words, the second doped region 40 is disposed in the first doped region 30.

[0052] In the following description, for convenience, the direction perpendicular to the main surface 21, i.e., the direction parallel to the normal of the main surface 21, is referred to as a normal direction Z of the silicon carbide substrate 10. Furthermore, the view from this normal direction Z is referred to as a plan view. For convenience, the direction perpendicular to the normal direction Z is referred to as a first direction X, and the direction perpendicular to both the normal direction Z and the first direction X is referred to as a second direction Y. The first direction X is different from the second direction Y. In the following non-limiting examples, the first direction X and the second direction Y are orthogonal to each other.

[0053] See Figure 3A The first doped region 30 includes a plurality of first extensions 31 and a plurality of first connecting portions 32, and the second doped region 40 includes a plurality of second extensions 41 and a plurality of second connecting portions 42. These portions, in a planar view (e.g., Figure 2 As shown, a cell configuration can be used. The first extension 31 and the second extension 41 extend along the first direction X, while the first connecting portion 32 and the second connecting portion 42 extend along the second direction Y.

[0054] Figure 2The unit cell configuration includes multiple unit cells UC1, each unit cell UC1 including two first extension regions 311, 312 and two first connection regions 321, 322. Viewed in plan view, the first extension regions 311, 312 are parallel to each other and extend along the first direction X, and the first connection regions 321, 322 are also parallel to each other and extend along the second direction Y. The first extension regions 311, 312 and the first connection regions 321, 322 are interconnected. The first doped region 30 in the unit cell UC1 extends linearly along the second direction Y and is box-like in shape. The first doped region 30 surrounds the drift layer 20 from the side (or laterally surrounds or forms a surrounding structure). The first doped region 30 and the drift layer 20 form multiple first pn junctions PN1 and multiple JFET regions JFET. The drift layer 20 has the first doping concentration of the first conductivity type, and the JFET region JFET has the second doping concentration of the first conductivity type, the second doping concentration being greater than the first doping concentration.

[0055] The second doped region 40 can be disposed within the first doped region 30. Each unit cell UC1 includes two second extension regions 411 and 412 and two second connection regions 421 and 422. The second extension regions 411 and 412 are interconnected with the second connection regions 421 and 422. The second extension regions 411 and 412 are parallel to each other and extend along the first direction X. The second extension regions 411 and 412 are laterally adjacent to the first extension regions 311 and 312. The second connection regions 421 and 422 are also parallel to each other and extend along the second direction Y. The second connection regions 421 and 422 are laterally adjacent to the first connection regions 321 and 322. The second extension regions 411 and 412 and the second connection regions 421 and 422 form a mesh structure that surrounds the first doped region 30 from the side (or laterally surrounds or forms a surrounding structure). The second doped region 40 and the first doped region 30 form a plurality of second pn junctions PN2. Multiple channel regions CH are disposed between the first pn junction PN1 and the second pn junction PN2 along the main surface 21 of the drift layer 20.

[0056] In this embodiment, the first extensions 31 have the same width and are substantially equally spaced, and the first connecting portions 32 have the same width and are substantially equally spaced. Furthermore, the first connecting portions 32 have the same length. In other embodiments, the first extensions 31 may have different widths, and the first connecting portions 32 may also have different widths and different lengths. Further, the first connecting portion 32 may have a length range between 3.2 μm and 100 μm. In this example, the width refers to the distance of the shorter dimension among these portions, and the length refers to the distance of the longer dimension among these portions. For example, for the first extension 31, the width refers to the distance in the second direction Y, and the length refers to the distance in the first direction X; for the first connecting portion 32, the width refers to the distance in the first direction X, and the length refers to the distance in the second direction Y.

[0057] like Figure 2 As shown, the third doped region 50 is configured to form a multi-stripe structure in the first direction X in the plan view of the silicon carbide semiconductor device 1. The multi-stripe structure includes a plurality of segments 51 extending parallel to each other. Each segment 51 is elongated and extends along an overall width (length in the first direction X) of the active region.

[0058] The third doped region 50 has the second conductivity type and can be disposed within the first doped region 30, just like the second doped region 40. The third doped regions 50 extend parallel to each other and at least partially extend along the first direction X with the first extension 31 and the second extension 41. The third doped region 50 laterally abuts the second extension 41. In this embodiment, each of the third doped regions 50 can extend through the active region (where the main current flows) of the silicon carbide semiconductor element 1.

[0059] See Figure 4 The silicon carbide semiconductor device 1 further includes a gate insulator 60, a gate electrode 70, and a source electrode 80. The gate insulator 60 is disposed on the main surface 21 of the drift layer 20 and extends over the JFET region, the channel region CH, and a first portion of the second doped region 40. The gate electrode 70 contacts the gate insulator 60, and the gate insulator 60 and the gate electrode 70 form a gate region located over the drift layer 20, the first doped region 30, and the first portion of the second doped region 40. The source electrode 80 contacts at least a portion of the second doped region 40 and at least a portion of the third doped region 50 via multiple source contact regions.

[0060] Figure 5 This is a planar schematic diagram of a silicon carbide semiconductor device according to another embodiment of the present invention. Figure 6Display along Figure 5 A perspective view of the structure with cleavage lines B1-B2 and B1-B3. As another embodiment of the invention, each of the third doped regions 50 is shown in a plan view (e.g., Figure 5 As shown, a broken stripe shape is formed along the first direction X.

[0061] Each of the third doped regions 50 includes one or more segments 51 extending laterally along the first direction X. Each segment 51 is elongated and extends along a width W (i.e., the length of the first direction X) of the active region. In other words, each segment 51 extends only a portion of the overall width of the active region, not the entire width. Furthermore, the width W satisfies the following relationship:

[0062] 3*W1≤W≤20000*W1

[0063] W1 represents the width of the first connecting part 32.

[0064] Specifically, the parallel segments 51 in adjacent rows are misaligned. In this example, a displacement D between adjacent parallel segments 51 is essentially equal to a distance between adjacent segments 51 in the first direction X. This displacement D may be a value other than the distance between adjacent segments 51, that is, the displacement D may be greater than or less than the distance between adjacent segments 51.

[0065] One of the advantages of the present invention is attributed to the geometry of the third doped region 50, which, according to calculations, can increase the channel width density. According to one or more embodiments, the channel width density of the active region is higher than 0.2 μm⁻¹.

[0066] To demonstrate some possible configurations, based on Figure 1 To the structure shown in Figure 3, Table 1 illustrates possible and non-limiting exemplary dimensions. See also Figure 2 and Figures 3A to 3B .

[0067] Table 1: Cell spacing and channel width density for each group.

[0068]

[0069] Considering that the minimum width of the contact opening is 1 μm, the minimum overlap between the gate electrode 70 and the n+ region (the second doped region 40) is 0.3 μm, the minimum spacing between the gate electrode 70 and the contact opening is 0.5 μm, and the channel length is 0.5 μm, the minimum width of the JFET region is 1.2 μm, making the minimum cell spacing of the conventional strip layout 1 (1 + (0.3 +0.5 + 0.5) * 2) + 1.2 = 4.8 μm, and the channel width density is 2 / 4.8 = 0.416 μm⁻¹.

[0070] According to the structural design of the present invention, the spacing of the smallest unit cell is no longer limited by the minimum width of the contact opening; only the minimum width of the first extension 31 is limited by the minimum width of the contact opening. In Example 1, following the same design rules as described above, the minimum width of the first extension 31 is (1 + (0.3 + 0.5 + 0.5) * 2) = 3.6 μm. If the width of the first connection 32 is 2 μm and the width of the second connection 42 is 1 μm, since the width of the JFET region is 1.2 μm, the cell spacing will become 2 + 1.2 = 3.2 μm, which is smaller than that of the conventional strip layout 1. If the length of the first connection 32 is 20 μm, the channel width density will reach 0.561 μm⁻¹, which is about 35% higher than that of the conventional strip layout 1.

[0071] In modern SiC planar MOSFETs, the channel region is defined through self-aligned processes, such as hard photomask sidewall spacing formed through an etch-back process. Therefore, the minimum width of the n+ region (the second doped region 40) is not limited by photolithography. In Example 2, if the width of the first connection portion 32 is reduced to 1.5 μm, the width of the second connection portion 42 will become 0.5 μm, and when the width of the JFET region JFET is 1.2 μm, the cell spacing will become 2.7 μm, and the channel width density will reach 0.665 μm⁻¹, which is about 60% higher than that of the conventional strip layout.

[0072] With the advent of commercially available 200 mm thick substrates, the minimum manufacturable size of SiC MOSFETs is also improving due to better photolithography and etching systems. Considering that the minimum width of the contact opening can be increased to 0.4 μm, the minimum overlap distance between the gate electrode 70 and the n+ region (the second doped region 40) is 0.2 μm, the minimum spacing between the gate electrode 70 and the contact opening is 0.3 μm, and the channel length is 0.4 μm, the minimum width of the JFET region is 0.8 μm, making the minimum cell spacing of the conventional strip layout 2 (0.4 + (0.2 + 0.3 + 0.4) * 2) + 0.8 = 3 μm, and the channel width density is 2 / 3 = 0.667 μm⁻¹.

[0073] According to the structural design of the present invention, the minimum cell spacing is no longer limited by the minimum width of the contact opening; only the minimum width of the first extension 31 is limited by the minimum width of the contact opening. In one embodiment (Example 3), following the same design rules described above, the minimum width of the first extension 31 is (0.4 + (0.2 + 0.3 + 0.4) * 2) = 2.2 μm. If the width of the first connection 32 is 1.2 μm, the width of the second connection 42 will be 0.4 μm. Since the width of the JFET in the JFET region is 0.8 μm, the cell spacing will become 1.2 + 0.8 = 2 μm, which is smaller than the conventional strip layout. If the length of the first connection 32 is 20 μm, the channel width density will reach 0.912 μm⁻¹, which is about 37% higher than the conventional strip layout.

[0074] This invention can flexibly use relaxed design rules to achieve similar channel width density compared to traditional strip layouts with strict design rules, thereby improving manufacturability and yield, or pursue the highest possible channel width density through strict design rules.

[0075] [Symbol Explanation]

[0076] 1: Silicon carbide semiconductor components

[0077] 10: Silicon carbide substrate

[0078] 20: Drift Layer

[0079] 21: Main Surface

[0080] 30: First doped region

[0081] 31: First Extension

[0082] 311, 312: First Extension Zone

[0083] 32: First connecting part

[0084] 321, 322: First connection area

[0085] 40: Second doped region

[0086] 41: Second Extension

[0087] 411, 412: Second Extension Zone

[0088] 42: Second connecting part

[0089] 421, 422: Second connection area

[0090] 50: Third doped region

[0091] 51: Section

[0092] 60: Gate insulator

[0093] 70: Gate electrode

[0094] 80: Source electrode

[0095] 900: N+ type substrate

[0096] 901: N-type drift layer

[0097] 902: P-type well area

[0098] 903: N+ type area

[0099] 904: Gate Insulator

[0100] 905: Gate electrode

[0101] 906: First Metal

[0102] 907: Second Metal

[0103] Z: Normal direction

[0104] X: First direction

[0105] Y: Second direction

[0106] UC1: Unit cell

[0107] PN1: First pn junction

[0108] PN2: Second pn junction

[0109] JFET: JFET region

[0110] CH: Channel area

[0111] D: Displacement

[0112] W: Width.

Claims

1. A silicon carbide semiconductor device, characterized in that, include: A silicon carbide substrate; A drift layer having a first conductivity type and a first doping concentration, the drift layer being disposed on the silicon carbide substrate and having a main surface and an active region; Multiple first doped regions are disposed in the active region. Each first doped region has a second conductivity type opposite to the first conductivity type. Each first doped region includes multiple first extensions extending laterally along a first direction and multiple first connection portions extending along a second direction different from the first direction. Each first connection portion laterally connects a pair of first extensions in the second direction. The first doped region and the drift layer form multiple first pn junctions and multiple JFET regions. A plurality of second doped regions having the first conductivity type and disposed within the first doped region, each second doped region including a plurality of second extensions extending laterally along the first direction and a plurality of second connecting portions extending laterally along the second direction, wherein each second connecting portion laterally connects a pair of the second extensions along the second direction, and the second doped region and the first doped region form a plurality of second pn junctions, and a plurality of channel regions are disposed along the main surface between the first pn junctions and the second pn junctions; A plurality of third doped regions having the second conductivity type, wherein the third doped region is disposed in the first extension of the first doped region and adjacent to the second extension of the second doped region, wherein the third doped region extends at least partially along the first extension and the second extension in the first direction. A gate insulator is disposed on the main surface, wherein the gate insulator extends over a portion of the JFET region, the channel region, and the second doped region; A gate electrode, in contact with the gate insulator; and A source electrode contacts at least a portion of the second extension of the second doped region and the third doped region via a plurality of contact openings.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The first direction is orthogonal to the second direction.

3. The silicon carbide semiconductor device according to claim 1, characterized in that, The first extension has the same width and is substantially equally spaced.

4. The silicon carbide semiconductor device according to claim 1, characterized in that, The first connecting parts have the same width and are substantially equally spaced.

5. The silicon carbide semiconductor device according to claim 1, characterized in that, The first extension has a different width.

6. The silicon carbide semiconductor device according to claim 1, characterized in that, The first connecting part has a different width.

7. The silicon carbide semiconductor device according to claim 1, characterized in that, The first connecting part has the same length.

8. The silicon carbide semiconductor device according to claim 1, characterized in that, The first connecting part has a different length.

9. The silicon carbide semiconductor device according to claim 1, characterized in that, The first extension, the second extension, and the third doped region are configured to form a plurality of structures along the first direction in a planar view of the silicon carbide semiconductor element.

10. The silicon carbide semiconductor device according to claim 9, characterized in that, The multiple structure comprises multiple segments, each of which is elongated and extends along an integral width of the active region.

11. The silicon carbide semiconductor device according to claim 10, characterized in that, Each of these segments extends parallel to the others.

12. The silicon carbide semiconductor device according to claim 9, characterized in that, Each of the third doped regions in the active region is elongated and extends along a width W, wherein the width W satisfies the following relationship: 3*W1≤W≤20000*W1 Wherein, W1 represents the width of the first connecting part.

13. The silicon carbide semiconductor device according to claim 9, characterized in that, The multiple structure comprises multiple segments, each of which is elongated and extends along a portion of the overall width of the active region.

14. The silicon carbide semiconductor device according to claim 13, characterized in that, Each of these segments extends parallel to the others.

15. The silicon carbide semiconductor device according to claim 13, characterized in that, The adjacent and parallel segments are spaced apart from each other.

16. The silicon carbide semiconductor device according to claim 13, characterized in that, The displacement between adjacent and parallel segments is essentially equal to the distance between adjacent segments in the first direction.

17. The silicon carbide semiconductor device according to claim 1, characterized in that, The length of the first connecting portion ranges from 3.2 μm to 100 μm.

18. The silicon carbide semiconductor device according to claim 1, characterized in that, The JFET region has a second doping concentration of the first conductivity type, which is greater than the first doping concentration.

19. The silicon carbide semiconductor device according to claim 1, characterized in that, The third doped region includes multiple dashed or dotted areas.

20. The silicon carbide semiconductor device according to claim 1, characterized in that, The channel width density of the active region is higher than 0.2 μm⁻¹.

21. The silicon carbide semiconductor device according to claim 1, characterized in that, The channel width density of the active region is higher than 0.4 μm⁻¹.

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