Semiconductor structure and manufacturing method thereof
By designing semiconductor structures with non-active and active layers in a P-type gate HEMT device, the problem of large gate leakage current was solved, and the reliability and stability of the device were improved.
Patent Information
- Application Number
- CN202411154401.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2026-03-03
AI Technical Summary
P-type gate HEMT devices suffer from problems such as large gate leakage current, low output current density, and poor device stability.
Design a semiconductor structure in which a P-type semiconductor layer comprises a non-active layer, an N-type doped layer and an active layer stacked sequentially, the non-active layer being located on the side closest to the substrate, the active layer being used to deplete the two-dimensional electron gas in the gate region, and the non-active layer being used to reduce gate leakage current.
This design reduces gate leakage current and improves device reliability and stability.
Smart Images
Figure CN121604479A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and specifically to a semiconductor structure and its manufacturing method. Background Technology
[0002] Compared to first- and second-generation semiconductor materials, third-generation semiconductor materials, especially GaN (gallium nitride)-based materials, have advantages such as large bandgap, high breakdown field strength, high electron mobility, and strong radiation resistance. GaN-based HEMT (High Electron Mobility Transistor) devices have great development potential in high-frequency, high-power fields such as wireless communication base stations, radar, and automotive electronics.
[0003] Typically, GaN-based HEMT devices are depletion-mode field-effect transistors. However, in practical applications, considering factors such as cost and fault protection, enhancement-mode HEMT devices are often required. There are many ways to implement enhancement-mode devices, such as by using a P-type semiconductor at the gate to deplete the two-dimensional electron gas. However, P-type gate HEMT devices still suffer from problems such as low output current density, high gate leakage current, and low device stability. Summary of the Invention
[0004] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same, in order to solve the problem of large gate leakage current in P-type gate HEMT devices.
[0005] According to one aspect of this disclosure, an embodiment of this disclosure provides a semiconductor structure, characterized in that it includes:
[0006] A substrate, a channel layer, and a barrier layer are stacked sequentially, wherein the channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region;
[0007] A P-type semiconductor layer, wherein the P-type semiconductor layer is at least located in the gate region and on the side of the barrier layer away from the substrate;
[0008] The P-type semiconductor layer includes an inactive layer, an N-type doped layer, and an active layer stacked sequentially, with the inactive layer located on the side of the P-type semiconductor layer closest to the substrate.
[0009] As an optional embodiment, the hydrogen concentration of the non-activated layer is higher than that of the activated layer.
[0010] As an optional embodiment, the thickness of the non-activated layer is smaller than the thickness of the activated layer.
[0011] As an optional embodiment, the N-type doped layer is an N-type delta doped layer.
[0012] As an optional embodiment, the P-type semiconductor layer includes a first P-type region located in the gate region and a second P-type region located in the non-gate region, wherein the thickness of the first P-type region is greater than the thickness of the second P-type region.
[0013] As an optional embodiment, the surface of the second P-type region on the side away from the substrate is an N-type doped layer.
[0014] As an optional embodiment, the thickness of the N-type doped layer located in the second P-type region is less than or equal to the thickness of the N-type doped layer located in the first P-type region.
[0015] As an optional embodiment, the side of the second P-type region closest to the substrate is a non-activated layer.
[0016] As an optional embodiment, the semiconductor structure further includes:
[0017] A gate is located in the gate region and on the side of the P-type semiconductor layer away from the substrate;
[0018] The source electrode is located in the source region and on the side of the channel layer away from the substrate; and,
[0019] The drain electrode is located in the drain region and on the side of the channel layer away from the substrate.
[0020] According to another aspect of this disclosure, one embodiment of this disclosure provides a method for manufacturing a semiconductor structure, characterized by comprising the following steps:
[0021] S1. A substrate, a channel layer, a barrier layer and a P-type semiconductor layer are sequentially stacked. The channel layer and the barrier layer include a gate region and a source region and a drain region located on both sides of the gate region.
[0022] S2. Etch the P-type semiconductor layer, while retaining at least the P-type semiconductor layer on the gate region of the barrier layer;
[0023] S3. An N-type doped layer is formed in the P-type semiconductor layer;
[0024] S4. High-temperature annealing activates the P-type semiconductor layer on the side of the N-type doped layer away from the substrate, forming an activated layer. The P-type semiconductor layer on the side of the N-type doped layer close to the substrate is not activated, forming a non-activated layer.
[0025] As an optional embodiment, the method for forming the N-type doped layer in step S3 is to form a delta doped layer by ion implantation of N-type ions.
[0026] As an optional embodiment, in step S2, the P-type semiconductor layer is etched to retain a first P-type region located in the gate region and a second P-type region located in the non-gate region, wherein the thickness of the first P-type region is greater than the thickness of the second P-type region.
[0027] As an optional embodiment, the surface of the second P-type region on the side away from the substrate is an N-type doped layer.
[0028] As an optional embodiment, the side of the second P-type region closest to the substrate is a non-activated layer.
[0029] As an optional embodiment, the method for manufacturing the semiconductor structure further includes:
[0030] S5. A gate is provided in the gate region and on the side of the P-type semiconductor layer away from the substrate; a source is provided in the source region and on the side of the channel layer away from the substrate; and a drain is provided in the drain region and on the side of the channel layer away from the substrate.
[0031] This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and the barrier layer include a gate region and a source region and a drain region located on both sides of the gate region. A P-type semiconductor layer is located in the gate region and on the side of the barrier layer away from the substrate. The P-type semiconductor layer includes a non-active layer, an N-type doped layer, and an active layer stacked sequentially. The non-active layer is located on the side of the P-type semiconductor layer closer to the substrate. Traditional techniques require high-temperature annealing of P-type semiconductor materials to sever the Mg-H complex junction and drive away H atoms, thus activating the P-type semiconductor. Designing an N-type doped layer in the P-type semiconductor material can block the dissipation path of H atoms in the P-type semiconductor material below the N-type doped layer, preventing activation. Therefore, the N-type doped layer design of this disclosure allows the P-type semiconductor layer to have both an active and a non-active layer. The active layer depletes the two-dimensional electron gas in the gate region channel, ensuring the semiconductor structure remains in a normally off state. The non-active layer reduces the gate leakage current formed by channel leakage to the gate and blocks the influence of the semiconductor structure surface state on the gate region channel, thereby improving device reliability. Attached Figure Description
[0032] Figure 1 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.
[0033] Figures 2 to 3 The diagram shown is a schematic diagram of a semiconductor structure provided in some embodiments of this disclosure.
[0034] Figure 4The diagram shows a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of this disclosure.
[0035] Figures 5 to 8 As shown Figure 4 The diagram shows the intermediate structure corresponding to the process shown. Detailed Implementation
[0036] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0037] To address the issue of high gate leakage current in P-gate HEMT devices, this disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and barrier layer include a gate region, and source and drain regions located on either side of the gate region. A P-type semiconductor layer is located at least in the gate region and on the side of the barrier layer furthest from the substrate. The P-type semiconductor layer includes a non-active layer, an N-type doped layer, and an active layer stacked sequentially, with the non-active layer located on the side of the P-type semiconductor layer closest to the substrate. The design of the N-type doped layer in this disclosure allows the P-type semiconductor layer to have both an active and non-active layer. The active layer ensures the semiconductor structure remains in a normally off state, while the non-active layer reduces gate leakage current and improves device reliability.
[0038] The following is combined Figures 1 to 8 A further example illustrates a semiconductor structure and its manufacturing method mentioned in this disclosure.
[0039] Figure 1 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. Figure 1 As shown, the semiconductor structure includes a substrate 10, a channel layer 20, and a barrier layer 30 stacked sequentially. The channel layer 20 and the barrier layer 30 include a gate region and a source region and a drain region located on both sides of the gate region. A P-type semiconductor layer 40 is located at least in the gate region and on the side of the barrier layer 30 away from the substrate 10. The P-type semiconductor layer 40 includes a non-active layer 41, an N-type doped layer 42, and an active layer 43 stacked sequentially. The non-active layer 41 is located on the side of the P-type semiconductor layer 40 closer to the substrate 10.
[0040] In this embodiment, the substrate 10 is made of any one or more combinations of Si, sapphire, GaN, SiC, AlN, or diamond. The materials of the channel layer 20 and the barrier layer 30 may include group III nitride materials, and a two-dimensional electron gas can be formed at the interface between the channel layer 20 and the barrier layer 30. In one optional embodiment, the channel layer 20 is a GaN layer, and the barrier layer 30 is an AlGaN layer. In other optional embodiments, the material combination of the channel layer 20 and the barrier layer 30 may also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. The material of the P-type semiconductor layer 40 is a group III nitride material, and the P-type doped ions of the P-type semiconductor layer 40 include at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions.
[0041] In this embodiment, the P-type semiconductor layer 40 includes a non-active layer 41, an N-type doped layer 42, and an active layer 43 stacked sequentially in the direction away from the substrate 10. The hydrogen concentration of the non-active layer 41 is higher than that of the active layer 43. The presence of the non-active layer 41 can reduce gate leakage current and improve device reliability. The thickness of the non-active layer 41 is less than that of the active layer 43, which can reduce the influence of the presence of the non-active layer 41 on the ability of the active layer 43 to deplete the two-dimensional electron gas. The N-type doped layer 42 is an N-type delta doped layer. The N-type dopant ions of the N-type doped layer 42 include at least one of Si ions, Ge ions, Sn ions, Se ions, or Te ions. The N-type doped layer 42 can form a PN junction with the P-type semiconductor layer 40, which can adjust the interface electric field between the gate metal and the semiconductor structure and further suppress gate leakage current.
[0042] In one embodiment, the semiconductor structure may include a nucleation layer and a buffer layer between the substrate 10 and the channel layer 20. Figure 1 (Not shown). This can be determined according to design requirements, such as to improve the quality of the semiconductor layer grown on substrate 10. Taking GaN growth on a silicon substrate as an example, a nucleation layer and a buffer layer are typically provided to improve the subsequent GaN growth quality. The nucleation layer can be, for example, AlN, and the buffer layer can be, for example, AlGaN, GaN, InGaN, etc. This disclosure is not limited thereto; the nucleation layer and buffer layer depend on the materials of substrate 10 and channel layer 20. For example, when growing GaN on a gallium nitride substrate, the nucleation layer and buffer layer may be omitted, or only one of the nucleation layer and buffer layer may be provided.
[0043] In one embodiment, such as Figure 1As shown, the semiconductor structure further includes: a gate 51 located in the gate region and on the side of the P-type semiconductor layer 40 away from the substrate 10; a source 52 located in the source region and on the side of the channel layer 30 away from the substrate 10; and a drain 53 located in the drain region and on the side of the channel layer 30 away from the substrate 10.
[0044] It should be noted that, Figure 1 Only the source 52 and drain 53 are shown in the diagram, located on the side of the barrier layer 30 away from the substrate 10. Optionally, the barrier layer 30 is thinned at the corresponding positions of the source 52 and drain 53; alternatively, the source 52 and drain 53 penetrate the barrier layer 30 and are in direct contact with the channel layer 20.
[0045] In one embodiment, Figures 2 to 3 The diagram shown is a schematic representation of a semiconductor structure provided in some embodiments of this disclosure. Figure 2 As shown, the P-type semiconductor layer 40 includes a first P-type region 401 located in the gate region and a second P-type region 402 located in the non-gate region. The thickness of the first P-type region 401 is greater than the thickness of the second P-type region 402. The arrangement of the second P-type region 402 ensures that the surface quality of the barrier layer 30 is not damaged when etching to form the P-type semiconductor layer 40. The surface of the second P-type region 402 away from the substrate 10 is an N-type doped layer 42, and the surface of the second P-type region 402 close to the substrate 10 is a non-active layer 41, which does not affect the two-dimensional electron gas and can ensure the channel conductivity. Figure 2 In the semiconductor structure shown, the thickness of the N-type doped layer 42 located in the second P-type region 402 is equal to the thickness of the N-type doped layer 42 located in the first P-type region 401. Optionally, such as... Figure 3 As shown, the thickness of the N-type doped layer 42 located in the second P-type region 402 is less than the thickness of the N-type doped layer 42 located in the first P-type region 401. This disclosure does not impose specific restrictions on the thickness of the N-type doped layer 42 in the second P-type region 402, and it is sufficient to ensure that the side of the second P-type region 402 close to the substrate 10 is not activated.
[0046] According to another aspect of this disclosure, one embodiment of this disclosure provides a method for manufacturing a semiconductor structure. Figure 4 The diagram shown is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of this disclosure; Figures 5 to 8 As shown Figure 4 The diagram shows the intermediate structure corresponding to the process flow. (See attached diagram.) Figure 4 As shown, a method for manufacturing a semiconductor structure according to an embodiment of this disclosure includes the following steps:
[0047] Step S1: The substrate, channel layer, barrier layer and P-type semiconductor layer are stacked sequentially. The channel layer and barrier layer include a gate region and source and drain regions located on both sides of the gate region.
[0048] Specifically, such as Figure 5 As shown, a substrate 10, a channel layer 20, a barrier layer 30, and a P-type semiconductor layer 40 are sequentially stacked. The channel layer 20 and the barrier layer 30 include a gate region, and source and drain regions located on both sides of the gate region. The substrate 10 is made of any one or more combinations of Si, sapphire, GaN, SiC, AlN, or diamond. The materials of the channel layer 20 and the barrier layer 30 may include group III nitride materials, and a two-dimensional electron gas can be formed at the interface between the channel layer 20 and the barrier layer 30. The channel layer 20 and the barrier layer 30 can be grown using atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof. The p-type semiconductor layer 40 is made of group III nitride material, and the p-type dopant ions in the p-type semiconductor layer 40 include at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions.
[0049] Step S2: Etch the P-type semiconductor layer, leaving at least the P-type semiconductor layer on the gate region of the barrier layer intact.
[0050] Specifically, such as Figure 6 As shown, the P-type semiconductor layer 40 is etched, while at least the P-type semiconductor layer 40 on the gate region of the barrier layer 30 is retained.
[0051] Step S3: Form an N-type doped layer in the P-type semiconductor layer.
[0052] Specifically, such as Figure 7 As shown, an N-type doped layer 42 is formed in the P-type semiconductor layer 40. The method for forming the N-type doped layer 42 is to form a delta doped layer by ion implantation of N-type ions. The N-type ions include at least one of Si ions, Ge ions, Sn ions, Se ions, or Te ions.
[0053] Step S4: High-temperature annealing activates the P-type semiconductor layer on the side of the N-type doped layer away from the substrate, forming an activated layer. The P-type semiconductor layer on the side of the N-type doped layer closer to the substrate is not activated, forming an inactive layer.
[0054] Specifically, such as Figure 8 As shown, high-temperature annealing activates the P-type semiconductor layer 40 on the side of the N-type doped layer 42 away from the substrate 10, forming an activation layer 43. The P-type semiconductor layer 40 on the side of the N-type doped layer 42 closer to the substrate 10 remains unactivated, forming an inactive layer 41. The hydrogen concentration in the inactive layer 41 is higher than that in the activation layer 43. The presence of the inactive layer 41 reduces gate leakage current and improves device reliability. The thickness of the inactive layer 41 is less than that of the activation layer 43, which reduces the impact of the presence of the inactive layer 41 on the ability of the activation layer 43 to deplete the two-dimensional electron gas. The N-type doped layer 42 can act as a barrier layer, preventing the P-type semiconductor layer 40 on the side closer to the substrate 10 from being activated, thus giving the P-type semiconductor layer 40 an inactive layer 41. Furthermore, it can form a PN junction with the P-type semiconductor layer 40, which can adjust the interfacial electric field between the gate metal and the semiconductor structure, further suppressing gate leakage current.
[0055] In one embodiment, the method for manufacturing a semiconductor structure further includes:
[0056] Step S5: A gate is disposed in the gate region and on the side of the P-type semiconductor layer away from the substrate; a source is disposed in the source region and on the side of the channel layer away from the substrate; and a drain is disposed in the drain region and on the side of the channel layer away from the substrate.
[0057] Specifically, a gate 51 is disposed in the gate region and on the side of the P-type semiconductor layer 40 away from the substrate 10; a source 52 is disposed in the source region and on the side of the channel layer 30 away from the substrate 10; and a drain 53 is disposed in the drain region and on the side of the channel layer 30 away from the substrate 10, forming a structure as follows: Figure 1 The semiconductor structure shown.
[0058] In one embodiment, step S2 involves etching the P-type semiconductor layer 40, retaining a first P-type region 401 located in the gate region and a second P-type region 402 located in the non-gate region. The thickness of the first P-type region 401 is greater than the thickness of the second P-type region 402, forming a structure as shown in the figure. Figure 2 The semiconductor structure shown has a second P-type region 402, which ensures that the surface quality of the barrier layer 30 is not damaged when the P-type semiconductor layer 40 is etched. The surface of the second P-type region 402 away from the substrate 10 is an N-type doped layer 42, and the surface of the second P-type region 402 close to the substrate 10 is a non-active layer 41, which does not affect the two-dimensional electron gas and can ensure the channel conductivity. Figure 2In the semiconductor structure shown, the thickness of the N-type doped layer 42 located in the second P-type region 402 is equal to the thickness of the N-type doped layer 42 located in the first P-type region 401. Optionally, such as... Figure 3 As shown, the thickness of the N-type doped layer 42 located in the second P-type region 402 is less than the thickness of the N-type doped layer 42 located in the first P-type region 401. This disclosure does not impose specific restrictions on the thickness of the N-type doped layer 42 in the second P-type region 402, and it is sufficient to ensure that the side of the second P-type region 402 close to the substrate 10 is not activated.
[0059] This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and the barrier layer include a gate region and a source region and a drain region located on both sides of the gate region. A P-type semiconductor layer is located in the gate region and on the side of the barrier layer away from the substrate. The P-type semiconductor layer includes a non-active layer, an N-type doped layer, and an active layer stacked sequentially. The non-active layer is located on the side of the P-type semiconductor layer closer to the substrate. Traditional techniques require high-temperature annealing of P-type semiconductor materials to sever the Mg-H complex junction and drive away H atoms, thus achieving P-type activation. Designing an N-type doped layer in the P-type semiconductor material can block the dissipation path of H atoms in the P-type semiconductor material below the N-type doped layer, preventing activation. Therefore, the N-type doped layer design of this disclosure allows the P-type semiconductor layer to have both an active and a non-active layer. The active layer depletes the two-dimensional electron gas in the gate region channel, ensuring the semiconductor structure remains in a normally off state. The non-active layer reduces the gate leakage current formed by channel leakage to the gate and blocks the influence of the semiconductor structure surface state on the gate region channel, thereby improving device reliability.
[0060] It should be understood that the term "comprising" and its variations as used in this disclosure are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0061] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A semiconductor structure, characterized in that, include: A substrate (10), a channel layer (20) and a barrier layer (30) are stacked sequentially. The channel layer (20) and the barrier layer (30) include a gate region and a source region and a drain region located on both sides of the gate region. A P-type semiconductor layer (40) is located at least in the gate region and on the side of the barrier layer (30) away from the substrate (10); The P-type semiconductor layer (40) includes an inactive layer (41), an N-type doped layer (42), and an active layer (43) stacked sequentially. The inactive layer (41) is located on the side of the P-type semiconductor layer (40) closer to the substrate (10).
2. The semiconductor structure according to claim 1, characterized in that, The hydrogen concentration of the non-activated layer (41) is higher than that of the activated layer (43).
3. The semiconductor structure according to claim 1, characterized in that, The thickness of the non-activated layer (41) is less than the thickness of the activated layer (43).
4. The semiconductor structure according to claim 1, characterized in that, The N-type doped layer (42) is an N-type delta doped layer.
5. The semiconductor structure according to claim 1, characterized in that, The P-type semiconductor layer (40) includes a first P-type region (401) located in the gate region and a second P-type region (402) located in the non-gate region, wherein the thickness of the first P-type region (401) is greater than the thickness of the second P-type region (402).
6. The semiconductor structure according to claim 5, characterized in that, The surface of the second P-type region (402) away from the substrate (10) is an N-type doped layer (42).
7. The semiconductor structure according to claim 6, characterized in that, The thickness of the N-type doped layer (42) located in the second P-type region (402) is less than or equal to the thickness of the N-type doped layer (42) located in the first P-type region (401).
8. The semiconductor structure according to claim 5, characterized in that, The second P-type region (402) is a non-activated layer (41) on the side closest to the substrate (10).
9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: A gate (51) is located in the gate region and on the side of the P-type semiconductor layer (40) away from the substrate (10); Source (52), located in the source region and on the side of the channel layer (30) away from the substrate (10); and, Drain (53) is located in the drain region and on the side of the channel layer (30) away from the substrate (10).
10. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: S1. A substrate (10), a channel layer (20), a barrier layer (30) and a P-type semiconductor layer (40) are stacked sequentially. The channel layer (20) and the barrier layer (30) include a gate region and a source region and a drain region located on both sides of the gate region. S2. Etch the P-type semiconductor layer (40) while retaining at least the P-type semiconductor layer (40) on the gate region of the barrier layer (30); S3. An N-type doped layer (42) is formed in the P-type semiconductor layer (40); S4. High-temperature annealing activates the P-type semiconductor layer (40) on the side of the N-type doped layer (42) away from the substrate (10), forming an activation layer (43). The P-type semiconductor layer (40) on the side of the N-type doped layer (42) close to the substrate (10) is not activated, forming a non-activation layer (41).
11. The method for manufacturing the semiconductor structure according to claim 10, characterized in that, The method for forming the N-type doped layer (42) in step S3 is to form a delta doped layer by ion implantation of N-type ions.
12. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, In step S2, the P-type semiconductor layer (40) is etched, retaining a first P-type region (401) located in the gate region and a second P-type region (402) located in the non-gate region, wherein the thickness of the first P-type region (401) is greater than the thickness of the second P-type region (402).
13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that, The surface of the second P-type region (402) away from the substrate (10) is an N-type doped layer (42).
14. The method for manufacturing a semiconductor structure according to claim 12, characterized in that, The second P-type region (402) is a non-activated layer (41) on the side closest to the substrate (10).
15. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The method for manufacturing the semiconductor structure further includes: S5. A gate (51) is provided in the gate region and on the side of the P-type semiconductor layer (40) away from the substrate (10); a source (52) is provided in the source region and on the side of the channel layer (30) away from the substrate (10); and a drain (53) is provided in the drain region and on the side of the channel layer (30) away from the substrate (10).