A semiconductor structure and its manufacturing method

Abstract

This invention relates to the field of semiconductor technology, specifically to a semiconductor structure and its manufacturing method, comprising: providing a substrate, the substrate including a first region and a second region arranged side by side; sequentially growing a pad oxide layer and a pad nitride layer on the substrate; forming a first shallow trench in the first region and a second shallow trench in the second region, the second shallow trench being arranged side by side with the first shallow trench, and the depth of the second shallow trench being greater than the depth of the first shallow trench; etching away the pad nitride layer; growing and forming a compensation nitride layer on the surface of the pad oxide layer, the inner wall of the first shallow trench, and the inner wall of the second shallow trench; filling the first shallow trench and the second shallow trench with an insulating medium; and performing planarization treatment on the insulating medium so that the surface of the insulating medium is flush with the surfaces of the compensation nitride layers on both sides. This can optimize the electrical performance of the pixel area and improve chip yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its manufacturing method. Background Technology

[0002] A CMOS image sensor (CIS) chip is mainly divided into two functional areas: the logic area and the pixel area. The core function of the image signal processing area is to perform image signal processing, while the pixel area is responsible for converting optical images into pixel digital signals.

[0003] To reduce dark current, devices in the pixel area employ a design that reduces the shallow trench isolation etching depth. However, the shallow trench isolation depth in the image signal processing area must maintain the original standard, hence the development of dual shallow trench isolation technology.

[0004] However, in traditional processes, the remaining height of silicon nitride in the dual shallow trench isolation regions differs, resulting in an excessively high shallow trench isolation step height in the pixel region. Consequently, in the subsequent ion implantation process of the pixel region, there is a significant difference in the antireflectivity of the photoresist at the interface between the active region and the shallow trench isolation, and the profile of the photoresist is distorted. Ultimately, this affects the electrical performance of the pixel region, leading to a decrease in chip yield. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor structure and its manufacturing method, which can optimize the electrical performance of the pixel area and improve the chip yield.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0008] A substrate is provided, the substrate comprising a first region and a second region arranged side by side;

[0009] A pad oxide layer and a pad nitride layer are sequentially grown on the substrate;

[0010] A first shallow trench is formed in the first region, and a second shallow trench is formed in the second region. The second shallow trench is arranged in parallel with the first shallow trench, and the depth of the second shallow trench is greater than the depth of the first shallow trench.

[0011] The pad nitride layer is removed by etching, and a compensation nitride layer is grown on the surface of the pad oxide layer, the inner wall of the first shallow trench, and the inner wall of the second shallow trench.

[0012] An insulating medium is filled into the first shallow trench and the second shallow trench, and the insulating medium is planarized so that the surface of the insulating medium is flush with the surface of the compensation nitride layer on both sides.

[0013] In one embodiment of the present invention, forming a first shallow trench in the first region specifically includes: forming a first photoresist layer covering the first region and the second region on the pad nitride layer; forming a plurality of openings for defining the position of the shallow trench on the first photoresist layer through exposure and development processes, the openings corresponding to the first region and the second region; using the first photoresist layer as a mask, performing a first etching to etch the pad nitride layer, pad oxide layer and part of the substrate exposed by the openings to form the first shallow trench.

[0014] In one embodiment of the present invention, a first shallow trench is formed by dry etching.

[0015] In one embodiment of the present invention, forming a second shallow trench in the second region specifically includes: forming a second photoresist layer on the pad nitride layer and the first shallow trench; removing the second photoresist layer located above the second region through exposure and development processes; and using the second photoresist layer and the pad nitride layer as a mask to continue etching the substrate exposed at the bottom of the first shallow trench in the second region to form a second shallow trench with a depth greater than that of the first shallow trench.

[0016] In one embodiment of the present invention, a second shallow trench is formed by dry etching.

[0017] In one embodiment of the present invention, the compensating nitriding layer and the pad nitriding layer are made of the same material.

[0018] In one embodiment of the present invention, before etching away the pad nitride layer, the method further includes: performing reflow etching on the side of the pad oxide layer and the pad nitride layer near the first shallow trench or the second shallow trench.

[0019] In one embodiment of the present invention, before etching away the pad nitride layer, the method further includes: thermally oxidizing the first shallow trench and the second shallow trench to form an inner oxide layer.

[0020] In one embodiment of the present invention, after planarizing the insulating medium, the method further includes etching away the compensation nitride layer on the upper surface of the pad oxide layer.

[0021] Secondly, the present invention provides a semiconductor structure, which is manufactured using the semiconductor structure manufacturing method described above.

[0022] The present invention has the following unexpected beneficial effects: The manufacturing method of the present invention first etches away the pad nitride layer to eliminate residual pad nitride layers of different heights; then, a compensation nitride layer of uniform thickness is grown on the surface of the pad oxide layer, the inner wall of the first shallow trench, and the inner wall of the second shallow trench, which effectively reduces the dark current in the pixel area, suppresses the leakage current in the logic area, improves the stability of subsequent processes, and reduces the defect rate caused by process errors. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic flowchart of a method for manufacturing a semiconductor structure according to an embodiment of this application is shown.

[0025] Figure 2 A schematic diagram of the substrate structure described in an embodiment of this application is shown.

[0026] Figure 3 This illustration shows a schematic diagram of the structure after a pad oxide layer and a pad nitride layer are sequentially grown on the substrate in an embodiment of this application.

[0027] Figure 4 This illustration shows a schematic diagram of the structure after the first photoresist layer is formed on the pad nitride layer in an embodiment of this application.

[0028] Figure 5 A schematic diagram of the first shallow trench after it has been formed in an embodiment of this application is shown.

[0029] Figure 6 This illustration shows a schematic diagram of the structure after the second photoresist layer is formed on the pad nitride layer and the first shallow trench in an embodiment of this application.

[0030] Figure 7 A schematic diagram of the second shallow trench after its formation is shown in an embodiment of this application.

[0031] Figure 8 A schematic diagram of the reflow etching process in an embodiment of this application is shown.

[0032] Figure 9 A schematic diagram of the lining oxide layer after its formation is shown in an embodiment of this application.

[0033] Figure 10 A schematic diagram of the pad nitriding layer after removal is shown in an embodiment of this application.

[0034] Figure 11A schematic diagram of the compensation nitriding layer after its formation is shown in an embodiment of this application.

[0035] Figure 12 A schematic diagram of the insulating medium formed in an embodiment of this application is shown.

[0036] Figure 13 This illustration shows a schematic diagram of the planarization of the insulating medium in an embodiment of this application, where the surface of the compensation nitriding layer is flush with the surface of both sides of the insulating medium.

[0037] Figure 14 A schematic diagram of the compensation nitriding layer after removal is shown in an embodiment of this application.

[0038] Label Explanation:

[0039] 1-Substrate, 2-Pad oxide layer, 3-Pad nitride layer, 4-First shallow trench, 5-Second shallow trench, 6-Compensation nitride layer, 7-Insulating dielectric, 8-First photoresist layer, 81-Opening, 9-Second photoresist layer, 10-Step, 11-First region, 12-Second region, 13-Inner oxide liner. Detailed Implementation

[0040] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0041] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] In one embodiment, see Figure 1 As shown, this invention discloses a method for manufacturing a semiconductor structure, comprising the following steps:

[0043] S1, please refer to Figure 2 As shown, a substrate 1 is provided, which includes a first region 11 and a second region 12 arranged side by side.

[0044] Specifically, substrate 1 can be made of any material suitable for semiconductor device fabrication, and can be categorized as follows: First, wide-bandgap semiconductor materials, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN); second, traditional compound semiconductor materials, including indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), and other III / V compounds; third, insulating and supporting materials, such as sapphire; and fourth, mainstream silicon-based materials, covering silicon wafers, silicon-on-insulator (SOI), silicon-on-insulator stacked layers, silicon-germanium-on-insulator (SGOI), and germanium-on-insulator (GOI). Furthermore, the substrate structure can also employ a stacked configuration of the aforementioned semiconductor materials to meet the performance requirements of complex devices.

[0045] In this embodiment, substrate 1 is preferably a silicon semiconductor substrate. This choice not only meets the compatibility requirements of mass production processes for CMOS image sensors but also reduces manufacturing costs. Meanwhile, the functional areas of substrate 1 are clearly defined: the first region 11 is specifically used to construct the pixel area of ​​the CIS, undertaking the core function of converting optical images into electrical signals; the second region 12 serves as the peripheral logic area of ​​the CIS, used to integrate logic devices such as metal-oxide-semiconductor field-effect transistors to achieve auxiliary functions such as signal transmission, preliminary processing, and circuit control.

[0046] S2, please refer to Figure 3 As shown, a pad oxide layer 2 and a pad nitride layer 3 are sequentially grown on substrate 1.

[0047] Specifically, after the substrate 1 is prepared, the pad oxide layer 2 and the pad nitride layer 3 need to be grown sequentially to construct the basic structure for subsequent processes.

[0048] The pad oxide layer 2 can be made of materials such as dense silicon oxide, and the preparation method is flexible and diverse, typically employing any one of the following methods: dry oxygen oxidation, wet oxygen oxidation, or in-situ water vapor growth. In this embodiment, dry oxygen oxidation is preferred. Specifically, the substrate 1 is placed in a furnace tube at the target temperature, and high-purity oxygen is introduced, causing the silicon atoms on the surface of the substrate 1 to undergo a chemical reaction with the oxygen in a high-temperature environment. The resulting pad oxide layer 2 not only has excellent density but also effectively reduces stress conflict between subsequent film layers and the substrate 1, while simultaneously preventing impurities from diffusing into the substrate.

[0049] The material selection for the pad nitride layer 3 focuses on insulation performance and process compatibility. Pure silicon nitride or a composite stacked structure of silicon nitride and silicon oxide can be used. In this embodiment, the pad nitride layer 3 is preferably prepared by low-pressure chemical vapor deposition (LPCVD). This method can precisely control the film thickness and uniformity, ensuring the accuracy of subsequent processes such as shallow trench etching.

[0050] As a key buffer and mask layer, the pad oxide layer 2 can significantly improve the lattice mismatch stress between the substrate 1 and the pad nitride layer 3 through its own stress regulation effect, thus preventing the film from cracking or peeling off.

[0051] S3, please refer to Figures 4 to 7 As shown, a first shallow trench 4 is formed in the first region 11, and a second shallow trench 5 is formed in the second region 12. The second shallow trench 5 is arranged side by side with the first shallow trench 4, and the depth of the second shallow trench 5 is greater than the depth of the first shallow trench 4.

[0052] S4, please refer to Figures 8 to 11 As shown, the pad nitride layer 3 is etched away, and a compensation nitride layer 6 is grown on the surface of the pad oxide layer 2, the inner wall of the first shallow trench 4, and the inner wall of the second shallow trench 5.

[0053] Specifically, please refer to Figure 7 As shown, the depth difference between the first shallow trench 4 and the second shallow trench 5 can lead to unevenness in the traditional pad nitride layer 3 after etching, with thinner residue in deep trenches and thicker residue in shallow trenches. These residual differences can cause interfacial stress concentration and become traps for impurity adsorption. Step S4 completely removes the pad nitride layer 3 by etching, which can eliminate the residual differences in different areas in one go, providing a defect-free substrate for subsequent film growth and avoiding problems such as interlayer peeling and charge trapping caused by residues from the source.

[0054] The newly grown compensation nitride layer 6 does not only cover the trench area, but is completely grown on the surface of the pad oxide layer 2, the inner wall of the first shallow trench 4, and the inner wall of the second shallow trench 5. On the one hand, the compensation nitride layer 6 on the surface of the pad oxide layer 2 forms a continuous buffer interface, and its uniformity can further optimize the stress matching between the subsequent insulating medium and the substrate 1, avoiding film cracking. On the other hand, for double trenches with significant depth differences, the compensation nitride layer 6 can achieve full coverage of the inner wall, especially the deep trench sidewall and bottom of the second shallow trench 5, which can form a protective film of uniform thickness, solving the problem of incomplete film coverage on the inner wall of the deep trench in traditional processes and improving the overall stability of the trench structure.

[0055] For the pixel region, i.e., the first shallow trench 4 corresponding to the first region 11, the uniformity of the compensating nitride layer 6 can reduce defects such as dangling bonds on the inner wall of the first shallow trench 4, reduce the probability of abnormal carrier transport, and facilitate the control of dark current in the pixel region. For the logic region, i.e., the second shallow trench 5 corresponding to the second region 12, the compensating nitride layer 6 on the inner wall of the second shallow trench 5 can enhance the insulation effect and avoid lateral leakage caused by defects on the inner wall of the trench. Furthermore, the uniformity of the compensating nitride layer 6 is the basis for the accuracy of subsequent high-density plasma (HDP) oxide layer deposition, planarization, and other processes. A uniform film layer can improve the filling uniformity of the HDP oxide layer in the double trenches and avoid oxide layer voids caused by uneven film layer on the inner wall of the trenches. At the same time, the compensating nitride layer 6 on the surface of the pad oxide layer 2 can serve as an etching stop layer for chemical mechanical polishing (CMP), providing a stable polishing reference for the planarization process and facilitating the achievement of the goal of consistent step height in the double shallow trench isolation structure.

[0056] S5, please refer to Figures 12 to 13 As shown, the first shallow trench 4 and the second shallow trench 5 are filled with insulating medium 7, and the insulating medium 7 is planarized so that the surface of the insulating medium 7 is flush with the surface of the compensation nitriding layer 6 on both sides.

[0057] Specifically, the filling effect of the insulating medium 7 directly determines the isolation reliability of the double shallow trench isolation structure. In this step, the uniform coverage of the compensating nitriding layer 6 provides an excellent wetting substrate for the insulating medium 7, ensuring that the dielectric material is completely filled to the corners of the first shallow trench 4 and the bottom of the deep trench of the second shallow trench 5, avoiding defects such as voids and gaps that are prone to occur in traditional filling.

[0058] In one embodiment of the present invention, forming a first shallow trench 4 in the first region 11 specifically includes:

[0059] Please see Figure 4 As shown, a first photoresist layer 8 is formed on the surface of the pad nitride layer 3. The first photoresist layer 8 needs to completely cover the first region 11 and the second region 12 of the substrate 1 to ensure the completeness of subsequent pattern definition. Subsequently, the first photoresist layer 8 is patterned through exposure and development processes to form multiple openings 81. The position and size of the openings 81 precisely correspond to the preset shallow trench layout in the first region 11 and the second region 12, providing a clear window for subsequent etching processes.

[0060] Please see Figure 5As shown, the first etching process is performed using the patterned first photoresist layer 8 as a mask. The etching process will sequentially remove the pad nitride layer 3 and the pad oxide layer 2 in the exposed area of ​​the opening 81, and partially etch the underlying substrate 1, ultimately forming the first shallow trench 4 in the first region 11 and the second region 12.

[0061] In this embodiment, the first etching is preferably a dry etching process, which has the advantages of fast etching rate and good anisotropy. It can accurately control the verticality of the trench sidewalls and avoid morphological defects such as inverted trapezoids in shallow trenches.

[0062] Specifically, the etching gas can be one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr), or it can be combined with oxygen (O2). Chlorine and hydrogen bromide are mainly used for etching the silicon substrate, while fluorine gases such as trifluoromethane and difluoromethane can assist in etching the pad oxide layer and pad nitride layer. After the first etching is completed, the first photoresist layer 8 is thoroughly removed using an ashing combined with wet cleaning method, reserving a clean process surface for the subsequent fabrication of the second shallow trench.

[0063] In one embodiment of the present invention, forming a second shallow trench 5 within the second region 12 specifically includes:

[0064] Please see Figure 6 and Figure 7 As shown, after the first shallow trench 4 is formed, a second photoresist layer 9 is formed on the pad nitride layer 3 and the first shallow trench 4. The second photoresist layer 9 located above the second region 12 is removed through exposure and development processes. Then, using the second photoresist layer 9 and the pad nitride layer 3 as a mask, the substrate 1 exposed at the bottom of the first shallow trench 4 in the second region 12 is further etched to form a second shallow trench 5 with a depth greater than the first shallow trench 4. That is, during the second etching, the area where a deeper shallow trench isolation structure needs to be formed is directly exposed, ensuring self-alignment between the first and second etching processes and preventing performance degradation of the semiconductor device due to failure of the shallow trench isolation structure.

[0065] Specifically, please refer to Figure 6As shown, a second photoresist layer 9 is formed to completely cover the surface of the pad nitride layer 3 after the first etching and the interior and surface of the first shallow trench 4. This second photoresist layer 9 must be free of pinholes and bubbles, especially ensuring good coverage at the trench edges of the first shallow trench 4 to avoid edge damage during subsequent etching. Subsequently, through precise exposure and development processes, the second photoresist layer 9 directly above the second region 12 is selectively removed, exposing the pad nitride layer 3 of the second region 12 and the substrate 1 at the bottom of the first shallow trench 4, while the first region 11 remains completely protected by the second photoresist layer 9, providing a clear mask boundary for subsequent differential etching.

[0066] Please see Figure 6 and Figure 7 As shown, using the patterned second photoresist layer 9 and the remaining pad nitride layer 3 as a composite mask, a second etching process is performed on the exposed substrate 1 in the second region 12. This etching starts from the bottom of the first shallow trench 4 formed in the first etching and continues to etch the substrate 1 downwards, ultimately forming a second shallow trench 5 with a depth greater than the first shallow trench 4. That is, during the second etching, the area requiring a deeper shallow trench isolation structure is directly exposed, ensuring the alignment accuracy and depth controllability of the first and second etching processes. Through the step-by-step design of the two etching processes, the trench foundation can be uniformly laid through the first etching, and the deep trench requirement of the second region 12 can be achieved through precise second etching, avoiding the depth deviation problem caused by etching two deep trenches in one go.

[0067] In this embodiment, the second etching is also preferably performed using a dry etching process. The etching gas can be a mixture of chlorine and hydrogen bromide, with an appropriate increase in the proportion of hydrogen bromide to enhance the etching selectivity of the silicon substrate and reduce lateral erosion of the sidewalls of the first shallow trench 4. During the etching process, the depth of the second shallow trench 5 is precisely controlled by real-time monitoring of the etching time and plasma emission spectrum to ensure that the depth difference between the second and first shallow trenches 4 meets the isolation performance requirements of the logic region. After the second etching is completed, the second photoresist layer 9 is removed using an ashing process, and wet cleaning is performed using diluted hydrofluoric acid (DHF) to remove residual polymers and impurities. Finally, a double shallow trench isolation structure with shallow trenches in the first region 11 and deep trenches in the second region 12 is obtained, providing a structural basis for the subsequent growth of the compensation nitride layer 6.

[0068] In one embodiment of the present invention, the compensation nitride layer 6 and the pad nitride layer 3 are made of the same material. Using the same material for both allows for the reuse of equipment and parameters, eliminating the need to redevelop the etching process, reducing process development costs, and mitigating issues such as film residue or over-etching caused by parameter deviations.

[0069] In one embodiment of the present invention, before etching away the pad nitride layer 3, the method further includes: (See attached diagram) Figure 8As shown, the pad oxide layer 2 and the pad nitride layer 3 are subjected to pull back etching on the side near the first shallow trench 4 or the second shallow trench 5 to form a step 10 in the pad oxide layer and the pad nitride layer.

[0070] Specifically, please refer to Figure 8 As shown, wet etching is the primary method used to selectively etch the pad oxide layer 2 and pad nitride layer 3 on the side closest to the first shallow trench 4 or the second shallow trench 5. This etching process only acts on the film region at the trench edge. By precisely controlling the etching time and rate, an inwardly contracting step 10 is formed at the trench side edge of the pad oxide layer 2 and pad nitride layer 3. The width of the step 10 is typically controlled within the range of 50-200 nm, which avoids over-etching and damaging the substrate while reserving optimized space for subsequent film growth.

[0071] After reflow etching, the pad oxide layer 2 and pad nitride layer 3 at the trench edges of the first shallow trench 4 and the second shallow trench 5 will form a micro-rough structure. This structure can increase the contact area with the subsequent compensation nitride layer 6 and strengthen the interlayer bonding force. Furthermore, the gradient trench inlet formed by the step 10 can optimize the filling flow field of the subsequent insulating medium 7. During the HDP oxide layer deposition process, the insulating medium material can flow smoothly into the trench along the step 10, reducing the eddy current effect at the trench inlet and improving the filling density of the insulating medium 7.

[0072] In one embodiment of the present invention, before etching away the pad nitride layer, the method further includes: (See attached document) Figure 9 As shown, the first shallow trench 4 and the second shallow trench 5 are subjected to thermal oxidation treatment to form an inner oxide layer 13.

[0073] After reflow etching, the inner walls of the first shallow trench 4 and the second shallow trench 5, which expose the substrate 1, undergo thermal oxidation treatment. In this embodiment, a high-temperature wet oxygen oxidation process is preferred. The substrate is placed in a furnace tube at 800~1000℃, and a mixture of oxygen and water vapor is introduced, causing the silicon atoms on the inner wall of the trench to react chemically with oxygen, forming a uniformly thick inner oxide layer 13. The thickness of the inner oxide layer 13 is typically controlled between 10~50nm, which achieves defect passivation without excessively occupying the trench filling space.

[0074] After the first shallow trench 4 and the second shallow trench 5 are etched twice, defects such as dangling bonds and lattice distortion are easily generated on the surface of the inner wall substrate. These defects are one of the main sources of dark current in the pixel area. The inner oxide layer 13 forms a stable SiO2 structure with the silicon atoms of the inner wall of the trench through a thermal oxidation process, which can effectively fill lattice defects and saturate dangling bonds, and reduce abnormal recombination and transport of charge carriers at the edge of the trench.

[0075] Furthermore, the inner oxide layer 13, serving as the first insulating barrier on the inner wall of the trench, forms an oxide-nitride composite insulation structure with the subsequent compensating nitride layer 6, exhibiting superior insulation performance compared to a single nitride layer. For the deep trench structure of the second region 12, this composite insulation layer can significantly enhance the breakdown electric field strength of the trench, preventing lateral leakage caused by defects on the inner wall of the trench.

[0076] Meanwhile, the inner oxide layer 13 has good hydrophilicity and smoothness, which can optimize the deposition and wetting effect of the compensation nitride layer 6, so that the compensation nitride layer 6 forms a more uniform covering film along the inner wall of the trench (including the bottom of the deep trench), avoiding the thickness fluctuation of the compensation nitride layer 6 caused by the roughness of the substrate 1 surface; at the same time, the lattice matching between the inner oxide layer 13 and the compensation nitride layer 6 is good, which can further reduce interlayer stress and reduce the risk of film peeling.

[0077] In one embodiment of the present invention, after planarizing the insulating medium, the method further includes: (See attached diagram) Figure 14 As shown, the compensation nitride layer 6 on the upper surface of the pad oxide layer 2 is etched away.

[0078] Specifically: Please refer to Figure 14 As shown, a hot phosphoric acid wet etching process, compatible with the etching system used to remove the pad nitride layer 3, is employed to selectively etch the compensation nitride layer 6 on the upper surface of the pad oxide layer 2. This etching process, through precise control of the hot phosphoric acid concentration, reaction temperature, and etching time, removes only the compensation nitride layer 6 on the surface of the pad oxide layer 2, while retaining the compensation nitride layer 6 on the inner walls of the first shallow trench 4 and the second shallow trench 5, as well as the edge of the insulating dielectric 7, ensuring the integrity of the composite insulation structure within the trenches.

[0079] After the compensation nitride layer 6 on the upper surface of the pad oxide layer 2 completes its auxiliary function for CMP polishing, its residue can become an interference factor in subsequent processes such as pixel area ion implantation and photoresist coating. Selectively removing the nitride layer in this area exposes a clean and uniform surface of the pad oxide layer 2, providing a consistent substrate for photoresist adhesion, avoiding photolithographic pattern distortion caused by the difference in antireflectivity between the nitride layer and the pad oxide layer 2, and improving the doping accuracy of ion implantation.

[0080] In summary, the manufacturing method of this invention completely solves the problem of uneven height of residual pad nitride layer 3 in different areas in traditional processes by etching away the pad nitride layer 3, providing a defect-free substrate for subsequent film growth. The uniform thickness of the compensation nitride layer 6 grown on the surface of the pad oxide layer 2 and the inner walls of the first shallow trench 4 and the second shallow trench 5 optimizes the interface states of the pixel region, reduces abnormal carrier transport, and effectively lowers dark current. Furthermore, the uniform compensation nitride layer 6 forms a complete and dense insulating interface with the logic region deep trench structure, i.e., the second shallow trench 5, avoiding lateral leakage caused by film defects or height differences, and improving insulation reliability. Simultaneously, the uniformity of the compensation nitride layer 6 and the elimination of residual pad nitride layer 3 provide a stable foundation for subsequent processes such as insulating dielectric 7 filling and planarization, reducing process fluctuations. By optimizing interface quality and improving process stability, device performance failures caused by process errors are reduced from the source, significantly lowering the defect rate.

[0081] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region arranged side by side; A pad oxide layer and a pad nitride layer are sequentially grown on the substrate; A first shallow trench is formed in the first region, and a second shallow trench is formed in the second region. The second shallow trench is arranged side by side with the first shallow trench, and the depth of the second shallow trench is greater than the depth of the first shallow trench. Reflow etching is performed on the side of the pad oxide layer and the pad nitride layer near the first shallow trench or the second shallow trench to form an inwardly contracting step on the trench side edge of the pad oxide layer and the pad nitride layer; the pad nitride layer is etched away, and a compensation nitride layer is grown on the surface of the pad oxide layer, the inner wall of the first shallow trench, and the inner wall of the second shallow trench, wherein the thickness of the compensation nitride layer in the step region is greater than the thickness of the compensation nitride layer in other regions, forming a gradient trench inlet; An insulating medium is filled into the first shallow trench and the second shallow trench, and the insulating medium is planarized so that the surface of the insulating medium is flush with the surface of the compensation nitride layer on both sides.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Forming a first shallow trench in the first region specifically includes: forming a first photoresist layer on the pad nitride layer that covers the first region and the second region; Through exposure and development processes, a plurality of openings are formed on the first photoresist layer to define the location of shallow trenches, the openings corresponding to the first region and the second region; Using the first photoresist layer as a mask, the first etching is performed to etch the exposed pad nitride layer, pad oxide layer, and part of the substrate to form the first shallow trench.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The first shallow trench was formed by dry etching.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: Forming a second shallow trench in the second region specifically includes: forming a second photoresist layer on the pad nitride layer and the first shallow trench; The second photoresist layer located above the second region is removed through exposure and development processes. Using the second photoresist layer and the pad nitride layer as masks, the substrate exposed at the bottom of the first shallow trench in the second region is further etched to form a second shallow trench with a depth greater than that of the first shallow trench.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The second shallow trench was formed by dry etching.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The compensating nitriding layer and the pad nitriding layer are made of the same material.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Before etching away the pad nitride layer, the process further includes: thermally oxidizing the first shallow trench and the second shallow trench to form an inner oxide layer.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After planarizing the insulating medium, the process further includes etching away the compensating nitride layer on the upper surface of the pad oxide layer.

9. A semiconductor structure, characterized in that: It is prepared by the manufacturing method of the semiconductor structure as described in any one of claims 1 to 8.

Images